extensive development environment that includes a copy of BASIC09. C and Pascal compilers were available. Members of the CoCo OS-9 community enhanced OS-9 Level 2 for the CoCo 3 at Tandy's request, but Tandy stopped production of the CoCo 3 before the upgrade was officially released. Most of the improvements made it into NitrOS-9, a major rewrite of OS-9/6809 Level 2 for the CoCo 3 to take advantage of the features and speed of the Hitachi 6309 (if available). A joystick adapter designed by Steve Bjork increases the resolution of the joystick/mouse interface by a factor of ten at the expense of CPU time. Hardware Internally the CoCo 1 and CoCo 2 models are functionally identical. The core of the system is virtually identical to the reference design included in the Motorola MC6883 data sheet and consists of five LSI chips: MC6809E Microprocessor Unit (MPU) MC6883/SN74LS783/SN74LS785 Synchronous Address Multiplexor (SAM) MC6847 Video Display Generator (VDG) Two Peripheral Interface Adapters (PIA), either MC6821 or MC6822 chips SAM The SAM is a multifunction device that performs the following functions: Clock generation and synchronization for the 6809E MPU and 6847 VDG Up to 64K Dynamic Random Access Memory (DRAM) control and refresh Device selection based on MPU memory address to determine if the MPU access is to DRAM, ROM, PIA, etc. Duplication of the VDG address counter to "feed" the VDG the data it is expecting The SAM was designed to replace numerous small LS/TTL chips into one integrated package. Its main purpose is to control the DRAM but, as outlined above, it integrates several other functions as well. It is connected to a crystal at 4 times the television colorburst frequency (14.31818 MHz for NTSC countries). This is divided by 4 internally and is fed to the VDG for its own internal timing (3.579545 MHz for NTSC). The SAM also divides the master clock by 16 (or 8 in certain cases) for the two phase MPU clock; in NTSC this is .89 MHz (or 1.8 MHz if divided by 8). Switching the SAM into 1.8 MHz operation gives the CPU the time ordinarily used by the VDG and refresh. As such, the display shows garbage; this mode was seldom used. However, an unusual mode available by the SAM is called the Address Dependent mode, where ROM reads (since they do not use the DRAM) occur at 1.8 MHz but regular RAM access