LEON4 the name typically refers to only the processor core, while LEON/GRLIB is used to refer to the complete system-on-chip design. LEON2 processor core LEON2 has the following characteristics: The GNU LGPL allows a high degree of freedom of intervention on the freely available source code. Configurability is a key feature of the project, and is achieved through the usage of VHDL generics. It offers all basic functions of a pipelined in-order processor. It is a fairly sized VHDL project (about 90 files, for the complete LEON2 distribution, including peripheral IP cores) LEON2-FT processor core The LEON2-FT processor is the single-event upset fault tolerant (FT) version of the LEON2 processor. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits. Special licence restrictions apply to this IP (distributed by the European Space Agency). Among other satellites, the processor was used in ESA's Intermediate eXperimental Vehicle (IXV) in 2015 and China's Chang'e 4 lunar lander. LEON3 processor core The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The full source code is available under the GNU GPL license, allowing use for any purpose without licensing fee. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications. There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes SMP support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline. LEON3FT processor core The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single-event upset (SEU) errors in all on-chip RAM memories. The LEON3FT processor supports most of the functionality in the standard LEON3 processor, and adds the following features: Register file SEU error-correction of up to 4 errors per 32-bit word Cache memory error-correction of up to 4 errors per tag or 32-bit word Autonomous and software transparent error handling No timing impact due to error detection or correction The following features of the standard LEON3 processor are not supported by LEON3FT Local scratchpad RAM (neither for instruction nor for data) Cache locking LRR (least recently replaced) cache replacement algorithm The LEON3FT core is distributed