of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. All processors in the LEON series use the SPARC V8 reduced instruction set computer (RISC) ISA. LEON2(-FT) has a five-stage pipeline while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2(-FT) design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design. The standard LEON2(-FT) distribution includes the following support cores: Interrupt controller Debug support unit with trace buffer Two 24-bit timers Two universal asynchronous receiver-transmitters (UARTs) 16-bit I/O port Memory controller. The LEON3, LEON3FT, and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for FPGA development boards and for ASIC targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a plug and play (PnP) extension to the on-chip Advanced Microcontroller Bus Architecture (AMBA) bus. IP cores available in GRLIB also include: 32-bit PC133 synchronous dynamic random-access memory (SDRAM) controller 32-bit Peripheral Component Interconnect (PCI) bridge with direct memory access (DMA) 10/100/1000 Mbit Ethernet media access control address (MAC address) 8/16/32-bit programmable read-only memory (PROM) and static random-access memory (SRAM) controller 16/32/64-bit DDR/DDR2 controllers Universal Serial Bus (USB) 2.0 host and device controllers Controller area network (CAN) controller JTAG TAP controller Serial Peripheral Interface (SPI) controller Inter-Integrated Circuit (I²C) controller Universal asynchronous receiver-transmitter (UART) with first in, first out (FIFO) Modular timer unit Interrupt controller 32-bit general-purpose I/O (GPIO) port FPGA design flow Design flow documentation for the LEON into FPGA are available from the manufacturer and from third party resources. Terminology The term LEON2/LEON2-FT often refer to the LEON2 system-on-chip design, which is the LEON2 processor core together with the standard set of peripherals available in the LEON2(-FT) distribution. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. With LEON3 and