a 32-bit immediate operand. Instructions without this operand are generally able to perform two or more operations simultaneously. Many instructions are conditional, and may be preceded with "if condition " in the assembly language. There are a number of condition choices, similar to the choices provided by the x86 flags register. There are two delay slots. After a jump, two instructions following the jump will normally be executed. The SHARC processor has built-in support for loop control. Up to 6 levels may be used, avoiding the need for normal branching instructions and the normal bookkeeping related to loop exit. The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an OS or between two threads. See also TigerSHARC Blackfin Qualcomm Hexagon Texas Instruments TMS320 CEVA, Inc. External links SHARC processors website Digital signal processors Very long instruction word computing VLIW microprocessors