The IBM Floating Point Architecture The EBCDIC character set Nine-track magnetic tape Architectural overview The System/360 series has a computer system architecture specification. This specification makes no assumptions on the implementation itself, but rather describes the interfaces and expected behavior of an implementation. The architecture describes mandatory interfaces that must be available on all implementations, and optional interfaces. Some aspects of this architecture are: Big endian byte ordering A processor with: 16 32-bit general purpose registers (R0–R15) A 64-bit program status word (PSW), which describes (among other things) Interrupt masks Privilege states A condition code A 24-bit instruction address An interruption mechanism, maskable and unmaskable interruption classes and subclasses An instruction set. Each instruction is wholly described and also defines the conditions under which an exception is recognized in the form of program interruption. A memory (called storage) subsystem with: 8 bits per byte A special processor communication area starting at address 0 24-bit addressing Manual control operations that allow A bootstrap process (a process called Initial Program Load or IPL) Operator-initiated interrupts Resetting the system Basic debugging facilities Manual display and modifications of the system's state (memory and processor) An Input/Output mechanism which does not describe the devices themselves Some of the optional features are: Binary-coded decimal instructions Floating-point instructions Timing facilities (interval timer) Key-controlled memory protection All models of System/360, except for the Model 20 and Model 44, implemented that specification. Binary arithmetic and logical operations are performed as register-to-register and as memory-to-register/register-to-memory as a standard feature. If the Commercial Instruction Set option was installed, packed decimal arithmetic could be performed as memory-to-memory with some memory-to-register operations. The Scientific Instruction Set feature, if installed, provided access to four floating-point registers that could be programmed for either 32-bit or 64-bit floating-point operations. The Models 85 and 195 could also operate on 128-bit extended-precision floating-point numbers stored in pairs of floating-point registers, and software provided emulation in other models. The System/360 used an 8-bit byte, 32-bit word, 64-bit double-word, and 4-bit nibble. Machine instructions had operators with operands, which could contain register numbers or memory addresses. This complex combination of instruction options resulted in a variety of instruction lengths and formats. Memory addressing was accomplished using a base-plus-displacement scheme, with registers 1 through F (15). A displacement was encoded in 12 bits, thus allowing a 4096-byte displacement (0–4095), as the offset from the address put in a base register. Register