___ ___ ___ ___ C/BE[3:0]# ---<__X__X___>---<___> | | | | ___ IRDY# ^^^^^^^^\__/ ^^^^^ | | | | ___ TRDY# ^^^^^^^^\__/ ^^^^^ | | | | ___ DEVSEL# ^^^^^^^^\__/ ^^^^^ ___ | | | ___ FRAME# \___/ | ^^^^\ _ _ |_ |_ |_ |_ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ 0 1 2 3 4 5 6 7 On clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors. That might be their turnaround cycle. On cycle 2, the target asserts both DEVSEL# and TRDY#. As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end. On clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle. On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines. The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#: 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ ___ ___ ___ ___ ___ AD[31:0] ---<___>---<__X__>---<___> ___ ___ ___ ___ ___ C/BE[3:0]# ---<__X__X___>---<___> ___ | | | | ___ IRDY# ^^^^\___/ ^^^^^ ___ _ | | | | ___ TRDY# ^^^^ \__/ ^^^^^ ___ | | | | ___ DEVSEL# ^^^^\___/ ^^^^^ ___ | | | ___ FRAME# \___/ | ^^^^\ _ _ _ |_ |_ |_ |_ _ _ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ 0 1 2 3 4 5 6 7 8 A high-speed burst terminated by the target will have an extra cycle at the end: 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ ___ ___ ___ ___ ___ AD[31:0] ---<___>---<__X__XXXX>---- ___ ___ ___ ___ ___ ___ C/BE[3:0]# ---<__X__X__>---- | | | | ___ IRDY# ^^^^^^^\___/ _ | | | | ___ TRDY# ^^^^^^^ \__/ | ___ STOP# ^^^^^^^ | | | \___/ | | | | ___