10 November 1997. Motorola and Apple liked the moniker and used the term "G4" for the 7400 family introduced in 1998 and the Power Mac G4 in 1999. At the time the G4 was launched, Motorola categorized all their PowerPC models (former, current and future) according to what generation they adhered to, even renaming the older 603e core "G2". Motorola had a G5 project that never came to fruition, but the name stuck and Apple reused it when the 970 family launched in 2003 even if those were designed and built by IBM. PowerPC generations according to Motorola, c. 2000. G1: The 601, 500 and 800 family processors G2: The 602, 603, 604, 620, 8200 and 5000 families G3: The 750 and 8300 families G4: The 7400 and 8400* families G5: The 7500* and 8500 families (Motorola didn't use the G5 moniker after Apple usurped the name) G6: The 7600* (*) These designs didn't become real products. Design features The PowerPC is designed along RISC principles and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added: Support for operation in both big-endian and little-endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC 970. Single-precision forms of some floating-point instructions, in addition to double-precision forms Additional floating-point instructions at the behest of Apple A complete 64-bit specification that is backward compatible with the 32-bit mode A fused multiply–add A paged memory management architecture that is used extensively in server and PC systems. Addition of a new memory management architecture called Book-E, replacing the conventional paged memory management architecture for embedded applications. Book-E is application software compatible with existing PowerPC implementations but needs minor changes to the operating system. Some instructions present in the POWER instruction set were deemed too complex and were removed in the PowerPC architecture. Some removed instructions could be emulated by the operating system if necessary. The removed instructions are: Conditional moves Load and store instructions for the quad-precision floating-point data type String instructions. Endian modes Most PowerPC chips switch endianness via a bit in the MSR (machine state register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as