is stopping for some reason (e.g. to save power). No device ever responds to this cycle; it is always terminated with a master abort after leaving the data on the bus for at least 4 cycles. 0010 I/O Read This performs a read from I/O space. All 32 bits of the read address are provided, so that a device may (for compatibility reasons) implement less than 4 bytes worth of I/O registers. If the byte enables request data not within the address range supported by the PCI device (e.g. a 4-byte read from a device which only supports 2 bytes of I/O address space), it must be terminated with a target abort. Multiple data cycles are permitted, using linear (simple incrementing) burst ordering. The PCI standard is discouraging the use of I/O space in new devices, preferring that as much as possible be done through main memory mapping. 0011 I/O Write This performs a write to I/O space. 010x Reserved A PCI device must not respond to an address cycle with these command codes. 0110 Memory Read This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bytes, the two least significant bits of the address are not needed during the address phase; equivalent information will arrive during the data phases in the form of byte select signals. They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect. If a memory space is marked as "prefetchable", then the target device must ignore the byte select signals on a memory read and always return 32 valid bits. 0111 Memory Write This operates similarly to a memory read. The byte select signals are more important in a write, as unselected bytes must not be written to memory. Generally, PCI writes are faster than PCI reads, because a device may buffer the incoming write data and release the bus faster. For a read, it must delay the data phase until the data has been fetched. 100x Reserved A PCI device must not respond to an address cycle with these command codes. 1010 Configuration Read This is similar to an I/O read, but reads from PCI configuration space. A device must respond only if the low 11 bits of the address specify