|CLA SCA \_ _/ | MQA MQL CODE 1* 2 2 2 3 7601 – CLA – Clear AC 7501 – MQA – Multiplier Quotient with AC (logical or MQ into AC) 7441 – SCA – Step counter load into AC 7421 – MQL – Multiplier Quotient Load (Transfer AC to MQ, clear AC) 7621 – CAM – CLA + MQL clears both AC and MQ. Typically CLA and MQA were combined to transfer MQ into AC. Another useful combination is MQA and MQL, to exchange the two registers. Three bits specified a multiply/divide instruction to perform: 7401 – No operation 7403 – SCL – Step Counter Load (immediate word follows, PDP-8/I and up) 7405 – MUY – Multiply 7407 – DVI – Divide 7411 – NMI – Normalize 7413 – SHL – Shift left (immediate word follows) 7415 – ASR – Arithmetic shift right 7417 – LSR – Logical shift right Memory control A 12-bit word can have 4,096 different values, and this is the maximum number of words the original PDP-8 can address indirectly through a word pointer. 4,096 12-bit words represent 6,144 bytes in modern terminology, or 6 kB. As programs became more complex and the price of memory fell, it became desirable to expand this limit. To maintain compatibility with pre-existing programs, new hardware outside the original design added high-order bits to the effective addresses generated by the program. The Memory Extension Controller expands the addressable memory by a factor of 8, to a total of 32,768 words. This expansion was thought sufficient because, with core memory then costing about 50 cents a word, a full 32K of memory would equal the cost of the CPU. Each 4K of memory is called a field. The Memory Extension Controller contains two three-bit registers: the DF (Data Field) and the IF (Instruction Field). These registers specify a field for each memory reference of the CPU, allowing a total of 15 bits of address. The IF register specifies the field for instruction fetches and direct memory references; the DF register specifies the field for indirect data accesses. A program running in one field can reference data in the same field by direct addressing, and reference data in another field by indirect addressing. A set of I/O instructions in the range 6200 through 6277 is handled by the Memory Extension Controller and give access to the DF and IF registers.