device load is spread fairly evenly across the four available interrupt pins. This alleviates a common problem with sharing interrupts. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific Basic Input/Output System (BIOS) code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to. PCI interrupt lines are level-triggered. This was chosen over edge-triggering to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss. Later revisions of the PCI specification add support for message-signaled interrupts. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines. PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively. Conventional hardware specifications These specifications represent the most common version of PCI used in normal PCs: clock with synchronous transfers Peak transfer rate of 133 MB/s (133 megabytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s) 32-bit bus width 32- or 64-bit memory address space (4 GiB or 16 EiB) 32-bit I/O port space 256-byte (per device) configuration space 5-volt signaling Reflected-wave switching The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards. The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master. Card voltage and keying Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.47 mm from the