modify the Athlon XP to function as an MP. Specifications L1-cache: 64 + 64 KB (data + instructions) L2-cache: 256 KB, full speed MMX, 3DNow!, SSE Socket A (EV6) Front-side bus: 133 MHz (266 MT/s) Vcore: 1.50 to 1.75 V Power consumption: 68 W First release: October 9, 2001 Clock-rate: Athlon 4: 850–1400 MHz Athlon XP: 1333–1733 MHz (1500+ to 2100+) Athlon MP: 1000–1733 MHz Thoroughbred The fourth-generation of Athlon was introduced with the Thoroughbred core, or T-Bred, on April 17, 2002. The Thoroughbred core marked AMD's first production 130 nm silicon, with smaller die size than its predecessor. There came to be two steppings (revisions) of this core commonly referred to as Tbred-A and Tbred-B. Introduced in June 2002, the initial A version was mostly a direct die shrink of the preceding Palomino core, but did not significantly increase clock speeds over the Palomino. A revised Thoroughbred core, Thoroughbred-B, added a ninth "metal layer" to the eight-layered Thoroughbred-A, offering improvement in headroom over the A and making it popular for overclocking. Specifications L1-cache: 64 + 64 KB (data + instructions) L2-cache: 256 KB, full speed MMX, 3DNow!, SSE Socket A (EV6) Front-side bus: 133/166 MHz (266/333 MT/s) Vcore: 1.50–1.65 V First release: June 10, 2002 (A), August 21, 2002 (B) Clock-rate: Thoroughbred "A": 1400–1800 MHz (1600+ to 2200+) Thoroughbred "B": 1400–2250 MHz (1600+ to 2800+) 133 MHz FSB: 1400–2133 MHz (1600+ to 2600+) 166 MHz FSB: 2083–2250 MHz (2600+ to 2800+) Barton / Thorton Fifth-generation Athlon Barton-core processors were released in early 2003. While not operating at higher clock rates than Thoroughbred-core processors, they featured an increased L2 cache, and later models had an increased 200 MHz (400 MT/s) front side bus. The Thorton core, a blend of thoroughbred and Barton, was a later variant of the Barton with half of the L2 cache disabled. The Barton was used to officially introduce a higher 400 MT/s bus clock for the Socket A platform, which was used to gain some Barton models more efficiency. By this point with the Barton, the four-year-old Athlon EV6 bus architecture had scaled to its limit and required a redesign to exceed the performance of newer Intel processors. By 2003, the Pentium 4 had become more than competitive with AMD's processors, and Barton only saw a small performance increase over the Thoroughbred-B it derived from, insufficient to outperform the Pentium 4. The K7-derived Athlons such