more data in-flight at once. The critical branch-predictor unit was enhanced compared to the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained. Like the AMD K5 and K6, the Athlon dynamically buffered internal micro-instructions at runtime resulting from parallel x86 instruction decoding. The CPU is an out-of-order design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the Alpha 21264's EV6 bus architecture with double data rate (DDR) technology. AMD ended its long-time handicap with floating point x87 performance by designing a super-pipelined, out-of-order, triple-issue floating-point unit (FPU). Each of its three units could independently calculate an optimal type of instructions with some redundancy, making it possible to operate on more than one floating-point instruction at once. This FPU was a huge step forward for AMD, helping compete with Intel's P6 FPU. The 3DNow! floating-point SIMD technology, again present, received some revisions and was renamed "Enhanced 3DNow!" Additions included DSP instructions and the extended MMX subset of Intel SSE. Specifications L1-cache: 64 + 64 KB (data + instructions) L2-cache: 512 KB, external chips on CPU module with 50%, 40% or 33% of CPU speed MMX, 3DNow! Slot A (EV6) Front-side bus: 200 MT/s (100 MHz double-pumped) Vcore: 1.6 V (K7), 1.6–1.8 V (K75) First release: June 23, 1999 (K7), November 29, 1999 (K75) Clock-rate: 500–700 MHz (K7), 550–1000 MHz (K75) Athlon Thunderbird (2000–2001) The second-generation Athlon, the Thunderbird or T-Bird, debuted on June 4, 2000. This version of the Athlon was available in a traditional pin-grid array (PGA) format that plugged into a socket ("Socket A") on the motherboard, or packaged as a Slot A cartridge. The major difference between it and the Athlon Classic was cache design, with AMD adding in 256 KB of on-chip, full-speed exclusive cache. In moving to an exclusive cache design, the L1 cache's contents were not duplicated in the L2, increasing total cache size and functionally creating a large L1 cache with a slower region (the L2) and a fast region (the L1), making the L2 cache into basically a victim cache. With the new cache design, need for high L2 performance and size was lessened, and the simpler L2 cache was less likely to cause clock scaling and yield issues. Thunderbird also moved to a 16-way associative layout. The Thunderbird was "cherished by many for its overclockability" and proved commercially successful, as AMD's most successful product since the