Ivy Bridge is the codename for Intel's 22 nm microarchitecture used in the third generation of the Intel Core processors (Core i7, i5, i3). Ivy Bridge is a die shrink to 22 nm process based on FinFET ("3D") Tri-Gate transistors, from the former generation's 32 nm Sandy Bridge microarchitecture—also known as tick–tock model. The name is also applied more broadly to the Xeon and Core i7 Ivy Bridge-E series of processors released in 2013. Ivy Bridge processors are backward compatible with the Sandy Bridge platform, but such systems might require a firmware update (vendor specific). In 2011, Intel released the 7-series Panther Point chipsets with integrated USB 3.0 and SATA 3.0 to complement Ivy Bridge. Volume production of Ivy Bridge chips began in the third quarter of 2011. Quad-core and dual-core-mobile models launched on April 29, 2012 and May 31, 2012 respectively. Core i3 desktop processors, as well as the first 22 nm Pentium, were announced and available the first week of September 2012. Ivy Bridge is the last Intel platform to fully support Windows XP and the earliest Intel microarchitecture to officially support Windows 10 64-bit. Overview The Ivy Bridge CPU microarchitecture is a shrink from Sandy Bridge and remains largely unchanged. Like its predecessor, Sandy Bridge, Ivy Bridge was also primarily developed by Intel's Israel branch, located in Haifa, Israel. Notable improvements include: New 22 nm Tri-gate transistor ("3-D") technology offer as much as a 50% reduction to power consumption at the same performance level as compared to 2-D planar transistors on Intel's 32 nm process. A new pseudorandom number generator and the RDRAND instruction, codenamed Bull Mountain. Ivy Bridge features and performance The mobile and desktop Ivy Bridge chips also include some minor yet notable changes over Sandy Bridge: CPU F16C (16-bit floating-point conversion instructions) RDRAND instruction (Intel Secure Key) Max CPU multiplier of 63 (versus 57 for Sandy Bridge) Configurable TDP (cTDP) for mobile processors A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss {| class="wikitable" style="text-align: center" |+ |- ! colspan="2" | Cache ! colspan="3" | Page Size |- ! Name ! Level ! 4KB ! 2MB ! 1GB |- | DTLB | 1st | 64 | 32 | 4 |- | ITLB | 1st | 128 | 8 / logical core | none |- | STLB | 2nd | 512 | none | none |} GPU The built-in GPU