and use bits 4 and 5 as part of the specification of the operation. Literal format Group 1 Format Group 1 instructions perform arithmetic, logical, exchange and shifting functions on the accumulator registers. This includes hardware multiply and divide instructions. Bit 4 is set if the K register is affected. Bit 5 is set if the J register is affected. Both bits are set of both registers are affected. Group 2 format Group 2 format instructions test for internal conditions of the J and K accumulator registers, manipulate the overflow and flag status bits and provide complement, increment and negation operations on the J and K accumulator registers. Bits 9, 10 and 11 select the condition to be tested. Two word instructions Bit 9, Change Fields, inhibits the absolute address from referencing a different field than the one containing the instruction. When bit 8 is 1, the upper accumulator K is used with the instruction, otherwise the lower accumulator J is used. When bit 7 is 1, indirect addressing is used, otherwise direct addressing is used. Status Word format The status register doest not exist as a distinct register. It is the contents of several groups of indicators that are all stored in the J register when desired. The JPS and Int bits hold the current field contents that would be used during a JPS instruction or interrupt. The flag and overflow bits can be set explicitly from the J register contents with the RFOV instruction, but the other bits must be set by distinct instructions. Subroutines The ND812 processor provides a simple stack for operands, but doesn't use this mechanism for storing subroutine return addresses. Instead, the return address is stored in the target of the JPS instruction and then the PC register is updated to point to the location following the stored return address. To return from the subroutine, an indirect jump through the initial location of the subroutine restores the program counter to the instruction following the JPS instruction. Instruction set Memory reference instructions Logical operations Arithmetic operations on accumulators Shift/rotate instructions Load and exchange operations Conditional skips Clear, complement, increment and set Overflow bit instructions Flag bit instructions Increment and negate Interrupt instructions Powerfail logic instructions Literal instructions INT and JPS register instructions Teletype system High-Speed paper tape Magnetic cassette tape system Miscellaneous instructions References External links ND812 Brochure Principles of Programming the ND812 Computer, 1971