of four character times. If an RQ character is received, then the transmitter will start a BQ-cycle in response, send an RQ character and repeat the last three characters sent. This phase of operation is called cycling as the same four characters will be recycled. Hopefully the receiver will have good reception of these and then forward them. If not the RQ will re sent again and repetition attempted. Standards ARQ-M is recommended by CCIR 342-2 (now called ITU-R F.342-2) and earlier CCIR 242. ARQ-M was standardised by the Comité consultatif international pour la radio. The XII Plenary session in New Delhi in 1970 approved recommendation 342-2 Automatic error-correcting system for telegraph signals transmitted over radio circuits. The CCITT produced recommendation S.13 Use on radio circuits of 7-unit synchronous systems giving error correction by automatic repetition. The earlier Recommendation 242 is not compatible with F.342-2. This had an equivalent CCIT document approved in 1956 at Geneva C.24. Alternative names for ARQ-M are TDM, TDM-242, TDM-342 or 96-TDM. ARQ-M2 is also known as TDM-2, or ARQ-28, and the ARQ-M4 variant is known as TDM-4, or ARQ-56. Equipment Companies that manufactured equipment for this system were found in Germany, Japan, Netherlands, Switzerland, and USA. The companies include RCA, the Marconi HU121, and the Electra Mux. Hasler from Berne in Switzerland made a four channel TOR (Telex on Radio) system. RCA called their equipment RCA Electronic Multiplex. Siemens AG made an ARQ terminal in 1956 called Multiplex-Funkfernschreibanlage MUX 4D 7a, and later a two channel ARQ terminal called the Elmux 1000. The equipment for the ARQ-M systems contained a receive side and a transmit side. Each channel also had supporting circuitry for channel A and B, and C and D if present. Each subchannel also had supporting circuitry controlled by a channel divider. The channel divider has output control lines for each subchannel A1 A2 A3 A4 B1 ... for both receive and transmit sides. The signals from the divider outputs are combined with and-gates in the subchannel circuitry. Each subchannel on the send section side includes a serial to parallel converter, and a tripping pulse that clocks in the next character. On the receive section side and output buffer is driven by the and-gate that picks the channel receive character selected by the channel divider signal at the appropriate time. On the send section the channel circuit includes a delay line feeding