Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was launched on January 9, 2012. GCN is a reduced instruction set SIMD microarchitecture contrasting the very long instruction word SIMD architecture of TeraScale. GCN requires considerably more transistors than TeraScale, but offers advantages for general-purpose GPU (GPGPU) computation due to a simpler compiler. GCN graphics chips were fabricated with CMOS at 28 nm, and with FinFET at 14 nm (by Samsung Electronics and GlobalFoundries) and 7 nm (by TSMC), available on selected models in AMD's Radeon HD 7000, HD 8000, 200, 300, 400, 500 and Vega series of graphics cards, including the separately released Radeon VII. GCN was also used in the graphics portion of Accelerated Processing Units (APUs), such as those in the PlayStation 4 and Xbox One. Instruction set The GCN instruction set is owned by AMD and was developed specifically for GPUs. It has no micro-operation for division. Documentation is available for: the Graphics Core Next 1 instruction set, the Graphics Core Next 2 instruction set, the Graphics Core Next 3 and 4 instruction sets, the Graphics Core Next 5 instruction set, and the "Vega" 7nm instruction set architecture (also referred to as Graphics Core Next 5.1). An LLVM compiler back end is available for the GCN instruction set. It is used by Mesa 3D. GNU Compiler Collection 9 supports GCN 3 and GCN 5 since 2019 for single-threaded, stand-alone programs, with GCC 10 also offloading via OpenMP and OpenACC. MIAOW is an open-source RTL implementation of the AMD Southern Islands GPGPU microarchitecture. In November 2015, AMD announced its Boltzmann Initiative, which aims to enable the porting of CUDA-based applications to a common C++ programming model. At the Super Computing 15 event, AMD displayed a Heterogeneous Compute Compiler (HCC), a headless Linux driver and HSA runtime infrastructure for cluster-class high-performance computing, and a Heterogeneous-compute Interface for Portability (HIP) tool for porting CUDA applications to the aforementioned common C++ model. Microarchitectures As of July 2017, the Graphics Core Next instruction set has seen five iterations. The differences between the first four generations are rather minimal, but the fifth-generation GCN architecture features heavily modified stream processors to improve performance and support the simultaneous processing of two lower-precision numbers in place of