Engine is the Graphics Command Processor, the 8 ACEs, the L2 cache and memory controllers as well as the audio and video accelerators, the display controllers, the 2 DMA controllers and the PCIe interface. The A10-7850K "Kaveri" contains 8 CUs (compute units) and 8 Asynchronous Compute Engines for independent scheduling and work item dispatching. At AMD Developer Summit (APU) in November 2013 Michael Mantor presented the Radeon R9 290X. Chips Discrete GPUs (Sea Islands family): Bonaire Hawaii integrated into APUs: Temash Kabini Liverpool (i.e. the APU found in the PlayStation 4) Durango (i.e. the APU found in the Xbox One and Xbox One S) Kaveri Godavari Mullins Beema Carrizo-L Graphics Core Next 3 GCN 3rd generation was introduced in 2014 with the Radeon R9 285 and R9 M295X, which have the "Tonga" GPU. It features improved tessellation performance, lossless delta color compression to reduce memory bandwidth usage, an updated and more efficient instruction set, a new high quality scaler for video, and a new multimedia engine (video encoder/decoder). Delta color compression is supported in Mesa. However, its double precision performance is worse compared to previous generation. Chips discrete GPUs: Tonga (Volcanic Islands family), comes with UVD 5.0 (Unified Video Decoder) Fiji (Pirate Islands family), comes with UVD 6.0 and High Bandwidth Memory (HBM 1) integrated into APUs: Carrizo, comes with UVD 6.0 Bristol Ridge Stoney Ridge Graphics Core Next 4 GPUs of the Arctic Islands-family were introduced in Q2 of 2016 with the AMD Radeon 400 series. The 3D-engine (i.e. GCA (Graphics and Compute array) or GFX) is identical to that found in the Tonga-chips. But Polaris feature a newer Display Controller engine, UVD version 6.3, etc. All Polaris-based chips other than the Polaris 30 are produced on the 14 nm FinFET process, developed by Samsung Electronics and licensed to GlobalFoundries. The slightly newer refreshed Polaris 30 is built on the 12 nm LP FinFET process node, developed by Samsung and GlobalFoundries. The fourth generation GCN instruction set architecture is compatible with the third generation. It is an optimization for 14 nm FinFET process enabling higher GPU clock speeds than with the 3rd GCN generation. Architectural improvements include new hardware schedulers, a new primitive discard accelerator, a new display controller, and an updated UVD that can decode HEVC at 4K resolutions at 60 frames per second with 10 bits per color channel. Chips discrete GPUs: Polaris 10 (also codenamed Ellesmere)