16-lane integer and floating point vector Arithmetic Logic Unit (ALU) 64 KiB Vector General Purpose Register (VGPR) file A 48-bit Program Counter Instruction buffer for 10 wavefronts (each wavefront is a group of 64 threads, or the size of one logical VGPR) A 64-thread wavefront issues to a 16-lane SIMD Unit over four cycles Each SIMD-VU has 10 wavefront instruction buffers, and it takes 4 cycles to execute one wavefront. Audio and video acceleration blocks Many implementations of GCN are typically accompanied by several of AMD's other ASIC blocks. Including but not limited to the Unified Video Decoder, Video Coding Engine, and AMD TrueAudio. Video Coding Engine The Video Coding Engine is a video encoding ASIC, first introduced with the Radeon HD 7000 Series. The initial version of the VCE added support for encoding I and P frames H.264 in the YUV420 pixel format, along with SVE temporal encode and Display Encode Mode, while the second version added B-frame support for YUV420 and YUV444 I-frames. VCE 3.0 formed a part of the third generation of GCN, adding high-quality video scaling and the HEVC (H.265) codec. VCE 4.0 was part of the Vega architecture, and was subsequently succeeded by Video Core Next. TrueAudio Unified virtual memory In a preview in 2011, AnandTech wrote about the unified virtual memory, supported by Graphics Core Next. Heterogeneous System Architecture (HSA) Some of the specific HSA features implemented in the hardware need support from the operating system's kernel (its subsystems) and/or from specific device drivers. For example, in July 2014, AMD published a set of 83 patches to be merged into Linux kernel mainline 3.17 for supporting their Graphics Core Next-based Radeon graphics cards. The so-called HSA kernel driver resides in the directory , while the DRM graphics device drivers reside in and augment the already existing DRM drivers for Radeon cards. This very first implementation focuses on a single "Kaveri" APU and works alongside the existing Radeon kernel graphics driver (kgd). Lossless Delta Color Compression Hardware schedulers Hardware schedulers are used to perform scheduling and offload the assignment of compute queues to the ACEs from the driver to hardware, by buffering these queues until there is at least one empty queue in at least one ACE. This causes the HWS to immediately assign buffered queues to the ACEs until all queues are full or there are no more queues to safely assign. Part of