BACKGROUND OF THE INVENTION 
   The present invention relates to a step-up converter based on an integrated transformer. More particularly, the invention relates to a step-up converter based on an integrated transformer that can be used as an alternative or a complement to conventional capacitive charge pump circuits. 
   In many fields of integrated electronics, as in the case of memory integration, some fundamental operations cannot be performed by applying only the low voltages of the power supply: one example is given by the write and delete operations of Flash and EEPROM memories. This aspect becomes more important in the field of microcontrollers with integrated Flash memories, where increasingly extreme scaling of the supply voltages contrasts with a substantial stability of the voltage levels required for programming. The task of capacitive charge pumps is therefore to generate voltage values higher than the power supply by using capacitors as storage systems in which the charge that will accumulate toward the output is made to pass. One of the most significant parameters for describing the performance of a charge pump is its efficiency, whose maximization has been the focus of the efforts made in recent years to improve known voltage booster architectures. 
   One characteristic that is common to all charge pumps is that it is impossible to achieve a complete charge transfer from one stage to the next, due to the loss of a threshold voltage of each one of the MOS used as diodes or due to the excessive channel resistance of the pass transistors. In particular, when the transistors are connected as diodes, the asymptotic charging level reached between one stage and the next is equal to the supply voltage minus a threshold V T , which becomes increasingly important as one approaches the last stages of the pump, where the body effect becomes predominant. 
   In the current background art, the charge pumps most frequently used to generate the high voltage levels required for the operation of non-volatile memories are based on control systems with four phases without voltage boosting. One rather valid architecture is also the one that uses a simple system with two phases, assisted by an operating frequency that is higher than the ones normally used. 
   The typical diagram of a four-phase NMOS charge pump is shown in  FIG. 1 , which shows generic stages. In addition to the gate precharge circuits, there are often branches for precharging to V dd  for the intermediate nodes of the pump. 
   Each stage is composed of a boost capacitor C(k) and by a pass transistor M(k); the figure also shows a switch M′(k), whose purpose is to precharge the node PRE(k) and the four phases A, B, C and D, whose timing is shown in  FIG. 2 . Both the boost phases B and D and the control phases A and C vary between 0 and V dd . When B goes high, the phase D has not yet reached 0 and the transistor M′(k) remains on, allowing to precharge the mode PRE(k) up to the potential value of the node k. Then C switches, and D reaches the low logic value, switches off M′(k) and allows the isolation of the node PRE(k). The phase C provides a miniboost effect on the gate of the transistor M(k), switching it on and partly limiting the problems linked to threshold voltage loss. 
   The packet of charge is transferred from the capacitor C(k) to the capacitor of the next stage C(k+1). When C and D switch again, the pass transistor opens and the node PRE(k) returns to the potential of the node k by virtue of M′(k) as soon as B has returned to the low value. In order to minimize the problems introduced by the body effect on the increase in the threshold voltages, suitable circuits for biasing the NMOS that provide the pass transistors are used, utilizing a partitioned version of the output voltage of the pump. 
   The architecture with two phases with voltage boost of the controls and low-voltage transistors is based on the use of low-voltage transistors for the execution of the individual stages and furthermore utilizes higher operating frequencies than used in conventional solutions (100 MHz instead of 10–20 MHz). The output resistance of a capacitive charge pump can in fact be reduced by increasing the operating frequency and by using MOS transistors with a low threshold to speed up the charge transfer operations. However, this type of approach forces the use of low-voltage transistors, which due to problems linked to possible oxide punch-through cannot withstand at their terminals voltages higher than the power supply. The single stage and a general diagram of a three-stage charge pump are shown in  FIGS. 3 and 4 . Each stage allows to obtain, in theory, a gain equal to the supply voltage, is provided without resorting to high-voltage MOS and is driven by two phases which must be perfectly nonoverlapping. 
   After an initial transient, a stationary situation is established. During the first half-cycle, ck=V dd , ck_neg=0, M 0  and M 6  are on, M 1  and M 5  are off; C 1  is charged to Vlow and Vhigh is charged to the value stored in C 0  (i.e., Vlow) plus V dd . During the second half of the cycle, ck=0, ck_neg=V dd , M 0  and M 6  are off, M 1  and M 5  are on; C 0  is charged to Vlow and Vhigh is charged to Vlow+V dd . In this manner, a gain in voltage between Vlow and Vhigh is achieved whose ideal value is V dd  and can be approximated, ignoring losses due to an insufficiently high overdrive, as: 
             Δ   ⁢           ⁢   v     =         V   dd     ·     C     C   +     C   par           -       R   out     ·     I   out                       R   out     =       1     f   ·   C       +     R   switch             
where C=C 0 =C 1 ; Cpar indicates the parasitic capacitances of the internal nodes of the individual stage, Rout is the output resistance of the charge pump, and Rswitch is the channel resistance of each MOS.
 
   If n stages are cascade-connected, one obtains:
 
 V   out   =V   dd   +n·Δv  
 
The main cause of power dissipation is constituted by the driving stages that lie downstream of the clocks. The formula used to calculate the efficiency is given hereafter:
 
   
     
       
         
           η 
           = 
           
             
               100 
               ⁢ 
               
                 % 
                 · 
                 
                   
                     P 
                     out 
                   
                   
                     P 
                     in 
                   
                 
               
             
             = 
             
               100 
               ⁢ 
               
                 % 
                 · 
                 
                   
                     
                       V 
                       out 
                     
                     · 
                     
                       I 
                       out 
                     
                   
                   
                     
                       V 
                       dd 
                     
                     · 
                     
                       
                         I 
                         _ 
                       
                       ⁡ 
                       
                         ( 
                         
                           V 
                           dd 
                         
                         ) 
                       
                     
                   
                 
               
             
           
         
       
     
   
   where I(V dd ) and V out  are the average values of I(V dd ) and V out . 
   A series of measurements was taken on 3- and 5-stage pumps implemented in 0.18-μm technology (6 levels of metal) with NMOS in triple well and supply voltages between 1.6 and 2V as the current drawn at the output and the frequency of the two phases varied. The results have shown a bell-curve behavior of the efficiency as the output current varies, with a peak around 350 μA. Other advantages of the high frequencies used are a rather short rise time and a reduction in the ripple on the output voltage. 
   The drawbacks of conventional capacitive charge pump circuits are high chip area occupation, long output rise time, and the lack of the possibility to adjust the output voltage of said circuit. 
   SUMMARY OF THE INVENTION 
   The aim of the present invention is to provide a step-up converter based on an integrated transformer that can be used as an alternative or complement to conventional capacitive charge pump circuits. 
   Within this aim, an object of the present invention is to provide a step-up converter based on an integrated transformer that allows to achieve an area reduction with respect to known types of circuit. 
   Another object of the present invention is to provide a step-up converter based on an integrated transformer that has a shorter output rise time than known types of circuit. 
   Another object of the present invention is to provide a step-up converter based on integrated transformer that allows to have output voltage adjustment. 
   Another object of the present invention is to provide a step-up converter based on an integrated transformer that is highly reliable, relatively simple to provide and at competitive costs. 
   This aim and these and other objects that will become better apparent hereinafter are achieved by a step-up converter based on an integrated transformer, comprising a self-resonating oscillator circuit that has inductive elements constituted by primary and secondary windings of at least one first transformer, said self-resonating oscillator circuit being powered by an external supply voltage. 


   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further characteristics and advantages of the invention will become better apparent from the description of preferred but not exclusive embodiments of the converter according to the present invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: 
       FIG. 1  is a view of generic stages of a known type of four-phase charge pump circuit; 
       FIG. 2  is a view of the timing of the four-phase charge pump circuit of  FIG. 1 ; 
       FIG. 3  is the diagram of a stage of a known type of two-phase charge pump circuit; 
       FIG. 4  is a diagram of a known type of three-stage two-phase charge pump circuit; 
       FIG. 5  is a diagram of a known type of LC oscillator; 
       FIG. 6  is a schematic view of the step-up converter according to a first embodiment of the present invention; 
       FIG. 7  is a schematic view of a second embodiment of the step-up converter according to the present invention; 
       FIG. 8  is a schematic view of a voltage multiplier used in the step-up converter of  FIG. 7 ; and 
       FIG. 9  is a view of the circuit model of the transformer used in the converters shown in  FIGS. 6 and 7 . 
   


   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   With reference to the cited figures, and particularly with reference to  FIGS. 6 to 9 , the step-up converter according to a first embodiment is shown in  FIG. 6 . 
   The step-up converter according to the first embodiment adopts an LC sinusoidal oscillator with negative differential resistance, as shown in  FIG. 5 , widely used in integrated RF technologies. 
   The availability of a sinusoidal source allows to utilize to the fullest extent the frequency response characteristics of the integrated transformer, which has a voltage gain peak proximate to the resonance frequency. 
   In the circuit shown in  FIG. 6 , the inductors of the LC oscillator, designated by L in  FIG. 5 , are replaced with primary windings P 1  and P 2  of two integrated transformers  10  and  11 , whose secondary windings S 1  and S 2  are connected as described hereinafter. 
   The primary windings of the transformers  10  and  11 , designated by P 1  and P 2 , are respectively connected to the supply voltage V dd  as regards the primary windings P 1  and to MOS transistors M 1  and M 2  respectively for the primary winding P 2  of the transformer  10  and the primary winding P 2  of the transformer  11 . 
   The gate terminals of the MOS transistors M 1  and M 2  are conveniently connected to the primary winding P 2  of the transformer that is opposite to the one to which the MOS transistors M 1  and M 2  are respectively connected. 
   A third MOS transistor M 3  is connected by means of its drain terminal to the source terminals of the MOS transistors M 1  and M 2 . Said MOS transistors M 1  and M 2 , together with the MOS transistor M 3 , have their body terminals connected to the ground. In the case of triple-well MOS transistors M 1  and M 2 , the bulk terminals can be connected to the source in order to limit the body effect. 
   The gate terminal of the transistor M 3  instead receives a control voltage Vc. 
   The reference numeral  12  in  FIG. 6  designates a load of the resistive-capacitive type driven by the step-up converter. 
   Diodes D 1  and D 2 , connected in series to the secondary winding S 2  of the transformer  10  and connected to the secondary winding S 1  of the transformer  11 , together with the capacitor C connected between the gate terminal and the drain terminal of the MOS transistors M 1  and M 2  and the line that connects the secondary winding respectively S 1  of the transformer  11  and the cathode of D 1  are meant to increase the voltage on the cathode of the diode D 1  in order to improve the performance of the converter. 
   An additional diode D 3  is interposed between the secondary winding S 2  of the transformer  11  and the load  12  driven by the step-up converter according to the invention. 
   The converter is self-resonating, since the oscillation that is established is due entirely to the inductive and capacitive (parasitic) effects of the transformers, without the need for additional reactive components. The advantage of self-resonance is that frequency tuning is not necessary and compensations of any process variations are not necessary. 
   The step-up converter has an efficiency, including all losses including the oscillator, of 16.2% with an output at 10 V, without any need for a clock signal. 
   The efficiency was determined as a ratio between the power supplied to the load  12  and the power delivered by the supply (product of the supply voltage and the average current absorbed by the converter). 
   The main advantage of the proposed solution is the occupation of area, with an extremely great reduction with respect to the voltage boosters currently in use. 
   The second embodiment of the step-up converter according to the present invention is instead shown in  FIG. 7 , and in this case the LC oscillator uses, as inductive elements, the primary and secondary windings of a single transformer  15 , designated by a different reference numeral than the transformers  10  and  11  described earlier but executed in a similar manner. The resulting sinusoidal voltage is amplified by a conventional voltage multiplier  16  (charge pump) with diodes and capacitors, as shown in  FIG. 8 , with diodes D and capacitors C. Essentially, in the second embodiment of the invention the transformer  15  is connected by means of the secondary winding S 1  to the drain terminal of the MOS transistor M 2 , by means of the primary winding P 1  to the secondary winding S 2  and to the power supply terminal V dd , and by means of the primary winding P 2  to the drain terminal of the transistor M 1 . 
   Both embodiments require from outside only the supply voltage V dd  and can provide an oscillator control pin Vc, in order to switch on and off the converter in order to adjust the output voltage by analog means (for example in order to maintain a stable output voltage as the load conditions vary). 
     FIG. 9  is a schematic view of the circuit model of the transformer  10  and  11  and also of the transformer  15  used in the first and second embodiments of the converter according to the present invention. P 1 , P 2  and S 1  and S 2  designate respectively the terminals of the primary and secondary windings of the transformer. 
   The model of the transformer is constituted by three mutually identical stages. 
   Essentially, the step-up converter according to the present invention, both in the first embodiment and in the second embodiment, allows a reduction in the area occupied on the chip with respect to voltage boosters of the known type and also allows to have a shorter output voltage rise time than known types of circuit, for an equal driven equivalent load. 
   Moreover, both of the illustrated embodiments provide an oscillator control pin for switching on and off the converter and for adjusting the output voltage by analog means. 
   In practice it has been found that the step-up converter according to the present invention fully achieves the intended aim and objects. 
   The converter according to the invention is susceptible of numerous modifications and variations, all of which are within the scope of the appended claims; all the details may further be replaced with other technically equivalent elements.
A step-up converter based on an integrated transformer, comprising a self-resonating oscillator circuit that has inductive elements constituted by primary and secondary windings of at least one first transformer, the self-resonating oscillator circuit being powered by an external supply voltage.