CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a Continuation Application of U.S. patent application Ser. No. 12/285,089 which was filed on Sep. 29, 2008, and is incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to constant current source circuits that are used in integrated circuits and are produced by way of CMOS integrated circuit technologies. 
         [0004]    The present application claims priority on Japanese Patent Application No. 2007-258529, the content of which is incorporated herein by reference. 
         [0005]    2. Description of Related Art 
         [0006]    It becomes difficult for engineers to determine lower limits for operation voltages of analog circuits due to demands for reducing operation voltages of LSI (Large Scale Integration) circuits used in electronic devices having reduced power consumptions. 
         [0007]    This is greatly affected by the fact in which threshold voltages Vt for MOS (Metal Oxide Semiconductor) transistors will not be subjected to scaling relative to reductions of operation voltages. 
         [0008]    For example, when the minimum output voltage of a constant current source is to be reduced, it is necessary to reduce the threshold voltage Vt of a MOS transistor in response to a reduction of the operation voltage. 
         [0009]    However, there is a limit in reducing the threshold voltage Vt due to an increase of a leak current. 
         [0010]    When low currents flow through MOS transistors each having a very large area so as to secure certain voltage margins by reducing voltages applied thereto, the manufacturing cost may be pushed up so as to cause demerits economically. 
         [0011]    Various types of LSI circuits essentially incorporate constant current source circuits which have low current reductions in case of low voltages and which can stabilize currents in a relatively broad range of voltages. 
         [0012]    Various types of constant current source circuits have been developed and disclosed in various documents such as Patent Document 1 and Patent Document 2.
   Patent Document 1: Japanese Unexamined Patent Application Publication No. H04-160511   Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-330657   
 
         [0015]    As a first example of the circuitry (serving as a constant current source circuit),  FIG. 13  shows a current mirror circuit, wherein a reference current I 0  flows through an n-channel MOS transistor M 100  subjected to diode connection in which the same potential is applied to the gate and drain, hence, V GS0 =V DS0 . 
         [0016]    A MOS transistor M 101  is used as the output of the constant current source circuit, wherein when the gate voltage V GS0  is identical to the drain voltage V DS0 , the same operation condition is applied to both of the transistors M 100  and M 101 . When they have the same dimensions regarding the factor L/W (where L designates the channel length, and W designates the channel width), an output current I 1  becomes identical to the reference current I 0  (see Patent Document 1). 
         [0017]    When an output voltage V OUT  becomes higher than the gate voltage V GS0 , the effective channel length may decrease due to the channel length modifying effect of the transistor while the drain voltage of the transistor M 101  increases, wherein the output current I 1  increases relative to the reference current I 0  so that I 1 &gt;I 0 , whereby the same current does not flow through the transistors M 100  and M 101 . 
         [0018]    In contrast, when the output voltage V OUT  becomes lower than the gate voltage V GS0 , the output current I 1  decreases so that I 1 &lt;I 0 , wherein the same current does not flow through the transistors M 100  and M 101 . 
         [0019]      FIG. 14  shows an example of I DS -V DS  characteristics of an n-channel MOS transistor (where I DS  designates a drain-source current, and V DS  designates a drain-source voltage), whereby an output resistance r OUT  of the circuitry of  FIG. 13  substantially matches a drain resistance r DS1  of the transistor M 101  when the inverse of the slope of the drain current I DS  in the saturation region is expressed as r DS =ΔV DS /ΔI DS  (where r DS  designates a drain resistance). 
         [0020]    In order to suppress variations of the output current I 1  dependent upon the output voltage V OUT , it is necessary to increase the output resistance r OUT , whereas the circuitry of  FIG. 13  suffers from a problem in that the output resistance r OUT  cannot be increased to be higher than the drain resistance r DS1 . 
         [0021]    In the case that I 0 =100 μA and r DS1 =50 kΩ, for example, current variations of 20 μA occur responsive to voltage variations of 1 V; this causes relatively high current variations of 20%/V, resulting in an incapability of supplying a constant current at a high precision. 
         [0022]    As a second example of the circuitry which is designed as the countermeasure to the circuitry of  FIG. 13  by increasing the output resistance of a constant current source,  FIG. 15  shows a cascode current mirror circuit constituted of transistors M 100 , M 101 , M 102 , and M 103  (see Patent Document 2). 
         [0023]    In the case of Patent Document 2, the gate potential of the transistor M 101  is identical to the gate potential V GS0 , while the gate potential of the transistor M 103  is identical to the gate potential V GS0 +V GS2  of the transistor M 102 . 
         [0024]    In the saturation region of the transistor M 103 , the gate-source voltage V GS3  of the transistor M 103  is identical to the gate-source voltage V GS2  of the transistor M 102 ; hence, the drain potential of the transistor M 101  becomes identical to the gate-source voltage V GS0  of the MOS transistor M 100 . 
         [0025]    Since potential variations of the output terminal do not affect the drain voltage of the transistor M 101 , it is possible to increase the output resistance r OUT , thus stabilizing the output current. 
         [0026]    By use of the drain resistance r DS3  and the mutual conductance gm3 of the transistor M 103 , gate-source voltage variations ΔV GS3  of the transistor M 103  dependent upon output voltage variations ΔV OUT  is expressed as follows: 
         [0000]    
       
         
           
             
               Δ 
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                 V 
                 
                   GS 
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                   3 
                 
               
             
             = 
             
               
                 Δ 
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                  
                 
                   V 
                   OUT 
                 
               
               
                 gm 
                  
                 
                     
                 
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                   3 
                   · 
                   
                     r 
                     
                       DS 
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                       3 
                     
                   
                 
               
             
           
         
       
     
         [0027]    In the case that gm3=1 ms and r DS3 =50 kΩ, for example, the above equation can be rewritten as ΔV GS3 =ΔV OUT /50. This indicates that potential variations of the output terminal may affect the drain potential of the MOS transistor M 100  by 1/50 of the actual variations. 
         [0028]    The output resistance r OUT  of the circuitry of  FIG. 15  is expressed as follows: 
         [0000]        r   OUT =( gm 3 ·r   DS3 )· r   DS1  
 
         [0029]    Compared with the circuitry of  FIG. 13 , the circuitry of  FIG. 15  provides (gm3·r DS3 ) times higher output resistance. In the case that I 0 =100 μA, r DS1 =r DS3 =50 kΩ, and gm3=1 mS, for example, the above equation produces r OUT =2.5 MΩ, wherein potential variations of 1 V may result in current variations of 0.4 μA; hence, output current variations can be suppressed as 0.4%/V. 
         [0030]    However, the present inventor has recognized that, in the constant current source circuit disclosed in Patent Document 2, due to the relatively high gate potential V GS0 +V GS2  of the transistor M 103 , the transistor M 103  produces the minimum value of the output voltage, i.e. V OUT (min), during the operation in the saturation region. 
         [0000]        V   OUT (min)≧ V   GS0   +V   GS2   −V   T3  
 
         [0031]    This reduces the range of operation voltage of the transistor M 103  by V GS2 . 
         [0032]    To cope with such a problem, as a further example of the constant current source circuit (having intermediate characteristics between the characteristics of Patent Document 1 and the characteristics of Patent Document 2),  FIG. 16  shows a cascode current mirror circuit for use at a low voltage. 
         [0033]    In the circuitry of  FIG. 16  constituted of the four transistors M 100  to M 103 , each of the drain voltages of the transistors M 100  and M 101  is expressed as V DS0 =Vncas−V GS2  or V DS1 =Vncas−V GS3  (where Vncas is a gate potential). 
         [0034]    In the above, the drain voltages V DS0  and V DS1  are reduced by adjusting the gate potential Vncas with respect to the transistors M 102  and M 103 , thus decreasing the lower limit of the operation voltage in a similar manner to the circuitry of  FIG. 15 . 
         [0035]    Since both the drain voltages V DS0  and V DS1  are relatively low, both transistors M 100  and M 101  do not operate in the saturation region but in the linear region, wherein the characteristics thereof may be similar to resistance characteristics. 
         [0036]    Since the drain voltages of the transistors M 100  and M 101  are maintained constant by way of the transistors M 102  and M 103 , the circuitry of  FIG. 16  is capable of operating as the constant current source. 
         [0037]    The output resistance r OUT  of the circuitry of  FIG. 16  is identical to that of the circuitry of  FIG. 15 , where r OUT =(gm3·r DS3 )·r DS1 . 
         [0038]    Compared with the circuitry of  FIG. 15 , the drain resistance r DS1  has a lower value in the circuitry of  FIG. 16  that operates in the linear region. In the case that the current of 100 μA in which the gate potential Vncas is adjusted to achieve V DS1 =200 mV, it is possible to calculate the drain resistance r DS1  by the following equation based on the approximation that the transistor M 101  has a linear resistance. 
         [0000]    
       
         
           
             
               r 
               
                 DS 
                  
                 
                     
                 
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                 1 
               
             
             = 
             
               
                 
                   200 
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                    
                   m 
                    
                   
                       
                   
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                   V 
                 
                 
                   100 
                    
                   μ 
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                   A 
                 
               
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                 2 
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                 k 
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                  
                 Ω 
               
             
           
         
       
     
         [0039]    In the case that r DS3 =50 kΩ and gm3=1 mS (in a similar manner to the circuitry of  FIG. 15 ), r OUT =100 kΩ, wherein current variations of 10 μA occur responsive to potential variations of 1 V; hence, it is possible to suppress output current variations by 10%/V. 
         [0040]    The aforementioned calculations indicate that when the gate potential Vncas is intentionally reduced with respect to the transistors M 102  and M 103  in order to increase the lower-limit range of the operation voltage, the drain voltage V DS1  becomes low so that the drain resistance r DS1  correspondingly becomes low, thus reducing the output resistance r OUT . 
         [0041]    In order to obtain the cascode effect in the aforementioned circuitries, it is necessary to establish a balance between the operation voltage and the output resistance by increasing the drain voltage V DS1 . 
         [0042]    In the case of the low-voltage cascode configuration, engineers cannot neglect a problem in that the range of the operation voltage is inevitably reduced by V DS1 . 
       SUMMARY 
       [0043]    The invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. 
         [0044]    In one embodiment, there is provided a constant current source circuit that includes a control voltage generation section for detecting the output voltage at the output terminal and for generating a control voltage based on the detected output voltage, a reference current adjustment section for adjusting a reference current based on the control voltage, and a current mirror section for outputting an output current responsive to the adjusted reference current at the output terminal. 
         [0045]    In another embodiment, there is provided a constant current source circuit that includes a reference current adjustment section for adjusting a reference current based on the output voltage at the output terminal, and a current mirror section for outputting the output current in response to the adjusted reference current. 
         [0046]    In the above, since the constant current source circuit of the present invention controls the reference current to be constant so as to reduce an influence of the output voltage to the output current at the output terminal, it is possible to reduce variations of the output current due to variations of the output voltage. Thus, the constant current source circuit is capable of supplying substantially the “constant” output current in the low-voltage range. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0047]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0048]      FIG. 1  is a block diagram showing the constitution of a constant current source circuit according to a first embodiment of the present invention; 
           [0049]      FIG. 2  is a circuit diagram showing the detailed constitution of the constant current source circuit of  FIG. 1 ; 
           [0050]      FIG. 3  is a graph showing potential variations of nodes dependent upon variations of output voltage in the constant current source circuit; 
           [0051]      FIG. 4  is a graph showing the relationship between the output voltage and the output current in connection with constant current source circuits of first and second embodiments; 
           [0052]      FIG. 5  is a circuit diagram showing the constitution of a constant current source circuit according to a second embodiment of the present invention; 
           [0053]      FIG. 6  is a circuit diagram showing the constitution of a constant current source circuit according to a third embodiment of the present invention; 
           [0054]      FIG. 7  is a graph showing potential variations of nodes dependent upon variations of output voltage in the constant current source circuit of the third embodiment; 
           [0055]      FIG. 8  is a graph showing the relationship between the output voltage and the output current in the constant current source circuit of the third embodiment; 
           [0056]      FIG. 9  is a circuit diagram showing the constitution of a constant current source circuit according to a fourth embodiment of the present invention; 
           [0057]      FIG. 10  is a circuit diagram showing the constitution of a constant current source circuit according to a fifth embodiment of the present invention; 
           [0058]      FIG. 11  is a circuit diagram showing the constitution of a constant current source circuit according to a sixth embodiment of the present invention; 
           [0059]      FIG. 12  is a circuit diagram showing the constitution of a constant current source circuit according to a seventh embodiment of the present invention; 
           [0060]      FIG. 13  is a circuit diagram showing one example of the constant current source circuit adapted to a current mirror circuit; 
           [0061]      FIG. 14  is a graph showing current-voltage characteristics of an n-channel MOS transistor; 
           [0062]      FIG. 15  is a circuit diagram showing another example of the constant current source circuit adapted to a cascode current mirror circuit; and 
           [0063]      FIG. 16  is a circuit diagram showing a further example of the constant current source circuit adapted to a cascode current mirror circuit for low voltage. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0064]    The present invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       1. First Embodiment 
       [0065]    Referring now to  FIG. 1 , a constant current source circuit according to a first embodiment of the present invention includes a bias generation section  1 , a reference current adjustment section  2 , a control voltage generation section  3 , and a current mirror section  4 . 
         [0066]    Based on a reference current I 0  caused by a constant current source  100 , the bias generation section  1  generates a first bias voltage pbias and a second bias voltage pcas for use in the reference current adjustment section  2  as well as a third bias voltage ncas for use in the current mirror section  4 . 
         [0067]    The output voltage of an output terminal TOUT is applied to the control voltage generation section  3 . The control voltage generation section  3  generates a control voltage oshift, which is produced by shifting a prescribed voltage from the output voltage. It outputs the control voltage oshift to the reference current adjustment section  2 . 
         [0068]    The reference current adjustment section  2  is constituted of p-channel MOS transistors M 1 , M 2 , and M 3 , which generates a current Im that is adjusted in response to the output voltage based on the first bias voltage pbias, the second bias voltage pcas, and the control voltage oshift. 
         [0069]    The current mirror section  4  is a cascode current mirror circuit and is constituted of n-channel MOS transistors M 4 , M 5 , and M 6 A. It outputs a constant current I 1  to the output terminal TOUT based on the current Im output from the reference current adjustment section  2 . 
         [0070]    Next, the detailed constitution of the constant current source circuit of  FIG. 1  will be described with reference to  FIG. 2 .  FIG. 2  is a circuit diagram showing the detailed constitution of the constant current source circuit of  FIG. 1 . 
         [0071]    The bias generation section  1  is constituted of p-channel MOS transistors M 10 , M 11 , and M 12  and n-channel MOS transistors M 13  and M 14 . The source of the transistor M 10  is connected to a voltage supply, while the gate and the drain of the transistor M 10  are connected together. 
         [0072]    The source of the transistor M 11  is connected to the drain and gate of the transistor M 10 , while the gate and drain of the transistor M 11  are grounded via the constant current source  100 . 
         [0073]    The source of the transistor M 12  is connected to the voltage supply, while the gate of the transistor M 12  is connected to the gate and drain of the transistor M 10 . 
         [0074]    The drain and gate of the transistor M 13  are connected to the drain of the transistor M 12 . 
         [0075]    The drain and gate of the transistor M 14  are connected to the source of the transistor M 13 . 
         [0076]    In the above constitution, the drain of the transistor M 10  outputs the first bias voltage pbias to the transistor M 1 , which is a p-channel MOS transistor serving as a constant current source transistor of a cascode current mirror circuit. 
         [0077]    The drain of the transistor M 11  outputs the second bias voltage pcas to the transistor M 3 , which is a p-channel MOS transistor serving as a cascode transistor of the current mirror circuit. 
         [0078]    The drain of the transistor M 13  outputs the third bias voltage ncas to the transistor M 5 , which is an n-channel MOS transistor serving as an n-channel cascode transistor of the current mirror circuit. 
         [0079]    The control voltage generation section  3  is constituted of a p-channel MOS transistor M 7  and n-channel MOS transistors M 8  and M 9 . 
         [0080]    The source of the transistor M 7  is connected to the voltage supply, while the gate of the transistor M 7  is connected to the gate and drain of the transistor M 10 . 
         [0081]    The drain of the transistor M 8  is connected to the drain of the transistor M 7 , while the gate of the transistor M 8  is connected to the output terminal TOUT. 
         [0082]    The drain of the transistor M 9  is connected to the source of the transistor M 8 , the source of the transistor M 9  is grounded, and the gate of the transistor M 9  is supplied with an internal bias voltage mbias of the “cascode” current mirror section  4 . 
         [0083]    The source of the transistor M 8  outputs the control voltage oshift as a gate bias to the gate of the transistor M 2  in the reference current adjustment section  2 . 
         [0084]    As described above, the reference current adjustment section  2  is constituted of the transistors M 1 , M 2 , and M 3 . 
         [0085]    The source of the transistor M 1  is connected to the voltage supply, while the gate of the transistor M 1  is connected to the gate and drain of the transistor M 10  so as to receive the first bias voltage pbias. 
         [0086]    The source of the transistor M 2  is connected to the drain of the transistor M 1 , while the gate of the transistor M 2  is connected to the source of the transistor M 8  so as to receive the control voltage oshift. 
         [0087]    The source of the transistor M 3  is connected to the drain of the transistor M 1 , while the gate of the transistor M 3  is connected to the gate and drain of the transistor M 11  so as to receive the second bias voltage pcas. The drain of the transistor M 3  is connected to the drain of the transistor M 2 . 
         [0088]    As described above, the current mirror section  4  is constituted of the transistors M 4 , M 5 , and M 6 A. 
         [0089]    The gate and drain of the transistor M 4  are connected to the drain of the transistor M 2 , while the source of the transistor M 4  is grounded, wherein the drain of the transistor M 4  outputs the internal bias voltage mbias. In addition, the gate and drain of the transistor M 4  are connected to the gate of the transistor M 9 , which thus receives the internal bias voltage mbias. 
         [0090]    The drain of the transistor M 5  is connected to the output terminal TOUT, while the gate of the transistor M 5  is connected to the gate and drain of the transistor M 13  so as to receive the third bias voltage ncas. 
         [0091]    The drain of the transistor M 6 A is connected to the source of the transistor M 5 , while the gate of the transistor M 6 A is connected to the gate and drain of the transistor M 4  so as to receive the internal bias voltage mbias. The source of the transistor M 6 A is grounded. 
         [0092]    Next, the operation of the constant current source circuit of the first embodiment will be described with reference to  FIG. 3 .  FIG. 3  shows simulation results of the constant current source circuit of  FIG. 2 , i.e., potential variations of nodes dependent upon variations of the output voltage in which the voltage supply is set to 1.5 V. The horizontal axis of the graph of  FIG. 3  represents the potential (or output voltage) of the output terminal TOUT, and the vertical axis represents potentials of nodes in the constant current source circuit. 
         [0093]      FIG. 3  apparently shows that the transistor M 2  of the reference current adjustment section  2  is turned off when the control voltage oshift, which is produced by shifting the level of the output voltage of the output terminal TOUT in the control voltage generation section  3 , is higher than the second bias voltage pcas generated by the bias generation section  1 , wherein the potential of the drain “md” of the transistor M 1  is clamped by the transistor M 3  and therefore becomes identical to the first bias voltage pbias. 
         [0094]    Since the transistors M 1  and M 3  are coupled together to form a cascode current mirror circuit, the current Im flowing through the MOS transistor M 1  becomes identical to the reference current I 0 . 
         [0095]    In contrast, the transistor M 3  of the reference current adjustment section  2  is turned off when the control voltage oshift is lower than the second bias voltage pcas, wherein the potential of the drain md of the transistor M 1  decreases following up with variations of the control voltage oshift. 
         [0096]    That is, the transistor M 2  forms a bypass path allowing a current to pass therethrough, wherein the source-drain voltage of the transistor M 1  increases as the control voltage oshift decreases, so that the current Im flowing through the transistor M 1  becomes higher than the reference current I 0 . 
         [0097]    The dotted line vertically drawn in the center of the graph of  FIG. 3  indicates the intersection point between the second bias voltage pcas and the control voltage oshift. In  FIG. 3 , the “stable” condition in which the relationship of Im=I 0  is fixed is established in the region (where pcas≦oshift) to the right of the dotted line. 
         [0098]    In the region (where pcas&gt;oshift) to the left of the dotted line, the reference current adjustment section  2  adjusts the current Im based on the voltage difference between the first bias voltage pbias and the potential of the drain and of the transistor M 1 , thus establishing the relationship of Im&gt;I 0 . 
         [0099]    In short, the constant current source circuit of the first embodiment makes the current Im, which flows through the transistor M 1  and which is adjusted based on the output voltage of the output terminal TOUT, flow through the transistor M 4  of the current mirror section  4 , thus producing the current I 1  in response to the current Im from the output terminal TOUT. 
         [0100]      FIG. 4  is a graph showing the relationship between the output voltage at the output terminal TOUT and the output current I 1  in the constant current source circuit of the first embodiment. In  FIG. 4 , the horizontal axis represents the output voltage at the output terminal TOUT, while the vertical axis represents the output current I 1  output from the output terminal TOUT. 
         [0101]    In  FIG. 4 , a one-dashed curve C indicates the voltage-current characteristics of the first example of the circuitry (serving as the current mirror circuit) shown in  FIG. 13 , while a two-dashed curve D indicates the voltage-current characteristics of the second example of the circuitry (serving as the cascode current mirror circuit) shown in  FIG. 15 . 
         [0102]    In relation to the curves C and D, a thin curve A indicates the voltage-current characteristics of the constant current source circuit of the first embodiment shown in  FIG. 2 . 
         [0103]    In the characteristics D of the cascode current mirror circuit of  FIG. 15 , the transistor M 103  cannot operate in the saturation region below the output voltage of 0.5 V so that the output resistance decreases so as to decrease the output current I 1 . 
         [0104]    As shown in  FIG. 4 , in the constant current source circuit of the first embodiment, the transistor M 2  turns on so as to compensate for a reduction of the current Im occurring due to a reduction of the output voltage at the output terminal TOUT, wherein the current Im flowing through the transistor M 1  is increased so as to expand the operation region below the output voltage of 0.2 V or so. 
       2. Second Embodiment 
       [0105]    Next, a constant current source circuit according to a second embodiment of the present invention will be described with reference to  FIGS. 4 and 5 .  FIG. 5  is a circuit diagram showing the constitution of the constant current source circuit of the second embodiment. 
         [0106]    Similar to the first embodiment, the constant current source circuit of the second embodiment is constituted of the bias generation section  1 , the reference current adjustment section  2 , the control voltage generation section  3 , and the current mirror section  4 . 
         [0107]    In  FIG. 5 , parts identical to those of the first embodiment shown in  FIG. 2  are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the second embodiment. 
         [0108]    Based on the reference current I 0  created by the constant current source  100 , the bias generation section  1  generates and outputs the first bias voltage pbias and the second bias voltage pcas for use in the reference current adjustment section  2  as well as the third bias voltage ncas and the fourth bias voltage nbias for use in the current mirror section  4 . 
         [0109]    The fourth bias voltage nbias is output from the drain of the transistor M 14  of the bias generation section  1 . 
         [0110]    In the current mirror section  4 , a n-channel MOS transistor M 6 B is connected in parallel to the transistor M 6 A, wherein it is an additional constituent element incorporated into the second embodiment compared to the first embodiment. 
         [0111]    The drain of the transistor M 6 B is connected to the source of the transistor M 5 ; the gate of the transistor M 6 B is connected to the drain and gate of the transistor M 14  so as to receive the fourth bias voltage nbias; and the source of the transistor M 6 B is grounded. 
         [0112]    The current flowing through the transistor M 6 A has the voltage-current characteristics indicated by the thin curve A shown in  FIG. 4 . 
         [0113]    The current flowing through the transistor M 6 B has the voltage-current characteristics indicated by the two-dashed curve D (representing the cascode current mirror circuit) shown in  FIG. 4 . 
         [0114]    By appropriately adjusting the voltage-current characteristics applied to the transistors M 6 A and M 6 B, it is possible to achieve the intermediate characteristics indicated by a bold curve B between the thin curve A and the two-dashed curve D in  FIG. 4 . 
         [0115]    That is, the second embodiment of  FIG. 5  is designed to adjust the voltage-current characteristics from the thin curve A (which shows “excessive” current compensation characteristics) to the bold curve B (which shows “flat” characteristics compared to the characteristics of the thin curve A). 
       3. Third Embodiment 
       [0116]    Next, a constant current source circuit according to a third embodiment of the present invention will be described with reference to  FIGS. 6 to 8 .  FIG. 6  is a circuit diagram showing the constitution of the constant current source circuit of the third embodiment. The third embodiment is designed to apply the reference current adjustment section  2  of the first embodiment to the low-voltage cascode current mirror circuit shown in  FIG. 16 . 
         [0117]    The constant current source circuit of the third embodiment does not include the control voltage generation section  3  used in the first embodiment and is thus constituted of the bias generation section  1 , the reference current adjustment section  2 , and the current mirror section  4 . 
         [0118]    In  FIG. 6 , parts identical to those of the second embodiment shown in  FIG. 5  are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with reference to the third embodiment. 
         [0119]    Due to the absence of the control voltage generation section  3 , the gate of the transistor M 2  is directly connected to the output terminal TOUT and is thus applied with the output voltage. 
         [0120]    The bias generation section  1  included in the third embodiment is designed differently from the bias generation section  1  of the first embodiment and is constituted of p-channel MOS transistors M 15 , M 18 , M 21 , and M 22  and n-channel MOS transistor M 16 , M 17 , M 19 , M 20 , and M 23  as well as the transistors M 10 , M 11 , and M 12 . 
         [0121]    In  FIG. 6 , the source of the transistor M 10  is connected to the voltage supply, and the gate of the transistor M 10  is connected to the constant current source  100 , which is grounded. 
         [0122]    The source of the transistor M 11  is connected to the drain of the transistor M 10 , and the drain of the transistor M 11  is connected to the gate of the transistor M 10  and is also connected to the constant current source  100 , which is grounded. 
         [0123]    In the above constitution, the transistors M 10  and M 11  generate the first bias voltage pbias based on the current I 0  created by the constant current source  100 . 
         [0124]    The transistor M 11  serving as a cascode transistor is arranged to maintain the current flowing through the transistor M 10  constant. 
         [0125]    Since the gate of the transistor M 10  is connected to the drain of the transistor M 11 , the transistor M 10  normally operates in the linear region. 
         [0126]    The source of the transistor M 12  is connected to the voltage supply, and the gate of the transistor M 12  is connected to the gate of the transistor M 10  and the drain of the transistor M 11 . 
         [0127]    The source of the transistor M 15  is connected to the drain of the transistor M 12 , and the gate of the transistor M 15  is connected to the gate of the transistor M 11 . 
         [0128]    The drain of the transistor M 16  is connected to the drain of the transistor M 15 . 
         [0129]    The drain of the transistor M 17  is connected to the source of the transistor M 16 , the gate of the MOS transistor M 17  is connected to the drain of the transistor M 16 , and the source of the transistor M 17  is grounded. 
         [0130]    In the above constitution, the transistors M 12  and M 15  form a current mirror circuit which makes the prescribed current corresponding to the reference current I 0  flow through the transistors M 16  and M 17 . 
         [0131]    The transistors M 16  and M 17  generate the fourth bias voltage nbias. 
         [0132]    The source of the transistor M 18  is connected to the voltage supply, and the gate and drain of the transistor M 18  are connected to the gates of the transistors M 11  and M 15 . 
         [0133]    The drain of the transistor M 19  is connected to the gate and drain of the transistor M 18 , and the gate of the transistor M 19  is connected to the gate of the transistor M 16 . 
         [0134]    The drain of the transistor M 20  is connected to the source of the transistor M 19 , and the gate of the transistor M 20  is connected to the drain of the transistor M 16  and the gate of the transistor M 17 . The source of the transistor M 20  is grounded. 
         [0135]    In the above constitution, the transistors M 19  and M 20  form a current mirror circuit which makes the prescribed current (corresponding to the current flowing through the transistor M 17 ) flow through the transistor M 18 . By appropriately adjusting the size (or dimensions) of the transistor M 18 , they generate the second bias voltage pcas having the prescribed level. 
         [0136]    The source of the transistor M 21  is connected to the voltage supply, and the gate of the transistor M 21  is connected to the gate of the transistor M 10  and the drain of the transistor M 11 . 
         [0137]    The source of the transistor M 22  is connected to the drain of the transistor M 21 , and the gate of the transistor M 22  is connected to the gate and drain of the transistor M 18 . 
         [0138]    The gate and drain of the transistor M 23  are connected to the drain of the transistor M 22  and the gate of the transistor M 19 , and the source of the transistor M 23  is grounded. 
         [0139]    In the above constitution, the transistors M 21  and M 22  form a current mirror circuit which makes prescribed current (corresponding to the current flowing through the transistor M 10 ) flow through the transistor M 23 . By appropriately adjusting the size (or dimensions) of the transistor M 23 , they generate the third bias voltage ncas having the prescribed level. 
         [0140]    The drain of the transistor M 11  outputs the first bias voltage pbias to the gate of the transistor M 1  included in the reference current adjustment section  2 . 
         [0141]    The drain of the transistor M 18  outputs the second bias voltage pcas to the gate of the transistor M 3  included in the reference current adjustment section  2 . 
         [0142]    The drain of the transistor M 23  outputs the third bias voltage ncas to the gate of the transistor M 5  included in the current mirror section  4 . 
         [0143]    The drain of the transistor M 16  outputs the fourth bias voltage nbias to the gate of the transistor MB 6  included in the current mirror section  4 . 
         [0144]    As described above, the constant current source circuit of the third embodiment shown in  FIG. 6  does not include the control voltage generation section  3 , which is included in both of the first and second embodiments. 
         [0145]    The reason why the control voltage generation section  3  is not arranged in the third embodiment is that the second bias voltage pcas is maintained at a relatively high level in the low-voltage cascode current mirror circuit. 
         [0146]    If the third embodiment is designed in a similar manner to the first and second embodiment, the control voltage generation section  3  performs level shifting so as to supply the control voltage oshift, which is lower than the output voltage of the output terminal TOUT, to the gate of the transistor M 2 , wherein the intersecting point between the second bias voltage pcas and the control voltage oshift should be raised to a very high level compared to the output voltage of the output terminal TOUT. 
         [0147]    In this case, the output current I 1  should be excessively corrected in the stable region in which the output current I 1  is not corrected any more. 
         [0148]    In order to avoid the occurrence of the above phenomenon, the third embodiment is designed so as not to arrange the control voltage generation section  3  but to directly connect the output terminal TOUT to the gate of the transistor M 2 , wherein the output voltage of the output terminal TOUT is directly applied to the gate of the transistor M 2 . 
         [0149]    Next, the operation of the constant current source circuit of the third embodiment will be described with reference to  FIG. 7 .  FIG. 7  shows simulation results of the constant current source circuit of  FIG. 6 , wherein similar to  FIG. 3 ,  FIG. 7  shows variations of the output voltage which is produced based on the supply voltage of 1.5 V. In  FIG. 7 , the horizontal axis represents the output voltage of the output terminal TOUT, and the vertical axis represents potentials of various nodes. 
         [0150]    In the region to the right of the intersecting point between the output voltage of the output terminal TOUT and the second bias voltage pcas in  FIG. 7 , the potential of the drain md of the transistor M 1  is maintained to be substantially identical to the potential of the drain pd of the transistor M 12 , wherein the current Im flowing through the transistor M 1  becomes identical to the current I 0 , i.e., Im=I 0 . 
         [0151]    In the region to the left of the intersecting point in  FIG. 7 , the output voltage of the output terminal TOUT gets smaller in comparison with the second bias voltage pcas, wherein the difference between the potential of the drain pd of the transistor M 12  and the potential of the drain md of the transistor M 1  is additionally applied to the drain of the transistor M 1 ; hence, Im&gt;I 0 . 
         [0152]      FIG. 8  is a graph showing the relationship between the output voltage of the output terminal TOUT and the output current I 1  in the constant current source circuit of the third embodiment. In  FIG. 8 , the horizontal axis represents the output voltage of the output terminal TOUT, and the vertical axis represents the output current I 1  output from the output terminal TOUT. 
         [0153]    In  FIG. 8 , a bold line C indicates the voltage-current characteristics of the low-voltage cascode current mirror circuit. A dashed line A indicates the voltage-current characteristics of the constant current source circuit (excluding the transistor M 6 B) which outputs the current Im at 100%. A thin line B indicates the voltage-current characteristics of the constant current source circuit in which the transistor M 6 A outputs the current Im and I 0  at 50% each. 
         [0154]      FIG. 8  clearly shows that, in the constant current source circuit of the third embodiment compared to the low-voltage cascode current mirror circuit shown in  FIG. 16 , the transistor M 2  turns on so as to compensate for a reduction of the current Im due to a reduction of the output voltage of the output terminal TOUT, wherein it is possible to expand the operation region below the output voltage of 0.2 V or so by increasing the current Im flowing through the transistor M 1 . 
       4. Fourth Embodiment 
       [0155]    Next, a constant current source circuit according to a fourth embodiment of the present invention will be described with reference to  FIG. 9 .  FIG. 9  is a circuit diagram showing the constitution of the constant current source circuit of the fourth embodiment, which is designed by eliminating the transistor M 3  from the reference current adjustment section  2  compared to the reference current adjustment section  2  included in the constant current source circuit of the second embodiment shown in  FIG. 5 . Due to the elimination of the transistor M 3 , it is unnecessary to produce the second bias voltage pcas; hence, the transistor M 11  is also eliminated from the bias generation section  1 . 
         [0156]    In  FIG. 9 , parts identical to those of the second embodiment shown in  FIG. 5  are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the fourth embodiment. 
         [0157]    The source of the transistor M 10  is connected to the voltage supply, and the gate and drain of the transistor M 10  are connected to the constant current source  100 , which is grounded. 
         [0158]    In the above constitution, when the output voltage of the output terminal TOUT increases to be higher in level, the source-drain voltage of the transistor M 8  (configured of an n-channel MOS transistor) decreases so that the operating state of the constant current source circuit is changed from the saturation region to the linear region. 
         [0159]    In the linear region, the transistor M 8  cannot achieve the source-follower function. This is clearly shown in  FIG. 3  in terms of the relationship between the control voltage oshift and the output voltage of the output terminal TOUT. In  FIG. 3 , the control voltage oshift is maintained in a flat manner above the output voltage of 1.1 V. 
         [0160]    In the fifth embodiment in which the transistor M 3  is eliminated from the second embodiment, the transistor M 2  does not turn off even when the output voltage of the output terminal TOUT increases to be higher in level in the right region from the dotted line in  FIG. 3  or  FIG. 4 . This makes it possible for the current Im to flow through the transistors M 1  and M 2 . 
         [0161]    In the region to the right of the dotted line in  FIG. 4 , the function for maintaining the constant current due to the cascode effect may disappear, whereby a tendency in which the output current I 1  gradually decreases appears in the region to the right of the dotted line. 
         [0162]    The fourth embodiment works effectively in the case in which the output voltage of the output terminal TOUT is used in only the low-level region in a similar manner to a tail current of a differential amplifier (not shown). 
       5. Fifth Embodiment 
       [0163]    Next, a constant current source circuit according to a fifth embodiment of the present invention will be described with reference to  FIG. 10 .  FIG. 10  is a circuit diagram showing the constitution of the constant current source circuit of the fifth embodiment. 
         [0164]    In  FIG. 10 , parts identical to those of the second embodiment shown in  FIG. 5  are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the fifth embodiment. 
         [0165]    Instead of the internal bias voltage mbias of the current mirror section  4 , the fourth bias voltage nbias is applied to the gate of the transistor M 9  of the control voltage generation section  3  included in the constant current source circuit of the fifth embodiment compared to the second embodiment. The drain of the transistor M 9  is connected to the source of the transistor M 8 , and the gate of the transistor M 9  is connected to the gate and drain of the transistor M 14 . 
         [0166]    When the internal bias voltage (or gate bias voltage) mbias is applied to the gate of the transistor M 9 , the drain current of the transistor M 9  is forced to be maintained constant in the region to the left of the dotted line in  FIG. 4  which occurs due to a reduction of the output voltage of the output terminal TOUT. This may excessively reduce the control voltage oshift. 
         [0167]    Since the fourth bias voltage nbias is applied to the gate of the transistor M 9 , even when the output voltage of the output terminal TOUT decreases such that the control voltage oshift (which corresponds to the drain voltage of the transistor M 9 ) also decreases, it is possible to moderate an excessive reduction of the control voltage oshift by way of a reduction of the drain current of the transistor M 9 , thus making it possible to relieve the output current I 1  from further correcting. 
       6. Sixth Embodiment 
       [0168]    Next, a constant current source circuit according to a sixth embodiment of the present invention will be described with reference to  FIG. 11 .  FIG. 11  is a circuit diagram showing the constitution of the constant current source circuit of the sixth embodiment. 
         [0169]    The sixth embodiment shown in  FIG. 11  is designed to additionally introduce the control voltage generation section  3  into the third embodiment shown in  FIG. 6 . In  FIG. 11 , parts identical to those of the third embodiment shown in  FIG. 6  are designated by the same reference numerals; hence, only differences in the constitution and operation will be described with respect to the sixth embodiment. 
         [0170]    The control voltage generation section  3  is constituted of n-channel MOS transistors M 25  and M 26  as well as the p-channel MOS transistors M 7  and M 8 . 
         [0171]    The source of the transistor M 7  is connected to a voltage supply, and the gate of the transistor M 7  is connected to the drain of the transistor M 11 . 
         [0172]    The source of the transistor M 8  is connected to the drain of the transistor M 7 , and the gate of the transistor M 8  is connected to the output terminal TOUT. 
         [0173]    The drain of the transistor M 25  is connected to the drain of the transistor M 8 , and the gate of the transistor M 25  is connected to the drain of the transistor M 23  so as to receive the third bias voltage ncas. 
         [0174]    The drain of the transistor M 26  is connected to the source of the transistor M 25 , and the gate of the transistor M 26  is connected to the drain of the transistor M 16  so as to receive the fourth bias voltage nbias. The source of the transistor M 26  is grounded. 
         [0175]    In the above constitution, when the voltage higher than the output voltage of the output terminal TOUT is applied to the gate of the transistor M 2 , the dotted lines of  FIGS. 7 and 8  are moved leftward so as to moderate the excessive correction, thus achieving the flat characteristics with respect to the output current I 1 . 
       7. Seventh Embodiment 
       [0176]      FIG. 12  is a circuit diagram showing a constant current source circuit according to a seventh embodiment of the present invention. The seventh embodiment shown in  FIG. 12  is designed to additionally insert resistors R 1  and R 2  in series between the source of the transistor M 8  and the drain of the transistor M 9  in the control voltage generation section  3  used in the second embodiment shown in  FIG. 5 . In addition, the connection point between the resistors R 1  and R 2  is connected to the gate of the transistor M 2 , whereby the voltage at the connection point is applied to the gate of the transistor M 2  as the control voltage oshift. 
         [0177]    Compared to the second embodiment, the seventh embodiment is designed to additionally insert the resistors R 1  and R 2  between the transistors M 8  and M 9 , thus reducing the control voltage oshift. This moves the dotted lines of  FIGS. 7 and 8  rightward so as to make the constant current source circuit of the seventh embodiment operate in a further low-voltage region. 
         [0178]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.