BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to semiconductor memory devices and, in particular, to a semiconductor memory device and a repair method that employ programmable self-contained repairable cells to repair defect cells of a semiconductor memory device in a package state. 
     2. Background Description 
     In a semiconductor memory device such as a dynamic random access memory (DRAM) device, a memory cell plays an important role. Therefore, when a single cell in a group of cells has a defect, which-results in a malfunction of the-entire group of cells, the corresponding memory device is considered to be “condemned goods”. The greater the degree of integration of a DRAM, the greater the probability that some of the cells contained therein will have defects. However, the disposal of such devices as defective goods is an inefficient way to reduce mass product yields. 
     Accordingly, pre-constructing redundancy cells in DRAMs is a common way to obtain an acceptable device when that device is defective. In such a case, defect cells are replaced with redundancy cells when the defect cells are detected. 
     Redundancy cell repair technology fabricates sufficient fuses in a semiconductor memory device, and replaces any defect column lines and row lines with spare lines by applying a laser beam method. However, the laser beam method is mainly employed in a wafer state that precedes the packaging of a semiconductor device. Therefore, the repair process cannot be performed when defect cells are found after the device has been packaged. U.S. Pat. Nos. 6,011,734 and 5,764,577 disclose repair technology that is implemented in the packaging step of a semiconductor device. 
     U.S. Pat. Nos. 6,011,734 and 5,764,577 disclose repair methods that pre-construct spare cells in a DRAM device, store a defect cell address to a latch, inactivate a corresponding defect cell by comparing the latched address with the address accessed from the outside, and then activate redundancy circuits. 
     However, the above-mentioned U.S. Patents disclose redundancy cells established in the same physical structures as those of a memory cell array, and developed by the same processes as those of the memory cell array. Therefore, redundancy memory cells exhibit a high probability of having the same defect cells as those of memory cells. As a result, the repair processes for such devices are difficult in the case that defect redundancy cells are found. 
     SUMMARY OF THE INVENTION 
     The problems stated above, as well, as other related problems of the prior art, are solved by the present invention, a semiconductor memory device and a repair method that employ programmable self-contained repairable cells to repair defect cells of a semiconductor memory device in a package state. The semiconductor memory device and the repair method of the invention pre-construct redundancy logic cells in the peripheries of a memory cell array to replace defect cells of the memory cell array with the redundancy logic cells. 
     According to an aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal, respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell address latches store defect cell addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a memory test. A plurality of comparators output repair signals when an address stored in the plurality of defect cell address latches corresponds to the external address received by the address buffer. A redundancy controller generates a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to a repair signal outputted in a normal mode, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells. 
     According to another aspect of the present invention, there is provided a semiconductor memory device. The device includes a row address buffer for receiving an external row address signal. A column address buffer receives an external column address signal. A row decoder decodes a row address provided by the row address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the column address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell row address latches store defect cell row addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a memory test. A plurality of defect cell column address latches store defect cell column addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in the memory test. A plurality of first comparators output row repair signals when a defect cell row address stored in one of the plurality of defect cell row address latches corresponds to the row address provided by the row address buffer in a normal mode. A plurality of second comparators output column repair signals when a defect cell column address stored in one of the plurality of defect cell column address latches corresponds to the column address provided by the column address buffer in the normal mode. A redundancy controller generates a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to a row and a column repair signal, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells. 
     According to yet another aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided. by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal respectively. A redundancy logic cell replaces defect cells in the memory cell array. A plurality of defect cell address storage devices store defect cell addresses corresponding to the defect cells in the memory cell array. The defect cells are detected in a test mode. A plurality of comparison devices output repair signals when an address stored in the plurality of defect cell address storage devices corresponds to the external address received by the address buffer. A plurality of redundancy control devices generate a control signal to intercept the word line selecting signal and the bit line selecting signal corresponding to the defect cells in response to the repair signals, and generate another control signal to enable a read/write operation of the redundancy logic cell, in a normal mode, in place of the defect cells. 
     According to still yet another aspect of the present invention, there is provided a semiconductor memory device. The device includes an address buffer for receiving an external address. A row decoder decodes a row address provided by the address buffer, and generates a word line selecting signal. A column decoder decodes a column address provided by the address buffer, and generates a bit line selecting signal. A memory cell array has a plurality of memory cells. Each of the plurality of memory cells is activated by a selection of a word line and a bit line by the word line selecting signal and the bit line selecting signal, respectively. First redundancy logic cells replace defect cells. Second redundancy logic cells replace the defect cells. A plurality of defect cell address latches store defect cell addresses corresponding to the defect cells. The defect cells are detected in a test mode. A plurality of comparators output repair signals when an address stored in the plurality of defect cell address latches corresponds to the external address received from the address buffer. A redundancy controller generates a control signal to intercept a pass of defect cell address signals of the row decoder and the column decoder in response to the repair signal, generates a first control signal to enable a read/write operation of the first redundancy logic cell when the memory cell array has the defect cells, and generates a second control signal to enable a read/write operation of the second redundancy logic cell when the first redundancy logic cell has the defect cells. The generating of the control signal, the first control signal, and the second control signal occurs in a normal mode. 
     These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram illustrating a semiconductor memory device having redundancy logic cells, according to a preferred embodiment of the present invention; 
     FIG. 2 is a circuit diagram illustrating a defective-cell-address latch unit  22  and a comparator  24  shown in FIG. 1, according to an illustrative embodiment of the present invention; 
     FIG. 3 is a circuit diagram illustrating a redundancy controller  26  and redundancy logic cell  28  shown in FIG. 1, according to a preferred embodiment of the present invention; 
     FIG. 4 is a diagram illustrating a semiconductor memory device having redundancy logic cells, according to an alternative preferred embodiment of the present invention; 
     FIG. 5 is a diagram illustrating a semiconductor memory device performing a re-repair process, according to another alternative preferred embodiment of the present invention; and 
     FIG. 6 is a flow chart illustrating a repair process for a semiconductor memory device, according to the preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Reference will now be made in detail to preferred embodiments of the present invention, examples of which being illustrated in the accompanying drawings. 
     FIG. 1 is a diagram illustrating a semiconductor memory device having redundancy logic cells, according to a preferred embodiment of the present invention. The semiconductor memory device includes an address buffer  10 , a row decoder  12 , a column decoder  14 , a memory cell array  16 , a redundancy decoder  18 , a redundancy memory cell  20 , a defect-cell-address latch unit  22 , a comparator  24 , a redundancy controller  26 , and a redundancy logic cell  28 . 
     After buffering an external address signal, the address buffer  10  provides a row address for the row decoder  12 , and a column address for the column decoder  14 . In addition, the output terminal of the address buffer  10  is connected to the defective-cell-address latch unit  22  and the comparator  24 . 
     The row decoder  12  decodes an inputted row address, and then selects a word line corresponding to a memory cell in the memory cell array  16 . 
     The column decoder  14  decodes an inputted column address, and then selects a bit line corresponding to a memory cell in the memory cell array  16 . 
     Therefore, when an input signal selects a word line and a bit line, the input signal, activates a corresponding cell to read data stored in a data bus, or to write data provided from the data bus. 
     The redundancy memory cell  20  is a spare cell manufactured in the same process with that of the memory cell array  16 , and replaces a defect memory cell of the memory cell array  16  when the defect memory cell is found. In other words, a laser beam cuts off fuses of the redundancy decoder  18  in a wafer state so that the redundancy memory cell  20  can repair (i.e., replace) a defective memory cell in the memory cell array  16 . 
     Advantageously, the present invention includes the redundancy logic cell  28 , which is disposed in the peripheries of the memory cell array  16  to repair any defect cell in the memory cell array  16  or any defect cell in the redundancy memory cell  20  after packaging. 
     All of the defective-cell-address latch unit  22 , the comparator  24 , and the redundancy controller  26  activate the redundancy logic cell  28 . 
     The defective-cell-address latch unit  22  comprises many latches. The defective-cell-address latch unit  22  latches a defect cell address when a package test finds a malfunctioned cell among the memory cell array  16  and among. repaired cells. 
     The comparator  24  comprises many comparators. The comparator  24  compares a latched address with an address from the outside (i.e., provided externally with respect to the semiconductor memory device), and generates a repair signal when the latched address corresponds to the externally provided address. 
     In a normal mode, the redundancy controller  26  responds to the repair signal. Therefore, the redundancy controller  26  generates a redundancy control signal RLC 2  that intercepts an employment of a normal cell address in the row decoder  12  and the column decoder  14 , and generates an enable-signal EN of the redundancy logic cell  28 . The enable-signal activates the redundancy logic cell  28  to read data stored in a data-bus by a read-control signal R, or to write data from a data-bus by a write-control signal W. 
     FIG. 2 is a circuit diagram illustrating a defective-cell-address latch unit  22  and a comparator  24  shown in FIG. 1, according to an illustrative embodiment of the present invention. 
     Each latch Lti in the defective-cell-address latch unit  22  includes inverters INV 1  and INV 2 , and transistors NM 1  and NM 2 . The output terminal of the inverter INV 1  is connected to a node N 1  and the input terminal of the inverter INV 1  is connected to a node N 2 . The output terminal of the inverter INV 2  is connected to the node N 2  and the input terminal of the inverter INV 2  is connected to the node N 1 . An active-signal AC or a read/write-control signal R/W switches the switching. transistor NM 1  between the node N 2  and a node N 3 . A redundancy control signal RLC 1  switches the switching transistor NM 2  placed between the output terminal of the address buffer  10  and the node N 3 . 
     Therefore, the latch Lti responds to the active signal AC or the read/write signal R/W, and latches the corresponding address bit-signal in test mode. 
     Each comparator in the comparator  24  includes four PMOS transistors PM 1  to PM 4 , four NMOS transistors NM 3  to NM 6 , and inverters INV 3  and INV 4 . 
     The transistor PM 1  has a gate, a source, and a drain respectively connected to the node N 2 , a power voltage VCC, and a node N 4 . The transistor PM 2  has a gate, a source, and a drain respectively connected to the node N 1 , the node N 4 , and a node N 5 . The transistor NM 3  has a gate, a source, and a drain respectively connected to the node N 1 , the node N 5 , and a node N 6 . The transistor NM 4  has a gate, a source, and a drain respectively connected to the node N 2 , the node N 6 , and a ground voltage VSS. 
     The transistor PM 3  has a gate, a source, and a drain respectively connected to the output terminal of the address buffer  10 , the power voltage VCC, and the node N 4 . The transistor PM 4  has a gate, a source, and a drain respectively connected to the output terminal of the address buffer  10  through an inverter INV  3 , the node N 4 , and the node N 5 . The transistor NM 5  has a gate, a source, and a drain respectively connected to the output terminal of the address buffer  10 , the node N 5 , and the node N 6 . The transistor NM 6  has a gate, a source, and a drain respectively connected to the output terminal of the address buffer  10  through the inverter INV 3 , the node N 6 , and the ground voltage VSS. An input terminal of the inverter INV 4  is connected to the node N 5 . The inverter INV 4  converts the signal of the node N 5  to the output signal of the comparator  24 . 
     FIG. 3 is a circuit diagram illustrating a redundancy controller  26  and redundancy logic cell  28  shown in FIG. 1, according to a preferred embodiment of the present invention. In the preferred embodiment, each address buffer  10  possesses each row address buffer  10 A and each column address buffer  10 B. 
     The row address buffer  10 A comprises each row address bit buffer RAB 0  to RABi. The output of each row address bit buffer is supplied to row defect-cell-address latch unit RLT 0  to RLTi, and row comparators RCOM 0  to RCOMi. The outputs of the row comparators are supplied to the row decoder  12  as a row repair signal. 
     The column address buffer  10 B comprises each column address bit buffer CAB 0  to CABi. The output of each column address bit buffer is supplied to column defect-cell-address latch unit CLT 0  to CLTi, and column comparators CCOM 0  to CCOMi. The outputs of the column comparators are supplied to the column decoder  14  as a column repair signal. 
     The redundancy controller  26  includes a redundancy row decoder RRD, a redundancy column decoder RCD, and an enable signal generator ENG. 
     The redundancy row decoder RRD includes multiple NAND gates, a NOR gate, and multiple input transistors RT 0  to RTi for receiving the output of each row comparator. In the normal mode, the redundancy control signal RLC 2  is activated to a “high” logic level when the redundancy logic cell  28  is employed, and then the redundancy control signal RLC 2  turns on each input transistor RT 0  to RTi. 
     The redundancy row decoder RRD activates a,row interception signal WLDEN to the “low” logic level when the output of every row comparator is at the “low” logic level. 
     The redundancy column decoder RCD includes multiple NAND gates, a NOR gate, and multiple input transistors CT 0  to CTi for receiving the output of each column comparator. In the normal mode, the redundancy control signal RLC 2  is activated to the “high” logic level when the redundancy logic cell is employed, and then the redundancy control signal RLC 2  turns on each input transistor CT 0  to CTi. 
     The redundancy column decoder RCD activates a column interception signal CSLDEN to the “low” logic level when the output of every column comparator is at the “low” logic level. 
     The enable signal generator ENG includes a first latch circuit LTA, a second latch circuit LTB, and a logic circuit G. The first latch circuit LTA latches the row interception signal WLDEN. The second latch circuit LTB latches the column interception signal CSLDEN. The logic circuit G combines the data latched in the first latch circuit LTA and the second latch circuit LTB, and then generates an enable-control signal EN of the redundancy logic cell  28 . 
     The redundancy logic cell  28  includes inverters INV 5  and INV 6 , NMOS transistors NM 7  and NM 8 , and NAND gates G 1  and G 2 . 
     The inverter INV 5  has an output terminal connected to a node N 7  and an input terminal connected to a node N 8 . The inverter INV 6  has an output terminal connected to the node N 8  and an input terminal connected to the node N 7 . The transistor NM 7  is placed between the node N 7  and a write pass. The transistor NM 8  is placed between the node N 8  and a read pass. 
     The NAND gate G 1  combines the enable-control signal EN and the write-control signal W, and then switches the transistor NM 7 . The NAND gate G 2  combines the enable-control signal EN and the read-control signal R, and then switches the transistor NM 8 . 
     Therefore, either reading or writing data to the redundancy logic cell  28  is performed in the only case that the enable-control signal EN is activated. 
     FIG. 4 is a diagram illustrating a semiconductor memory device having redundancy logic cells, according to an alternative preferred embodiment of the present invention. The alternative preferred embodiment includes redundancy logic cell  28 A and  28 B. The redundancy logic cell  28 A is associated with a defective-cell-address latch unit  22 A, a comparator  24 A, and a redundancy controller  26 A. The redundancy logic cell  28 B is associated with a defective-cell-address latch unit  22 B, a comparator  24 B, and a redundancy controller  26 B. In addition, a redundancy control signal RLC 11  is applied to the defective-cell-address latch unit  22 A. Similarly, a redundancy control signal RLC 12  is applied to the defective-cell-address latch unit  22 B. 
     Therefore, the first address signal from the address buffer  10  is latched to the latch unit  22 A when the redundancy control signal RLC 11  is activated, and the second address signal from the address buffer  10  is latched to the latch unit  22 B when the redundancy control signal RLC 12  is activated. 
     The first redundancy logic cell  28 A is activated in the case that the first redundancy logic cell  28 A receives the first enable-control signal EN 1 , and the second redundancy logic cell  28 B is activated in the case that the second redundancy logic cell  28 B receives the second enable-control signal EN 2 . 
     FIG. 5 is a diagram illustrating a semiconductor memory device performing a re-repair process, according to another alternative preferred embodiment of the present invention. The other alternative preferred embodiment includes a pair of redundancy logic cells  28 A and  28 B. The pair of redundancy logic cell are associated with a defective-cell-address latch unit  22 , a comparator  24 , and a redundancy controller  26 C. 
     The redundancy controller  26 C includes a redundancy row decoder RRD, a redundancy column decoder RCD, an enable signal generator ENG, and a re-repair unit RRP. 
     The re-repair unit RRP includes transistors NM 9  and NM 10 , and an inverter INV 7 . The transistor NM 9  is connected between an output terminal of the enable-control signal generator ENG and an input terminal of an enable-control signal EN 1  in the first redundancy logic cell  28 A. The transistor NM 10  is connected between the output terminal of the enable-control signal:generator ENG and an input terminal of an enable-control signal EN 2  in the second redundancy logic cell  28 B. A third redundancy control signal RLC 3  is applied to a gate of the transistor NM 10 , and to a gate of the transistor NM 9  through the inverter INV 7 . In the case that the third redundancy control signal RLC 3  is at the “low” logic level, the enable-control signal EN is only applied to the first redundancy logic cell  28 A. On the contrary, in the case that the third redundancy control signal RLC 3  is at the “high” logic level, the enable-control signal EN is only applied to the second redundancy logic cell  28 B. 
     Therefore, in the case that the first redundancy logic cell  28 A is detected as a defect cell in a device test, the third redundancy control signal RLC 3  is activated to the “high” logic level so that the second redundancy logic cell  28 B can replace the defect cell in the first redundancy logic cell  28 A. 
     FIG. 6 is a flow chart illustrating a repair process for a semiconductor memory device, according to the preferred embodiment of the present invention. 
     Numerous semiconductor memory devices are produced on the wafer (step  100 ). Tests for semiconductor memory devices are performed at the wafer state (step  102 ). When any of the memory devices have no defects, these memory devices pass the test performed at step  102  to perform a package process, and then these devices are delivered to customers after the package process (step  104 ). 
     At step  102 , in the case that testing of the semiconductor memory devices finds any defective devices, then laser repair equipment employs the redundancy memory cell to repair the defect memory device (step  106 ). 
     These repaired memory devices are tested again in the package state (step  108 ). In the case that the test performed at the package state does not detect a defect, these devices are delivered to customers per step  104 . 
     In the case that the package test finds a defective device at step  108 , the defective device is reviewed to determine whether or not the defect is due to a malfunction in the memory cells (step  112 ). In the case of a malfunction in the memory cells (step  110 ), a redundancy logic cell is employed to repair the defective memory device by latching a defect cell address to a defect-cell-address latch unit (step  114 ). Repaired semiconductor memory devices employing the redundancy logic cell are treated as normal products. 
     In the case that a defect cell is found in a semiconductor memory device delivered to a customer, repairing the delivered defective device is also performed through steps  112  and  114 . In addition, another alternative preferred embodiment of the present invention illustrates “re-repairing” a malfunctioned redundancy logic cell of a semiconductor memory device. 
     As described above, the present invention performs a memory test in the package state to detect defective memory cells. The defect cell address is stored to a defective-cell-address latch in the case that the defect cell is found. Then, the defect cell is replaced with a redundancy logic cell in the case that the accessed address from the outside corresponds to the latched address. As a result, the repair of any defective memory cells of a semiconductor memory device may be performed without constraint. In addition, the redundancy logic cell established in the peripheries of a memory cell array has different physical structures from the memory cell array, which drastically decreases the probability of defects in the redundancy logic cell as compared with a semiconductor memory device having a conventional redundancy cell. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
A semiconductor memory device includes an address buffer for receiving an external address. A row decoder and a column decoder respectively decode a row address and a column address, and respectively generate a word line selecting signal and a bit line selecting signal. A memory cell array has cells. Each cell is activated by a selection of a word line and,a bit line. A redundancy logic cell replaces defect cells in the memory cell array. Latches store defect cell addresses corresponding to the defect cells in the memory cell array. Comparators output repair signals when an address stored in the latches corresponds to the external address. A redundancy controller generates a control signal to intercept signals corresponding to the defect cells in response to a repair signal, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.