PRIORITY CLAIM UNDER 35 U.S.C. §119(e) 
     This patent application claims the priority benefit of the filing date of provisional application Ser. No. 61/848,775 having been filed in the United States Patent and Trademark Office on Dec. 19, 2012 and now incorporated by reference herein. 
    
    
     STATEMENT OF GOVERNMENT INTEREST 
     The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon. 
    
    
     BACKGROUND OF THE INVENTION 
     Matrix-vector multiplication is one of the most commonly used mathematical operations in science and engineering computations. Mathematically, a matrix is usually represented by a two-dimensional array of real numbers, and a vector is represented by a one-dimensional array of real numbers. Since a matrix can be viewed as an array of vectors, the matrix-vector multiplication operation can be generalized to vector-vector multiplication (inner product) or matrix-matrix multiplication operations. In today&#39;s computer systems, matrix-vector multiplication operations are performed by digital integrated circuits, in which the numbers are represented in binary format and the computation is performed by Boolean logic circuits. 
     The existence of resistive memory devices, such as the memristor, resistive random-access memory (RRAM), and spintronic switches, were predicted in circuit theory nearly forty years ago. However, it wasn&#39;t until 2008 that the first physical realization was demonstrated by HP Labs through a TiO 2  thin-film structure. Afterward, many resistive memory materials and devices have been reported or rediscovered. The resistive memory device has many promising features, such as non-volatility, low-power consumption, high integration density, and excellent scalability. More importantly, the unique property to record the historical profile of the excitations on the device makes it an ideal candidate to perform storage and computation functions in one device. 
     For the purpose of succinct description, the present invention uses the terminology “memristor” to represent the category of “resistive memory device”. For the remainder of the patent description, references to “memristor” shall be regarded as referring to any “resistive memory device”. 
     Based on circuit theory, an ideal memristor with memristance M builds the relationship between the magnetic flux φ and electric charge q that passes through the device, that is, dφ=M·dq. Since the magnetic flux and the electric charge are time dependent parameters, the instantaneous memristance varies with time and reflects the historical profile of the excitations through the device. 
     When developing actual memristive devices, many materials have demonstrated memristive behavior in theory and/or experimentation via different mechanisms. In general, a certain energy (or threshold voltage) is required to enable a state change in a memristor. When the electrical excitation through a memristor is greater than the threshold voltage, e.g., |v in |&gt;|v th |, the memristance changes. Otherwise, the memristor behaves like a resistor. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an apparatus that performs mathematical matrix-vector multiplication approximation. 
     It is a further object of the present invention to provide an apparatus that utilizes resistive memory devices to store matrix coefficients so as to facilitate matrix-vector multiplication approximation. 
     It is yet a further object of the present invention to apply matrix-vector multiplication approximation to facilitate auto-associative neural network recall functionality. 
     Briefly stated, the present invention is an apparatus that performs mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture. 
     SUMMARY OF THE INVENTION 
     In this invention, we describe a matrix-vector multiplication approximation hardware method and design based on crossbar arrays of resistive memory devices. 
     By nature, the memristor crossbar array is attractive for the implementation of matrix-vector multiplication operations. The crossbar array inherently provides capabilities for this type of operation. In this invention, we focus on a hardware architecture and realization of the matrix-vector multiplication approximation assuming all of the memristors have been pre-programmed to store the elements of the matrix. During the multiplication operations, the voltages across the memristors are constrained below the threshold voltage so that all the memristance values remain unchanged. The crossbar architecture can naturally transfer the weighted combination (matrix) of input voltages (input vector) to output voltages (output vector). We also describe a fast approximation mapping method so that the matrix can be mapped to pure circuit element relations. 
     As shown in  FIG. 1 , the proposed hardware method and design includes two crossbar arrays of resistive memory devices, M 1    10  for positive elements of the matrix and M 2    20  for negative elements of the matrix. The input vector is represented by the input voltages VI that are driving the row (horizontal) wires  30  of the crossbar arrays. The matrix-vector multiplication approximation resulting vector is represented by the outputs VO of the analog subtraction amplifier circuits  40  connected to the column (vertical) wires  50  of the crossbar arrays. 
     This invention also includes an extended method and design that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture (see  FIG. 4  and  FIG. 5 ). The Brain-State-in-a-Box (BSB) model recall operation will be used as an example to illustrate the method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts the two crossbar arrays of memristive devices and subtraction amplifier used by the present invention to perform matrix-vector multiplication approximation. 
         FIG. 2  depicts a single crossbar array used in the present invention showing more clearly the word lines, bit lines, and the connection of memristive devices between them. 
         FIG. 3  depicts the circuit schematic of the subtraction amplifier used in the preferred embodiment of the present invention. 
         FIG. 4  depicts an alternate embodiment of the present invention employing the auto-associative neural network recall function. 
         FIG. 5  depicts the circuit schematic of the summation-subtraction amplifier circuit used in the alternate embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A. Crossbar Array Implementation of Matrix 
     Referring to  FIG. 2 , the present invention uses an N-by-M memristor crossbar array as a basic building block to achieve matrix-vector multiplication approximation computation functionality. 
     A set of input voltages VI T ={vi 1 , vi 2 , . . . , vi N } are applied on each of the N word-lines (WLs)  30  of the array, and the current is collected through each of the M bit-lines (BLs)  50  by measuring the voltage across a sensing resistor  60 . The same sensing resistors are used on all the BLs with resistance r s , or conductance g s =1/r s . The output voltage vector is VO T ={vo 1 , vo 2 , . . . , vo M }. Assume the memristive device (i.e., memristor)  70  sitting on the connection between WL j  and BL i  has a memristance of m i,j . The corresponding conductance is g i,j =1/m i,j . Then the relation between the input and output voltages can be approximated by:
 
 VO≅C×VI   (1)
 
Here, C is an MA-by-N matrix that can be represented by the memristors  70  and the sensing (load) resistors  60  as:
 
                   C   =       D   ×   G     =       diag   ⁡     (       d   1     ,   …   ⁢           ,     d   M       )       ×     [           g     1   ,   1           …         g     1   ,   N                 g     2   ,   1                         g     2   ,   N               ⋮       ⋱       ⋮             g     M   ,   1           …         g     M   ,   N             ]                 (   2   )               
where D is a diagonal matrix with diagonal elements of:
 
 d   i =1/( g   s +Σ k=1   N   g   i,k ) i= 1, 2  . . . , M.   (3)
 
     Eq. (1) indicates that a trained memristor crossbar array can be used to construct the connection matrix C, and transfer the input vector VI to the output vector VO. However, Eq. (2) shows that C is not a direct one-to-one mapping of conductance matrix G of the memristor crossbar array, since the diagonal matrix D is also a function of G. We have two methods to obtain the solution of G: an complex numerical iteration method to obtain the exact mathematical solution of G, and a simple approximation useful for frequent or resource constrained updates. In this invention we adopt the second method, which is described next. 
     In this section we first show how to map C to G when c i,j  is in the range of [0, 1.0]. In the next section we will show the method of mapping a general matrix A with both positive and negative elements. 
     We assume any g i,j εG satisfies g min ≦g i,j ≦g max , where g min  and g max  respectively represent the minimum and the maximum conductance of all memristors in the crossbar array. Instead, we propose a simple and fast approximation to the mapping problem by allowing:
 
 g   i,j   =c   i,j ·( g   max   −g   min )+ g   min   (4)
 
     In the following, we will prove that by using this mapping method, a scaled version Ĉ of the connection matrix C can be approximately mapped to the conductance matrix G of the memristor array. 
     P ROOF . By plugging Eq. (4) into Eq. (3), we have: 
     
       
         
           
             
               
                 
                   
                     
                       c 
                       ^ 
                     
                     
                       i 
                       , 
                       j 
                     
                   
                   = 
                   
                     
                       
                         
                           c 
                           
                             i 
                             , 
                             j 
                           
                         
                         · 
                         
                           ( 
                           
                             
                               g 
                               max 
                             
                             - 
                             
                               g 
                               min 
                             
                           
                           ) 
                         
                       
                       + 
                       
                         g 
                         min 
                       
                     
                     
                       
                         g 
                         s 
                       
                       + 
                       
                         N 
                         · 
                         
                           g 
                           min 
                         
                       
                       + 
                       
                         
                           ( 
                           
                             
                               g 
                               max 
                             
                             - 
                             
                               g 
                               min 
                             
                           
                           ) 
                         
                         · 
                         
                           
                             ∑ 
                             
                               k 
                               = 
                               1 
                             
                             N 
                           
                           ⁢ 
                           
                             c 
                             
                               i 
                               , 
                               k 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Note that many memristor materials, such as the TiO 2  memristor, demonstrate a large g max /g min  ratio. Thus, a memristor at the high resistance state under a low voltage excitation can be regarded as an insulator, that is, g min ≅0. And Σ k=1   N c i,k  can be further reduced by increasing the ratio of g s /g max . As a result, the impact of Σ k=1   N c i,k  can be ignored. These two facts indicate that Eq. (5) can be further simplified to: 
     
       
         
           
             
               
                 
                   
                     
                       c 
                       ^ 
                     
                     
                       i 
                       , 
                       j 
                     
                   
                   = 
                   
                     
                       c 
                       
                         i 
                         , 
                         j 
                       
                     
                     · 
                     
                       
                         g 
                         max 
                       
                       
                         g 
                         s 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     In summary, with the proposed mapping method, the memristor crossbar array performs as a scaled connection matrix Ĉ between the input and output voltage signals. 
     B. Transformation of Matrix 
     In this section we describe the method of mapping from a matrix A to the memristor conductances G, under the condition that a i,j  is in the range from −1.0 to +1.0. In the general case, we can scale any given matrix to the [−1.0, 1.0] range, then perform the operation, and finally scale the resulting outputs back to the original range. 
     Given a matrix A with all its elements scaled to the range of [−1.0, 1.0], we first split the positive and negative elements of A into two matrixes A +  and A −  as: 
     
       
         
           
             
               
                 
                   
                     a 
                     
                       i 
                       , 
                       j 
                     
                     + 
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             
                               
                                 a 
                                 
                                   i 
                                   , 
                                   j 
                                 
                               
                               , 
                             
                           
                           
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               &gt; 
                               0 
                             
                           
                         
                         
                           
                             
                               0 
                               , 
                             
                           
                           
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               ≤ 
                               0 
                             
                           
                         
                       
                       , 
                       
                           
                       
                       ⁢ 
                       and 
                     
                   
                 
               
               
                 
                   ( 
                   
                     7 
                     ⁢ 
                     a 
                   
                   ) 
                 
               
             
             
               
                 
                   
                     a 
                     
                       i 
                       , 
                       j 
                     
                     - 
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             
                               0 
                               , 
                             
                           
                           
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               &gt; 
                               0 
                             
                           
                         
                         
                           
                             
                               
                                 - 
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               , 
                             
                           
                           
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               ≤ 
                               0 
                             
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   
                     7 
                     ⁢ 
                     b 
                   
                   ) 
                 
               
             
           
         
       
     
     As such, a general matrix-vector multiplication approximation becomes:
 
 VO=A·VI=A   +   ·VI−A   −   ·VI   (8)
 
Here, the two matrices A +  and A −  can be mapped to two memristor crossbar arrays M 1  and M 2  in a scaled version Â +  and Â − , respectively, by combining the mapping method in Eq. (4) with Eq. (7a) and (7b) as follows.
 
                     For   ⁢           ⁢     M   1     ⁢     :     ⁢           ⁢     g     i   ,   j         =     {                 a     i   ,   j       ·     (       g   max     -     g   min       )       +     g   min       ,       if   ⁢           ⁢     a     i   ,   j         &gt;   0.0                   g   min     ,       if   ⁢           ⁢     a     i   ,   j         ≤   0.0                       (   9   )                 For   ⁢           ⁢     M   2     ⁢     :     ⁢           ⁢     g     i   ,   j         =     {                 -     a     i   ,   j         ·     (       g   max     -     g   min       )       +     g   min       ,       if   ⁢           ⁢     a     i   ,   j         &lt;   0.0                   g   min     ,       if   ⁢           ⁢     a     i   ,   j         ≥   0.0                       (   10   )               
C. Circuit Realization of Matrix-Vector Multiplication
 
     To realize the matrix-vector multiplication approximation function y=A·x at the circuit level, the elements of the input vector x are converted to the range of input voltage levels VI. The corresponding functions for the multiplication approximation can be expressed as: 
                   VO   =         g   s       g   max       ⁢     (       VO   +     -     VO   -       )               (   11   )                 where   ⁢           ⁢     VO   +       =             A   ^     +     ·   VI     ⁢           ⁢   and   ⁢           ⁢     VO   -       =         A   ^     -     ·   VI               (   12   )                 where   ⁢           ⁢   VI     =         v   bn            x   max            ·   x             (   13   )               
where |x max | is the maximum possible magnitude of any element of input vector x, and v bn  is the input voltage boundary, that is, −v bn ≦vi j ≦v bn  for any vi j εVI. In implementation, v bn  must be smaller than v th  so that the memristance values will not change during the multiplication operation.
 
     As shown in  FIG. 1 , the memristor crossbar arrays  10 ,  20  are used to realize the matrix-vector multiplication approximation operation. To obtain both positive and negative elements in the matrix, two memristor crossbar arrays M 1    10  and M 2    20  are required in the design to represent the positive and negative matrices Â +  and Â − , respectively. The memristor crossbar arrays have the same dimensions as the transposed matrix A. 
     In the present invention, the input signal VI along with VO +  and VO − , the corresponding voltage outputs of two memristor crossbar arrays, are fed into a number of analog subtraction amplifier circuits  40 . The design of the subtraction amplifier  40  is shown in  FIG. 3 . 
     Resulting from the scaled mapping method, the required VO should be g s /g max  times the generated VO +  or VO − . In the present invention, we set R 1 =R 2 =1/g s  and R 3 =R 4 =1/g max . The resulting output of the subtraction amplifier  40  is: 
                     vo   i     =           g   s       g   max       ·     vo   i   +       -         g   s       g   max       ·     vo   i   -                 (   14   )               
which indicates that the scaled effect (caused by mapping from A to Â +  and Â − ) has been canceled out. The M-by-N dimensional matrix requires M summing amplifiers  40  to realize the subtraction operation in Eq. (14). Also, for subtraction amplifiers  40 , we should adjust their power supplies to make their maximum/minimum output voltages to reflect the same scaling factor when converting the input vector x to voltage VI. Finally the resulting vector y can be obtained from VO with inversed scaling factor of x, as shown in Eq. (15).
 
     
       
         
           
             
               
                 
                   y 
                   = 
                   
                     
                       
                          
                         
                           x 
                           max 
                         
                          
                       
                       
                         v 
                         bn 
                       
                     
                     · 
                     VO 
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     Description of an Alternate Embodiment of the Present Invention 
     D. Extended Method and Design for Auto-Associative Neural Network Recall Function 
     The Brain-State-in-a-Box (BSB) model is a typical auto-associative neural network. The mathematical model of the BSB recall function can be represented as:
 
 x ( t+ 1)= S (α· A·x ( t )+λ· x ( t ))  (16)
 
where x is an N dimensional real vector, and A is an N-by-N connection matrix. A·x(t) is a matrix-vector multiplication operation, which is the main function of the recall function. α is a scalar constant feedback factor. λ is an inhibition decay constant. S(y) is the “squash”
 
     
       
         
           
             
               
                 
                   
                     S 
                     ⁡ 
                     
                       ( 
                       y 
                       ) 
                     
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             1 
                             , 
                             if 
                           
                         
                         
                           
                             y 
                             ≥ 
                             1 
                           
                         
                       
                       
                         
                           
                             y 
                             , 
                             if 
                           
                         
                         
                           
                             
                               - 
                               1 
                             
                             &lt; 
                             y 
                             &lt; 
                             1 
                           
                         
                       
                       
                         
                           
                             
                               - 
                               1 
                             
                             , 
                             if 
                           
                         
                         
                           
                             y 
                             ≤ 
                             
                               - 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
     For a given input pattern x(0), the recall function computes Eq. (16) iteratively until convergence, that is, when all entries of x(t+1) are either “1” or “−1”. 
     Using the same method for general matrix-vector multiplication approximation described previously. Eq. (16) converts to:
 
 x ( t+ 1)= S ( A   +   ·x ( t )− A   −   ·x ( t )+ x ( t ))  (18)
 
Here, for the default case we set α=λ=1. The two connection matrices A +  and A −  can be mapped to two N-by-N memristor crossbar arrays M 3    100  and M 4    110  in a scaled version Â +  and Â − , respectively, by following the mapping method in Eq. (9) and Eq. (10).
 
     To realize the BSB recall function at the circuit level, the normalized input vector x(t) is converted to a set of input voltage signals V(t). The corresponding function for the voltage feedback system can be expressed as: 
                           V   ⁡     (     t   +   1     )       =       ⁢       S   ′     ⁡     (           A   ^     +     ·     V   ⁡     (   t   )         -         A   ^     -     ·     V   ⁡     (   t   )         +     V   ⁡     (   t   )         )                   =       ⁢       S   ′     ⁡     (         V     A   +       ⁡     (   t   )       -       V     A   -       ⁡     (   t   )       +     V   ⁡     (   t   )         )                     (   19   )               
v bn  represents the input voltage boundary, that is, −v bn ≦v i (t)≦v bn  for any v i (t)εV(t). The new saturation boundary function S′( ) needs to be modified accordingly as:
 
                 S   ′     ⁡     (   v   )       =     {             v   bn     ,   if           v   ≥     v   bn                 v   ,   if             -     v   bn       &lt;   v   &lt;     v   bn                   -     v   bn       ,   if           v   ≤     -     v   bn                       
In implementation, v bn  can be adjusted based on requirements for convergence speed and accuracy. Meanwhile, v bn  must be smaller than v th  so that the memristance values will not change during the recall process.
 
       FIG. 4  illustrates the BSB recall circuit built based on Eq. (19). The design is an analog system consisting of three major components. The selector (switch) selects V(0) as input voltage at the start of the recall computation, then selects V(t+1) afterward. We assume that “t” is discretized time, so we have t=0, 1, 2, . . . . After the output voltages are all converged, we reset t to 0 so that the circuit takes the new input V(0) to be computed (recalled). Below is the detailed description. 
     Memristor Crossbar Arrays: 
     As the key component of the overall design, the memristor crossbar arrays  100 ,  110  are used to approximate the matrix-vector multiplication functions in the BSB recall operation. To obtain both positive and negative weights in the original BSB algorithm in Eq. (16), two N-by-N memristor crossbar arrays M 3    100  and M 4    110  are required in the design to represent the connection matrices Â +  and Â − , respectively. The memristor crossbar arrays have the same dimensions as the BSB weight matrix A transposed. 
     Summation-Subtraction Amplifiers: 
     In the present invention, the input signal v i (t) along with v Â     +,i   (t) and v Â     −,i   (t), the corresponding voltage outputs of two memristor crossbar arrays  100 ,  110 , are fed into a summation-subtraction amplifier  80 . The design of the summation-subtraction amplifier circuit  80  can be found in  FIG. 5 . 
     Resulting from the decayed mapping method, the required v A     +,i   (t) and v A     −,i   (t) should be g s /g max  times of the generated v Â     +,i   (t) and v Â     +,i   (t), respectively. In the present invention R 1 =R 4 =R 6 =1/g s  and R 2 =R 3 =R 5 =R 7 =1/g max . The resulting output of the summation-subtraction amplifier  80  is: 
                             v   i     ⁡     (     t   +   1     )       =       ⁢           g   s       g   max       ·       v       A   ^       +     ,   i           ⁡     (   t   )         -         g   s       g   max       ·       v       A   ^       -     ,   i           ⁡     (   t   )         +       v   i     ⁡     (   t   )                     =       ⁢         v       A   +     ,   i       ⁡     (   t   )       -       v       A   -     ,   i       ⁡     (   t   )       +       v   i     ⁡     (   t   )                       (   20   )               
which indicates that the decayed effect has been canceled out. The N dimensional BSB model requires N summation-subtraction amplifiers  80  to realize the addition/subtraction operation in Eq. (20). Also, for the amplifiers, we should adjust their power supply levels to make their maximum/minimum output voltages to be equal to ±v bn , respectively. In the present invention the resistances R 1  through R 7  can be adjusted to match the required α and λ in Eq. (16), if they are not the default value 1.
 
     Comparator: 
     Once a new set of voltage signals V(t+1) is generated from the summation-subtraction amplifiers  80 , the present invention sends them back as the input of the next iteration. Meanwhile, each v i (t+1)εV(t+1) is compared to v bn  and −v bn  so that when v i  equals to either v bn  or −v bn , we deem the output i as having “converged”. The recall operation stops when all N outputs reach convergence. In total, N comparators  90  are needed to cover all the outputs. 
     There are three major physical constraints in the circuit implementation: (1) For any v i (0)εV(0), the voltage amplitude of initial input signal v i (0) is limited by the input circuit; (2) boundary voltage v bn  must be smaller than v th  of memristors  70 ; and (3) the summation-subtraction amplifier  80  has finite resolution. 
     In the BSB recall function, the ratio between boundaries of S(y) and the initial amplitude of x i (0), x i (0)εx(0) determines the learning space of the recall function. If the ratio is greater than the normalized value, the recall operation will take more iterations to converge with a higher accuracy. Otherwise, the procedure converges faster by lowering stability. Thus, minimizing the ratio of |v i (0)| and v bn  can help obtain the best performance. However, the real amplifier has a finite resolution and v bn  is limited within v th  of the memristor  70 . Continuously reducing |v i (0)| eventually will lose a significant amount of information in the recall circuit. 
     Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to these precise embodiments, and that various changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.
An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. Memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.