TECHNICAL FIELD 
     Embodiments of the present invention relate generally to integrated memory devices, and more specifically, to sense amplifiers that compensate for threshold voltage differences in the transistors of the sense amplifier. 
     BACKGROUND OF THE INVENTION 
     Memory devices are structured to have one or more arrays of memory cells that are arranged, at least logically, in rows and columns. Each memory cell stores data as an electrical charge that is accessed by a digit line associated with the memory cell. A charged memory cell, when the memory cell is accessed, causes a positive change in voltage on the associated digit line, and an accessed memory cell that is not charged causes a negative change in voltage on the associated digit line. The change in voltage on the digit line may be sensed and amplified by a sense amplifier to indicate the value of the data state stored in the memory cell. 
     Conventional sense amplifiers are typically coupled to a pair of complementary digit lines to which a large number of memory cells (not shown) are connected. As known in the art, when memory cells are accessed, a row of memory cells are activated and sense amplifiers are used to amplify a data state for the respective column of activated memory cells by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have complementary logic levels. 
     When a memory cell is accessed, the voltage of one of the digit lines increases or decreases slightly, depending on whether the memory cell coupled to the digit line is charged or not, resulting in a voltage difference between the digit lines. While the voltage of one digit line increases or decreases slightly, the other digit line does not and serves as a reference for the sensing operation. Respective transistors are enabled due to the voltage difference, thereby coupling the slightly higher voltage digit line to a supply voltage and the other digit line to a reference voltage, such as ground to further drive each of the digit lines in opposite directions and amplify the selected digit line signal. 
     The digit lines are precharged during a precharge period to a precharge voltage, such as one-half of a supply voltage, so that a voltage difference can be accurately sensed and amplified during a subsequent sensing operation. However, due to random threshold voltage mismatch of transistor components, the digit lines may be abruptly imbalanced before a voltage change is sensed and amplified on one of the digit lines. Such threshold voltage deviations can cause the sense amplifier to erroneously amplify input signals in the wrong direction. There is, therefore, a need for a sense amplifier design that reduces threshold voltage mismatches. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a portion of a sense amplifier and digit line arrangement. 
         FIG. 2  is a schematic diagram of a sense amplifier according to an embodiment of the invention. 
         FIGS. 3A and 3B  are schematic diagrams of the sense amplifier of  FIG. 2  during operation according to an embodiment of the invention. 
         FIG. 4  is a block diagram of a memory including a sense amplifier according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
       FIG. 1  illustrates a portion of a sense amplifier and digit line arrangement. A sense amplifier  110  is coupled to digit lines  120 ,  130 . Memory cells  140  are coupled through respective access devices (e.g., transistors)  150  to either the digit line  120  or  130 . In operation, a memory cell  140  is coupled to a digit line  120 ,  130  through the respective access device  150  in response to a respective word line  160  becoming active. A data state stored by the memory cell  140  is sensed by the sense amplifier  110  and amplified by driving the digit line to which that memory cell is coupled to a high or low voltage level corresponding to the sensed data state. The other digit line is driven to the complementary voltage level. 
       FIG. 2  is a schematic diagram of a sense amplifier  200  according to an embodiment of the invention. The sense amplifier  200  includes p-type field effect transistors (PFET)  210 ,  215  having drains coupled to drains of n-type field effect transistors (NFET)  220 ,  225 . The PFETs  210 ,  215  and NFETs  220 ,  225  form complementary transistor inverters. The PFETs  210 ,  215  are coupled through PFETs  240 ,  245  to a supply voltage (e.g., VCC) under the control of p-sense control signal PSA. The NFETs  220 ,  225  are coupled through respective NFETs  250 ,  255  to a reference voltage (e.g., ground) under the control of n-sense control NSA. A capacitance, such as a discrete  260 , couples the sources of NFETs  220 ,  225 . The sense amplifier  200  senses and amplifies the data state applied to input/output (IO) nodes  230 ,  235  through the digit lines  120 ,  130 , respectively. The IO nodes are also coupled through NFETs  270 ,  275  to a precharge voltage (e.g., VCC 2 , which is one-half of VCC) and through NFET  272  to each other under the control of an equilibration signal EQ. The NFETs  270 ,  272 ,  275  are used to “precharge” the sense amplifier  200  in preparation for a sense and amplify operation. 
     In operation, the sense amplifier  200  is precharged to a precharge voltage VCC 2  and the IO nodes  230 ,  235  are equilibrated by an active EQ signal. Additionally, the NFETs  250 ,  255  are biased by the NSA signal to provide resistance. That is, the voltage of the NSA signal places the NFETs  250 ,  255  into a linear region of operation and the transistors effectively behave as resistors. In this mode, the NFETs  220 ,  225  are effectively diode coupled to VCC 2  with the sources coupled to ground through a resistor, as illustrated in  FIG. 3A . As a result, the voltages at the sources of the NFETs  220 ,  225  is the VCC 2  voltage less the respective voltage threshold (VT) for each of the transistors: the voltage at the source of NFET  220  is (VCC 2 -VT( 220 )) and the voltage at the source of NFET  225  is (VCC 2 -VT( 225 )). Any VT imbalance between the NFETs  220  and  225  will result in a voltage difference between the sources of the NFETs that is stored by the capacitance  260 . The stored voltage difference stored by the capacitance  260  provides voltage compensation for VT mismatch of the NFETs  220 ,  225 . Following the setting of the VT mismatch compensation voltage at the sources of NFETs  220 ,  225 , the NFETs  250 ,  255  are made non-conductive to capture the voltages (VCC 2 -VT( 220 )), (VCC 2 -VT( 225 )) at the sources of NFETs  220 ,  225  as well as any voltage difference across the capacitance  260  as shown in  FIG. 3B . The EQ signal is deactivated to end the precharge operation resulting in both IO nodes  230 ,  235  set at the VCC 2  voltage. 
     Normal sense and amplify operations are then performed, but benefit from the VT mismatch compensation voltage to balance the response of the NFETs  220 ,  225 . For example, in response to a memory cell  140  being coupled to a digit line through its respective access device  150  ( FIG. 1 ), a voltage difference is created between the IO nodes  230 ,  235 . The voltage difference is sensed by NFETs  220 ,  225  as the sources of the NFETs  220 ,  225  begin to be pulled to ground through fully activated NFETs  250 ,  255 , and the NFET with a gate coupled to the IO node with the slightly higher voltage begins conducting. Assuming a memory cell coupled to the IO node  230  through the digit line stores a high data state, for example, the NFET  225  will begin conducting. Additionally, the other NFET becomes less conductive as the voltage of the other IO node with the slightly lower voltage decreases through the conducting NFET. With the VT mismatch compensation voltage stored by the capacitance  260  between the sources, the NFETs  220 ,  225  are in a balanced state of activation, and a smaller voltage difference across the IO nodes  230 ,  235  may be sensed because any VT mismatch between the NFETs  220 ,  225  does not need to be overcome by the voltage difference created at the IO nodes  230 ,  235  by the coupling of the memory cell to the digit line. 
     The PFETs  210 ,  215  are coupled to VCC through activated PFETs  240 ,  245 , and the PFET having a gate coupled to the IO node that is pulled to ground through the NFET (i.e., the IO node having the slightly lower voltage) becomes conductive to pull the other JO node (i.e., the IO node having the slightly higher voltage) to VCC. Using the previous example, the PFET  210  will begin conducting. The positive feedback resulting from the conductive PFET and NFET amplify the sensed state until the IO node initially having the slightly higher voltage is pulled to VCC and the IO node initially having the slightly lower voltage is pulled to ground. 
     An optional capacitance  265  may couple the sources of PFETs  210 ,  215  to provide VT mismatch compensation voltage for a VT mismatch between PFETs  210 ,  215 . During precharge, the PFETs  210 ,  215  are effectively diode coupled. With the PFETs  240 ,  245  biased by the PSA signal to provide resistance, the voltage developed at the sources will be VCC 2  plus the VT of the respective PFET  210 ,  215 . Any VT imbalance between the PFETs  210 ,  215  will result in a voltage difference between the sources of the PFETs that is stored by the capacitance. Operation to provide PFET VT mismatch compensation will be similar to that for providing NFET VT mismatch compensation as previously described. 
     In some embodiments, the frequency of developing a voltage difference across the capacitance  260  to provide VT mismatch compensation may occur with every precharge cycle of the sense amplifier  200 . In other embodiments, the frequency is less than every precharge cycle. Additionally, changing the capacitance  260  will alter the time a VT difference voltage is stored by the capacitance. 
       FIG. 4  illustrates a portion of a memory  400  according to an embodiment of the present invention. The memory  400  includes an array  402  of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other types of memory cells. The memory system  400  includes a command decoder  406  that receives memory commands through a command bus  408  and generates corresponding control signals within the memory system  400  to carry out various memory operations. Row and column address signals are applied to the memory system  400  through an address bus  420  and provided to an address latch  410 . The address latch then outputs a separate column address and a separate row address. 
     The row and column addresses are provided by the address latch  410  to a row address decoder  422  and a column address decoder  428 , respectively. The row address decoder  422  is connected to word line driver  424  that activates respective rows of memory cells in the array  402  corresponding to received row addresses. In response, memory cells of the array  402  are coupled to digit lines extending through the array  402  for the respective data states to be sensed by sense amplifiers  432 . The sense amplifiers  432  include at least one sense amplifier according to an embodiment of the invention. The column address decoder  428  selects the sense amplifier coupled to the digit lines corresponding to respective column addresses. The selected digit lines corresponding to a received column address are coupled to read/write circuitry  430  to provide read data to a data output buffer  434  via an input-output data bus  440 . Write data are applied to a data input buffer  444  and the memory array read/write circuitry  430 . The write data are written to the memory cells of the array  402  through the sense amplifiers  432 . The command decoder  406  responds to memory commands applied to the command bus  408  to perform various operations on the memory array  402 . In particular, the command decoder  406  is used to generate internal control signals to read data from and write data to the memory array  402 . 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.