BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory), and more particularly to a data interface device for accessing an SDRAM that can address a phase problem between a clock and data incurable at a high-speed SDRAM access time.  
         [0003]     2. Description of the Related Art  
         [0004]      FIG. 1  is a schematic diagram illustrating a typical connection state of a data bus and a clock for an SDRAM (Synchronous Dynamic Random Access Memory) interface. A timing diagram associated with  FIG. 1  is shown in  FIG. 2 . Input PADs  2  and  3  and output PADs  4  and  6  are provided between an SDRAM  1  and a memory controller  2 . As shown in  FIG. 2 , it can be seen that a board clock and board DATA are measured between the PAD of the SDRAM  1  and the memory controller  2 . That is, when an internal clock of the memory controller  2  is changed to a board level signal through the PADs, it can be seen that data has larger delay in comparison with the internal clock. This delay can be different according to various elements such as voltage, temperature, board state, etc.  FIG. 3  shows larger delay as compared with  FIG. 2 . The SDRAM  1  outputs data at a rising edge of the board clock. As shown in  FIGS. 2 and 3 , as a clock for driving the SDRAM  1  is delayed, input data has larger delay in comparison with the internal clock.  
         [0005]     When delay of a signal such as a clock or data is large, a time point of inputting internal DATA into the memory controller  2  can be the same as a time point of a rising edge of the internal clock as indicated by “V” in  FIG. 3 . That is, when the internal DATA is used with the internal clock, setup or hold violation can be incurred. To prevent this violation, there is present a method using a negative edge of the internal clock. However, the method has a problem in that data may be inputted at a time point of the negative edge of the internal clock as delay in the method is smaller than delay in  FIG. 3 .  
         [0006]     That is, this phenomenon occurs because a relationship between the internal clock and the data input is asynchronous. When the phenomenon cannot be removed, an operating frequency must be lowered according to an operating state, such that the lowered operating frequency may have a negative effect on the performance of a device.  
         [0007]     In many methods for preventing the negative effect, a DLL (Delay Locked Loop) circuit  7  is used as shown in FIG.  4 . When the DLL circuit  7  is used, externally inputted data can be predicted to some degree because an external clock (i.e., a board clock) and an internal clock can be matched to each other. Consequently, the above-described asynchronous problem can be avoided. In particular, there are problems in that a design of the DLL circuit  7  requires complicated technology differently from general circuits and it is very difficult for replica delay in PADs, pins, etc. to be predicted.  
       SUMMARY OF THE INVENTION  
       [0008]     Therefore, the present invention has been made in view of the above and other problems, and it is an object of the present invention to provide a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory) that uses a clock for the SDRAM and a selective data capturing method so that an operating rate of an SDRAM interface can be improved and data can be matched at SDRAM data input and output times.  
         [0009]     In accordance with an aspect of the present invention, the above and other objects can be accomplished by the provision of a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory), comprising: a clock used in the SDRAM; and selective data capturing, wherein the clock and the selective data capturing are used to improve an operating rate of an SDRAM interface and to match data at SDRAM data input and output times. Preferably, the clock is used to drive the SDRAM, and is a feedback clock used for synchronization in an SDRAM controller as well as the SDRAM. Preferably, the feedback clock is generated from the SDRAM controller through a sequential path of an output pad, the SDRAM, and an input pad and is used for approximating a clock when an external SDRAM is used and an output data time point of the SDRAM.  
         [0010]     Preferably, the selective data capturing uses a register part for storing data inputted into the SDRAM. Preferably, the register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock. Preferably, an inverter is provided in an input stage of one of the registers so that phases of feedback clocks inputted into the registers can be different. Preferably, a cycle of the feedback clock is set to two to four times that of a main clock so that an operation can be ensured. Preferably, the stored data is selected using a signal generated by the internal clock.  
         [0011]     Preferably, the register part comprises: a first T flip-flop for receiving a generated internal clock and outputting an internal clock selection signal; a second T flip-flop for receiving a feedback clock in which a board clock delayed through a pad from the internal clock is fed back and outputting a feedback clock selection signal; a first AND element for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal outputted from the second T flip-flop; a second AND element for simultaneously receiving the feedback clock and the feedback clock selection signal outputted from the second T flip-flop; a first D flip-flop for simultaneously receiving a clock outputted from the first AND element and data; a second D flip-flop for simultaneously receiving a clock outputted from the second AND element and data; a data selection element for selecting one of data outputted from the first D flip-flop and data outputted from the second D flip-flop in response to the internal clock selection signal outputted from the first T flip-flop; and a third D flip-flop for simultaneously receiving the internal clock and the data outputted from the data selection element and outputting the data in response to the internal clock. Preferably, the data interface device further comprises: an inverter coupled between the first AND element and a contact point coupled to an input terminal of the second AND element and an output terminal of the second T flip-flop, the inverter generating the inversion signal of the feedback clock selection signal. Preferably, the data interface device further comprises: a third AND element for simultaneously receiving a command signal and the internal clock, carrying out an operation and outputting a result of the operation to a reset terminal of the first T flip-flop; and a fourth D flip-flop for simultaneously receiving the command signal and the internal clock, carrying out an operation and outputting a result of the operation to a reset terminal of the second T flip-flop, wherein the third AND element and the fourth D flip-flop are configured to perform reset control of the first and second T flip-flops outputting the internal clock selection signal and the feedback clock selection signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0013]      FIG. 1  is a schematic diagram illustrating a typical connection state of a data bus and a clock for an SDRAM (Synchronous Dynamic Random Access Memory) interface;  
         [0014]      FIG. 2  is a timing diagram illustrating data delay due to board clock delay;  
         [0015]      FIG. 3  is a timing diagram illustrating a case where setup or hold violation is caused by increased delay;  
         [0016]      FIG. 4  is a circuit diagram illustrating a control circuit for matching phases of an internal clock and a board clock using a DLL (Delay Locked Loop);  
         [0017]      FIG. 5  is a block diagram illustrating a data interface device for accessing an SDRAM;  
         [0018]      FIG. 6  shows a timing diagram associated with the data interface device for accessing the SDRAM;  
         [0019]      FIGS. 7A  to  7 D are timing diagrams illustrating the motion of data according to a phase difference between an internal clock and a feedback clock; and  
         [0020]      FIGS. 8A  to  8 D are timing diagrams illustrating reset signals and signals select_i and select_f according to feedback clock delay. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]     Now, preferred embodiments of the present invention will be described in detail with reference to the annexed drawings.  
         [0022]      FIG. 5  shows a circuit for addressing an asynchronous problem between an internal clock and a data input described in “Description of the Related Art”. Referring to  FIG. 5 , a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory) in accordance with the present invention comprises a register part  10  and a reset part  20 . The register part  10  uses a board clock fed back as a clock used in the SDRAM. Moreover, the register part  10  uses selective data capturing and stores data inputted from the SDRAM. Moreover, the register part  10  uses double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock. This configuration will be described below in detail.  
         [0023]     The register part  10  includes a first T flip-flop  101  for receiving a generated internal clock and outputting an internal clock selection signal “select_i”; a second T flip-flop  102  for receiving a feedback clock in which a board clock delayed through a PAD from the internal clock is fed back and outputting a feedback clock selection signal “select_f”; a first AND element  103  for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal “select_f” outputted from the second T flip-flop  102 ; a second AND element  104  for simultaneously receiving the feedback clock and the feedback clock selection signal “select_f” outputted from the second T flip-flop  102 ; a first D flip-flop  106  for simultaneously receiving a clock outputted from the first AND element  103  and data; a second D flip-flop  107  for simultaneously receiving a clock outputted from the second AND element  104  and data; a data selection element  108  for selecting one of data outputted from the first D flip-flop  106  and data outputted from the second D flip-flop  107  in response to the internal clock selection signal “select_i” outputted from the first T flip-flop  101 ; and a third D flip-flop  109  for simultaneously receiving the internal clock and the data outputted from the data selection element  108  and outputting the data in response to the internal clock. Here, the register part  10  further comprises an inverter  105  between the first AND element  103  and a contact point coupled to the second AND element  104  and the second T flip-flop  102 .  
         [0024]     The reset part  20  comprises a third AND element  201  for simultaneously receiving a command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the first T flip-flop  101 ; and a fourth D flip-flop  202  for simultaneously receiving the command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the second T flip-flop  102 .  
         [0025]     As described above, the feedback clock in  FIG. 5  is the board clock used for operating the SDRAM in  FIG. 1  re-inputted into the controller. Moreover, a signal corresponding to internal DATA in  FIG. 1  is DATA_IN in  FIG. 5 . DATA_IN is stored in response to the internal clock as DATA in  FIG. 5 .  
         [0026]     Assuming that a difference between delay of an input path of external DATA and delay of an input path of a clock is small, a problem in storing DATA_IN is not incurred when the feedback clock is used. However, when DATA is stored, a phase relationship between the feedback clock and the internal clock may be a problem. This problem can be addressed using the circuit structure of  FIG. 5 .  
         [0027]     There is a problem in that DATA associated with the internal clock may not be stabilized when DATA captured by the feedback clock is used in the internal clock. Thus, DATA is used in the next internal clock after being captured by the feedback clock in accordance with the present invention. For this, DATA must be stored once during two clocks. Double registers can be alternately used. A signal for selecting a register must be generated according to the feedback clock so that no asynchronous problem is incurred. This is shown in  FIG. 6 . As shown in  FIG. 6 , DATA_F 0  and DATA_F 1  are stored once during two clocks in response to the feedback clock selection signal “select_f”, respectively. DATA_F outputted from the data selection element is inputted into the third D flip-flop  109  in response to the internal clock selection signal “select_i”. Consequently, DATA is outputted in response to the internal clock selection signal “select_i”.  
         [0028]      FIGS. 7A  to  7 D are timing diagrams illustrating the motion of data according to a phase difference between an internal clock and a feedback clock.  FIG. 7A  shows the case where a phase difference between the internal clock and the feedback clock is smaller than half a clock.  FIG. 7B  shows the case where a phase difference between the internal clock and the feedback clock is accurately half a clock cycle.  FIGS. 7C and 7D  show a data interface when a delay value is relatively large. In particular,  FIG. 7D  shows the case where a phase difference between the internal clock and the feedback clock is one clock.  
         [0029]     It can be seen that DATA stored according to a feedback operation in relation to various types of delay shown in  FIGS. 7A  to  7 D does not cause violation due to the internal clock when using the structure shown in  FIG. 5 .  
         [0030]     However, when the feedback clock selection signal “select_f” is generated by the feedback clock, no problem occurs in a clock control process. The internal clock selection signal “select_i” for deciding internal data between two data units DATA_F 0  and DATA_F 1  must be generated by the internal clock. In this case, because motion between the signals “select_i” and “select_f” plays an important role as shown in  FIGS. 7A  to  7 D, reset signals to be inputted into two flip-flops must be appropriately generated. Because the motion between the signals “select_i” and “select_f” can be different according to a phase difference between two clocks, there is a problem in that a reset signal cannot be generated by each clock.  
         [0031]     To address this problem, a circuit such as the reset part  20  shown in  FIG. 5  can be implemented. Here, a reset signal is generated according to a command signal. A command that is inherently generated at a rising edge of the internal clock and is stored at a falling edge of the internal clock is referred to as “CMD”.  
         [0032]     That is, a reset input of a flip-flop for generating the signal “select_i” is generated by ANDing the CMD and a high-level internal clock. A reset input of a flip-flop for generating the signal “select_f” uses the CMD stored at a negative edge of the internal clock.  FIGS. 8A  to  8 D show reset signals and motion between the signals “select_i” and “select_f” according to feedback delay shown in  FIGS. 7A  to  7 D.  
         [0033]     As apparent from the above description, the input rate of DATA associated with a used clock decreases as an existing memory access rate increases, such that violation may occur when DATA is stored. Because a DATA input time and an internal clock are not influenced by each other in a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory) in accordance with the present invention, an operating frequency can be increased without a complex circuit such as a DLL (Delay Locked Loop) circuit that cannot easily be designed.  
         [0034]     Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.  
         [0035]     The entire content of Priority Document No. 10-2003-72893 is incorporated herein by reference.
Disclosed is a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory). A clock and selective data capturing are used to improve an operating rate of an SDRAM interface and to match data at SDRAM data input and output times. A clock used for driving the SDRAM uses a feedback clock for synchronization in an SDRAM controller as well as the SDRAM as a clock used to drive the SDRAM. The selective data capturing uses a register part for storing data inputted into the SDRAM. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.