BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a memory controller, and in particular to a memory control technique supporting a plurality of different specifications of random access memory (RAM).  
           [0003]    2. Description of the Related Art  
           [0004]    With increasing the speed of CPUs, the demand for high-speed dynamic RAM (DRAM) is growing and thereby various types of DRAM have been developed and put in use. A well-known type of DRAM is a synchronous DRAM (SDRAM) which transfers data synchronously with an external clock signal. In SDRAM, the data transfer timing for read and write operations is synchronized with the rising edge of the external clock signal. Current information processing systems such as PC systems are typically designed to use SDRAM.  
           [0005]    As a next generation DRAM, there are considered a Rumbus DRAM for personal computers and a double data rate (DDR) SDRAM for servers. In DDR SDRAM, the data transfer timing for read and write operations is synchronized with the rising and falling edges of the clock signal or data strobe signal. Since SDRAM employs a rising edge of the clock signal, a memory controller designed for SDRAM is not applied to DDR SDRAM. Accordingly, it is desirable to provide compatibility for both SDRAM and DDR SDRAM within the same system.  
           [0006]    To provide such compatibility, a semiconductor memory device selectively operating in a single data rate (SDR) mode and a DDR mode has been disclosed in Japanese Patent Application Unexamined Publication No. 10-302465. More specifically, the semiconductor memory device is provided with an operation controller which selects one of the SD mode and the DDR mode depending on an external adjustment signal. When the SDR mode is selected, pulses are generated at timing corresponding to one edge of a system clock signal. In the case of the DDR mode selected, pulses are generated at timing corresponding to both edges of the system clock signal.  
           [0007]    However, the conventional mode selection mechanism is incorporated within the semiconductor memory device. Accordingly, memory manufacturing steps become complicated, resulting in increased cost of manufacturing. Taking into consideration progression of technical innovation in the field of memory, it is necessary to enhance general versatility and extensibility in a memory controller to handle different types of memory which may be developed in the future.  
         SUMMARY OF THE INVENTION  
         [0008]    An object of the present invention is to provide a memory controller and control method having general versatility and enhanced extensibility, allowing different types of memory devices to be supported.  
           [0009]    According to the present invention, a memory controller separately from a memory device to be controlled is provided with a function of supporting different types of memory devices.  
           [0010]    According to an aspect of the present invention, a memory controller for controlling data communication with a memory device, includes: a timing adjuster for adjusting timing of data transfer between the memory device and a data bus depending on a timing control signal; and a mode controller for controlling the timing control signal to meet timing requirement of the memory device depending on a mode selection signal inputted from outside.  
           [0011]    The memory controller may further include a level adjuster for adjusting a voltage level of data to be transferred between the memory device and the data bus depending on a type of the memory device.  
           [0012]    According to another aspect of the present invention, a memory controller includes: a first buffer for capturing data at a rising edge of a timing control signal; a second buffer for capturing data at a falling edge of the timing control signal; and a mode controller for controlling the timing control signal to meet timing requirement of the memory device depending on a mode selection signal inputted from outside.  
           [0013]    The mode controller may select one of a clock signal and a data strobe signal as the timing control signal depending on the mode selection signal. In the case where the memory device is a synchronous RAM (random access memory), the mode controller selects the clock signal to supply it as the timing control signal to the first buffer. In the case where the memory device is a double data rate (DDR) synchronous RAM, the mode controller selects the data strobe signal to supply it as the timing control signal to the first and second buffers.  
           [0014]    The memory controller may further include a level adjuster for adjusting a voltage level of data to be transferred between the memory device and the data bus depending on a type of the memory device.  
           [0015]    According to still another aspect of the present invention, an interface device connecting a processor and a memory device through a bus, includes: a memory controller for controlling data communication with the memory device, wherein the memory controller comprises: a timing adjuster for adjusting timing of data transfer between the memory device and a data bus depending on a timing control signal; and a mode controller for controlling the timing control signal to meet timing requirement of the memory device depending on a mode selection signal inputted from outside.  
           [0016]    According to further another aspect of the present invention, a control method for controlling data communication with a memory device, includes the steps of: a) storing data in a first buffer at a rising edge of a timing control signal; b) storing the data in a second buffer at a falling edge of the timing control signal; and a) controlling the timing control signal to meet timing requirement of the memory device depending on a mode selection signal inputted from outside. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a schematic diagram showing a mode selection operation according to the present invention;  
         [0018]    [0018]FIG. 2 is a block diagram showing an example of an information processing system employing a memory controller according to an embodiment of the present invention;  
         [0019]    [0019]FIG. 3 is a block diagram showing an internal circuit of the memory controller according to the embodiment;  
         [0020]    [0020]FIG. 4 is a block diagram showing an internal circuit of a data buffer in the memory controller of FIG. 3;  
         [0021]    FIGS.  5 A- 5 D are tine charts showing a DDR-mode read operation in the embodiment;  
         [0022]    FIGS.  6 A- 6 C are time charts showing an SDRAM-mode read operation in the embodiment;  
         [0023]    FIGS.  7 A- 7 D are time charts showing a DDR-mode write operation in the embodiment; and  
         [0024]    FIGS.  8 A- 8 C are time charts showing an SDRAM-mode write operation in the embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]    Referring to FIG. 1, a memory controller according to the present invention is designed to support a plurality of memories A, B, . . . , which have different specifications, for example, single data rate synchronous RAM such as SDRAM, double data rate RAM such as DDR SDRAM, static RAM (SRAM), DDR SRAM, and so on. The memory controller can be set to a selected one of a plurality of internal states each corresponding to the different-type memories depending on a mode selection signal received from outside. The details of the memory controller will be described hereafter, taking as an example the case where both SDRAM and DDR SDRAM are supported.  
         [0026]    System configuration  
         [0027]    Referring to FIG. 2, an information processing system includes an interface section  1 , a CPU  2 , a memory  3 , and a flash memory  4 . The interface section  1  is composed of a memory controller  11  according to the present invention, device interfaces to the CPU  2 , the flash RAM  4 , and PCI bus, and registers for function setting, factor indication and the like. The CPU  2  performs data read and write of the memory  3  and flash RAM  4  through the interface section  1 . In this example, the memory  3  is one of SDRAM and DDR SDRAM, which may be used as a work memory in the system. The flash RAM  4  may previously store necessary data such as programs and various control data.  
         [0028]    The interface section  1  and the CPU  2  may be formed as an integrated circuit on a single semiconductor substrate. The interface section  1  and the CPU  2  may be formed individually as an integrated circuit. As described before, the memory controller  11  is supplied with the mode selection signal. For example, when the mode selection signal is high, the internal state of the memory controller  11  is changed to SDRAM mode and, when low, it is changed to DDR mode.  
         [0029]    Accordingly, even if the memory  3  is changed from SDRAM to DDR SDRAM, the memory controller  11  allows data communication with the memory  3  without changing specifications of CPU and DDR SDRAM.  
         [0030]    Memory controller  
         [0031]    Referring to FIG. 3, a delay-locked loop circuit  12  supplies the memory controller  11  with a necessary internal clock signal. Further, a power supply circuit (not shown) supplies the memory controller  11  with a power supply voltage.  
         [0032]    The memory controller  11  is provided with a control signal generator  31 , which supplies respective control signals to address/data switch  35 , address signal generator  34 , and data buffer  36  in response to control data received from selector  32  and refresh circuit  33 . The selector  32  determines access mode from data and address data on an address/data bus to output access mode control data to the control signal generator  31 . The refresh circuit  33  generates refresh timing control data from data and address data on an address/data bus and outputs it to the control signal generator  31 .  
         [0033]    The CPU  2  supplies data and address data to the selector  32 , the refresh circuit  33  and the address/data switch  35  through the address/data bus. The address/data switch  35  divides data and address data on the address/data bus respectively to the data buffer  36  and the address signal generator  34  depending on the control signal from the control signal generator  31 . The address signal generator  34  inputs the address data from the address/data switch  35  to generate an address signal based on the control signal received from the control signal generator  31 . The address signal is output to the memory  3 .  
         [0034]    The data buffer  36  receives the mode switch signal from outside and further a clock signal and a data strobe signal from the control signal generator  31 . The data buffer  36  has a bidirectional data port and a bidirectional data strobe port, which are connected to the memory  3  through the level adjuster  37 . The data buffer  36  performs data input/output timing adjustment depending on which one of SDRAM mode and DDR mode is selected which will be described later. Therefore, the data buffer  36  may be referred to as a timing adjuster. Here, when the mode switch signal is high, the data buffer  36  is set to SDRAM mode, allowing data read and write of SDRAM. When the mode switch signal is low, the data buffer  36  is set to DDR mode, allowing data read and write of DDR SDRAM.  
         [0035]    The level adjuster  37  includes two pairs of input and output amplifiers, the respective two pairs corresponding to the bidirectional data port and the bidirectional data strobe port of the data buffer  36 . Each pair of the input and output amplifiers is supplied with an I/O power supply voltage depending on which one of SDRAM and DDR SDRAM is connected as the memory  3 . In the case where the memory  3  is a SDRAM, the voltage relationship related to I/O signals is set to a level of LVTTL (Low Voltage Transistor Transistor Logic). On the other hand, in the case where the memory  3  is a DDR SDRAM, the voltage relationship related to I/O signals is set to a level of SSTL-2 (Series Stub Termination Logic-2). Such a level interface circuit supporting both LVTTL and SSTL has been disclosed in Japanese Patent Application Unexamined Publication No. 11-58146.  
         [0036]    In SDRAM-mode write operation, the data is output from the address/data switch  35  to the data buffer  36 , in which the output timing of the data is adjusted so as to meet the SDRAM-mode requirement. The voltage level of data outputted from the data buffer  36  is adjusted to the LVTTL level by the level adjuster  37  and then the data is written onto the memory  3  (here, SDRAM).  
         [0037]    In DDR-mode write operation, the data is output from the address/data switch  35  to the data buffer  36 , in which the output timing of the data is adjusted so as to meet the DDR-mode requirement. The voltage level of the data and data strobe outputted from the data buffer  36  is adjusted to the SSTL-2 level by the level adjuster  37 . Thereafter, the data and the data strobe signals are output to the memory  3  (here, DDR SDRAM). In this manner, the data is written onto the memory  3 .  
         [0038]    In SDRAM-mode read operation, data read out from the memory  3  (here, SDRAM) is adjusted in voltage to a CPU-side voltage level at the level adjuster  37  and then is adjusted in timing at the data buffer  36 . The timing-adjusted data is output from the data buffer  36  to the CPU  2  through the address/data switch  35  and the address/data bus.  
         [0039]    In DDR-mode read operation, data and data strobe signals read out from the memory  3  (here, DDR SDRAM) are adjusted in voltage to a CPU-side voltage level at the level adjuster  37 . The data is adjusted in timing depending on the data strobe signal at the data buffer  36 . The timing-adjusted data is output from the data buffer  36  to the CPU  2  through the address/data switch  35  and the address/data bus.  
         [0040]    Data buffer  
         [0041]    Referring to FIG. 4, the data buffer  36  includes a mode controller  41 , a rising-edge buffer  42 , and a falling-edge buffer  43 . The mode controller  41  inputs the clock signal and data strobe signal from the control signal generator  31  and further inputs the mode switch signal from outside.  
         [0042]    When the mode switch signal is high, that is, in SDRAM mode, the mode controller  41  supplies the clock signal to only the rising-edge buffer  42  Accordingly, data received from the CPU  2  is captured and stored in the rising-edge buffer  42  at the rising edge of the clock signal, allowing transfer timing of the data to be adjusted so as to meet the SDRAM requirement.  
         [0043]    When the mode switch signal is low, that is, in DDR mode, the mode controller  41  supplies an input data strobe signal to both the rising-edge buffer  42  and the falling-edge buffer  43  and further outputs it as an output data strobe to the memory  3  through the level adjuster  37 . Accordingly, data received from the CPU  2  is captured and stored in the rising-edge buffer  42  at the rising edge of tho data strobe signal and is captured and stored in the falling-edge buffer  43  at the falling edge of the data strobe signal, allowing transfer timing of the data to be adjusted so as to meet the DDR SDRAM requirement.  
         [0044]    The mode switch operation as described above may be implemented by a mode switch program running on a program-controlled processor.  
       OPERATION  
       [0045]    Hereafter, read and write operations and mode switch operation of the embodiment will be described with reference to FIGS.  5 - 8 , taking as an example the case where CAS (column address strobe) latency CL is 2 and burst length BL is 4. The CAS latency CL is defined as the number of clocks needed until data issued at a point of time when a read command has issued. The burst length BL is defined as the number of consecutive data.  
         [0046]    DDR-mode read operation  
         [0047]    Referring to FIGS.  5 A- 5 D, when a read (R) command is issued at clock timing t0, a data strobe signal from the DDR memory  3  goes low for a preamble section at clock timing t2, which is two clocks after the read command issue because of CL=2. After a lapse of one clock, the data strobe signal goes high for clock timing t3. At the rising edge of the data strobe signal, first data D 0  from the DDR memory  3  is captured and stored in the rising-edge buffer  42  of the data buffer  36 . Subsequently, when the data strobe signal goes low between t3 and t4, second data D 1  from the DDR memory  3  is captured and stored in the falling-edge buffer  43  of the data buffer  36 .  
         [0048]    Similarly, at the next rising edge of the data strobe signal for clock timing t4, third data D 2  from the DDR memory  3  is captured and stored in the rising-edge buffer  42  of the data buffer  36 . Subsequently, at the next falling edge of the data strobe signal between t4 and t5, fourth data D 3  from the DDR memory  3  is captured and stored in the falling-edge buffer  43  of the data buffer  36 .  
         [0049]    SDRAM-mode read operation  
         [0050]    Referring to FIGS.  6 A- 6 C, in SDRAM mode, the data strobe signal is not used. Only a rising edge of the clock signal is used to read data from the SCRAM memory  3 . Accordingly, the falling-edge buffer  43  is not used in the SDRAM mode.  
         [0051]    More specifically, when a read (R) command is issued at clock timing t0, first data D 0  is output from the DDR memory  3  at clock timing t2, which is two clocks after the read command issue because of CL=2. The first data D 0  is captured and stored in the rising-edge buffer  42  at clock timing t3. Similarly, second data D 1  is captured and stored in the rising-edge buffer  42  at clock timing t4, and subsequently third data D 2  and fourth data D 3  are captured and stored in the rising-edge buffer  42  at clock timing t5 and t6, respectively.  
         [0052]    DDR-mode write operation  
         [0053]    Referring to FIGS.  7 A- 7 D, when a write (W) command is issued at clock timing t0, an input data strobe signal goes low for a preamble section at clock timing t1. After a lapse of one clock, the data strobe signal goes high synchronously with clock timing t2 and first data D 0  is output from the rising-edge buffer  42  of the data buffer  36  to the DDR memory  3 . Subsequently, when the data strobe signal goes low between t2 and t3, second data D 1  is output from the falling-edge buffer  43  of the data buffer  36  to the DDR memory  3 . In this manner, a predetermined number of data D 0 -D 3  (here, BL=4) are written onto the DDR memory  3  while synchronizing the data strobe signal with the clock signal.  
         [0054]    SDRAM-mode write operation  
         [0055]    Referring to FIGS.  8 A- 8 C, in SDRAM mode, the data strobe signal is not used. Accordingly, when a write (W) command is issued at clock timing t0, first data D 0  is output from the rising-edge buffer  42  of the data buffer  36  to the DDR memory  3 . Similarly, second to fourth data D 1 -D 3  are sequentially written onto the DDR memory  3  synchronously with clock timing t1 to t3 of the clock signal.  
         [0056]    As described above, in SDRAM mode, no data strobe signal is used and therefore the mode controller  41  does not supply the data strobe signal to the rising-edge and falling edge buffers  42  and  43 . Accordingly, there is no need of masking control of data strobe signal.  
         [0057]    In the above embodiment, the case of DRAM was described. However, the present invention can be also applied to the case of SRAM because DDR-SRAM is provided. Further, the present invention can be also applied to the case of three or more types of memories.
A memory controller having general versatility and enhanced extensibility to allow different types of memory devices to be supported is disclosed. The memory controller has a first buffer for capturing data at a rising edge of a timing control signal and a second buffer for capturing data at a falling edge of the timing control signal. A mode controller controls the timing control signal depending on which one of SDRAM mode and DDR mode. In SDRAM mode, a clock signal is supplied to only the first buffer. In DDR mode, a data strobe signal is supplied to both the first and second buffers.