CROSS-REFERENCE TO RELATED APPLICATION 
   This application is claiming under 35 USC 119(e) the benefit of provisional patent application Ser. No. 60/388,249 filed on Jun. 12, 2002. 


   FIELD OF THE INVENTION 
   The present invention relates to reducing the time-to-market concerns for embedded system design. 
   BACKGROUND OF THE INVENTION 
   The electronics industry has become increasingly driven to meet the demands of high-volume consumer applications, which comprise a majority of the embedded systems market. Embedded systems face challenges in producing performance with minimal delay, minimal power consumption, and at minimal cost. As the numbers and types of consumer applications where embedded systems are employed increases, these challenges become even more pressing. Examples of consumer applications where embedded systems are employed include handheld devices, such as cell phones, personal digital assistants (PDAs), global positioning system (GPS) receivers, digital cameras, etc. By their nature, these devices are required to be small, low-power, light-weight, and feature-rich. 
   In the challenge of providing feature-rich performance, the ability to update the product&#39;s capabilities with advancements in a given industry to meet customer needs remains desirable. However, significant time in incurred as each design goes through the development process and reaches the market. Any reduction in the time-to-market for embedded processing products to meet the needs of the customer is considered beneficial. Accordingly, what is needed is a manner of reducing the time-to-market concerns for embedded processing solutions that attack particular application spaces. The present invention addresses such a need. 
   SUMMARY OF THE INVENTION 
   Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine. 
   With the aspects of the present invention, supplementation of an existing infrastructure for an embedded system with individualized/proprietary functionality reduces the time needed to develop a signal processing product to meet a particular market need. Such time savings is of considerable value in the rapidly changing environment of the embedded system market. These and other advantages will become readily apparent from the following detailed description and accompanying drawings. 


   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating an adaptive computing engine. 
       FIG. 2  illustrates a network architecture in accordance with the present invention. 
       FIG. 3  illustrates a block diagram of the elements of the nodal architecture in a preferred embodiment for a single node. 
       FIG. 4  illustrates signals for the interfaces within a node between the node wrapper unit, the node memory unit, and the node execution unit in accordance with a preferred embodiment of the present invention. 
       FIGS. 5   a  and  5   b  present tables of the signals, signal directions, and signal description for the node wrapper unit and memory unit interface signals shown in  FIG. 4 . 
       FIGS. 6   a ,  6   b ,  6   c ,  6   d ,  6   e ,  6   f , and  6   g  present tables for the signals, signal directions, and signal descriptions for node wrapper unit and execution unit interface signals shown in  FIG. 4 . 
   


   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention relates to reducing the time-to-market concerns for embedded system design. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein. 
   In order to reduce the time-to-market of an embedded system design/signal processing product, the present invention utilizes a homogeneous, scalable, extreme bandwidth network that connects heterogeneous nodes (computational elements), intelligent memory controllers, and configurable input/output ports and system bus interfaces, as described in co-pending U.S. patent application Ser. No. 10/241,511, entitled Method and System for an Interconnection Network to Support Communications among a Plurality of Heterogeneous Processing Elements, filed Sep. 10, 2002, assigned to the assignee of the present invention and incorporated by reference in its entirety herein. Portions of that description are reproduced hereinbelow for clarity of presentation of the aspects of the present invention. 
   Referring to  FIG. 1 , a block diagram illustrates an adaptive computing engine (“ACE”)  100 , which is preferably embodied as an integrated circuit, or as a portion of an integrated circuit having other, additional components. In the preferred embodiment, and as discussed in greater detail below, the ACE  100  includes a controller  120 , one or more reconfigurable matrices  150 , such as matrices  150 A through  150 N as illustrated, a matrix interconnection network  10 , and preferably also includes a memory  140 . 
   The controller  120  is preferably implemented as a reduced instruction set (“RISC”) processor, controller or other device or IC capable of performing the two types of functionality. The first control functionality, referred to as “kernal” control, is illustrated as kemal controller (“KARC”)  125 , and the second control functionality, referred to as “matrix” control, is illustrated as matrix controller (“MARC”)  130 . 
   The various matrices  150  are reconfigurable and heterogeneous, namely, in general, and depending upon the desired configuration: reconfigurable matrix  150 A is generally different from reconfigurable matrices  150 B through  150 N; reconfigurable matrix  150 B is generally different from reconfigurable matrices  150 A and  150 C through  150 N; reconfigurable matrix  150 C is generally different from reconfigurable matrices  150 A,  150 B and  150 D through  150 N, and so on. The various reconfigurable matrices  150  each generally contain a different or varied mix of computation units, which in turn generally contain a different or varied mix of fixed, application specific computational elements, which may be connected, configured and reconfigured in various ways to perform varied functions, through the interconnection networks. In addition to varied internal configurations and reconfigurations, the various matrices  150  may be connected, configured and reconfigured at a higher level, with respect to each of the other matrices  150 , through the matrix interconnection network (MIN)  110 . 
   In accordance with the present invention, the MIN  110  provides a foundation that allows a plurality of heterogeneous processing nodes, e.g., matrices  150 , to communicate by providing a single set of wires as a homogeneous network to support plural services, these services including DMA (direct memory access) services, e.g., Host DMA (between the host processor and a node), and Node DMA (between two nodes), and read/write services, e.g., Host Peek/Poke (between the host processor and a node), and Node Peek/Poke (between two nodes). In a preferred embodiment, the plurality of heterogeneous nodes is organized in a manner that allows scalability and locality of reference while being fully connected via the MIN  110 . U.S. patent application Ser. No. 09/898,350 entitled Method and System for an Interconnection Network to Support Communications Among a Plurality of Heterogeneous Processing Elements filed on Jul. 3, 2001, discusses an interconnection network to support a plurality of processing elements and is incorporated by reference herein. 
     FIG. 2  illustrates a network architecture  200  in accordance with the present invention. In this embodiment there are four groupings  210 - 280  of nodes. As is seen, grouping  210 - 240  can communicate with MIN  272  and groupings  250 - 280  communicate with MIN  274 . MINs  272  and  274  communicate with the network root  252 . A MIN  110  further supports communication between nodes in each grouping and a processing entity external to the grouping  210 , via a network root  252 . The network root  250  is coupled to a K-Node  254 , network input and output I/O blocks  256  and  258 , system interface I/O blocks  261 , a SRAM memory controller  262 , and an on/chip bulk RAM/bulk memory  264 . In a preferred embodiment, the organization of nodes as a grouping  210 - 280  can be altered to include a different number of nodes and can be duplicated as desired to interconnect multiple sets of groupings, e.g., groupings  230 ,  240 , and  250 , where each set of nodes communicates within their grouping and among the sets of groupings via the MIN  110 . 
   This ability to interconnect different nodes in a flexible and seamless manner provides structured support within which flexibility exists for customization of function, i.e., the structure and flexibility of the infrastructure of the MIN  110  is conducive for achieving structure and flexibility within each node of the MIN  110 . Referring now to  FIG. 3 , the elements of the nodal architecture in a preferred embodiment are illustrated for a single node  301 . The node wrapper  303  provides all support services for the nodes, including network interfacing, PEEK/POKE support, DMA, etc., through its pipelines  305  coupled to a network input and a network output and its data distributor  307 , hardware task manager  309 , DMA engine  311 , and data aggregator  313 . Through an API, the node wrapper  303  interfaces seamlessly to execution unit  315 /memory unit  317  combinations within the node  301 . 
     FIG. 4  illustrates signals for the interfaces within a node between the node wrapper unit  303 , the node memory unit  317 , and the node execution unit  315  in accordance with a preferred embodiment of the present invention. While  FIGS. 5   a  and  5   b  present tables of the signals, signal directions, and signal description for the node wrapper unit and memory unit interface signals shown in  FIG. 4 , and  FIGS. 6   a ,  6   b ,  6   c ,  6   d ,  6   e ,  6   f , and  6   g  present tables for the signals, signal directions, and signal descriptions for node wrapper unit and execution unit interface signals shown in  FIG. 4 , it should be appreciated that the names and number of bits for each signal are illustrative and not restrictive. Further, the descriptions of the signals illustrate the transactions anticipated as necessary for achieving robust processing by the node, as is well appreciated by those skilled in the art. 
   With these interfaces common within each node and across the node network, the integration of a particular execution unit  315  readily occurs by exploiting the set of interfaces. Thus, individual and proprietary designs need only address the functions required by the execution unit within one or more nodes to achieve a desired processing function while meeting the signal requirements for the infrastructure of the network and node interfaces presented herein. By relying on the infrastructure of the node network that supports heterogenuity and adaptability, quick and efficient development of embedded system architecture can be realized in less time than would traditionally be required and with reduced program risk. Further reduction in the time-to-market concerns are realized when the individual and proprietary designs are combined with other, preexisting node type designs, such as RISC processors, DSP processors, reconfigurable arithmetic processors, reconfigurable bit-manipulative intensive processors, reconfigurable Viterbi decoders and finite arithmetic units, reconfigurable, high sample rate correlators and convolvers, etc. 
   From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the novel concept of the invention. It is to be understood that no limitation with respect to the specific methods and apparatus illustrated herein is intended or should be inferred. It is, of course, intended to cover by the appended claims all such modifications as fall within the scope of the claims.
Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.