BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to the field of semiconductor packaging, and more particularly to a Package-on-Package (PoP) assembly and a method for manufacturing the same. 
         [0003]    2. Description of the Prior Art 
         [0004]    With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. To reduce the dimensions of such components, the structures by which these components are packages and assembled with circuit boards must become more compact. In order to meet the requirements of smaller footprints with higher densities, 3D stacking packaging such as PoP (Package-on-Package) assembly has been developed. 
         [0005]    A PoP assembly typically includes a top package with a device die bonded to a bottom package with another device die. In PoP designs, the top package may be interconnected to the bottom package through peripheral solder balls. However, the prior art PoP assembly is not able to provide very tight pitch stacking. Further, the prior art PoP assembly has large package form factor and poor warpage control. 
         [0006]    In wafer level packaging, the wafer and the dies mounted on the wafer are typically covered with a relatively thick layer of the molding compound. The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging. It is known that wafer warpage continues to be a concern. Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer. Warpage issue is serious especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process that requires fine-pitch RDL process. 
       SUMMARY OF THE INVENTION 
       [0007]    One object of the present invention is to provide a semiconductor device having package-on-package (PoP) configuration. 
         [0008]    In one aspect of the invention, a package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one through-substrate-via (TSV) chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side. 
         [0009]    According to one embodiment of the invention, the top die package is mounted on the bottom die package through a plurality of third bumps disposed on the TSV chip. 
         [0010]    In one aspect of the invention, a package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the dummy chip is directly mounted on a passivation layer of the interposer; a dielectric layer covering the at least one active chip and the at least one dummy chip; at least one TSV connecter penetrating through the dielectric layer and the dummy chip; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
           [0013]      FIG. 1  to  FIG. 9  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a package-on-package (PoP) assembly according to one embodiment of the invention; and 
           [0014]      FIG. 10  to  FIG. 20  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a package-on-package (PoP) assembly according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments maybe utilized and structural changes may be made without departing from the scope of the present invention. 
         [0016]    The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
         [0017]    One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The terms “die”, “semiconductor chip”, and “semiconductor die” are used interchangeable throughout the specification. 
         [0018]    The terms wafer and substrate used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the circuit structure such as a redistribution layer (RDL). The term substrate is understood to include semiconductor wafers, but not limited thereto. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. 
         [0019]    Please refer to  FIG. 1  to  FIG. 9 .  FIG. 1  to  FIG. 9  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a package-on-package (PoP) assembly according to one embodiment of the invention. 
         [0020]    As shown in  FIG. 1 , a carrier  300  is prepared. The carrier  300  may be a releasable substrate material with an adhesive layer (not explicitly shown), but not limited thereto. At least a dielectric layer or a passivation layer  310  is then formed on a top surface of the carrier  300 . The passivation layer  310  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like. 
         [0021]    As shown in  FIG. 2 , subsequently, a redistribution layer (RDL)  410  is formed on the passivation layer  310 . The RDL  410  may comprise at least one dielectric layer  412  and at least one metal layer  414 . The dielectric layer  412  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like, but not limited thereto. The metal layer  414  may comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. 
         [0022]    According to the illustrated embodiment, the metal layer  414  may comprise a plurality of first bump pads  415   a  and second bump pads  415   b  exposed from a top surface of the dielectric layer  412 . The first bump pads  415   a  are disposed within a chip mounting area  102 , while the dummy pads  415   b  are disposed outside the chip mounting area such as a peripheral area  104  around the chip mounting area  102 . 
         [0023]    Subsequently, a passivation layer  413  such as polyimide or solder mask material may be formed on the dielectric layer  412 . The passivation layer  413  may include openings (not explicitly shown) that expose the respective first and second bump pads  415   a  and  415   b . A conventional electroplating solder bumping process may be performed to form first bumps  416   a  and second bumps  416   b  on the respective first and second bump pads  415   a  and  415   b.    
         [0024]    As shown in  FIG. 3 , subsequently, individual flip-chips or dies  420   a  with their active sides facing down toward the RDL  410  are then mounted on the RDL  410  through the first bumps  416   a  to thereby forming a stacked chip-to-wafer (C2W) construction. These individual flip-chips or dies  420   a  are active integrated circuit chips with certain functions, for example, GPU (graphic processing unit), CPU (central processing unit), memory chips, etc. 
         [0025]    According to the illustrated embodiment, a plurality of TSV chips  420   b  are mounted in the peripheral area  104  around the chip mounting area  102  through the second bumps  416   b.  Each of the TSV chips  420   b  may comprise a substrate  440  such as a silicon substrate. A plurality of through substrate via (TSV) connecters  441  fabricated within the substrate  440 . A plurality of bumps  442  may be formed on a top surface of the substrate  440  opposite to the second bumps  416   b.    
         [0026]    Optionally, an underfill (not shown) maybe applied under each chip  420   a / 420   b.  Thereafter, a thermal process may be performed to reflow the first bumps  416   a  and second bumps  416   b.    
         [0027]    After the chip-bonding process, a molding compound  500  is applied. The molding compound  500  covers the attached active chips  420   a  and the TSV chips  420   b  and the top surface of the RDL  410 . The molding compound  500  may be subjected to a curing process. The mold compound  500  may comprise a mixture of epoxy and silica fillers, but not limited thereto. 
         [0028]    As shown in  FIG. 4 , a top portion of the molding compound  500  may be polished away to expose top surfaces of the active chips  420   a  and a portion of the bumps  442  of the TSV chips  420   b.  During the molding compound grinding process, a portion of the chips  420   a  maybe removed, but not limited thereto. At this point, the top surfaces of the active chips  420   a  are flush with the top surface of the molding compound  500 . 
         [0029]    As shown in  FIG. 5 , a bump forming process is performed to form bumps  444  directly and respectively on the exposed bumps  442  of the TSV chips  420   b.  These bumps  444  protrude from the top surface of the molding compound  500  for further connections. According to the illustrated embodiment, the bumps  444  may be formed by using electroplating methods, but not limited thereto. The bumps  444  may comprise copper, nickel, tin, or any suitable solderable material known in the art. 
         [0030]    As shown in  FIG. 6 , the wafer level package is then adhered to another carrier  600 . The bumps  444  face toward, and may contact, the carrier  600 . The carrier  600  may be a glass substrate, but not limited thereto. Optionally, an adhesive layer or a glue layer  602  may be used. Subsequently, the carrier  300  is removed to thereby expose a major surface of the passivation layer  310 . The RDL  410  and the passivation layer  310  function as an interposer. The de-bonding of the carrier  300  may be performed by using a laser process or UV irradiation process, but not limited thereto. 
         [0031]    As shown in  FIG. 7 , after de-bonding the carrier  300 , openings may be formed in the passivation layer  310  to expose respective solder pads, and then solder bumps or solder balls  520  may be formed on the respective solder pads. Thereafter, the carrier  600  and the adhesive layer  602  are removed to expose the bumps  444 . 
         [0032]    As shown in  FIG. 8 , after the carrier  600  and the adhesive layer  602  are removed, the wafer level package is then diced and singulated into individual die package  10 . For example, the wafer level package may be first attached to a dicing tape (not shown), where the bumps  520  face toward, and may contact, the dicing tape. 
         [0033]    As shown in  FIG. 9 , a die package  20  comprising at least a molded semiconductor die  201  is mounted on the die package  10  to thereby form a PoP assembly  1 . The die package  20  may be electrically connected to the die package  10  through the bumps  444  and the TSV chips  420   b.    
         [0034]    It is advantageous to use the invention because most of the peripheral area  104  around the chip mounting area  102  is occupied by the TSV chips  420   b,  the used amount of the molding compound  500  is reduced, and therefore the warpage of the wafer or die package is alleviated or avoided. 
         [0035]    Please refer to  FIG. 10  to  FIG. 20 .  FIG. 10  to  FIG. 20  are schematic, cross-sectional diagrams showing an exemplary method for fabricating a package-on-package (PoP) assembly according to another embodiment of the invention, wherein like numeral numbers designate like layers, regions, or elements. 
         [0036]    As shown in  FIG. 10 , likewise, a carrier  300  is prepared. The carrier  300  may be a releasable substrate material with an adhesive layer (not explicitly shown), but not limited thereto. At least a dielectric layer or a passivation layer  310  is then formed on a top surface of the carrier  300 . The passivation layer  310  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like. 
         [0037]    As shown in  FIG. 11 , subsequently, a redistribution layer (RDL)  410  is formed on the passivation layer  310 . The RDL  410  may comprise at least one dielectric layer  412  and at least one metal layer  414 . The dielectric layer  412  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like, but not limited thereto. The metal layer  414  may comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. 
         [0038]    According to the illustrated embodiment, the metal layer  414  may comprise a plurality of bump pads  415   a  exposed from a top surface of the dielectric layer  412 . The bump pads  415   a  are disposed within a chip mounting area  102 . The metal layer  414  may comprise a plurality of pads  415   b  disposed within a peripheral area  104  around the chip mounting area  102 . 
         [0039]    Subsequently, a passivation layer  413  such as polyimide or solder mask material may be formed on the dielectric layer  412 . The passivation layer  413  may include openings (not explicitly shown) that expose the respective bump pads  415   a.  A conventional electroplating solder bumping process maybe performed to form bumps  416   a  on the respective bump pads  415   a.    
         [0040]    As shown in  FIG. 12 , subsequently, individual flip-chips or dies  420   a  with their active sides facing down toward the RDL  410  are then mounted on the RDL  410  through the first bumps  416   a  to thereby forming a stacked chip-to-wafer (C2W) construction. These individual flip-chips or dies  420   a  are active integrated circuit chips with certain functions, for example, GPU (graphic processing unit), CPU (central processing unit), memory chips, etc. 
         [0041]    According to the illustrated embodiment, a plurality of dummy chips (or warpage-control chips)  420   c  are mounted in the peripheral area  104  around the chip mounting area  102 . According to the illustrated embodiment, the dummy chips  420   c  may comprise silicon or dummy silicon chip. According to the illustrated embodiment, the dummy chips  420   c  may be attached onto the passivation layer  413  by using an adhesive (not shown). 
         [0042]    Optionally, an underfill (not shown) maybe applied under each chip  420   a.  Thereafter, a thermal process may be performed to reflow the first bumps  416   a  and second bumps  416   b.    
         [0043]    After the chip-bonding process, a molding compound  500  is applied. The molding compound  500  covers the attached active chips  420   a  and the dummy chips  420   c  and the top surface of the RDL  410 . The molding compound  500  may be subjected to a curing process. The mold compound  500  may comprise a mixture of epoxy and silica fillers, but not limited thereto. 
         [0044]    As shown in  FIG. 13 , likewise, a top portion of the molding compound  500  may be polished away to expose top surfaces of the active chips  420   a  and top surfaces of the dummy chips  420   c  . During the molding compound grinding process, a portion of the chips  420   a  may be removed, but not limited thereto. At this point, the top surfaces of the active chips  420   a  and the top surfaces of the dummy chips  420   c  are flush with the top surface of the molding compound  500 . 
         [0045]    As shown in  FIG. 14 , a dielectric layer  610  such as a silicon oxide layer is deposited onto the top surfaces of the active chips  420   a,  the top surfaces of the dummy chips  420   c,  and the top surface of the molding compound  500 . According to the illustrated embodiment, the dielectric layer  610  is deposited in blanket fashion. Thereafter, an etching process is performed to form through substrate vias (TSVs)  620  into the dielectric layer  610  and the dummy chips  420   c.  The TSVs  620  expose respective pads  415   b  in the peripheral area  104 . 
         [0046]    As shown in  FIG. 15 , an isolation oxide layer  630  is formed on the sidewalls of the TSVs  620 . For example, a conformal silicon oxide layer is deposited on the sidewalls and bottom surfaces of the TSVs  620  and on the dielectric layer  610 . A dry etching process may be performed to etch away the silicon oxide layer from the bottom surfaces of the TSVs  620  to expose the pads  415   b.    
         [0047]    As shown in  FIG. 16 , a metal filling process is then performed. Each of the TSVs  620  is filled with a metal layer  650 . According to the illustrated embodiment, the TSVs  620  may not be completely filled with the metal layer  650 . A lithographic process and an etching process may be performed to form a metal trace pattern  652  such as a bump pad on the dielectric layer  610 . 
         [0048]    As shown in  FIG. 17 , the wafer level package is then adhered to another carrier  600 . The metal trace pattern  652  faces toward, and may contact, the carrier  600 . The carrier  600  may be a glass substrate, but not limited thereto. Optionally, an adhesive layer or a glue layer (not shown) may be used to attach the wafer level package to the carrier  600 . Subsequently, the carrier  300  is removed to thereby expose a major surface of the passivation layer  310 . The de-bonding of the carrier  300  may be performed by using a laser process or UV irradiation process, but not limited thereto. 
         [0049]    As shown in  FIG. 18 , after de-bonding the carrier  300 , openings may be formed in the passivation layer  310  to expose respective solder pads, and then solder bumps or solder balls  520  may be formed on the respective solder pads. Thereafter, the carrier  600  and the adhesive layer  602  are removed to expose the metal trace pattern  652 . 
         [0050]    As shown in  FIG. 19 , after the carrier  600  and the adhesive layer  602  are removed, the wafer level package is then diced and singulated into individual die package  10 . For example, the wafer level package may be first attached to a dicing tape  700 , where the solder bumps  520  face toward, and may contact, the dicing tape  700 . 
         [0051]    As shown in  FIG. 20 , a die package  20  comprising at least a molded semiconductor die  201  is mounted on the die package  10  to thereby form a PoP assembly  1   a . The die package  20  may be electrically connected to the die package  10  through the bumps  252 , the metal trace pattern  652  and the TSVs  620 . 
         [0052]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
A package-on-package assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one TSV chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side.