CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of U.S. Provisional Patent Application Ser. No. 61/174,640, filed on May 1, 2009, which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure is related to current leakage. Various embodiments provide current compensation for bit line leakage in single-ended SRAMs. 
     BACKGROUND 
     Single-ended read Static Random Access Memory (SRAM) has been widely used in the industry because it can separate read and write operations to achieve lower minimum operating supply voltage (e.g., Vdd). Its large bit line leakage, however, could result in misread, especially in a long bit line scheme. Worst case current leakage to a bit line generally occurs when reading a cell storing a low while other cells are storing a high. When this happens, the current leakage causes a large voltage drop in the read bit line signal and thus can cause misread. Some approaches use a “keeper” to hold the reading state to avoid the misread. In many designs, however, the keeper is always on and thus can pull the logic level of the memory cell to be read in an undesirable direction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
         FIG. 1  shows an exemplary circuit according to an embodiment of the invention. 
         FIG. 2  shows the exemplary circuit of  FIG. 1  in a leakage sampling phase, in accordance with an embodiment. 
         FIG. 3  shows the exemplary circuit of  FIG. 1  in a read phase, in accordance with an embodiment. 
         FIG. 4  shows illustrative signals corresponding to the exemplary circuit of  FIG. 1 . 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Embodiments, or examples, of the invention illustrated in the drawings are now being described using specific languages. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and modifications in the described embodiments, and any further applications of principles of the invention described in this document are contemplated as would normally occur to one skilled in the art to which the invention relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number. 
     A Compensation Circuit Embodiment in Operation with a Single-Ended SRAM 
       FIG. 1  shows an exemplary circuit  100  according to an embodiment of the invention that includes an exemplary single-ended SRAM  120  and an embodiment of a compensation circuit  110 . 
     Each memory cell MC of SRAM  120  corresponds to a signal read word line RWL. For illustration, only a pair of transistors TR 1  and TR 2  of each memory cell MC are shown, but other components including, for example, the cross latch, are not shown. Transistors TR 1  and TR 2  of a memory cell are configured to allow access to the corresponding memory cell (e.g., by turning it on or off). Transistor TR 1  of a memory cell MC controls (e.g., turns on/off) that memory cell MC. For example regarding memory cell MC[ 0 ], if signal RWL[ 0 ] is activated (e.g., at a high voltage level, or “high” hereinafter for simplicity), it turns on transistor TR 1 [ 0 ] and if signal RWL[ 0 ] is deactivated (e.g., at a low voltage level, or “low” hereinafter for simplicity), it turns off transistor TR 1 [ 0 ]. Transistor TR 1 [ 0 ], when being off, disconnects signal line RBL from transistor TR 2 [ 0 ], and, when being on, allows current to flow through transistor TR 1 [ 0 ] and TR 2 [ 0 ]. The data at the gate of transistor TR 2  represents the data stored by the memory cell MC. For example, if the gate of transistor TR 2 [ 0 ] is low then memory cell MC[ 0 ] stores a low, and if the gate of transistor TR 2 [ 0 ] is high then memory cell MC[ 0 ] stores a high. Generally, to read a memory cell MC (e.g., cell MC[ 0 ]), signal line RBL is configured to be high, the signal RWL (e.g., RWL[ 0 ]) for that memory cell MC[ 0 ] is activated, which turns on the corresponding transistor TR 1  (e.g., transistor TR 1 [ 0 ]). If memory cell MC[ 0 ] stores a low, then transistor TR 2 [ 0 ] is off, signal line RBL is high, which, via sense amplifier inverter SA_INV, provides a low at output Qout. If memory cell MC[ 0 ], however, stores a high, then transistor TR 2 [ 0 ] is on, and current flows from signal line RBL through transistors TR 1 [ 0 ] and TR 2 [ 0 ] to ground, resulting in a low at signal line RBL, which, in turns, provides a high at output Qout. 
     Because the data at the gate of each transistor TR 2  (e.g., TR 2 [ 0 ], TR 2 [ 1 ], . . . , TR 2 [N], etc.) represents the data stored by a corresponding memory cell MC, the data low, Vdd, and Vdd at the gate of transistor TR 2 [ 0 ], TR 2 [ 1 ], and TR 2 [N] as shown in  FIG. 1  show the stored data low, high, high at cells MC[ 0 ], MC[ 1 ] and MC[N], respectively. As will be explained below, this set of data represents the worst case leakage scenario that can benefit from the disclosed embodiments. 
     Transistor P 3  in conjunction with signal BLEQB, at appropriate time, pre-charges signal line RBL, and may be referred to as a pre-charge circuit. When signal BLEQB is activated (e.g., low), it turns on transistor P 3  allowing signal line RBL to be pre-charged to Vdd, which is a desired level for a memory cell MC to be read. When signal BLEQB is deactivated (e.g., high), it turns off transistor P 3  disallowing the pre-charge mode for signal line RBL. Generally, circuit  100  is in the read mode when one of the cells MC is in the read mode (e.g., one of the signals RWL[ 0 :n] is activated). Further, before sampling the current leakage, signal line RBL is pre-charged to a high state so that the amount of leakage can be determined. Similarly, before the read operation, signal line RBL is also pre-charged to discriminate the data stored in a memory cell MC to be read. To read signal line RBL, transistor P 3  is off so that the pre-charge mode can be turned off. 
     Sense amplifier inverter SA_IVN inverts the logic state of signal line RBL to output Qout. When a memory cell MC to be read stores a low, signal line RBL is high, and, via inverter SA_IVN, provides a low to output Qout. On the other hand, if the memory cell MC to be read stores a high, signal line RBL starts discharging to a low, turning output Qout to a high via inverter SA_IVN. 
     In an embodiment, compensation circuit  110 , in the leakage sampling phase, determines the amount of current leaked from signal line RBL and thus the voltage level of signal line RBL being pulled down by the leakage current, and stores that leakage information via a capacitive device, e.g., capacitor C in the embodiment of  FIG. 1 . In the reading phase, compensation circuit  110 , based on the stored information, provides current to compensate for the current leaked from signal line RBL. 
     Transistor P 1  (e.g., a PMOS transistor) via signal A controls operation of compensation circuit  110 . Signal A in fact controls the operation of transistor P 1 . When signal A is activated (e.g., low) transistor P 1  is on, and when signal A is deactivated (e.g., high) transistor P 1  is off. When transistor P 1  is on, compensation circuit  110  is enabled and when transistor P 1  is off, compensation circuit  110  is disabled. 
     Transistor P 2  (e.g., a PMOS transistor) via the voltage level at node N 1  (e.g., voltage V) controls the amount of compensation current. When voltage V is not low, it turns off transistor P 2 , and when it is low, it biases transistor P 2  to provide the compensation current flow from Vdd through transistors P 1  and P 2  to signal line RBL. 
     Capacitor C via a first end (e.g., node N 1 ) stores the current leakage information at signal line RBL and when appropriate provides this information via voltage V and transistor P 2  to provide the compensation current to signal line RBL. 
     Voltage V at node N 1  controls transistor P 2  and therefore also controls the current compensated for the leakage current to signal line RBL. Voltage level V, when appropriate, is the voltage level of signal line RBL being pulled down by the leakage current. 
     Transmission gate Tg and signals B and B/ provide a connection path between its first end coupled to node N 1  and its second end coupled to signal line RBL. During leakage sampling phase transmission gate Tg is on (e.g., forming a closed circuit) allowing current leakage information to be transferred from signal line RBL to node N 1 . During compensation, transmission gate Tg is off (e.g., forming an open circuit) disconnecting node N 1  from signal line RBL and therefore enables voltage V to control transistor P 2 . Signals B and B/ control the operation of transmission gate Tg (e.g., for it to be closed or open). 
     Compensation 
     Embodiments of the invention provide compensation current to improve current leakage from signal line RBL. The amount of compensation current provided depends on the amount of leakage current. The larger the leakage current, the larger the compensation current is provided, and the smaller the leakage current, the smaller the compensation current is provided. 
     Generally, clock signals are used to synchronize SRAM designs. High performance systems using memories (e.g., SRAM) can operate without skews with a fast system clock. A clock signal provided by a system implementing the SRAM can be used to synchronize the system speed and the SRAM speed. In an embodiment, a rising edge of the clock signal and a delay circuit is used to generate signals read word line (e.g., signals RWL) pulses, and the falling edge of the clock and additional circuitry are used for the sampling phase generation. Embodiments of the invention can utilize this system clock signal. 
     In an embodiment with a compensation scheme, reading a memory cell MC is separated into two phases, e.g., a leakage sampling phase and an “actual” read phase. Further, the leakage sampling phase occurs at a low cycle of a clock signal while the read phase occurs at the high cycle of the clock signal. The invention, however, is not limited to such operation. That is, the sampling leakage phase can occur at the high cycle while the read phase occurs at the low cycle of the clock, etc. 
       FIG. 2  shows a circuit  200  reflecting circuit  100  in the leakage compensation phase. For simplicity, various labels are not shown. In this phase, compensation circuit  110  is off, i.e., transistors P 1  and P 2  are off (e.g., marked with an “X”). Transistor P 3  is also off (e.g., also marked with another “X”). Before sampling the current leakage signal line RBL is pre-charged to a high state (e.g., Vdd), which, in various embodiments, is the normal state for this signal line RBL for a read operation. 
     Because transistor P 3  is off, signal line RBL is high, leakage current IL (e.g., the sum of current IL[ 0 ], IL[ 1 ], . . . , IL[N]), flows from signal line RBL into transistors TR 1  and TR 2  of memory cells MC as shown. As a result, the voltage level of signal line RBL is pulled down (e.g., dropped) and the amount of dropped voltage (e.g., Vpd) depends on the amount of current being leaked out of signal line RBL (e.g., current IL). The more number of memory cells MC store a high, the higher the leakage current IL flows, and the more signal line RBL is dropped. The amount of leakage current per memory cell MC (e.g., IL[ 0 ], IL[ 1 ], . . . , IL[N], etc.), depends on circuit implementations, technologies, and the logic level stored in the memory cells MC. Those skilled in the art will recognize that, in the exemplary embodiment of  FIG. 1 , leakage current per memory cell MC is higher when that cell MC stores a high than when it stores a low. Further, in a scenario having worst case leakage, a memory cell (e.g., memory cell MC[ 0 ]) stores a low and all other cells (e.g., memory cells MC[ 1 ] to MC[N]) store a high and reading is to occur at the cell storing a low (e.g., cell MC[ 0 ]). In this situation, many memory cells MC store a high, a lot of current leaks form signal line RBL and disadvantageously affects the voltage level of signal line RBL. For illustration purposes, circuit  100  shows a worst case scenario where memory cell MC[ 0 ] stores a low while other memory cells MC[ 1 ] to MC[N] store a high, and reading occurs at cell MC[ 0 ]. 
     In an embodiment, the leakage current per memory cell MC ranges from 10 nA to 46 nA. Generally, the lower end of the range (e.g., 10 nA) is for the memory cell MC storing a low and the upper end of the range (e.g., 46 nA) is for a memory cell MC storing a high. For a rough estimation, the total leakage current IL in an embodiment is about 12 μA for an array of 256 memory cells MC. Further, the voltage level of signal line RBL being pulled down by the leakage current for an array of 256 memory cells MC is about 0.4V (e.g., Vpd=0.4V). The voltage level of signal line RBL affected by this pulled-down voltage level Vpd is therefore Vdd−Vpd or Vdd−0.4 V is passed through transmission gate Tg to node N 1 , and is stored by capacitor C. This voltage level is later used to provide the compensation current. 
       FIG. 3  shows a circuit  300  reflecting circuit  100  in the reading phase. For simplicity, various labels are not shown. In this read phase, compensation circuit  110  is activated to provide current compensation to signal line RBL. Signal A is activated (e.g., low) to turn on transistor P 1 . Transmission gate Tg is off to separate node N 1  and capacitor C from signal line RBL. Transistor P 3  is also off so that signal line RBL is not in the pre-charge mode. As transmission gate Tg and transistor P 3  are off, they, for illustration, are marked with an “X.” 
     Embodiments of the invention provide compensation current to compensate for the leakage current. The amount of compensation current depends on the amount of current measured as leakage in the leakage sampling phase (e.g., current IL). In various embodiments, if the leakage current IL is large, the level of signal line RBL is strongly pulled down, which in turns enables lower level for voltage V at node N 1 . The lower voltage level V at node N 1  strongly turns on transistor P 2 , which in turns provides a larger source-to-drain current (IDS) for transistor P 2 , which is in fact the compensation current provided to signal line RBL. If the leakage current is small, the voltage level V at node N 1  is higher, which weakly turns on transistor P 2 . As a result, a smaller current IDS for transistor P 2  is provided, resulting in a smaller compensation current for signal line RBL. 
     For illustration, during compensation (e.g., transistor P 1  is on), transistor P 1  charges node N 2  to Vdd. Fort further illustration, the pulled-down voltage Vpd is 0.4V as discussed above. As a result, the voltage from the drain to the source of transistor P 2  (e.g., Vdsp 2 ) is Vdd−Vpd−Vdd=Vpd. Further, the voltage from the gate to the source of transistor P 2  (e.g., Vgsp 2 ) is Vdd−Vpd−Vdd=Vpd. Because Vdsp 2 , which is Vpd, equals to Vgdp 2 , which is also Vpd, transistor P 2  operates in the saturation mode. Because the compensation current (e.g., Icomp) is in fact current IDS of transistor P 2  in this saturation mode:
 
Icomp= K (| Vgsp 2|−| Vtp 2|) 2  
 
where Vtp 2  is the threshold voltage for transistor P 2 , and, in an embodiment, is about 0.2 V. K is an electrical constant, and, in an embodiment, is about 300 μA/V 2 . Further, Vdsp 2 =Vpd=0.4 V as illustrated above. As a result, Icomp˜12 μA, which is about the same as leakage current IL of 12 μA. Those skilled in the art will recognize that the above calculation is a rough estimate for illustration purposes only. Further, even if there is variation between the leakage current IL and the compensation current Icomp, the spirit and scope of embodiments of the invention are maintained because, in various embodiments, it is not required that the compensation current Icomp is exactly the same as the leakage current IL. An amount of current Icomp close to current IL and/or sufficient to pull up signal line RBL to prevent the misread is within the scope of the disclosed embodiments. Additionally, because the leakage current IL was translated into the pulled down voltage Vpd of signal line RBL and is part of the calculation for the compensation current Icomp, embodiments of the invention provide the compensation current Icomp based on the leakage current IL. Alternatively expressed, embodiments of the invention are applicable in various variations of the leakage current.
 
     Illustration Signals 
       FIG. 4  shows illustration signals for reading memory cell MC[ 0 ] where memory cell MC[ 0 ] stores a low while all other cells MC[ 1 ] to MC[N] store a high. In some embodiments, this situation indicates the worst case leakage to circuit  100 . 
     In an embodiment, during the leakage sampling phase clock signal CLK is low, signal RWL[ 0 ] is also low indicating no memory cell MC is selected for reading. 
     Signal A is activated (e.g., high) to turn off transistor P 1 , which, in effect, turns off compensation circuit  100 . 
     Signal B is activated (e.g., high) to allow current to flow from signal line RBL to node N 1 , which, in effect, allows node N 1  to record the leakage current or the voltage level of signal line RBL taking account of the leakage current, which, at this time, is Vdd−Vpd. 
     Signal BLEQB is raised to a high during time T 1  (and T 2 ) to disable the pre-charge mode to signal line RBL. Outside of times T 1  and T 2 , signal BLEBQ is low to activate transistor P 3  to pre-charge signal line RBL. 
     Signal line RBL shows a glitch  410  indicating current IL being leaked from signal line RBL into memory cells MC[ 0 ] to MC[N] and thus pulling the voltage level of signal line RBL down an amount of Vpd. The bottom of glitch  410  is Vdd−Vpd. 
     Voltage level V also shows a glitch  410  having a bottom level at Vdd−Vpd. Because voltage V is transferred to node N 1  of capacitor C, at the end of time T 1 , voltage V, however, stays at Vdd−Vpd. 
     During the reading phase, signal B is deactivated to disconnect signal line RBL from node N 1 . 
     Signal RWL[ 0 ] is raised to a high during time T 2  so that memory cell MC[ 0 ] is selected for reading. 
     During this time T 2 , signal A is also activated (e.g., low) to turn on transistor P 2  and thus compensation circuit  110 . 
     During time T 2 , signal BLEQB is de-activated (e.g., high) to turn off transistor P 3 , disallowing signal line RBL from the pre-charge mode. 
     Voltage V stays at Vdd−Vpd, which is the voltage level of signal line RBL taking account of the leakage current IL and being pulled down by Vpd. 
     Due to the compensation mechanisms, signal line RBL shows no glitch indicating the leakage current IL is compensated by current Icomp. Without the compensation of embodiments of the invention (e.g., providing compensation current Icomp), there would be some glitch (e.g., like glitch  410 ) reflecting the leakage current IL. 
     A number of embodiments of the invention have been described. It will nevertheless be understood that various variations and/or modifications may be made without departing from the spirit and scope of the invention. For example, various transistors are shown to be NMOS (e.g., transistors TR 1 , TR 2 , etc.) and some others (e.g., transistors P 1 , P 2 , P 3 , etc.) are shown to be PMOS, but the invention is not limited to such a configuration because selecting a transistor type (e.g., NMOS or PMOS) is a matter of design choice based on need, convenience, etc. Embodiments of the invention are applicable in all variations and combinations of transistor types. Further, some signals are illustrated with a particular logic level to operate some transistors (e.g., activated high, deactivated low, etc.), but selecting such levels and transistors are also a matter of design choice, and embodiments of the invention are applicable in various design choices. Electronic components (e.g., transistors, P 1 , P 2 , P 3 , transmission gate Tg, capacitor C, etc.) in conjunction with corresponding voltages and current (voltage V, signal A, BLEQB, etc.) are shown to perform a certain function (e.g., provide a compensation current, pre-charge the signal line RBL, store the leakage information, etc.) for illustration only, but similar components and/or circuits may be used to perform the intended functions, and the invention is not limited to a particular circuit or component. 
     Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within scope of the invention and will be apparent to those skilled in the art after reviewing this disclosure. Accordingly, the scope of the invention should be determined with reference to the following claims, along with the full scope of equivalences to which such claims are entitled.
Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line.