FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to power-up circuits, and particularly to power-up circuits used to turn on BGREF (bandgap voltage reference) circuits, and BGREF level comparators.  
       BACKGROUND OF THE INVENTION  
       [0002]     In many types of non-volatile memory (NVM) cells, such as flash memory or electrically erasable, programmable read only memory (EEPROM), an example of which is a nitride, read only memory (NROM), reading data stored in the memory cell should be performed at a known minimum VDD voltage. For example, but not necessarily, the read voltage should be not less than 2.4V. Below this voltage, charge pump circuits, sense amplifiers, regulator circuits, and the NROM cell itself may not function properly, resulting in incorrect data and margin loss. Thus, it is desirable that the circuitry (chip) should have internal circuit to detect that VDD has reached the required minimum value.  
         [0003]     Reference is now made to  FIG. 1 , which illustrates a prior art circuit for detecting that VDD is greater than a minimum value (e.g., VDD&gt;2.4V). This circuit is also called an accurate power-up comparator or accurate level comparator or accurate comparator. The circuit compares a reference voltage, BGREF (bandgap voltage reference), to a resistor divider  5  from VDD. The resistor divider  5  comprises two resistors R 1  and R 2  connected in series at a node n 1 . The comparator comprises a differential pair of NMOS (n-channel metal oxide semiconductor) transistors M 1  and M 2 , a tail current source I 1 , and a current mirror (active load) that includes PMOS (p-channel metal oxide semiconductor) transistors M 4  and M 5 .  
         [0004]     In the current mirror (active load), the gates of PMOS transistors M 4  and M 5  are connected to each other, and the drain of PMOS transistor M 5  is connected to its gate. The sources of PMOS transistors M 4  and M 5  may be connected to a reference voltage, such as VDD.  
         [0005]     The gate of NMOS transistor M 2  is connected to BGREF, whereas the gate of NMOS transistor M 1  is connected to node n 1 . The sources of NMOS transistors M 1  and M 2  are connected to current source I 1 . The drain of NMOS transistor M 2  is connected to the drain of PMOS transistor M 4  via a node n 2  and the drain of NMOS transistor M 1  is connected to the drain of PMOS transistor M 5  via a node n 3 .  
         [0006]     Two inverters  6  and  7  buffer the comparator output OPC (from node n 2 ) to the general output OP. Inverter  6  is connected to the drain of PMOS transistor M 4  via node n 2  and the output of inverter  7  is connected to the input of inverter  6 .  
         [0007]     In this particular example, the value of resistor R 1  is identical to that of resistor R 2 , and BGREF equals 1.2V. For these values, the node OPC is at a low voltage, close to GND for VDD&lt;2.4. When VDD&gt;2.4V, node n 1  is greater than BGREF, and the current in NMOS transistor M 1  is greater than the current in NMOS transistor M 2 . The current in NMOS transistor M 1  is mirrored from PMOS transistor M 5  to PMOS transistor M 4 , which forces the comparator output OPC to a high state, close to VDD. The inverters  6  and  7  buffer this signal to the general output OP, which is a logical signal indicating that VDD&gt;2.4 when it is high.  
         [0008]     In order to function properly, the accurate comparator assumes that BGREF is at a stable voltage, meaning that VDD is sufficiently high to allow BGREF to function.  
         [0009]     Reference is now made to  FIG. 2 , which illustrates a prior art BGREF circuit. The BGREF circuit is connected to power-up circuit  8  (also referred to as start-up circuitry or a BGREF level comparator), used to indicate that VDD has reached a level at which BGREF can operate. Power-up circuit  8  is shown and described hereinbelow with reference to  FIG. 3 .  
         [0010]     The illustrated BGREF circuit comprises three branches, headed by PMOS transistors XA 1 A, XA 1 B and XA 1 C, whose sources are all connected to VDD. PMOS transistors XA 1 A and XA 1 B form a current mirror, wherein the gates of PMOS transistors XA 1 A and XA 1 B are connected together and the drain of PMOS transistor XA 1 B is connected to its gate. The gate of PMOS transistor XA 1 A is connected to the power-up circuit  8 . The drains of PMOS transistors XA 1 A and XA 1 B are connected to the drains of NMOS transistors XA 2 A and XA 2 B.  
         [0011]     NMOS transistors XA 2 A and XA 2 B form a current mirror, wherein the gates of NMOS transistors XA 2 A and XA 2 B are connected together and the drain of NMOS transistor XA 2 A is connected to its gate, which is also connected to the power-up circuit  8 . The source of NMOS transistor XA 2 A is connected to a diode D 1 . The source of NMOS transistor XA 2 B is connected to a diode D 2  via a resistor R 1 .  
         [0012]     The gate of PMOS transistors XA 1 C is connected to the gate of PMOS transistor XA 1 B. The drain of PMOS transistor XA 1 C is connected to a diode D 3  via a resistor R 2 . The output of the BGREF circuit is designated as OP.  
         [0013]     As is known in the art, in order for the BGREF circuit to turn on, VDD must be sufficiently high for each transistor and diode in the circuit to turn on. For a transistor to turn on, its Vgs (gate-source voltage) must be above Vtn (threshold for NMOS) or Vtp (threshold for PMOS), which may be 0.7V (although not necessarily this value). The Vtn and Vtp parameters are very process dependent and can vary independently of each other. The transistor Vgs must have sufficient overdrive (Vdsat), which may be 0.2V, to drive its current. The transistor Vds (drain-source) voltage must be above Vdsat to be in the saturation regime. The diode voltages must be above Vd, which may be 0.7V.  
         [0014]     Thus in the branch of PMOS transistor XA 1 A, VDD must be above Vtn+Vd+2*Vdsat. For the PMOS transistor XA 1 B branch, VDD&gt;Vtp+Vd+2*Vdsat. In the output branch of PMOS transistor XA 1 C, the output should be at 1.2V, thus VDD&gt;1.2V +Vdsat. It is apparent that Vtn, Vtp, and Vd all may play a critical role in determining the minimum supply voltage of the BGREF.  
         [0015]     Reference is now made to  FIG. 3 , which illustrates a prior-art power-up circuit, used to indicate that VDD has reached a level at which BGREF can operate. The circuit may be identical to that of  FIG. 1 , except that the gate of NMOS transistor M 2  is connected to the gate of an NMOS transistor M 3 . The NMOS transistors M 2  and M 3  form a current mirror in the more general meaning, wherein the drain of NMOS transistor M 3  is connected to its gate but the source of M 3  is connected to ground, while as mentioned above the source of M 2  can be connected to a current source I 1 . The drain of NMOS transistor M 3  is connected to a current source I 2  at a node n 4 . The current source I 2  may be connected to a reference voltage, such as VDD.  
         [0016]     The circuitry of  FIG. 3  compares Vtn of NMOS transistor M 3  to VDD divided by the resistor divider  5 . The comparator output flips, trips or changes state when VDD is a multiple of Vtn. The resistor divider  5  can be scaled such that the trip point of the comparator is close to the operating VDD of the BGREF circuit in  FIG. 2 . This trip point is typically between 1.6V and 2.3V. The trip point can be designed to be arbitrarily large, by changing the resistor divider  5 . However, it is necessary to keep the trip point sufficiently below the minimum operating VDD voltage of the chip.  
         [0017]     It is clear that the circuit of  FIG. 3  depends only on Vtn, while the operating VDD voltage of the BGREF in  FIG. 2  depends on the Vtn, Vtp, and Vd. Thus, there are situations where Vtn is small and Vtp, Vd are large. In these cases, the comparator flips at a voltage where BGREF is not yet ready. This can result in the accurate comparator giving an erroneous reading, resulting in an incorrect first read.  
       SUMMARY OF THE INVENTION  
       [0018]     The present invention seeks to provide a novel power-up system and BGREF level comparator, as is described more in detail hereinbelow. In one embodiment, the present invention seeks to provide a BGREF level comparator whose trip point is a function of all of the parameters in BGREF, and is scaled to BGREF in all process corners, providing a logical signal that BGREF has sufficient VDD voltage to be operational.  
         [0019]     There is thus provided in accordance with an embodiment of the present invention circuitry including a BGREF comparator including a plurality of MOS transistors (e.g., a differential pair of NMOS transistors) that compare a resistor divided supply voltage to a function (e.g., an average or weighted average) of at least two process parameter voltages.  
         [0020]     In accordance with an embodiment of the present invention the process parameter voltages include a threshold voltage Vtn for an NMOS transistor of a BGREF circuit, a threshold voltage Vtp for a PMOS transistor of the BGREF circuit, and a diode voltage Vd of the BGREF circuit.  
         [0021]     Further in accordance with an embodiment of the present invention one or more legs of the differential pair may be degenerate, and one or more branches of the degenerate leg may receive a process parameter voltage at its input.  
         [0022]     Still further in accordance with an embodiment of the present invention a power-up circuit is provided to turn on a BGREF circuit at a supply voltage at which the BGREF circuit is operational. The BGREF comparator and the power-up circuit may power up a non-volatile memory circuit to perform a read operation.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:  
         [0024]      FIG. 1  is a simplified circuit diagram of a prior art circuit for detecting that VDD is greater than a minimum value;  
         [0025]      FIG. 2  is a simplified circuit diagram of a prior art BGREF circuit;  
         [0026]      FIG. 3  is a simplified circuit diagram of a prior-art power-up circuit, used to indicate that VDD has reached a level at which BGREF can operate;  
         [0027]      FIG. 4  is a simplified block diagram of a power-up system, constructed and operative in accordance with an embodiment of the invention;  
         [0028]      FIG. 5  is a simplified circuit diagram of a BGREF level comparator, constructed and operative in accordance with an embodiment of the present invention; and  
         [0029]      FIG. 6  is a simplified graphical illustration of a simulation of the BGREF level comparator and the BGREF circuit, in accordance with an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0030]     Reference is now made to  FIG. 4 , which illustrates a simplified block diagram of a power-up system  10 , constructed and operative in accordance with an embodiment of the present invention. Power-up system  10  may be useful for powering up a chip (not shown), such as but not limited to, a chip with NROM cells.  
         [0031]     Power-up system  10  may comprise a CMOS (complementary metal oxide semiconductor) level comparator C 1  whose output is input to a BGREF level comparator C 2 , described hereinbelow with reference to  FIG. 5 . The output of BGREF level comparator C 2  is input to an accurate level comparator C 3 , and to a BGREF circuit  12 . The output of BGREF circuit  12  is input to comparator C 3 . Although not necessarily, the BGREF circuit  12  may be identical to the BGREF circuit of  FIG. 2 , and the accurate level comparator C 3  may be identical to the accurate level comparator of  FIG. 1 . Alternatively, the BGREF circuit  12  may be some scale of the BGREF circuit of  FIG. 2 , being dependent on the same process parameters.  
         [0032]     The circuitry of CMOS level comparator C 1  is well known in the art. Some examples include those described in U.S. Pat. Nos. 5,534,804; 5,612,642 or 6,005,423.  
         [0033]     CMOS level comparator C 1  may provide a reset for the chip and for all of the comparators in the power-up system  10  when VDD is less than the threshold voltage Vt. This reset may be necessary, because below the threshold voltage Vt, all voltages in the chip are not well defined. When VDD is sufficiently above Vt, the CMOS level comparator C 1  provides a signal cmos_ok, which indicates that the BGREF level comparator C 2  can turn on. The BGREF level comparator C 2  outputs a logical signal bgref_ok at a VDD level at which the BGREF circuit  12  may function. Upon output of the logical signal bgref_ok, the BGREF circuit  12  becomes enabled, and the accurate level comparator C 3  becomes enabled.  
         [0034]     There may be a small delay (maybe 1 μs) between enabling of the BGREF circuit  12  and enabling of the accurate level comparator C 3  to allow BGREF to turn on. The accurate comparator outputs an OK signal VDD — 2.4__OK when VDD&gt;2.4V.  
         [0035]     Reference is now made to  FIG. 5 , which illustrates BGREF level comparator C 2 , constructed and operative in accordance with an embodiment of the present invention. Components of the circuitry of  FIG. 5  that are similar to that of  FIG. 3  are designated with the same reference labels, and the description is not repeated for the sake of brevity.  
         [0036]     In the illustrated embodiment of BGREF level comparator C 2 , NMOS transistor M 2  ( FIG. 3 ) is replaced with an NMOS transistor M 2 C. Two more NMOS transistors M 2 B and M 2 A are provided. The drains of NMOS transistors M 2 A, M 2 B and M 2 C are all connected via node n 2 , and all their sources are connected to current source I 1 . The gate of NMOS transistor M 2 B is connected to a current source I 3  via a node n 5 . The gate of NMOS transistor M 2 A is connected to a current source I 4  via a node n 6 . A PMOS transistor M 6  has its gate and drain connected together to ground. The source of PMOS transistor M 6  is connected to current source I 3  via node n 5 . A diode D 1  is connected to current source I 4  via node n 6  and is grounded.  
         [0037]     BGREF level comparator C 2  compares a resistor divided VDD to a function of Vtn, Vtp and Vd. The illustrated embodiment compares the resistor divided VDD to an average or a weighted average of Vtn, Vtp and Vd, but the invention is not limited to an average and other functions may be used. In the illustrated embodiment, the comparison may be accomplished by using a differential pair with a degenerate leg. The differential pair is formed by NMOS transistor M 1  on one side and a degenerate leg comprising NMOS transistors M 2 A, M 2 B and M 2 C on the other side. Each of the NMOS transistors M 2 A, M 2 B and M 2 C are referred to as the branches of the degenerate leg.  
         [0038]     The current of the degenerate leg M 2 A depends on the voltage level at node n 6 , which in turn depends on the process parameter Vd. The current of the degenerate leg M 2 B depends on the voltage at node n 5 , which in turn depends on the process parameter Vtp. The current of the degenerate leg M 2 C depends on the voltage at node n 4 , which in turn depends on the process parameter Vtn.  
         [0039]     The trip point of BGREF level comparator C 2  may occur when the current in NMOS transistor M 1  equals the sum of the currents in NTMOS transistors M 2 A, M 2 B and M 2 C. In general, the BGREF level comparator C 2  may compare the resistor divided VDD to some mathematical function of Vtn, Vtp and Vd. Depending on the relative values of NMOS transistors M 2 A, M 2 B and M 2 C, the mathematical function may be a type of average. For example, it is possible to make the mathematical function a weighted average by adjusting the ratios of NMOS transistors M 2 A, M 2 B and M 2 C.  
         [0040]     Reference is now made to  FIG. 6 , which illustrates a simulation of the BGREF level comparator C 2  and the BGREF circuit  12 .  FIG. 6  shows the BGREF and bgref_ok signals. When the bgref_ok signal rises it enables the BGREF circuit  12 . The BGREF signal is capable of reaching its full value at this point. This will be true in all process corners and conditions.  
         [0041]     It will be appreciated by person skilled in the art that variations of the embodiment described above are possible within the scope of the invention. For example, it is possible to design the BGREF level comparator C 2  using a degenerate leg with just two transistors (instead of all three transistors M 2 A, M 2 B and M 2 C), and use only two of the process parameters Vd, Vtn, and Vtp. Such a BGREF level comparator would be useful for other BGREF architectures using only those two parameters. It is further possible to design the BGREF level comparator C 2  using a degenerate leg with more than three transistors. It is also possible to increase the degeneracy of the leg and add process parameters.  
         [0042]     It will be appreciated by person skilled in the art, that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the present invention is defined only by the claims that follow:
Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.