BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a microcontroller with on-chip debugging features. 
         [0003]    2. Description of the Related Art 
         [0004]    Microcontrollers are used in a vast range of consumer and industrial products. A typical microcontroller is a semiconductor chip including both a central processing unit (CPU) and peripheral modules, as well as a read-only memory (ROM) storing program code and permanent data and a random-access memory (RAM) for temporary data storage. All of these facilities are interconnected by a system bus. By executing the program code, the CPU controls the peripheral modules, processes data, and communicates with or controls external devices. 
         [0005]    Some recent microcontrollers have an on-chip RAM monitor function to aid in the debugging of the program code or the circuit in which the microcontroller is installed, by enabling a debugging device to read the microcontroller&#39;s RAM data and the contents of registers in its peripheral modules. The RAM monitor function is implemented by a data transceiver that transfers data between the microcontroller and the debugging device, and an access controller interposed between the data transceiver and the system bus that operates as a direct memory access controller, capable of accessing the RAM and the peripheral module registers independently of the CPU. The data transceiver and access controller are built into the microcontroller. 
         [0006]    A conventional access controller operates according to address information received from the debugging device and a bus enable signal received from the CPU. The address information specifies an address or a range of addresses that the access controller wants to monitor. If the bus enable signal indicates that the bus is currently available, the access controller immediately reads data from the supplied address or address range and sends the data to the debugging device. If the bus enable signal indicates that the bus is in use by the CPU or a peripheral module, the access controller waits for the bus to become available, and then transfers the data to the debugging device. 
         [0007]    A problem with this conventional access controller is that the debugging device cannot easily control the timing at which the RAM or register is actually accessed, since this timing depends only on the time at which the debugging device sets information in the access controller and on the bus enable signal output by the CPU. In many debugging situations it would be desirable to know what data are stored at a particular address when the CPU is executing a particular part of its program or when a particular event occurs, but the address setting timing and bus enable signal do not provide this type of access timing control. 
         [0008]    U.S. Pat. No. 7,020,813 to Fujiuchi discloses a microcontroller with an on-chip RAM monitor function in which the access controller includes a control flag that can be set by instructions in the program. The access controller operates only when the flag is set. This enables the RAM monitor timing to be synchronized with program execution, but the need to embed extra instructions in the program is sometimes inconvenient. 
       SUMMARY OF THE INVENTION 
       [0009]    A general object of the present invention is to facilitate the debugging of a microcontroller. 
         [0010]    A more particular object is to synchronize RAM monitoring with a specific event. 
         [0011]    The invention provides a microcontroller having a CPU, a memory, and at least one peripheral module interconnected by a system bus. The microcontroller also has a data transceiver and an access controller. 
         [0012]    The data transceiver receives monitor address information from an external device. The monitor address information designates a location in the memory or a location in the peripheral module. 
         [0013]    The access controller is interposed between the data transceiver and the system bus and is connected directly to the CPU. When the CPU or the peripheral module satisfies a predetermined condition, the access controller accesses the location designated by the monitor address and transfers data between the external device and the designated location. 
         [0014]    The predetermined condition may be, for example, the execution by the CPU of an instruction at a designated address, or the generation of an interrupt by the CPU or the peripheral module. 
         [0015]    The predetermined condition may also include availability of the system bus, as indicated by a bus enable signal output by the CPU. 
         [0016]    An external debugging device can accordingly monitor a designated location in the memory or the peripheral module and determine the contents of the designated memory location at a particular point in the program executed by the CPU, or when a particular event occurs and generates an interrupt. Debugging is facilitated because the debugging device can be sure of obtaining information relevant to the instruction or event, and no extra instructions need be embedded in the program to control the monitoring operation. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    In the attached drawings: 
           [0018]      FIG. 1  is a block diagram of a microcontroller according to a first embodiment of the invention; 
           [0019]      FIG. 2  is a block diagram of a microcontroller according to a second embodiment; and 
           [0020]      FIG. 3  is a block diagram of a conventional microcontroller. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. 
       First Embodiment 
       [0022]    Referring to  FIG. 1 , the microcontroller in the first embodiment comprises a central processing unit (CPU)  1 , a nonvolatile read-only memory (ROM)  2 , a random access memory (RAM)  3 , and at least one peripheral module  4 . These facilities are linked to a system bus  5  comprising an address bus  5 A and a data bus  5 D. 
         [0023]    The CPU  1  is a well-known circuit that executes a program stored in the ROM  2 . The CPU  1  has a program counter (not shown) that indicates the address of the next instruction the CPU  1  will execute, so that the CPU  1  can fetch the instruction from the ROM  2  via the system bus  5 . During program execution, the CPU  1  may also access the RAM  3  via the system bus  5 , either to write data for temporary storage or to read data stored earlier. The CPU  1  outputs a bus enable signal (BEN) that is inactive (low) when the system bus  5  is in use and active (high) when the system bus  5  is not in use and is therefore available for RAM monitoring use. 
         [0024]    The peripheral module  4  comprises specialized hardware for executing a specific function at the direction of the CPU  1 . The peripheral module  4  has one or more internal registers, sometimes referred to as special function registers, for storing control data or other data related to the function performed by the peripheral module  4 . These registers are designated by addresses on the address bus  5 A and are accessed in substantially the same way as the RAM  3 . 
         [0025]    The microcontroller also includes a data transceiver  6  and an access controller  10 A. 
         [0026]    The data transceiver  6  has external terminals  7  for receiving a clock signal (CLK) and address signals (ADR) from an external device (not shown) and transferring data (DAT) between the external device and the access controller  10 A in synchronization with the clock signal. In the following description the external device is a debugging device. Upon receiving address signals, the data transceiver  6  passes the address as a monitor address to the access controller  10 A and generates a set signal. 
         [0027]    The access controller  10 A comprises an address register  11  that stores the monitor address received from the data transceiver  6 , a data register  12  that stores data transferred to or from the data transceiver  6 , and a timing controller  13  that receives the monitor address from the address register  11  and generates control signals. The control signals access the location designated by the monitor address by transferring data between the data register  12  and designated location via the system bus  5 . The designated location may be a memory location in the RAM  3  or a register in the peripheral module  4 , and may be a single-address location or a location spanning a range of addresses. When the timing controller  13  finishes accessing the designated location, it also asserts a reset (RST) signal. 
         [0028]    The set signal generated by the data transceiver  6  and the reset signal generated by the timing controller  13  are received at the set terminal (S) and reset terminal (R) of a first flip-flop (FF)  14  in the access controller  10 A. The first flip-flop  14  outputs a flag signal (FLG) from its output terminal (Q). 
         [0029]    The access controller  10 A also includes an AND gate  15 A, a comparison register  16 , a comparator  17  and a second flip-flop  18 . The comparison register  16  stores an instruction address, which may be set by the external debugging device or by manual switches (not shown). The comparator  17  is connected to the comparison register  16  and the CPU  11  and compares the program counter value (PCV) in the CPU  1  with the instruction address stored in the comparison register  16 . When the program counter value matches the stored instruction address, the comparator  17  generates an equality signal (EQU) that sets the second flip-flop  18 . The second flip-flop  18  is reset by the set signal from the data transceiver  6 , and generates a timing signal (TIM). The AND gate  15 A receives the timing signal from the second flip-flop  18 , the flag signal from the first flip-flop  14 , and the bus enable signal from the CPU  1 , and generates a start signal (STA) that activates the timing controller  13 . 
         [0030]    Next the debugging of the microcontroller in  FIG. 1  will be described. 
         [0031]    The debugging is typically carried out in-circuit, that is, with the microcontroller mounted in a circuit similar to the one in which it will actually be used. The debugging device is typically an engineering workstation connected to the external terminals  7  of the data transceiver  6  by a cable. In the debugging process, the CPU  1  executes the program stored in the ROM  2  under various conditions, and the debugging device observes the results produced. 
         [0032]    During the debugging process, it is often useful to observe the contents of a particular RAM location or a particular peripheral module register at a particular point in program execution. Alternatively, it may be useful to intervene at a particular point in program execution by writing particular data in a particular RAM location or peripheral module register. In these cases, before program execution begins, an instruction address indicating the particular point in the program is set in the comparison register  16  by the debugging device or manually, and the address of the particular location or register is sent to the data transceiver  6  and set in the address register  11  as a monitor address. If write access to the monitor address is required, the data to be written are also sent to the data transceiver  6  and stored in the data register  12 . 
         [0033]    When the data transceiver  6  writes the monitor address in the address register  11 , it drives the set signal to the high (‘1’) logic level. This action sets the first flip-flop  14  and resets the second flip-flop  18 , so that the flag signal (FLG) is high (‘1’) and the timing signal (TIM) is low (‘0’). Since the timing signal is low, the start signal (STA) output by the AND gate  15 A is also low, despite the active flag signal (FLG) and regardless of the state of the bus enable signal (BEN). The low start signal (STA) holds the timing controller  13  in the inactive state. 
         [0034]    The CPU  1  then executes its program until the program counter value (PCV) matches the instruction address stored in the comparison register  16 . At that point the equality signal (EQU) output by the comparator  17  goes high, setting the second flip-flop  18 , so the timing signal (TIM) goes high. 
         [0035]    If the system bus  5  is not in use at this instant and is available for use by the access controller  10 A, the bus enable signal BEN will also be high. Accordingly, all inputs to the AND gate  15 A will be high, so the start signal (STA) will go high, activating the timing controller  13 . The timing controller  13  then places the monitor address on the address bus  5 A and generates control signals that transfer the data stored at the location designated by the monitor address into the data register  12  (read access) or transfer the data stored in the data register  12  to the designated location (write access). 
         [0036]    If the CPU  1 , peripheral module  4 , or another peripheral module (not shown) is using the system bus  5  when the timing signal goes high, so that the bus enable signal (BEN) is low, the start signal remains low until the CPU  1  or peripheral module relinquishes the bus, at which point the bus enable signal goes high. When the bus enable signal goes high, the start signal also goes high, and the timing controller  13  accesses the monitor address location. 
         [0037]    In either case, as soon as the timing controller  13  has finished transferring data to or from the monitor address location, it asserts the reset signal (RST), thereby forcing the flag signal (FLG) to the low logic level. The start signal (STA) then goes low and the timing controller  13  is deactivated. In the read access case, the external device can now read the data obtained by the timing controller  13  from the data register  12  while the CPU  1  continues to execute the program stored in the ROM  2 . 
         [0038]    The first embodiment enables the debugging device to access a designated RAM location or peripheral module register at a known point in program execution, either at the execution of a known instruction or at the first opportunity after the execution of the known instruction. A person skilled in the debugging art will realize that there are many ways in which this feature can be used. 
         [0039]    In a variation of the first embodiment, the timing controller  13  is used only for read access to the location designated by the monitor address. 
         [0040]    In another variation, the comparator  17  obtains the program counter value from the value placed by the CPU  1  on the address bus  5 A, instead of receiving it directly from the CPU  1 . 
       Second Embodiment 
       [0041]    The second embodiment modifies the access controller so that monitor access is responsive to an interrupt instead of to the program counter value. 
         [0042]    Referring to  FIG. 2 , the access controller  10 B in the second embodiment includes an OR gate  19  in place of the comparison register and comparator of the first embodiment. The OR gate  19  receives an interrupt request (IRQ) signal from the peripheral module  4  and an interrupt signal from the CPU  1 , and outputs an interrupt signal (INT) to the set terminal (S) of the second flip-flop  18 . Other parts of the microcontroller in  FIG. 2  are identical to the corresponding parts of the microcontroller in the first embodiment ( FIG. 1 ). 
         [0043]    For the debugging process in the second embodiment, it is not necessary to set an instruction address before program instruction begins. The debugging device only has to transfer a monitor address to the data transceiver  6 , which sets the monitor address in the address register  11 . As in the first embodiment, this activates the set signal, setting the first flip-flop  14  and resetting the second flip-flop  18 , so that the start signal (STA) output by the AND gate  15 A is low and the timing controller  13  is held in the inactive sate. 
         [0044]    During program execution, the timing controller  13  remains inactive until the CPU  1  or peripheral module  4  generates an interrupt. An interrupt generated by the peripheral module  4  typically indicates the completion of a timing interval or a specialized hardware operation. An interrupt generated by the CPU  1  typically indicates a program exception such as an undefined instruction or some other type of error. When an interrupt occurs, one of the signals received by the OR gate  19  goes high, causing the interrupt signal output by the OR gate  19  to go high, setting the second flip-flop  18 . The timing signal (TIM) consequently goes high. 
         [0045]    When the timing signal goes high, the start signal output by the timing controller  13  goes high, either immediately or as soon as the system bus  5  becomes available, as explained in the first embodiment. The high start signal activates the timing controller  13 , which accesses the memory location or peripheral module register designated by the monitor address. Upon completion of access, the timing controller  13  asserts the reset signal (RST), resetting the first flip-flop  14  so that the flag signal (FLG) and start signal (STA) return to the low logic level, deactivating the timing controller  13 . 
         [0046]    The second embodiment enables the debugging device to access a designated memory location or peripheral module register when a particular event occurs, as indicated by an interrupt. This provides a useful way to monitor circumstances surrounding events that are not synchronized with the execution of a particular instruction but might occur at any point in program execution. 
         [0047]    The variations of the first embodiment noted above also apply to the second embodiment. 
         [0048]    For comparison with the preceding embodiments,  FIG. 3  shows a conventional microcontroller generally similar to the microcontrollers in  FIGS. 1 and 2  but lacking the comparison register and comparator of the first embodiment and the OR gate of the second embodiment. Accordingly, the AND gate  15  in the access controller  10  receives only the flag signal (FLG) from the first flip-flop  14  and the bus enable signal (BEN) from the CPU  1 . 
         [0049]    In this conventional microcontroller, the debugging device can monitor arbitrary memory locations and peripheral module registers by sending their addresses to the data transceiver  6  to be written in the address register  11  of the access controller  10 , but the access controller  10  cannot accurately synchronize its monitoring activities with the execution of particular instructions by the CPU  1  or the occurrence of particular interrupt-generating events. The information obtained by monitoring is therefore not as useful as the information obtainable in the first and second embodiments. 
         [0050]    A few variations of the preceding embodiments have already been mentioned, but those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.
A microcontroller has a RAM monitor function that facilitates debugging by enabling a debugging device to specify a location and access the specified location during program execution. Access takes place when the microcontroller's central processing unit or a peripheral module in the microcontroller satisfies a predetermined condition. The access can therefore be synchronized with the execution of a particular instruction, or the occurrence of an interrupt.