BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to a super VGA (video graphic array) monitor interface circuit and, more particularly, to a super VGA monitor interface circuit in which an output mode of a monitor is controlled by an input signal frequency regardless of the width and polarity of vertical and horizontal synchronizing input signals. 
     (2) Related Prior Art 
     A conventional super VGA (video graphic array) interface circuit controls an output mode of a monitor according to the width and polarity of vertical and horizontal synchronizing input signals. Because the resolution and screen display technique of the monitor becomes different in accordance with the output mode of the monitor, it is considerably important to definitely divide the output modes. The exact dividing and controlling of the output mode of the monitor makes the definite display of the picture information on a screen possible. 
     However, because the conventional super VGA monitor interface circuit controls the output mode of the monitor according to the width and polarity of the vertical and horizontal synchronizing input signals, it is difficult to control the output mode of the monitor when the width and polarity of the vertical and horizontal synchronizing input signals are different from each other to the kind of video cards. 
     SUMMARY OF THE INVENTION 
     Thus, to overcome the above-described conventional art, an object of the present invention is to provide a super VGA monitor interface circuit which controls the output mode of a monitor only by a frequency of an input signal regardless of the width and polarity of vertical and horizontal synchronizing input signals. 
     The structure of the present invention is formed by a polarity converting part in which the vertical and horizontal synchronizing signals are employed as an input signal, and, if the input signal is negative polarity, it is converted to positive polarity to be output, whereas, if the input signal is positive polarity, it is output as positive polarity; a signal separating part which divides the input signals into 800×600 mode, 1024×768 mode and the other mode with being connected to the above polarity converting part; and an output part which is connected to the polarity converting part and signal separating part and divides the input signals into each mode to output a control signal needed in a monitor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further advantages and other objects of the present invention will be apparent from the detailed description of the invention in connection with the accompanying drawings, in which: 
     FIG. 1 is a whole block diagram of a super VGA (video graphic array) interface circuit of an embodiment of the present invention; 
     FIG. 2 is a detailed circuit diagram of a polarity converting part of an embodiment of the present invention; 
     FIG. 3 is a detailed circuit diagram of a signal separating part of an embodiment of the present invention; and 
     FIG. 4 is a detailed circuit diagram of an output part of an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiment of the present invention of the above structure will be, in detail, disclosed with reference to the drawings as follows. FIG. 1 shows, in a block diagram, a super VGA (video graphic array) interface circuit of an embodiment of the present invention. As revealed in the figure, the super VGA interface circuit structure has 
     a polarity converting part 10 employing vertical and horizontal synchronizing signals VSYNC, HSYNC as an input signal; 
     a signal separating part 20 where input terminals are connected to an output terminal of the polarity converting part 10; and 
     an output part 30 where input terminals are connected to the output terminals of the polarity converting part 10 and signal separating part 20. 
     FIG. 2 shows, in a circuit diagram, the polarity converting part of an embodiment of the present invention. As revealed in the figure, the polarity converting part 10 has 
     a resistor R11 connected between a vertical synchronizing signal line VSYNC and a ground; 
     a first exclusive OR gate G11 where one input terminal is connected to the vertical synchronizing signal line VSYNC, and another input terminal is grounded; 
     the resistor R12 where one terminal is connected to an output terminal of the first exclusive OR gate G11; 
     a capacitor C11 connected between another terminal of the resistor R12 and the ground; 
     a second exclusive OR gate G12 where one input terminal is connected to the connecting point of the resistor R12 and the capacitor C11, and another input terminal is connected to the vertical synchronizing signal line VSYNC; 
     the resistor R13 connected between a horizontal synchronizing signal line HSYNC and the ground; 
     a third exclusive OR gate G13 where one input terminal is connected to the horizontal synchronizing signal line HSYNC, and another input terminal is grounded; 
     the resistor R14 where one terminal is connected to an output terminal of the third exclusive OR gate G13; 
     the capacitor C12 connected between another terminal of the resistor R14 and the ground; and 
     a fourth exclusive OR gate G14 where one input terminal is connected to one terminal of the resistor R14, and another input terminal is connected to the horizontal synchronizing signal line HSYNC. 
     FIG. 3 shows, in a circuit diagram, the signal separating part of an embodiment of the present invention. As revealed in the figure, the signal separating part 20 has 
     the resistor R21 where one terminal is connected to the output terminal of the second exclusive OR gate G12 of the polarity converting part 10; 
     a first transistor Q21 where a base terminal is connected to another terminal of the resistor R21, and an emitter terminal is grounded; 
     the resistor R22 connected between a supply voltage Vcc and a collector terminal of the first transistor Q21; 
     a first monostable multivibrator MV21 where an A input terminal is connected to the collector terminal of the first transistor, and a B input terminal is connected to the supply voltage Vcc; 
     the resistor R23 where one terminal is connected to a reverse output terminal Q of the monostable multivibrator MV21; 
     the capacitor C21 connected between another terminal of the resistor R23 and the ground; 
     the capacitor C22 where one terminal is connected to the output terminal of the fourth exclusive OR gate G14 of the polarity converting part 10; 
     a second transistor Q22 in which the base terminal is connected to another terminal of the capacitor C22, and the emitter terminal is grounded; 
     the resistor R25 connected between the supply voltage Vcc and the collector terminal of the second transistor Q22; 
     the resistor R24 connected between the supply voltage Vcc and the base terminal of the second transistor Q22; 
     a second monostable multivibrator MV22 where the A input terminal is connected to the collector terminal of the second transistor, and the B input terminal connected to the supply voltage Vcc; 
     the resistor R26 where one terminal is connected to a reverse output terminal Q of the second monostable multivibrator MV22; and 
     the capacitor C23 connected between another terminal of the resistor R26 and the ground. 
     In the embodiment of the invention, an MC14538B chip is used as a monostable multivibrator MV21, MV22. However, the technical range of the invention is not limited within that. 
     FIG. 4 shows, in a circuit diagram, an output part of an embodiment of the present invention. As revealed in the figure, the output part has 
     the resistor R31 where one terminal is connected to the connecting point of the resistor R23, and the capacitor C21 of the signal separating part; 
     the transistor Q31 where the base terminal is connected to another terminal of the resistor R31, and the emitter terminal is grounded; 
     the resistor R32 connected between the supply voltage Vcc and the collector terminal of the transistor Q31; 
     the resistor R39 where one terminal is connected to the connecting point of the resistor R26a and the capacitor C23, of the signal separating part 20; 
     the transistor Q34 where the base terminal is connected to another terminal of the resistor R39, and the emitter terminal is grounded; 
     the resistor R40 connected between the supply voltage Vcc and the collector terminal of the transistor Q35; 
     the resistor R41 where one terminal is connected to the collector terminal of the transistor Q34; 
     the transistor Q35 where a base terminal is connected to another terminal of the resistor, and an emitter terminal is grounded; 
     the resistor R42 connected between the supply voltage Vcc and the collector terminal of the transistor Q35; 
     a first decoder D31 where the B input terminal is connected to the collector terminal of the transistor Q31, the A input terminal is grounded, and an enable terminal G is connected to the collector terminal of the transistor Q35; 
     the resistor R43 where one terminal is connected to the collector terminal of the transistor Q35; 
     the resistor R44 connected between another terminal of the resistor R43 and the ground; 
     the transistor Q36 where the base terminal is connected to the connecting point of the resistors R43, R44, and the emitter terminal is grounded; 
     the resistor R45 connected between the collector terminal of the transistor Q36 and the supply voltage Vcc; 
     a second decoder D32 where the A input terminal is connected to the connecting point of the resistor R12, and capacitor C11 of the polarity converting part 10, the B input terminal is connected to the connecting point of the resistor R14 and capacitor C12 of the polarity converting part 10, and the enable terminal G is connected to the collector terminal of the transistor Q34; 
     the resistor R33 where one terminal is connected to an output terminal Y0 of the first decoder D31; 
     the resistor R34 connected between another terminal of the resistor R33 and the ground; 
     the transistor Q32 where the base terminal is connected to the connecting point of the resistors R33, R34, and the emitter terminal is grounded; 
     the resistor R35 connected between the collector terminal of the transistor Q32 and the supply voltage Vcc; 
     the resistor R36 where one terminal is connected to the collector terminal of the transistor Q32; 
     the resistor R38 connected between another terminal of the resistor R36 and the ground; 
     the transistor Q33 where the base terminal is connected to the connecting point of the resistors R36, R38, and the emitter terminal is grounded; and 
     the resistor R37 connected between the collector terminal of the transistor Q33 and the supply voltage Vcc. 
     In this embodiment of the present invention, a 74139 chip is used as the decoders D31, D32. However, the usable range of the invention is not limited to the above description. 
     According to the embodiment of the present invention of the above structure, the operation of the super VGA (video graphic array) monitor interface circuit is as follows. 
     After applying the supply voltage Vcc, the vertical and horizontal synchronizing signals VSYNC, HSYNC of modes such as in Table 1 are input into the polarity converting part 10. 
     
                       TABLE 1______________________________________   VSYNC             HSYNCMODE      frequency polarity  frequency                                 polarity______________________________________640 × 480     60 Hz     -         31.5 KHz                                 -640 × 400     70 Hz     +         31.5 KHz                                 -640 × 350     70 Hz     -         31.5 KHz                                 +800 × 600     56 Hz     --        35.5 KHz                                 -1024 × 768     87 Hz     +         35.5 KHz                                 +______________________________________ 
    
     When a duty cycle of the input signal is small, it is called a positive polarity. When the duty cycle is large, it is called a negative polarity. According to the characteristics of video cards, there may be a difference in the polarity input signal of each mode. The range is not limited by the polarity of the input signal of Table 1 as shown above. 
     The input signals VSYNC, HSYNC pass through the first and third exclusive OR gate G11, G13 and the capacitors C11, C12 are, respectively, charged. Since the duty cycle is large when the polarity of the input signal VSYNC, HSYNC is positive, the capacitors C11, C12 are, respectively, charged with a high potential. Whereas, those which are negative when the duty cycle is small, the capacitors C11, C12 are, respectively, charged with a low potential. When the polarity of the input signals VSYNC, HSYNC is negative, the input signals are reversed to output signals. When the input signals are positive, the input signals are then output. 
     If the output signal of the polarity converting part 10 is input into the signal separating part 20, the signal separating part 20 is operated. If the signal a high state is input into the base terminal of the transistors Q21, Q22, the transistors Q21, Q22 turn on. If the signal of a low state is input into the base terminal of the transistors Q21, Q22, the transistors turn off, so that the phase of the input signal is reversed to output, and the output signals of the transistors Q21, Q22 are input into the A terminals of the first and second monostable multivibrators MV21, MV22. 
     The first monostable multivibrator MV21 has the operating characteristics that when it is triggered at the positive-going edge of the input signal, the reverse output terminal Q has a low state during a period of time which is comparatively somewhat less than 1/87(HZ). Thus, when the input signal is in a 1024×768 mode, the capacitor C21 is charged by the low potential to be output. When it is in the other mode, the capacitor C21 is charged by the high potential to be output. The second monostable multivibrator MV22 has the operating characteristics that when it is triggered at the top edge of the A input signal, the reverse output terminal Q has a low state during a period of time which is somewhat less than 1/35.5(KHZ). Accordingly, when the input signal is in an 800×600 mode or 1024×768 mode, the capacitor is charged by the low potential to be output. When it is in the other mode, the capacitor C22 is charged by the high potential to be output. 
     If the output signal of the signal separating part 20 is input into the output part 30, the output part 30 is operated. When the high state signal is input into the transistor Q34, it turns on. Thus, the second decoder D32 is enabled, and the transistor Q35 turns off. Because the transistor Q35 turns off, the first decoder D31 is disabled, and the transistor Q36 turns on. However, if the low state signal is input into the transistor Q34, it turns off. The second decoder D32 is disabled, and the transistor Q35 turns on. Thus, the transistor Q35 turns on, so that the first decoder D31 is enabled, and the transistor Q36 turns off. 
     Thus, when the input signal is in a 800×600 mode or 1024×768 mode, the low state signal is output to the output terminal OUT1. When the input signal is in the other mode, the high state signal is output. 
     When the first decoder D31 is disabled, the output terminals Y0, Y2 output the high state signal. When the first decoder D31 is enabled, and when the input signal of the transistor Q31 is in a low state, the transistor Q31 turns off. When the B input terminal of the decoder D31 is supplied with a high state signal, the output terminals Y0, Y2 of the first decoder D31 each output the low and high state signals. Also, when the first decoder D31 is enabled, and when the input signal of the transistor Q31 is in a high state, the transistor Q31 turns on. When the B terminal of the decoder D31 is supplied with the low state signal, then the output terminals Y0, Y2 of the first decoder D31 each output the high and low state signals. 
     When the output signal of output terminal Y0 of the first decoder D31 is in a high state, transistor Q32 turns on, and transistor Q33 turns off. Thus, the collector terminal of transistor Q33 outputs the high state signal. However, when the output signal of output terminal Y0 of the first decoder D31 is in a low state, transistor Q32 turns off, and transistor Q33 turns on. Accordingly, the collector terminal of transistor Q33 outputs the low state signal. 
     When the input signal is in the 800×600 mode, the low state signal is output to the second output terminal OUT2. In case of the other mode, the high state signal is output. 
     When the second decoder D32 is disabled, the output terminals Y1, Y2, Y3 output the high state signal. When the second decoder D32 is enabled, the second decoder D32 of the output terminals Y1, Y2, Y3 output the decoding signal of the A and B input signals. 
     Table 2 shows the result of changing the output signals OUT1, OUT2, OUT31-OUT34 of output part 30 according to the mode of the vertical and horizontal synchronizing input signals VSYNC, HSYNC. 
     
                       TABLE 2______________________________________mode     OUT1    OUT2    OUT31 OUT32 OUT33 OUT34______________________________________640 × 480    L       H       H     H     L     H640 × 400    L       H       H     L     H     H640 × 350    L       H       L     H     H     H800 × 600    H       L       H     H     H     H1024 × 768    H       H       H     H     H     L______________________________________ Note) L is represented as the low state. H is represented as the high state. 
    
     The above output signal OUT1 is used as the control signal of B + , H-Hold, H-SHIFT, and the like, by dividing the horizontal synchronizing signal frequencies of 31.5 kHz and 35.5 kHz. The output signal OUT2 is used as the control signal of H-SHIFT, V-HOLD, and the like, by dividing the basic mode of 800×600 mode. The output signals OUT31-OUT 34 are used as the control signal of V-SIZE and the line by dividing each mode. 
     As described above, the embodiment of the present invention can provide the super VGA monitor interface circuit which may control the output mode only by the input signal frequency regardless of the width and polarity of the vertical and horizontal synchronizing input signals. Such effect of the present invention can be applied to the information output field using the monitor of the computer.
The conventional super VGA (video graphic array) monitor interface circuit controls the output mode of the monitor according to the width and polarity of vertical and horizontal synchronizing input signals, so it has disadvantage that it is difficult to control the output mode of the monitor when the width and polarity of the vertical and horizontal synchronizing input signals are different according to the kind of video cards. The present invention is such that the vertical and horizontal synchronizing signals are employed as an input signal. If the input signal is negative polarity, it is converted to positive polarity for output and, if the input signal is positive polarity, it is output with positive polarity. The signal separating part divides the input signal connected to the above polarity converting part into an 800x600 mode, a 1024x768 mode or any other mode. An output part which is connected to a polarity converting part and signal separating part outputs a control signal needed in a monitor by dividing the input signal into each mode. Thus, the present invention relates to the super VGA monitor interface circuit which solves conventional problems in the art by controlling the output mode of the monitor only by an input signal frequency regardless of the width and polarity of the vertical and horizontal synchronizing input signals.