BACKGROUND OF THE INVENTION  
         [0001]    1. Field of Invention  
           [0002]    The present invention pertains to the field of electronic circuits. More particularly, this invention relates to switching circuits.  
           [0003]    2. Art Background  
           [0004]    A wide variety of systems commonly include switching circuits that employ field effect transistors (FETs) as switching devices. A typical switching circuit based on an FET provides an “on” state in which electrical current flows in the channel of the FET between the source and the drain of the FET and an “off” state in which electrical current is pinched off from flowing through the channel of the FET. The on/off state of a switching circuit based on an FET is usually controlled by bias voltages applied to the FET.  
           [0005]    In many systems, the FETs in switching circuits are commonly subjected to relatively large voltages when in the off state. For example, a mobile telephone usually includes a switching circuit that connects its antenna to its receiver. Typically, the FET in the switching circuit when in its off state is subjected to a relatively large voltage drop from a transmit signal generated in the mobile telephone.  
           [0006]    A relatively large voltage applied across the channel of an FET when it is in its off state may cause the FET to inadvertently switch to its on state. The maximum voltage that can be applied across the channel of an FET while maintaining its off state may be referred to as the withstanding voltage of the FET.  
           [0007]    Unfortunately, an FET that inadvertently switches on when its withstanding voltage is exceeded may cause a variety of undesirable effects. In a mobile telephone, for example, a switching circuit that connects an antenna to a receiver may inadvertently switch on if the withstanding voltage of the FET in the switching circuit is exceeded, thereby severely distorting its transmit signal.  
         SUMMARY OF THE INVENTION  
         [0008]    A switching circuit is disclosed that employs equity voltage division among a series of transistors to reduce the likelihood that the withstanding voltages of individual transistors will be exceeded. A switching circuit according to the present teachings includes a series of transistors and circuitry for biasing the transistors such that a voltage input to the switching circuit divides substantially equally among the transistors when the transistors are in an off state.  
           [0009]    Other features and advantages of the present invention will be apparent from the detailed description that follows.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention is described with respect to particular exemplary embodiments thereof and reference is accordingly made to the drawings in which:  
         [0011]    [0011]FIG. 1 shows a switching circuit with equity voltage division according to the present teachings;  
         [0012]    [0012]FIG. 2 shows one embodiment of a switching circuit according to the present teachings including the components in its bias circuit;  
         [0013]    [0013]FIGS. 3-5 show embodiments of a switching circuit according to the present teachings including the components in its bias circuit.  
     
    
     DETAILED DESCRIPTION  
       [0014]    [0014]FIG. 1 shows a switching circuit  10  with equity voltage division according to the present teachings. The switching circuit  10  includes a set of FETs (transistors Q 1  through Qn) that are arranged in series from a node  20  of the switching circuit  10  through a series of nodes  22 - 26  to a node  28  of the switching circuit  10 . The switching circuit  10  includes a bias circuit  14  that biases the transistors Q 1 -Qn. An AC source  12  is shown coupled to the node  20  and a load  16  is shown connected to the node  28 .  
         [0015]    The transistors Q 1 -Qn and the components in the bias circuit  14  are selected and arranged such that the voltage generated by the AC source  12  is substantially equally divided among the transistors Q 1 -Qn when the transistors Q 1 -Qn are biased in the off state. For example, the AC voltage drop across the transistor Q 1  between the nodes  20  and  22  is substantially equal to the voltage drop across the transistor Q 2  between the nodes  22  and  24  which is substantially equal to the AC voltage drop across the transistor Qn between the nodes  26  and  28  when the transistors Q 1 -Qn are in an off state. As a consequence, each of the transistors Q 1 -Qn in its off state is subjected to 1/n of the total magnitude of the voltage from the AC source  12 , thereby decreasing the likelihood that the withstanding voltages of the transistors Q 1 -Qn will be exceeded. The number and the sizes of the transistors Q 1 -Qn may be pre-selected such that the voltage drop across each transistor Q 1 -Qn does not exceed its withstanding voltage given the magnitude of the AC source  12 .  
         [0016]    The bias circuit  14  applies bias voltages to the transistors Q 1 -Qn to switch each transistor Q 1 -Qn between its on and off states as needed to open and close the switching circuit  10 . The components in the bias circuit  14  are selected and arranged so that the substantially equal voltage division among the transistors Q 1 -Qn is maintained. For example, the selection and arrangement of components in the bias circuit  14  avoids the creation of AC paths to ground that might otherwise destroy the symmetry of the switching circuit  10  and defeat its equity voltage division.  
         [0017]    [0017]FIG. 2 shows one embodiment of the switching circuit  10  including the components in its bias circuit  14 . This embodiment provides equity voltage division using two series connected transistors—the transistors Q 1  and Q 2 , i.e. n=2. The transistors Q 1  and Q 2  are the switching FETs and are operated in series to maximize the overall withstanding voltage of the switching circuit  10 .  
         [0018]    The bias circuit  14  in this embodiment includes a DC supply  30 , a set of resistors R 1 -R 8 , and a set of capacitors C 1 -C 3 . In this embodiment, the AC source  12  is AC coupled to the node  20  via a capacitor C 4 . The bias circuit  14  in the embodiment shown turns off the transistors Q 1  and Q 2  by applying −3 volts to the gates of the transistors Q 1  and Q 2 . The resistors R 1 -R 6  are selected such that R 1 =R 2 , R 3 =R 5 , and R 4 =R 6 . Thus, in the absence of resistors R 7 , R 8  and the DC supply  30  the voltage drop across the transistor Q 1  between the nodes  20  and  22  is substantially equal to the voltage drop across the transistor Q 2  between the nodes  22  and  28 .  
         [0019]    The resistors R 7 , R 8  and the DC supply  30  are arranged so as to not upset the symmetry of voltage division across the transistors Q 1  and Q 2 . The DC supply  30  is tied in through the resistors R 7  and R 8 . The capacitors C 1 -C 3  AC couple the resistor divider of R 3 -R 6  to the transistors Q 1 -Q 2 .  
         [0020]    The terminals of the resistors R 7  and R 8  that are opposite of ground have the same AC potential. The DC supply  30  appears as a circuit that is in parallel with the AC source  12  from an AC perspective. There are no additional paths through which current can escape from the nodes  22 ,  28  to ground and all of the AC current that enters the node  20  and proceeds into the first transistor Q 1  flows through to the node  28 . Thus, the AC current in the transistor Q 1  equals the AC current in the transistor Q 2 . Given that the transistors Q 1  and Q 2  are surrounded by substantially identical components and provided that the size of the transistors Q 1  and Q 2  are substantially similar, the AC voltage drop is substantially equally divided among the transistors Q 1  and Q 2 .  
         [0021]    The resistors R 1 , R 2 , and R 7  provide a DC reference for the channels of the transistors Q 1  and Q 2  to ground. The capacitors C 4  and C 5  provide the channels of the transistors Q 1  and Q 2  with DC isolation from the AC source  12  and the load R 9 . The resistors R 3 -R 6  connect the gates of the transistors Q 1  and Q 2  to the DC supply- 30 .  
         [0022]    The entire ladder structure defined by the resistors R 1 -R 6 , the capacitors C 1 -C 3 , and the transistors Q 1 -Q 2  may be viewed as a periodic ladder structure in which each stage of the ladder structure is substantially similar to the last including substantially similar arrangements of components with substantially similar component values. As a consequence, an input voltage at the node  20  drops equally across the transistors Q 1  and Q 2  because each ladder stage has the same impedance as the previous stage.  
         [0023]    When the DC supply  30  voltage is below the threshold voltage of the transistors Q 1  and Q 2 , the switching circuit  10  is off, and the voltage at the node  28  is close to zero. When the DC supply  30  voltage is above the threshold voltage of the transistors Q 1  and Q 2 , the switching circuit  10  is on and signal energy from the AC source  12  is effectively coupled to the load R 9 .  
         [0024]    In embodiments in which enhancement mode FETs are used as the transistors Q 1  and Q 2 , a finite amount of gate current should be supplied in the on state. The appropriate amount of gate current may be supplied through the gate bias resistors. Other methods may be employed to apply the appropriate gate bias voltages to the FETs. In addition, either pole of the DC supply  30  may be referenced to ground.  
         [0025]    If an even number of transistors is used to form the switching circuit  10 , its ladder structure is preferably composed of substantially identical pairs of ladder sections, i.e. R 3 =R 5 , R 4 =R 6 , R 1 =R 2 . In addition, the widths W of the transistors Q 1  and Q 2  are substantially equal, i.e. W(Q 1 )=W(Q 2 ). Alternatively, if an even number of transistors is used to form the switching circuit  10 , its ladder structure is preferably composed of mirror image ladder sections, i.e. R 3 =R 6 , R 4 =R 5 , R 1 =R 2 , and W(Q 1 )=W(Q 2 ).  
         [0026]    If an odd number of transistors is used to form the switching circuit  10 , the ladder structure is preferably composed of substantially similar sections, i.e. R 3 =R 5 , R 4 =R 6 , R 1 =R 2 , and W(Q 1 )=W(Q 2 ).  
         [0027]    In one embodiment, the resistors connecting each gate to the corresponding FET source and drain may be identical, i.e. R 3 =R 4 , and R 5 =R 6 .  
         [0028]    The nodes  40 - 43  have paths to ground through the resistor R 8 . The electrical current paths to ground from each node  40 - 43  includes the node  20  or nodes that are the AC equivalent to the node  20 . Thus, the AC signal in the switch  10  that flows past the node  20  and proceeds into the first transistor Q 1  has no escape from the switch structure until it emerges from the node  28 . This maintains substantial equity voltage division in the switch  10 .  
         [0029]    [0029]FIG. 3 shows another embodiment of the switching circuit  10  including the components in its bias circuit  14 . In this embodiment, the connection to node  22  is eliminated and the capacitor C 2  is eliminated and the resistors R 4  and R 5  are merged into R 11  where preferably R 11 = 2 R 3 = 2 R 6 .  
         [0030]    [0030]FIG. 4 shows yet another embodiment of the switching circuit  10 . In this embodiment, the opposite side of the DC supply  30  is referenced to ground in comparison to the embodiments shown above.  
         [0031]    [0031]FIG. 5 shows still another embodiment of the switching circuit  10 . In this embodiment, two separate DC supplies  30 - 31  are employed.  
         [0032]    Each transistor in a ladder structure of a switching circuit according to the present teachings operates beneficially from having. the magnitude of AC gate to source voltage being equal to the AC gate to drain voltage. This is in addition to the benefit derived from having substantially equal AC voltage drops across each transistor. It is also preferable that the transistors used in the ladder structure be formed symmetrically, so that no physical distinction exists between the source and drain terminals.  
         [0033]    A switching circuit according to the present teachings provide a high power switch that creates a relatively low on state insertion loss as well as a relatively high off state isolation and withstanding voltage. The present teachings enable the use of a relatively low overall transistor size in comparison to prior art schemes. The present techniques yield an off state withstanding voltage that is proportional to the number of transistors that are arranged in series. This lowers the number series transistors required to achieve a particular off state withstanding voltage and consequently lowers the insertion loss and final die size.  
         [0034]    The foregoing detailed description of the present invention is provided for the purposes of illustration and is not intended to be exhaustive or to limit the invention to the precise embodiment disclosed. Accordingly, the scope of the present invention is defined by the appended claims.
A switching circuit that employs equity voltage division among a series of transistors to reduce the likelihood that the withstanding voltages of individual transistors will be exceeded. A switching circuit according to the present teachings include a series of transistors and circuitry for biasing the transistors such that a voltage input to the switching circuit divides substantially equally among the transistors when the transistors are in an off state.