BACKGROUND OF INVENTION 
     1. Field of Invention 
     The present invention relates to a pulse width modulation neuron circuit. More particularly, the present invention relates to pulse width modulation neuron circuit, in which its output pulse width realizes a sigmoid activation function of its voltage input, and power-down of some circuits of the neuron circuit in pulse interval will reduce the power assumption significantly. 
     2. Description of Related Art 
     As the most important block in the artificial neural network (ANNs), the behavior of the neuron has vast influence on the performance of the whole network. The sigmoid function is adopted as the activation function of artificial neuron popularly. Pulse stream approach is often used to realize the neuron with this function, which has a digital stream output as an analog information axis. There have been several kinds of pulse stream neuron circuits. Other existed circuits have various kinds of limitations, such as sensitivity to noise due to narrow dynamic range, and bulky size due to the complicated voltage integrator circuit and the operational amplifier in them. Furthermore, all these neuron circuits are not power-optimized. 
     SUMMARY OF INVENTION 
     The invention provides a novel compact pulse width modulation (PWM) neuron circuit, in which its output pulse width realizes a sigmoid activation function of its voltage input. 
     The invention provides a novel compact pulse width modulation (PWM) neuron circuit, in which the power-down of some circuits in pulse interval will reduce the power assumption greatly. 
     As embodied and broadly described herein, the invention provides a pulse width modulation (PWM) neuron circuit including an input control circuit, a charge/discharge circuit and an output control circuit. The input control circuit is coupled to an input voltage source and an operation voltage source. The charge/discharge circuit is coupled to the current mirror circuit. The output control circuit is being coupled to the charge/discharge circuit and the input control circuit. The input control circuit is activated and controlled by the output control circuit and a first current is generated from the input control circuit in accordance with the input voltage source and the operation voltage source. The charge/discharge circuit is charged to a predetermined voltage level in accordance with the first current from the input control circuit. The predetermined voltage level is sufficient enough to make an output of the output control circuit being changed with logic status of the output. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, further includes a current mirror circuit. The current mirror circuit is interposed between the input control circuit and the charge/discharge circuit. The first current of the input control circuit is mirrored by a second current generated by the charge/discharge circuit. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, the charge/discharge circuit comprises a capacitor and a first transistor. The capacitor is charged by the second current and discharged when the first transistor being turned on. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, the first transistor is controlled by the output of the output control circuit. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, the input control circuit comprises a second transistor. A gate of the second transistor is coupled to and controlled by the output of the output control circuit. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, the input control circuit further comprises a third transistor (M 1 ), one of a pair of source/drain regions of the third transistor being coupled to one of a pair of source/drain regions of the second transistor; a forth transistor (M 2 ), one of a pair of source/drain regions of the forth transistor being coupled to the other of the source/drain regions of the third transistor and the first current; a fifth transistor (M 3 ), one of a pair of source/drain regions of the fifth transistor being coupled to the other of the source/drain regions of the forth transistor and being coupled to a gate of the fifth transistor and a gate of the third transistor, the other source/drain region of the fifth transistor being coupled to the operation voltage source; and a sixth transistor, one of a pair of source/drain regions of the sixth transistor being coupled to a gate of the forth transistor and the other source/drain region of the fifth transistor being coupled to the input voltage source, a gate of the fifth transistor being coupled to the operation voltage source. 
     In the above-mentioned pulse width modulation (PWM) neuron circuit, the output control circuit comprises a 3-port NOR gate. The 3-port NOR gate controls the output of the output control circuit. One port of the 3-port NOR gate is coupled to a operation clock signal. One port of the 3-port NOR gate is coupled to the capacitor. When the operation clock signal is on a logic high status, the output of the output control circuit is changed its logic status when the capacitor is charged to or over the predetermined voltage level. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIG. 1 is a schematic diagram of a preferred embodiment of a neuron circuit of the invention; 
     FIG. 2 is a schematic diagram showing an input voltage to a output pulse width and a relative error, in which a simulated neuron activation function compared with a fitted sigmoid and the relative error between the neuron activation function and the fitted sigmoid is introduced; and 
     FIG. 3 is a schematic diagram showing an input voltage to an average power consumption, in which the average power consumption of the circuit of the preferred embodiment of the invention is compared with a conventional architecture. 
    
    
     DETAILED DESCRIPTION 
     The invention provides a novel compact pulse width modulation (PWM) neuron circuit, in which its output pulse width realizes a sigmoid activation function of its voltage input. The dynamic range of the activation voltage can be (V Tn , V DD −T Tn ), here V Tn  is the threshold voltage of the NMOS transistor. Moreover, the transfer function is symmetrical about the supply voltage and the ground. By using special techniques, the invention has very low power dissipation. All these merits ensure its suitability for large-scale integration. 
     Refer to FIG. 1, showing a schematic diagram of a preferred embodiment of a neuron circuit of the invention. The neuron circuit includes an input control circuit  110 , a current mirror circuit  120 , a charge/discharge circuit  130  and an output control circuit  140 . The input control circuit  110  is coupled to an input source (“V in ”) and an operation voltage V DD . The current mirror circuit  120  is coupled to the input control circuit  110  and the charge/discharge circuit  130 . The currents I r  and are applied to the current mirror circuit  120  respectively through the input control circuit  110  and the charge/discharge circuit  130 . The current I exp  is mirrored to the current I r  by the current mirror circuit  120 . The output control circuit  140  is coupled to the charge/discharge circuit  130  and the input control circuit  110 . The input control circuit  110  is activated and controlled by the output control circuit  140  and the output current I r  is generated therefrom. The current I r  is generated in accordance with the input source V in  and the operation voltage V DD  under the control of the output control circuit  140 . If the input control circuit  110  is not activated by the output control circuit  140 , the output current I r  of the input control circuit  110  will not be generated. That is, the input control circuit  110  and the current mirror circuit  120  are deactivated with no power, by which the circuit of the preferred embodiment provides a significant low power consumption circuit. 
     Refer to FIG. 1, the falling edge of the CLK fires the pulse at V out , and this pulse turns transistor M 0  on. Then current I r  is gotten through the circuit in the input control circuit  110  corresponding to a special V in  as well as current I exp  through the current mirror circuit  120 , for example, an Wilson current mirror circuit, shown in FIG. 1. I exp  charges the capacitor C sum  till its voltage reaches the threshold voltage V thres  of the 3-input NOR gate, then V out  charges to zero, and the pulse is finished, the turn-on of transistor M 5  discharges C sum  to ground at the same time. The time to drive the voltage on C sum  from zero to V thres  is equal to the pulse width. 
     Assuming V in  keeps constant in the pulse duration period, pulse width T can be calculated by equation (1):              T   =         C   sum     ·     V   thres         I     e                 xp                 (   1   )                                
     When M 0  is turned on, there well be 5 states for I r  as V in  grows from ground to V DD . It is assumed that the substrate bias modulation effect is ignored. 
     (1) When V in &lt;V Tn , transistors M 2 , M 3  and M 4  shown in FIG. 1 are shut down. By properly selecting k 0 , k 1  and k r , which are the transconductance parameters of M 0 , M 1  and the 2 PMOS transistors that carry I r  in the current mirror circuit  120  respectively, V A  can be pulled nearly to ground. Thus I r  can be expressed as                I   r     ≈         k   r          (       -       V   DD     2       -     V   Tp       )       2             (   2   )                                
     Corresponding to this state, the transfer function keeps at low saturation level. 
     (2) When V in &gt;V Tn , the transistor M 1  is unsaturated while the transistor M 2  is saturated. Assuming the transistor M 3  and M 4  are identical, the current I d3  that flows out the drain of the transistor M 3 , the drain current I d2  and I d1  of M 2  and M 1  respectively, and Ir satisfies following equations:                I     d                 3       =         k   3          (           V   B     -     V   DD       2     -     V   Tp       )       2             (   3   )                 I     d                 2       =         k   2          (       V     i                 n       -     V   A     -     V   Tp       )       2             (   4   )                 I     d                 1       =         k   1          [       2        (       V   B     -     V   Tn       )       -     V   A       ]       ·     V   A               (   5   )                 I   r     =         k   r          (           V   A     -     V   DD       2     -     V   Tp       )       2             (   6   )                   I   d2     =     I     d                 3         ,       I   r     =       I     d                 1       -     I   d2                 (   7   )                                
     By solving above equations, it can be found that I r  decreases slowly with the increase of V in . 
     (3) Both transistors M 1  and M 2  are saturated. Since I r  is relatively small compared with I d3  and I d1 , so equation (8) is tenable:                    k   1          (       V   B     -     V   Tn       )       2     =         I     d                 1       ≈     I     d                 3         =         k   3          (           V   B     -     V   DD       2     -     V   Tp       )       2               (   8   )                                
     Thus V B  and V A  can be depicted as                V   B     =         V   DD     +     2        V   TP       +     2            k   1     /     k   3              V   Tn           1   +     2            k   1     /     k   3                       (   9   )                 V   A     =       V     i                 n       -         k   3       k   2                       V   B     -     V   DD       2     -     V   Tp              -     V   Tn               (   10   )                                
     I r  decrease squarely with V A  as equation (6) indicates. 
     (4) Transistor M 2  becomes unsaturated while transistor M 1  keeps saturated. I d3  is almost fixed because of the clamp of V B , and V A  approaches a constant value near V B , as 
     
       
           I   d2   =k   2 [( V   in   −V   A   −V   Tn ) 2 −( V   in   −V   B   −V   Tn ) 2   ]=I   d3    
       
     
     indicates. I r  declines slowly with V in . 
     (5) The gate voltage of transistor M 2  is clamped to V DD -V Tn  and no longer follows the change of V in  after V in &gt;VDD-VTn due to the turn-off of the input NMOS switch. Thus, I r  also keeps constant in the state, and the transfer function keeps at high saturation level. 
     I r  is mirrored to I exp  through the current mirror circuit  120 , and a sigmoid function is realized between the activation voltage V in  and the pulse width T. 
     It can be noticed that the output information is contained in the pulse width only and not in the pulse interval. When V out  is low, the input control circuit  110  and the current mirror circuit  120  are useless. The power-down of these circuits in pulse interval will reduce the power assumption greatly. Transistor M 0  is used in the embodiment to realize the target with V out  as its gate voltage. When V out  is zero, M 0  is shut off, the input control circuit  110  and the current mirror circuit  120  are deactivated with no power consumption. Thus, the analog block is active periodically synchronized with the output pulse stream, and the turn-off of the analog block lessens the power dissipation in the pulse interval. 
     The embodiment of the invention is simulated using TSMC™ 0.35 um, 3.3V standard CMOS process with HSPICE. The neuron activation function and its fitted sigmoid curve are shown in FIG.  2 . The activation function is at low saturation level before about 0.6V, which is V Tn , and at high saturation level after about 2.7 V, which is V DD -V Tn . So the dynamic range is very wide compared to other circuits. Moreover, this activation function is symmetrical about the ground and the power supply. Refer to FIG. 2, showing the relative error is not more than 1.6%, so it realizes a very precise function. 
     Experiment also has been done to verify the effectiveness of the power efficient architecture, the average power consumption as the functions of activation voltage are plotted in FIG.  3 . The average power of the circuit of the preferred embodiment of the invention with no power efficient architecture is measured with the gate voltage of M 1  connected to power supply, as in the conventional design. The maximum, minimum and the mean value under random activation voltage of the average power dissipation are 43.0 uW, 10.5 uW and 27.0 uW respectively after the adoption of the power efficient architecture. Compared with those values of 69.3 uW, 41.7 uW and 59.9 uW respectively before this architecture is adopted, the reduction are 38%, 75% and 55% respectively. So it can be concluded that this circuit reduces its power dissipation dramatically. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
A pulse width modulation (PWM) neuron circuit. The neuron circuit includes an input control circuit, a charge/discharge circuit and an output control circuit. The input control circuit is coupled to an input voltage source and an operation voltage source. The charge/discharge circuit is coupled to the current mirror circuit. The output control circuit is being coupled to the charge/discharge circuit and the input control circuit. The input control circuit is activated and controlled by the output control circuit and a first current is generated from the input control circuit in accordance with the input voltage source and the operation voltage source. The charge/discharge circuit is charged to a predetermined voltage level in accordance with the first current from the input control circuit. The predetermined voltage level is sufficient enough to make an output of the output control circuit being changed with logic status of the output.