BACKGROUND OF THE INVENTION 
     Field of the Invention 
     A threshold logic circuit substantially includes elements for summation of weighted input variables and ensuing threshold value formation. So-called neural MOS transistors, which have a floating gate similar to that in EPROMs, can be used, among others, for such logic circuits. 
     The structure of neural MOS transistors and their use in threshold logic circuits are known from IEEE Transactions on Electron Devices, Vol. 39, No. 6, June 1992, pp. 1444-1455. 
     In a threshold logic circuit which is known from International Pat. application WO 96/42049, at least one first and one second circuit part, each with its own evaluator circuit, and elements for summation of convoluted input variables, are present. 
     However, such threshold logic circuits have a relatively large chip area. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide a threshold logic circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and has the smallest possible chip area. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a threshold logic circuit, comprising a first circuit portion having an evaluator circuit and a neural MOS transistor with a gate electrode supplying a partial sum signal; and at least one second circuit portion having an evaluator circuit and at least one further neural MOS transistor to be triggered the partial sum signal. 
     In accordance with another feature of the invention, there is provided a common polysilicon region, at least two of the neural MOS transistors in at least two of the circuit portions having channels simultaneously triggered by the partial sum signal through the common polysilicon region. 
     In accordance with a concomitant feature of the invention, the gate electrode of the neural MOS transistor in the first circuit portion is electrically insulated from input signals for multiplication bits, a carry input bit and a sum input bit; and the partial sum signal triggers the at least one further neural MOS transistor to form a multiplication sum bit in the second circuit portion, for forming a multiplication carry bit at the gate electrode of the neural MOS transistor in the first circuit portion. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a threshold logic circuit with a low space requirement, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a threshold logic circuit according to the invention, using a multiplier as an example; and 
     FIG. 2 is a fragmentary, diagrammatic, sectional view of a portion of the threshold logic circuit of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Many logic operations, such as binary multiplication or binary addition, can be described in the form of a system of threshold equations as follows: ##EQU1## In this case x i  where i=1 . . . m are the input variables, W ki  where i=1 . . . m and k=1 . . . n are the weighting factors, and T i  where i=1 . . . n are the threshold values of the equation system or inequality system. In actual circuitry embodiments, the x i  values are often binary values that can assume only the values of 0 and 1. If at least two vectors (W i1 , W i2 , . . . , W im ) and (W j1 , W j2 , . . . , W jm ) of the weighting factors of one line, where i≠j, i≦n and j≦n are similar in such a way that many elements agree, that is that W ik  =W jk  is true for as many subscripts k as possible, where 1≦k≦m, then the condition sides of lines i and j of the equation system (1) can be converted in such a way that identical partial sums are located on the one side, referred to below as the left-hand side, of the &#34;≧&#34; symbol, while the terms that do not agree in the two lines are located on the other side, referred to below as the right-hand side. Written in a formal way, the following results are obtained for lines i and j: ##EQU2## As long as it is also true that T i  =T j , then T i  and T j  are also placed on the side with identical partial sums. 
     In order to provide a conversion by circuitry, it then follows from system (2) that the common partial sum term, in this case the left-hand side of the inequalities, is now realized only once. Then this partial sum signal, which is realized once in a partial circuit, is also delivered to other parts of the threshold logic circuit for processing. 
     As already noted above, the minimum condition is that at least two functions f i  and f j  of the equation system (1) have identical partial sum terms in the condition portion. If one equation system has a plurality of functions with identical partial sums, then these sums can be combined into corresponding groups, where in the minimum case the respective identical term is generated only a single time for each function group. 
     Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is seen, by way of example, a multiplier cell according to the invention which is shown as a threshold logic circuit, having the following equations: ##EQU3## in which a i  and b i  are bits to be multiplied, C i  and S i  are a carry bit and a sum bit of an immediately preceding stage, and C i+1  and S i+1  are a carry bit and sum bit for an immediately subsequent stage, and the multiplier cell has one cell portion CZ for forming the carry bit C i+1  and one cell portion SZ for forming the sum bit S i+1 . 
     The cell portion or first circuit portion CZ includes an evaluator circuit, which has two input branches for the weighted summation of input and reference signals. The evaluator circuit has p-channel MOS transistors M1 and M2 and n-channel MOS transistors M3, M4 and M7. The transistors M1 and M3 form an inverter, and the transistors M2 and M4 form an inverter. The inverters are fed back crosswise and thus form a hold element with one another, which can be reset with the aid of a reset signal Φ reset1  through the use of the transistor M7 that connects the inputs of these inverters. The inverter having the transistors M1 and M3 forms the carry signal C i+1  and is connected through a left-hand branch in the form of an n-channel MOS transistor MS to a reference potential VSS. A reference voltage Vref for adjusting the threshold in accordance with equation (3) is present at the gate of the transistor M5. The inverter having the transistors M2 and M4 is connected through a right-hand path in the form of a neural MOS transistor M6 to the reference potential VSS. A floating gate G of the transistor M6 carries a partial sum signal TS=a 1  +a 2  +2*S i  +2*C i , and input gates isolated from it are connected to the inputs for the bits a i , b i , C i  and S i . 
     The cell portion or second circuit portion SZ for forming the sum bit S i+1 , like the cell portion CZ for forming the carry bit C i+1 , also contains an evaluator with two input branches. The evaluator circuit has transistors M1&#39;, M2&#39;, M3&#39;, M4&#39; and M7&#39;, and it forms the signal S i+1  instead of the signal C i+1 . A left-hand branch in the cell portion SZ has a neural MOS transistor M5&#39; for forming a value 4*C i+1  +2. This term is obtained by a conversion of equation (4). A right-hand branch of the cell portion SZ is supplied with the partial sum signal TS=a 1  +a 2  +2*S i  +2*C i  by a floating gate G of the n-channel MOS transistor M6&#39;. 
     This is advantageously accomplished by providing that the channel regions of the corresponding neural MOS transistors M6 and M6&#39; are located relatively close together and are covered by a common electrically conductive region for the floating gate G, is as shown as an example in FIG. 2. The common electrically conductive region is insulated by a thin insulator film OX1. Input gates 1 . . . 4 of the transistor M6 are separated from the floating gate G by a thin insulator film OX2 and thus form input capacitors which are connected to one another on one side and are provided for generating the partial sum signal TS at the floating gate G. The insulator layers OX1, OX2 in this case are formed of SiO 2  for instance, and the electrically conductive region is, for instance, formed of polysilicon. 
     The same is correspondingly true for each threshold logic circuit having a first circuit portion CZ and at least one second circuit portion SZ, with threshold equations that can be converted in such a way that they have identical partial sum signals TS. A partial sum signal TS formed in the first circuit portion CZ is delivered to the second circuit portion SZ, so that in the at least one second circuit portion, the partial sum signal no longer needs to be formed with the aid of a relatively large-area neural MOS transistor that has many input gates.
A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.