BACKGROUND STATEMENTS 
     The inventive aspects disclosed herein were made with Government support under contract DABT-63-94-C-0055. The Government has certain rights in these inventive aspects. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor memory circuits and their manufacture and, more particularly, to memory structures and fabrication providing benefits relating to reductions in terms of both circuit-implementation area and processing. 
     BACKGROUND OF THE INVENTION 
     The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of a silicon wafer. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. Main objectives in manufacturing many such devices include obtaining a device that occupies as small an area as possible and consuming low levels of power using low supply levels, while performing at speeds comparable to speeds realized by much larger devices. 
     Marketplace needs have created a demand for increased fast data-storage capability in an ever-decreasing package size. For many applications, this has translated to efforts to increase the number of memory cells in a given chip size (or real estate area) but using fewer elements to implement each of the cells. The tension between attempting to increase the number of memory cells while using a smaller package, has resulted in a variety of efforts and approaches to memory cell design. 
     One type of fast data-storage device that has been consistently used to address such demands is high density DRAM, which is approaching an era of giga-bit scale. Technology has been developed leading to the advent of 4 Gbit DRAM which requires the minimum cell area of 0.1 μm 2 . This degree of scaling has been enabled by advances in photolithography and memory cell technology such as complicated capacitor structures and dielectric materials. However, as the cell area decreases, process margins such as alignment tolerance have become limiting factors for developing next generation DRAM cells. In addition, the leakage current through transistors and isolations between adjacent cells increases significantly degrading refresh characteristics of devices. These problems expand with decreases in the cell area without changing basic cell layouts such as the conventional 1 M DRAM structure dating back to the late 1980&#39;s. 
     FIG. 1A illustrates such a conventional layout. The layout of FIG. 1A consists of 8 F 2  size boundary, where F is the minimum feature size. A structure including conventional MOSFET and a stack or trench capacitor, is placed laterally in this layout. 
     There have been efforts to decrease the number of features, and several reports have proposed fabricating DRAM cells with significantly different layouts. One such approach proposes building DRAM cells with a 4 F 2  layout. This type of structure is shown in FIG.  1 B. The key benefit of this technology lies in the basic layout. Given a minimum feature size (F), the cell area is 4 F 2  rather than 8 F 2  for the conventional structure. Accordingly, the cell area can be reduced by one half using this type of layout. 
     Further, within this cell area of size-reduced layouts, large process margins can be achieved using a vertically-arranged pass transistor. Since the pass transistor is formed vertically, the channel length does not change as the cell size decreases. This long channel permits the transistor device to have low-level subthreshold currents and small drain-induced-barrier-lowering (DIBL) effects. Also, because the pass transistors in each pair of adjacent cells are not formed along an electrically intercoupled path, isolation between the pass transistors is inherent. 
     While the architectures of such structures show promise, the processing steps used to implement the architectures have been overly-complex. These processing proposals typically involve the introduction of complex processing steps into a less-burdensome conventional process, for the purpose of manufacturing a DRAM memory cell including a pillar-type pass transistor over a capacitor. Examples of these architectures and their proposed processing approaches are characterized in: U.S. Pat. Nos. 5,252,845 (“Trench DRAM Cell With Vertical Transistor”) 5,316,962 (“Method Of Producing A Semiconductor Device Having Trench Capacitors and Vertical Switching Transistors”), and 5,102,817 (“Vertical DRAM Cell And Method”); and various papers including S. Maedada et al., VLSI Tech. Symp., p.133 (1994), and K. Sinouchi et al., IEDM Techical Digest, p.23 (1989). Some of the process problems presented by these approaches include: the epi process from the contact hole being barely controllable; the gate oxide grown from the gate (rather than the channel) causing a potential reliability problem; alignment tolerances between contact holes; and word lines that are patterned before the contact process. Even though each of the above approaches uses vertical pillar structure that permits construction of the word line via the self-alignment, these approaches have the tendency of decreasing process margins more than conventional processes. 
     Accordingly, there is a need for a semiconductor manufacturing process for constructing a memory cell that reduces the complexity typically associated with vertically-arranged transistors in DRAM cells, maintains process margins of conventional processes, and overcomes problems associated with the above- mentioned prior art. 
     SUMMARY OF THE INVENTION 
     One important aspect of the present invention is directed to a process of manufacturing a DRAM cell structure using a poly-silicon pillar transistor for 4-Gbit applications and beyond. One such DRAM cell structure, manufactured in accordance with the present invention, is implemented using a layout contained in a 4 F 2  area. 
     A specific example embodiment of a process in accordance with the present invention involves the formation of a DRAM cell arrangement including a pillar transistor and a capacitive structure over or under the pillar transistor (depending upon the implementation). This particular process includes forming a non-conductive layer, such as SiN layer, over a semiconductor material, which forms the pillar transistor structure such that it includes the semiconductor material and the overlying non-conductive layer. To save process steps, the pillar photolithography and anisotropic etching processes can be performed directly over the capacitive structure in a self-aligned manner. Next, a conductive layer is formed around the pillar structure to form a pillar transistor that includes the conductive layer and the pillar structure. A dielectric material is formed over the pillar transistor and is then removed, via CMP, until the non-conductive layer is exposed to open the contacts. The non-conductive layer is then removed and a conductive layer on the pillar structure is formed. 
     In one application in which the capacitive structure is beneath the pillar transistor, the conductive layer formed on the pillar structure is used as the bit line, the conductive layer formed around the pillar structure is used as the word line, and multiple implants are used to provide uniform channel doping in the semiconductor material of the pillar structure. 
     Using various aspects of the present invention, significant improvements in high-performance electrical characteristics and fewer defects in the pillar transistor have been realized. Other aspects and embodiments of the present invention will be apparent upon review of the discussion in connection with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may be more completely understood in consideration of the detailed description of various embodiments of the invention which follows in connection with the accompanying drawings, in which: 
     FIG. 1A shows a conventional DRAM cell layout; 
     FIG. 1B shows a pillar DRAM cell with a cell layout consistent with an embodiment of the present invention; 
     FIGS. 2A-2D show an example process sequence of a pillar DRAM cell consistent with an embodiment of the present invention; and 
     FIG. 3 shows the optional stack capacitor DRAM cell manufactured consistent with an alternate embodiment of the present invention. 
    
    
     While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
     DETAILED DESCRIPTION 
     The present invention is believed to be applicable to a variety of systems and arrangements that benefit from large-scale data storage. The invention has been found to be particularly advantageous in DRAM circuit applications where there is a need to store large amounts of data in a compact area Examples of such applications include, but are not necessarily limited to, stand-alone and embedded DRAM circuits. An appreciation of various aspects of the invention is best gained through a discussion of application examples operating in such an environment. 
     A specific example embodiment of a process in accordance with the present invention involves the formation of a DRAM cell arrangement. For each cell in an array accessed by word lines and bit lines, the process includes forming a capacitor and a poly-Si pillar transistor so that it connects directly above the capacitor. The capacitor is used as a storage cell with one electrode connected to the pillar transistor&#39;s source/drain region for maintaining a charge. The pillar transistor has its gate formed as a conductive layer around an erected channel that is also part of the pillar structure. The pillar transistor&#39;s gate is implemented as part of the cell&#39;s word line. The drain/source region of the pillar transistor, which is part of the cell&#39;s bit line, is formed as a self-aligned conductive layer over the top of the pillar structure. To minimize the number of processing steps, this particular example embodiment can be completed using only three photolithography steps, respectively for the trench, the pillar and the bit line. 
     An example process according to the present invention that can be used to manufacture a DRAM cell arrangement, such as the one characterized above, includes several operations. These operations include: forming a capacitive structure over a semiconductor material and a semiconductor material over the capacitive structure, and forming a non-conductive layer, such as SiN layer, over the semiconductor material. The non-conductive layer is part of a pillar structure formation in which the semiconductor material and the overlying non-conductive layer are stacked. Next, a conductive layer is formed around the pillar structure to form a pillar transistor that includes the conductive layer and the pillar structure. A dielectric material is formed over the pillar transistor and is then removed, via chemical-mechanical polishing (CMP), until the non-conductive layer is exposed to open the contacts. The non-conductive layer is then removed, and a conductive layer on the pillar structure is formed. 
     FIG. 1B illustrates an example layout of the pillar DRAM cell, manufactured as described above in connection with this example embodiment of the present invention. Since the word line is formed by a spacer etch process in this example, there is no word line illustrated in the layout of FIG.  1 B. 
     An example process flow for fabricating a pillar DRAM cell, such as one having the layout of FIG. 1B, can be appreciated with reference to the various stages of the fabrication of the structure in FIGS. 2A-2D. FIG. 2A depicts conventional formation of trench capacitors  210  and  212 . Each of the trench capacitors  210  and  212  includes an doped poly-Silicion plug  214  or  216  that, in one example embodiment, acts as the storage node for holding the charge of the memory cell. The illustrated embodiment involves the formation of an n-type pass transistor; thus the plug  214  or  216  (connecting to the source of the transistor) is doped n+. In alternative embodiments, the above trench capacitor is replaced with stacked and planar capacitors used to provide a storage node with adequate capacity (typically high-capacity (Hi-C)) for the memory cells. Transistor configurations other than the type and structure of the above pass transistor can also be used. 
     In the illustrated embodiment, each of the trench capacitors  210  and  212  further includes an outer capacitor dielectric layer  218  and an outer electrode layer (not shown). An insulative layer  220 , e.g., an oxide layer formed using a chemical-vapor deposition (CVD) process, is then formed. The skilled artisan will appreciate that the insulative layer  220  can be formed before or after formation of the trench capacitors  210  and  212 . 
     As depicted in FIG. 2B, after filling the trenches with the n+ doped poly-silicon, a layer of silicon is formed over the top of the trench capacitors  210  and  212 . In one embodiment, about 1 μm of amorphous silicon (“α-Si”) is deposited to form α-Si layer  222 . Although use of amorphous silicon is not required, it is advantageous because it avoids formation of a channeling tail as is known in the art. Multiple energy boron implants into the α-Si layer are used to obtain uniform channel dopings. Silicon nitride (e.g., Si 3 N 4 ) is then deposited over the α-Si layer to form the silicon-nitride layer  224 . The pillar photolithography and etching processes are performed directly above the trench plugs. Crystallization annealing is then performed, e.g., at 800° C. for 24 hours. 
     As shown in FIG. 2C, gate oxidation is performed followed by gate poly deposition. A gate poly layer is deposited to create to a structure from which a self-aligned word line  228  can be formed. In one example embodiment, the self-aligned word line  228  is created by anisotropic spacer etching of the gate poly, and the space between the pillars (including the layers  222  and  224 ) along the word line direction is greater than the bit line direction so that the gate  228  can surround the channel  222  and be connected only in the word line direction. N-type dopants are implanted over the gate poly spacer for control of the offset (LDD) structure in the transistor devices. 
     Next, a self-aligned contact is formed on top of each of the pillars. After deposition of a doped oxide  230 , such as BPSG (borophosphosilicate glass), the structure is chemically-mechanically polished (CMP). This CMP process is advantageous in terms of both providing planarization and opening a self-aligned contact. During the CMP operation, the previously-deposited silicon-nitride layer  224  on top of the pillar is used as an etch stop layer for the CMP process. Opening of the contacts is completed by wet etching of the silicon-nitride layer  224 . With the contacts to the transistor opened, conventional photolithography processes are used to form the bit line  232 . 
     In another more specific example embodiment, an n-type &lt;100&gt; substrate is annealed at 900° C. for 1 hour in a POCL 3  (phosphorus oxychloride) environment. Amorphous silicon is deposited by PECVD with SiH 4  and Ar as a carrier gas at 580° C. for 6 hours resulting in a thickness of 1 μm. Triple boron implantations (e.g., 90 keV/180 keV/320 keV) are then performed to form a uniform doping profile in the channel. Pillar photolithography is conducted using an E-beam direct writing machine with the pillar diameter ranging from 0.15 μm to 5 μm. A RIE etch machine (such as a LAM) is used to etch the pillars all the way down to the substrate. Crystallization annealing is then performed at 600° C. for 24 hours in an N 2  furnace followed by sacrificial oxidation at 800° C. for 15 minutes in wet O 2 . After the wet etching of the oxide, gate oxidation is conducted at 600° C. in wet O 2  for time ranging from 10 to 15 minutes; thereby forming a thickness of oxide from 12 nm to 18 nm respectively. The pillar width and gate oxide thickness at the side wall of the pillar can be measured by a cross-sectional TEM. After deposition of an in situ n+ doped poly layer over pillars, the gate pattern is produced by a spacer etching technique using the same recipe of pillar etching. As+ implantation is then conducted to form the source/drain regions with the dose of 1E15 and energy of 35 keV. Activation annealing is performed at 900° C. for 2 minutes by rapid thermal annealing (RTA). After the metallization process, an ECR plasma etcher is used to perform hydrogenation. The gas flow for hydrogenation is 1 sccm at 450° C. for 30 minutes. Device parameters can be measured using a HP4155DC parameter analyzer. Using an automatic DC measurement machine, such as a HP4062, the uniformity of device characteristics can be checked. 
     While the above structure has been characterized for a DRAM cell having a poly-silicon pillar transistor in connection with the trench capacitor, as mentioned above, the cell construction is not limited to trench capacitors. FIG. 3 illustrates the fabrication of a stacked DRAM cell with the poly-Si pillar transistor structure of FIGS. 2A-2D and with a stacked capacitor. Similar reference numeral assignments are used to show the correlation between the various items depicted in the example structure of FIGS. 2A-2D and in the example structure of FIG.  3 . 
     In FIG. 3, bit-line  332  is formed by poly-Si or tungsten (W) by the Damascene process which simultaneously forms a planar surface. Fabrication procedures of the cell transistor and self-aligned contact, capacitor to transistor, are the same as the process described above in connection with FIGS. 2A-2D. The stacked capacitor in FIG. 3 is shown to include a storage n+ poly  318  covered by a capacitor dielectric  318 , in turn, covered by a plate poly  313 . 
     Various kinds of stack cells can be integrated with this structure. FIG. 3 shows the stack capacitor with high-k dielectric material as an optional structure. Since the contact between the capacitor and transistor is formed using a self-aligned process, process margin improves significantly. 
     For background information and details regarding alternative devices for implementing various parts of the above-illustrated cells and regarding conventional processes used to implement operations associated with the above-discussed implementations of the present invention, reference may be made to the documents identified herein in the background section and to “Silicon Processing for the VLSI Era, Vol. 2: Process Integration,” Stanley Wolf, Lattice Press, Sunset Beach, Calif., 1990. 
     Accordingly, various example implementations of the present invention are advantageous in that they do not overly-burden the semiconductor manufacturing process for construction of pillar-based transistors in memory cells, and they yield high process flexibility and cost reduction for the fabrication of high-density DRAM cell arrays. Further, these implementations maintain conventional process margins and overcome problems associated with the above-mentioned prior art. These example implementations described above, and their associated advantages, are provided by way of illustration only and are not intended to limit the invention. Those skilled in the art will readily recognize that various modifications and changes can be made to the present invention, including but not limited to the alternative embodiments and associated advantages mentioned above. Rather than limiting the scope of the present invention, the example implementations are used for illustrative purposes in support of the following claims which set forth the scope of the present invention.
A fabrication process benefits high-density DRAM cells, including four-Gbit cells and beyond. In one embodiment, a poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. To reduce the process steps, word line formation is achieved by a spacer etch process and a self-aligned process is used for formation of bit line contact using a CMP process. This embodiment reduces necessary layout area and provides improvements in overall device performance.