RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2016-006486 filed on Jan. 15, 2016, the entire content of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a voltage regulator configured to operate with low current consumption, and having good responsiveness. 
         [0004]    The present application claims priority based on Japanese Patent Application No. 2016-006486 filed in Japan on Jan. 15, 2016, the disclosures of which are incorporated herein by reference in their entirety. 
         [0005]    2. Description of the Related Art 
         [0006]    Voltage regulators are provided in electronic devices such as cellular phones, which are configured to operate with rechargeable batteries, such that the electronic devices stably operate even when a charged state of the batteries fluctuates. Further, the voltage regulator, which is configured to prevent an output voltage from fluctuating such that the electronic device stably operates even when a load sharply fluctuates, is provided with a control circuit for achieving a more stable output voltage of the voltage regulator in some cases. 
         [0007]      FIG. 3  is a circuit diagram of a related-art voltage regulator  30 . A reference voltage circuit  31  is configured to output a reference voltage Vref. From a resistor  32  and a resistor  33 , a feedback voltage VFB obtained by dividing an output voltage Vout at an output terminal by the resistors is output. A voltage amplifier circuit  34  is configured to control a PMOS transistor  35  based on a result of comparison between the reference voltage Vref and the feedback voltage VFB such that the output voltage Vout is constant. A transient response improvement circuit  36  is configured to receive the reference voltage Vref and a power supply voltage as input to control an operating current of the voltage amplifier circuit  34 . 
         [0008]    The transient response improvement circuit  36  includes a detection portion configured to detect fluctuation in power supply voltage, and an output portion, and is configured to detect fluctuation in power supply voltage and to control an operating current that is to flow through the voltage amplifier circuit  34 . With increase in current of the voltage amplifier circuit  34  depending on the detected power supply voltage level, the transient response characteristics of the voltage amplifier circuit  34  are improved. 
         [0009]      FIG. 4  is a circuit diagram of the transient response improvement circuit and the voltage amplifier circuit according to the related art. The transient response improvement circuit  36  includes a constant current portion including PMOS transistors  1  and  2 , a detection portion including NMOS transistors  3  and  4  and a capacitor  6  and being configured to detect fluctuation in power supply voltage, and an output portion including an NMOS transistor  5 . 
         [0010]    The transient response improvement circuit  36  is configured to detect fluctuation in power supply voltage to control a current that is to flow through the voltage amplifier circuit  34 . The operating current of the voltage amplifier circuit  34  is increased depending on a decreasing level of the detected power supply voltage, that is, the transient response of the voltage amplifier circuit  34  is improved (for example, see Japanese Patent Application Laid-open No. 2006-18774). 
         [0011]    However, in the transient response improvement circuit described above, after fluctuation in power supply voltage is detected and the operating current of the voltage amplifier circuit is increased, timing at which the operating current of the voltage amplifier circuit is returned to a normal value cannot be arbitrarily set. Thus, there is a drawback that the operating current of the voltage amplifier circuit is returned to the normal value during transient response, and optimal transient response characteristics cannot be obtained. 
         [0012]    In addition, the transient response improvement circuit described above has a drawback that the operating current of the voltage amplifier circuit is excessively increased and the voltage amplifier circuit does not stably operate, when a voltage decreasing level of a detected power supply voltage is large. 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention has been made in order to solve the problems described above, and achieves a voltage regulator having optimal transient response characteristics. 
         [0014]    In order to solve the related-art problems, a voltage regulator according to one embodiment of the present invention has the following configuration. 
         [0015]    The voltage regulator includes: 
         [0016]    a voltage amplifier circuit configured to compare a feedback voltage depending on an output voltage of an output transistor and a reference voltage to each other to control the output transistor; 
         [0017]    a transient response improvement circuit configured to detect fluctuation in one of a power supply voltage and the output voltage; and 
         [0018]    a delay circuit connected to an output terminal of the transient response improvement circuit, 
         [0019]    in which an operating current of the voltage amplifier circuit is controlled depending on a signal that is output from the transient response improvement circuit. 
         [0020]    According to the voltage regulator of the present invention, the delay circuit is provided between the transient response improvement circuit and the voltage amplifier circuit, and hence there is an effect that the transient response characteristics of the voltage amplifier circuit can be optimized. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a circuit diagram of a voltage regulator according to an embodiment of the present invention. 
           [0022]      FIG. 2  is a circuit diagram for illustrating examples of a transient response improvement circuit, a delay circuit, and a voltage amplifier circuit of the voltage regulator according to this embodiment. 
           [0023]      FIG. 3  is a circuit diagram of a related-art voltage regulator. 
           [0024]      FIG. 4  is a circuit diagram of a transient response improvement circuit and a voltage amplifier circuit according to the related art. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0025]      FIG. 1  is a circuit diagram of a voltage regulator according to an embodiment of the present invention. 
         [0026]    A voltage regulator  10  includes a reference voltage circuit  11 , resistors  12  and  13  serving as feedback resistors, a voltage amplifier circuit  14 , a PMOS transistor  15  serving as an output transistor, a transient response improvement circuit  16 , and a delay circuit  17 . 
         [0027]    The reference voltage circuit  11  is configured to output a reference voltage Vref. From the resistor  12  and the resistor  13 , a feedback voltage VFB obtained by dividing an output voltage Vout at an output terminal by the resistors is output. The voltage amplifier circuit  14  is configured to control the PMOS transistor  15  based on a result of comparison between the reference voltage Vref and the feedback voltage VFB such that the output voltage Vout is constant. The transient response improvement circuit  16  is configured to receive the reference voltage Vref and the output voltage Vout as input to control an operating current of the voltage amplifier circuit  14 . 
         [0028]      FIG. 2  is a circuit diagram for illustrating examples of the transient response improvement circuit, the delay circuit, and the voltage amplifier circuit according to this embodiment. 
         [0029]    The transient response improvement circuit  16  includes a detection portion configured to detect fluctuation in power supply voltage, and a constant current portion configured to supply a constant current to the detection portion. 
         [0030]    The constant current portion includes a current mirror circuit including PMOS transistors  161  and  162 . The PMOS transistors  161  and  162  are configured to cause a predetermined constant current to flow with the reference voltage Vref applied to gate electrodes thereof, to thereby supply the constant current to the detection portion. 
         [0031]    The detection portion includes NMOS transistors  163  and  164  whose gate electrodes are connected to each other, a capacitor  165  connected to the gates of the NMOS transistors  163  and  164 , for monitoring the output voltage Vout at the output terminal, and a first inverter including an NMOS transistor  167  and a constant current source  166 . The detection portion is configured to detect fluctuation in output voltage Vout. A drain of the NMOS transistor  167  corresponds to an output terminal of the transient response improvement circuit  16 . 
         [0032]    The delay circuit  17  includes a second inverter including a PMOS transistor  171  and a constant current source  172 , and a capacitor  173 , and is configured to delay a signal that is output from the transient response improvement circuit  16 . 
         [0033]    The PMOS transistor  171  has a gate connected to the output terminal of the transient response improvement circuit  16 , and a drain connected to the constant current source  172  and the capacitor  173 . The drain of the PMOS transistor  171  corresponds to an output terminal of the delay circuit  17 . 
         [0034]    The voltage amplifier circuit  14  includes a differential amplifier portion including NMOS transistors  143  and  144  that are a differential pair of PMOS transistors  141  and  142  forming a current mirror circuit, and a constant current source  145  configured to supply an operating current to the differential amplifier portion. The voltage amplifier circuit  14  further includes an NMOS transistor  146  and a constant current source  147  for additionally supplying an operating current to the differential amplifier portion. 
         [0035]    The NMOS transistor  146  and the constant current source  147  that are connected in series, and the constant current source  145  are connected in parallel to each other. The NMOS transistor  146  has a gate connected to the output terminal of the delay circuit  17 . 
         [0036]    Now, the operation of the voltage regulator  10  of this embodiment is described. 
         [0037]    When the output voltage Vout at the output terminal does not fluctuate, the NMOS transistors  163  and  164  of the detection portion in the transient response improvement circuit  16  are on, and a constant current supplied from the constant current portion flows. A source of the NMOS transistor  164  is grounded, and hence a drain voltage of the NMOS transistor  164  at this time is lower than a threshold value of the NMOS transistor  167 . Thus, the NMOS transistor  167  is off, and a voltage at the drain of the NMOS transistor  167 , namely, a voltage at the output terminal of the transient response improvement circuit  16  is substantially the power supply voltage, due to the constant current source  166 . 
         [0038]    In the delay circuit  17 , the PMOS transistor  171  is off, and hence the capacitor  173  is discharged by the constant current source  172 . Consequently, the delay circuit  17  outputs a ground voltage. 
         [0039]    Thus, the NMOS transistor  146  is off, and hence the voltage amplifier circuit  14  operates with an operating current supplied from the constant current source  145 . 
         [0040]    When the output voltage Vout at the output terminal fluctuates, in the capacitor  165  of the detection portion in the transient response improvement circuit  16 , charges depending on an amount of fluctuation in output voltage Vout and gate voltages of the NMOS transistors  163  and  164  are accumulated. 
         [0041]    When the output voltage Vout drops, the gate voltages of the NMOS transistors  163  and  164  also drop accordingly to the output voltage Vout. As the gate voltages of the NMOS transistors  163  and  164  decrease, the NMOS transistors  163  and  164  are turned off. As a consequence, a voltage at the drain of the NMOS transistor  164  is increased. Thus, the NMOS transistor  167  is turned on, and the voltage at the drain of the NMOS transistor  167 , namely, the voltage at the output terminal of the transient response improvement circuit  16  becomes substantially the ground voltage. 
         [0042]    In the delay circuit  17 , the PMOS transistor  171  is turned on, and hence the capacitor  173  is charged. Consequently, the delay circuit  17  outputs the power supply voltage. 
         [0043]    Thus, the NMOS transistor  146  is turned on, and hence the voltage amplifier circuit  14  operates with operating currents supplied from the constant current source  145  and the constant current source  147 . That is, the operating current of the voltage amplifier circuit  14  is increased to improve the transient response thereof. 
         [0044]    For example, when the NMOS transistor  164  is a transistor having a threshold voltage of 0.3 V, and the NMOS transistor  163  is a transistor having a threshold voltage of 0.5 V, gate potentials of the NMOS transistors  163  and  164  are 0.5 V or more. In this case, a fluctuation level of the output voltage Vout needs to be substantially 0.2 V in order to turn off the NMOS transistor  164 . This is because there is no need to increase the operating current of the voltage amplifier circuit  14  when the fluctuation level of the output voltage Vout is small. 
         [0045]    The threshold voltages of the NMOS transistors described above are examples, and the threshold voltages and the currents of the PMOS transistors  161  and  162  may be arbitrarily set depending on a detected level of the output voltage Vout. 
         [0046]    In addition, according to this embodiment, delay time may be arbitrarily set through adjustment of the capacitance value of the capacitor  173 , the current value of the constant current source  172 , and the size of the PMOS transistor  171  in the delay circuit  17 . 
         [0047]    Further, the voltage regulator  10  of this embodiment has the configuration in which the operating current of the voltage amplifier circuit  14  is increased by the constant current source  147 . As a consequence, the operating current is not excessively increased and the voltage amplifier circuit  14  can thus stably operate, even when the decreasing level of the output voltage is large, for example. 
         [0048]    As described above, according to the voltage regulator of the present invention, the delay circuit  17  is provided between the transient response improvement circuit  16  and the voltage amplifier circuit  14 , and hence the effect that the transient response characteristics of the voltage amplifier circuit  14  can be optimized is provided. 
         [0049]    Although fluctuation in output voltage Vout is detected in the above description, it is apparent that a similar effect is obtained also when fluctuation in power supply voltage is detected.
Provided is a voltage regulator configured to stably operate with low current consumption, and having good responsiveness. A delay circuit is provided between a transient response improvement circuit and a voltage amplifier circuit.