CLAIM OF PRIORITY  
       [0001]     This application claims priority to U.S. Provisional Application Ser. No. 60/583,268, filed on Jun. 25, 2004, which is incorporated by reference. 
     
    
     BACKGROUND  
       [0002]     A switching power supply provides a high-efficiency regulated output voltage for a variety of power-management functions that are often required in modern electronic systems. These systems have either a battery or an unregulated power supply as their input power sources, and may have multiple power output voltages that require power conversion, power management functions, and tight regulation.  
         [0003]     The function of a switching power supply is to convert power from an input power source to output power for an electronic system. This conversion should be at high efficiency for the various operational modes of the system. For example, when a notebook computer or cellular phone system is operated in a low-power mode, it is desired to extend battery life. On the other hand, a well-regulated voltage supply is desired when the notebook or phone is operated in a high-power mode. Furthermore, the switching power supply is required to respond with little or no regulation error when the notebook or phone changes from a low- to a high-power mode.  
         [0004]     Traditionally, a switching power supply provides a regulated output voltage by controlling a supply current through a power switching stage. The switched current is connected to a filter stage, which reduces the resulting ripple voltage. A feedback stage measures the regulated output voltage and, in response to the measured value of the regulated output voltage, generates a control signal that controls the power switching stage.  
         [0005]     To regulate the output voltage of a pulse-width-modulated (PWM) switching power supply, the control signal activates the power switching stage when the regulated output voltage drops below a threshold voltage (for a positive regulated output voltage) and then deactivates the switching power stage when the regulated output voltage increases above the threshold voltage. The pulse width of the control signal determines the period of time that the power switching stage provides current to the filter stage, and hence, the supply regulates the output voltage by controlling the widths of the control-signal pulses. Therefore, the pulse width of the control signal is proportional to the current being drawn by the load, and the frequency of the control signal is typically constant.  
         [0006]     To regulate the output voltage of a constant-on-time switching power supply, the control signal activates the power switching stage for a predetermined constant time when the regulated output voltage drops below a threshold voltage (for a positive voltage). Therefore, the pulse width of the control signal is constant, and the frequency of the control signal is proportional to the current drawn by the load. Ideally, under steady-state conditions, the supply operates at a constant switching frequency without a synchronizing signal. But in noisy environments, noise may be superimposed on the output voltage or threshold voltage, and this noise may cause jitter in the phase, and thus the frequency, of the control signal. Unfortunately, this jitter may cause the power supply to irradiate electromagnetic interference that can adversely affect the electronic system that incorporates the power supply or nearby electronic systems.  
       SUMMARY  
       [0007]     An embodiment of the invention is a signal regulator that includes a switching circuit, a controller, and a threshold generator. The switching circuit generates an output voltage regulated by the controller, which regulates the output voltage by, activating the switching circuit for a predetermined time when the output voltage has a predetermined relationship to a threshold voltage. The threshold generator generates the threshold voltage in response to the controller.  
         [0008]     Generating the threshold voltage in response to the controller can reduce the affect that noise has on the operation of the switching circuit, and can thus decrease the noise-induced jitter in the regulator&#39;s steady-state switching frequency. For example, the threshold circuit may generate the threshold voltage as the sum of a base voltage and a virtual ripple voltage. The virtual ripple voltage decreases the affect that noise has on jitter by increasing the signal-to-noise ratio. The output equivalent-series-resistance (ESR) voltage ramp combines with the virtual ripple signal to create a total signal that compares to the threshold voltage. Increasing the total signal acts to reduce the magnitude of noise-induced jitter. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     Features and advantages of the invention may best be understood by making reference to the following non-limiting description taken in conjunction with the accompanying drawings, in the several figures of which like referenced numerals identify like elements.  
         [0010]      FIG. 1  is a schematic block diagram of a constant-on-time switching power supply with virtual ripple feedback according to an embodiment of the invention.  
         [0011]      FIGS. 2A-2C  are timing diagrams of some of the signals that the power supply of  FIG. 1  generates according to an embodiment of the invention.  
         [0012]      FIG. 3  is a schematic block diagram of a constant-on-time switching power supply with virtual ripple feedback according to another embodiment of the invention.  
         [0013]      FIGS. 4A-4C  are timing diagrams of some of the signals that the power supply of  FIG. 3  generates according to an embodiment of the invention.  
         [0014]      FIG. 5  is a detailed schematic diagram of the power supply of  FIG. 1  according to an embodiment of the invention.  
         [0015]      FIG. 6  is a schematic block diagram of a computer system that can incorporate the power supplies of  FIGS. 1 and 4  according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof. The detailed description and the drawings illustrate specific exemplary embodiments by which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is understood that other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the invention. The following detailed description is therefore not to be taken in a limiting sense.  
         [0017]      FIG. 1  is a schematic block diagram of a constant-on-time buck-converter power supply  10 , which uses virtual ripple feedback and which provides a regulated voltage Vout to a load  12  according to an embodiment of the invention. The supply  10  includes a filter  14 , a switching circuit  16 , and a regulator  18 . The following discussion assumes that Vout is a positive voltage, although a similar discussion applies where Vout is negative. Furthermore, one can incorporate the supply  10  into virtually any electronic system, such as a laptop computer, that requires power conversion.  
         [0018]     The filter  14  includes an inductor L and a capacitor C, and the switching circuit  16  includes NMOS power transistors  20   a  and  20   b , which have their source and drain, respectively, coupled to the inductor L. The drain of the transistor  20   a  is coupled to Vin, which is the supply voltage (possibly unregulated) from which the supply  10  generates Vout. Because the supply  10  is a buck step-down converter, Vin is higher than Vout. Vin may also be coupled to the regulator  18  as discussed below.  
         [0019]     The regulator  18  includes a switching controller  22  and a threshold-signal generator  24 . The controller  22  includes a comparator  26  for comparing Vout to the threshold signal, which is a voltage Vthresh in this embodiment, and includes conventional switching logic  28  for activating the transistor  20   a  for a predetermined constant time in response to Vthresh being greater than Vout. The generator  24  includes a ramp circuit  30  for sourcing a ramped current IRamp to a node  32 , a resistor R for coupling a reference voltage Vref to the node, and an offset circuit  34  for sinking from the node a constant current that induces an offset voltage Voffset on the node. Therefore, when IRamp=0, Vthresh=Vref−Voffset. The circuit  34  may also be coupled to Vref and Vout as discussed below. Furthermore, Vref may be derived from a band-gap reference generator, or generated in any other suitable manner.  
         [0020]      FIG. 2A  is a timing diagram of Vout as generated by the power supply  10  ( FIG. 1 ) during steady-state operation of the load  12  according to an embodiment of the invention. Ideally the power supply  10  generates Vout so that it does not fall below Vref Therefore, the average level of Vout under ideal steady-state conditions equals Vref+A/2, where A is the peak-to-peak ripple amplitude, which is typically on the order of a few millivolts (mV).  
         [0021]      FIG. 2B  is a timing diagram of Vthresh according to an embodiment of the invention where Voffset is negative. The ramp circuit  30  generates IRamp so as to generate Vthresh (at the node  32 ) as a saw-tooth wave having a base voltage equal to Vref−Voffset and a peak voltage on the order of a few millivolts. Therefore, Vthresh is a virtual ripple voltage that is superimposed on the base voltage. Furthermore, Vthresh is generated in response to switching state feedback from the controller  22 , and optional feedback from Vout (dashed line to the offset circuit  34 ).  
         [0022]      FIG. 2C  is a timing diagram of Vthresh and Vout according to an embodiment of the invention. Because of the saw-tooth shape of Vthresh and the ripple on Vout, the difference between Vout and Vthresh is relatively large except when Vout and Vthresh simultaneously “meet” at Vref. This difference significantly increases the noise margin compared to conventional techniques such as where Vthresh merely equals Vref.  
         [0023]     Referring to  FIGS. 1 and 2 C, the operation of the power supply  10  is discussed according to an embodiment of the invention wherein Vin is not coupled to the regulator  22  and neither Vref nor Vout is coupled to the offset circuit  34 .  
         [0024]     At time t 0 , in response to the comparator  26  sensing Vout becoming less than Vthresh, the switching logic  28  deactivates the transistor  20   b  and activates the transistor  20   a , thus causing a charging current to flow from Vin, through the inductor L, to the filter capacitor C and to the load  12 . Ideally, the rising Vthresh and falling Vout “meet” at Vref, such that Vout becomes less than Vref at the same time that it becomes less than Vthresh. This charging current causes Vout to rise. Assuming that in a steady state the load  12  draws a constant current, the actual rate of this rise depends on the capacitance and equivalent series resistance (ESR) of C. In one embodiment, the capacitance and ESR of C are sufficiently large such that Vout increases at a substantially constant rate (i.e., straight line) as shown.  
         [0025]     Also at time t 0 , in response to activating the transistor  20   a , the switching logic  23  generates a DISABLE signal, which causes the threshold-signal generator  24  to “discharge” the node  32  to the base voltage of Vref−Voffset.  
         [0026]     At time t 1 , which is a predetermined constant time after t 0 , the switching logic  23  deactivates the transistor  20   a  and activates the transistor  20   b , thus allowing the current stored in the inductor L to continue flowing. As this current decays, Vout falls. When Vout falls below Vthresh, the above-described cycle is repeated.  
         [0027]     Also at time t 1 , in response to deactivating the transistor  20   a , the switching logic  23  generates a TURN-ON SYNC signal, which causes the ramp generator  30  to generate IRamp, and thus causes the threshold-signal generator  24  to ramp Vthreshold upward from the base voltage Vref−Voffset at a predetermined rate. When Vthresh rises above Vout, the above-described cycle is repeated. If one knows the steady-state current drawn by the load  12 , then he can calculate the steady-state ripple of Vout, and set Voffset and the slope of the Vthresh ramp such that during steady-state operation of the load, Voffset and Vout “meet” at Vref as is desired.  
         [0028]     Referring to  FIGS. 2A and 2C , during load transients, the minimum level of Vout may be less than or greater than Vref. During a transient period when the load  12  draws more current, the ripple amplitude A increases, and Vthresh and Vout “meet” at a voltage less than Vref. Conversely, during a transient period when the load  12  draws less current, the ripple amplitude A decreases, and Vthresh and Vout “meet” at a voltage greater than Vref.  
         [0029]     But one typically knows or can determine the parameters of the load transient currents, and can thus design the power supply  10  such that the minimum and maximum voltages where Vthresh and Vout “meet” during load transients are within respective voltage ranges that allow the load  12  to operate properly during these transients.  
         [0030]     Furthermore, because the comparator  26  compares Vout to Vthresh instead of to the constant Vref, the noise margin is often increased, and thus jitter in the switching frequency, and the undesirable affects of such jitter, are often reduced.  
         [0031]     Referring again to  FIG. 1 , if Vin changes over time (e.g., a discharging battery), then the ripple amplitude A ( FIG. 2 ) may at some times exceed (e.g., when the battery fully charged) an amount acceptable by the load  12 . Therefore, the regulator  22  (typically the switching logic  28 ) can include circuitry that adjusts the on time of the transistor  20   a  (on time=t 1 −t 0 ) based on the amplitude of Vin. As Vin increases, the regulator  22  decreases the on time, and as Vin decreases, the regulator increases the on time. Examples of such on-time adjusting circuits are included in U.S. provisional application Ser. No. 60/565,058 and in U.S. Pat. No. 6,495,995, which are incorporated by reference.  
         [0032]     Furthermore, because the generator  24  operates in an open-loop configuration relative to Vout, if the generator is not properly calibrated or drifts with temperature or other environmental conditions, then Voffset and IRamp may be such that Vout and Vthreshold do not “meet” at Vref. Therefore, the offset circuit  34  can receive Vout and Vref, and adjust Voffset such that the switching logic  28  activates the transistor  20   a  when Vout falls to Vref as in  FIG. 2A . This effectively adds feedback control to the supply  10 . But because such drifting usually occurs relatively slowly, then this feedback loop can be relatively slow, and thus have a relatively large stability margin.  
         [0033]      FIG. 3  is a schematic block diagram of a constant-on-time buck-converter power supply  40 , which uses virtual ripple feedback and which provides a regulated voltage Vout to the load  12  according to another embodiment of the invention. The supply  40  is similar to the supply  10  of  FIG. 1  except that the switching controller  22  provides a pulse RAMP to the threshold-signal generator  24  instead of providing the signals DISABLE and TURN-ON SYNC to the generator. Therefore, like numbers refer to components common to the supplies  10  and  40 . Furthermore, the following discussion assumes that Vout is a positive voltage, although a similar discussion applies where Vout is negative. Moreover, like the supply  10 , one can incorporate the supply  40  into virtually any electronic system, such as a laptop computer, that requires power conversion.  
         [0034]      FIG. 4A , which is similar to  FIG. 2A , is a timing diagram of Vout as generated by the power supply  40  ( FIG. 3 ) during steady-state operation of the load  12  according to an embodiment of the invention.  
         [0035]      FIG. 4B  is a timing diagram of Vthresh as generated by the threshold-signal generator  24  of the power supply  40  ( FIG. 4 ) according to an embodiment of the invention where Voffset is negative. Vthresh of  FIG. 4B  is similar to Vthresh of  FIG. 2B  except that Vthresh of  FIG. 4B  is ramped, not flat, between times t 0  and t 1 . Vthresh is generated in response to the RAMP pulse from the controller  22  as discussed below.  
         [0036]      FIG. 4C  is a timing diagram of Vthresh and Vout as generated by the power supply  40  of  FIG. 4  according to an embodiment of the invention. The timing diagram of  FIG. 4C  is similar to the timing diagram of  FIG. 2C  except that the timing diagram of  FIG. 4C  is ramped, not flat, between times t 0  and t 1 .  
         [0037]     Referring to  FIGS. 3 and 4 C, the operation of the power supply  40  is discussed according to an embodiment of the invention wherein Vin is not coupled to the regulator  22  and neither Vref nor Vout is coupled to the offset circuit  34 .  
         [0038]     At time t 0 , in response to the comparator  26  sensing Vout becoming less than Vthresh, the switching logic  28  deactivates the transistor  20   b  and activates the transistor  20   a , thus causing a charging current to flow from Vin, through the inductor L, to the filter capacitor C and to the load  12 . Ideally, the rising Vthresh and falling Vout “meet” at Vref, such that Vout becomes less than Vref at the same time that it becomes less than Vthresh. This charging current causes Vout to rise. Assuming that in a steady state the load  12  draws a constant current, the actual rate of this rise depends on the capacitance and equivalent series resistance (ESR) of C. In one embodiment, the capacitance and ESR of C are sufficiently large such that Vout increases at a substantially constant rate (i.e., straight line) as shown.  
         [0039]     Also at time to, in response to activating the transistor  20   a , the switching logic  23  generates a RAMP pulse, which causes the threshold-signal generator  24  to “discharge” the node  32  to the base voltage of Vref−Voffset, to generate IRamp, and to thus ramp Vthreshold upward from the base voltage Vref−Voffset at a predetermined rate.  
         [0040]     At time t 1 , which is a predetermined constant time after t 0 , the switching logic  23  deactivates the transistor  20   a  and activates the transistor  20   b , thus allowing the current stored in the inductor L to continue flowing. As this current decays, Vout falls. When Vout falls below Vthresh, the above-described cycle is repeated.  
         [0041]     Other than the threshold-signal generator  24  ramping Vthreshold before the switching logic  23  deactivates the transistor  20   a  and activates the transistor  20   b , the operation of the power supply  40  of  FIG. 3  is similar to the operation of the power supply  10  of  FIG. 1 .  
         [0042]      FIG. 5  is a schematic diagram of the threshold generator  24  of the power supply  40  of  FIG. 4  according to an embodiment of the invention.  
         [0043]     The ramp circuit  30  includes a constant current source  41 , which, when active charges a capacitor  42  to generate a voltage that ramps upward at a constant rate. An amplifier  44  draws from the input branch of a current mirror  46  a current that is proportional to the voltage across the capacitor  42 , and the output branch of the current mirror sources IRamp to the node  32 , thus generating the ramped portion of Vthresh. The current source  41  is adjustable so that one can select the slope of the ramped portion of Vthresh for the desired frequency of the ripple on Vout. When Vout becomes less than Vthresh ( FIG. 4C ), the RAMP pulse causes a transistor  48  to discharge the capacitor  42 , thus bringing IRamp to zero and returning Vthresh to Vref−Voffset as in  FIGS. 4B and 4C . But when the voltage across the capacitor  42  falls below a predetermined voltage Vclear, then a signal Lclear causes the transistor  48  to deactivate, thus allowing the capacitor  42  to begin charging again. Consequently, Vthresh begins ramping again a short time after t 0  and a significant time before t 1  as shown in  FIG. 4C . In one embodiment, Vclear is approximately 100 millivolts or less.  
         [0044]     The offset circuit  34  includes an amplifier circuit  50  that sinks a predetermined constant current from an input branch of current mirror  52 . An output branch of the current mirror  52  sinks an offset current from the node  32  to generate Voffset.  
         [0045]     A circuit  54  prevents the current source  41  from saturating by limiting the voltage across the capacitor  42  to a level that is at least approximately one transistor-threshold Vth drop below Vcc. That is, a voltage BuF≦Vcc−Vth, where Vth is the threshold voltage of the transistors that compose the current source  41 .  
         [0046]     In a similar manner, a circuit  56  prevents the current source  52  from saturating.  
         [0047]     Other embodiments of the power supplies  10  ( FIG. 1 ) and  40  ( FIG. 3 ) are contemplated. For example, the supplies  10  and  40  may generate a negative voltage for Vout.  
         [0048]      FIG. 6  is a schematic block diagram of a computer system  100 , such as a notebook computer system, which incorporates the power supply  10  of  FIG. 1 , the supply  40  of  FIG. 3 , or both the supplies  10  and  40  according to an embodiment of the invention. For clarity, however, the computer system  100  is shown incorporating only the supply  40 .  
         [0049]     The computer system  100  includes a central processing unit (CPU)  102 , a memory  104 , an input device  106 , and output device  108 , a data-storage device  110 , a battery  112 , a power source  114 , and a supply selector  116 . The CPU  102  executes programming instructions and manipulates data stored in the memory  104 , which is, e.g., a volatile memory such as dynamic random access memory (DRAM). The CPU  102  can also store data in the data-storage device  110 , which is, e.g., a nonvolatile device such as a hard-disk drive. The CPU  102  receives data and commands from the input device  106 , which is, e.g., a keyboard or a mouse, and provides data to the output device  108 , which is, e.g., a monitor or printer.  
         [0050]     The power source  114 , when active, converts  110 - 120  VAC from an electrical receptacle (not shown) into Vin, and the selector  116  couples Vin from the power source to the power supply  40  for conversion into the regulated output voltage Vout. The power source  114  may also charge the battery  112 .  
         [0051]     When the power source  114  is inactive, the selector  116  selects the battery  112  to supply Vin to the power source  40 .  
         [0052]     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.
A signal regulator includes a switching circuit, a controller, and a threshold generator. The switching circuit generates a regulated output voltage, and the controller activates the switching circuit for a predetermined time when the regulated output signal has a predetermined relationship to a threshold voltage. The threshold generator generates the threshold voltage in response to the controller. Generating the threshold voltage in response to the switching controller can reduce the affect that noise has on the operation of the switching circuit, and can thus decrease the magnitude of the noise-induced jitter in the regulator's steady-state switching frequency as compared to conventional switching regulators.