BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a voltage regulator. The output voltage of which depends on the drive to a transistor contained in the voltage regulator. 
     A voltage regulator of this type is shown in FIG.  5 . 
     The configuration shown in FIG. 5 contains a direct voltage regulator and a load impedance Zout connected thereto. 
     The voltage regulator contains a differential amplifier (a differential transconductance amplifier) OTA 1 , an NMOS transistor MN 1 , a first resistor Rfb, a second resistor Re, a third resistor Rs 1 , a first capacitor Cs 1 , a second capacitor Cs 2 , and a third capacitor Cs 3 . 
     The voltage regulator generates an output voltage Vout which is picked up at a source terminal of the transistor MN 1  and which is supplied as a supply voltage to the load Zout. A supply voltage supplying the voltage regulator with power is applied to a drain terminal of the transistor MN 1 , and the gate terminal is connected to the output terminal of the transconductance amplifier OTA 1 . The transconductance amplifier OTA 1  has two input terminals, one of which is supplied with an input voltage Vin and the other of which is supplied with a voltage depending on (fed back from) the output voltage Vout. The transconductance amplifier OTA 1  forms the difference between the voltages and outputs the result to the gate terminal of the transistor MN 1 . The voltage fed back is picked up at a node x 2  located between the resistors Rfb and Re. The resistors Rfb and Re are connected in series and are disposed between the source terminal of the transistor MN 1  and ground. 
     FIG. 6 shows the small-signal equivalent circuit of the configuration shown in FIG.  5 . 
     The voltage regulator described is a series voltage regulator with a common-drain NMOS transistor as a driver stage. It should be clear, and does not require further explanation, that the voltage regulator shown is capable of generating a constant output voltage Vout that depends only on Vin and the feedback factor (determined by the resistors Rfb and Re). However, this is not guaranteed under all circumstances, especially in the case of complex loads Zout, i.e. in the case of loads with inductive and/or capacitive components. The system may become unstable in this case. 
     The stability problems would not occur if it could be ensured, by suitable dimensioning of Rfb and Re, that the current Is 1  flowing through the transistor MN 1  does not drop below a certain minimum value even with a large Zout, that is to say a low load current, that is to say the transistor MN 1  has a certain minimum transconductance (a certain minimum output conductance). However, providing a large (shunt) current flowing via the transistor MN 1  and the resistors Rfb and Re is associated with various disadvantages. In particular, such a voltage regulator has a high intrinsic power requirement, and the transistor MN 1  has to be configured to be larger than would be the case with a low shunt current. In addition, the minimum shunt current necessary for ensuring the stability is not available for driving the load Zout. 
     The dependence of the stability of the voltage regulator on the minimum shunt current is now explained. 
     In a simplified way, the configuration according to FIG. 5 can be understood to be a two-pole system. The stability criterion requires that the two poles are apart by a factor of at least n≧10. 
     The first pole fp 1  is obtained in a simplified manner in accordance with equation 1.1.                f   p1     ≅     1     2   *   π   *     C   ml     *     1   /     gm   OTA1                   (   1.1   )                                
     It can be seen that the first dominant pole is determined by the transconductance gm of the transconductance amplifier OTA 1  and by the stabilization capacitance Cm 1 . In practice, the first pole is invariant and is determined by the necessary bandwidth of the configuration. 
     The second pole is determined in a simplified manner by the load capacitance Cout at the output Vout, the load impedance Zout and the output conductance gds of the driving transistor MN 1 . Equation 1.2 reproduces the mathematical relationship for calculating the second pole.                f   p2     ≅     1     2   *   π   *     C   out     *     (       1   /     gds   MN1               Zout             (     Re   +   Rfb     )       )                 (   1.2   )                                
     Using the aforementioned simplified dimensioning rule, according to which fp 2 ≧10*fp 1  is to apply for a given load, the necessary minimum shunt current and thus the resistance value Rmin (the sum of resistors Re and Rfb) can be calculated. 
     The second pole fp 2  is directly proportional to the output conductance of the driving transistor. The minimum output conductance of the transistor is directly proportional to the minimum shunt current Iq=Is 1  set and thus ultimately to the minimum phase margin of the configuration. 
     As has already been explained above, these relationships are disadvantageous. 
     For this reason, alternatives for influencing the stability of voltage converters that do not have these disadvantages have long been sought. 
     One possibility for this consists in providing additional elements by which the transfer function of the system or, more precisely, the position of the pole positions and zero positions of the transfer function can be influenced in order to thus guarantee a minimum phase margin for stabilization purposes. In the case of the voltage regulator shown in FIG. 5, these possibilities have been used. The additional elements contain the resistor Rs and the capacitors Cs 1 , Cs 2  and Cs 3 . Of the elements, resistor Rs and capacitor Cs 1  are connected in series and disposed between the output terminal of the transconductance amplifier OTA 1  and ground, the capacitor Cs 2  is disposed between the feedback branch and ground, and the capacitor Cs 3  is disposed in parallel with the resistor Rfb. 
     The elements make it possible to influence the position of the pole and zero positions of the transfer function and thus also the stability characteristic of the system. However, it is difficult and complex and in some cases even impossible to dimension the elements in such a manner that the voltage regulator operates in a stable manner over the entire load range. 
     There are a large number of publications in which these and other possibilities for stabilizing voltage regulators are described. Reference is made, for example, to: 
     a) Thomas M. Frederiksen: “A Monolithic High-Power Series Voltage Regulator”, IEEE Journal of Solid-State Circuits, December 1968, page 380 ff.; 
     b) Gabriel A. Rincon-Mora et al.: “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 1, January 1998, pages 36 ff.; 
     c) Gerrit W. den Besten et al.: “Embedded 5 V-to-3.3 V Voltage Regulator for Supplying Digital ICs in 3.3 V CMOS Technology”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 7, July 1998, page 956 ff; and 
     d) the other references mentioned therein. 
     Among the known methods for stabilizing voltage regulators, there is none which is simple to configure and implement and can guarantee reliable stabilization with little intrinsic power requirement under all circumstances. 
     This applies not only to the series voltage regulator described above but also to so-called low drop output (LDO) regulators which have a common-source PMOS transistor as the driving transistor. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide a voltage regulator which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which it can guarantee reliable stabilization under all circumstances with minimum intrinsic power requirement and, in addition, is simple to configure and implement. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a voltage regulator. The voltage regulator contains a transistor and an output supplying an output voltage that depends on a drive to the transistor. The output is connected to the transistor. A stabilizing circuit is connected to the transistor for changing a current flowing through the transistor. 
     The voltage regulator according to the invention is distinguished by the fact that it contains a stabilization circuit that can change the current flowing through the transistor. 
     The stabilization circuit can ensure that the current flowing through the transistor is increased in phases, specifically only in phases in which it would be too small for guaranteeing stable operation of the voltage regulator. 
     This dispenses with the necessity of having a high shunt current flowing permanently through the transistor. The voltage regulator can be constructed in such a manner that the shunt current flowing through the transistor is very low in phases in which it is not increased by the stabilization circuit, as a result of which the current flowing through the transistor is only slightly higher with large loads than the current drawn by the load. 
     This has the positive effect that the transistor can be dimensioned in sole dependence on the maximum load, that is to say it does not have to be made larger for reasons of the stability of the voltage regulator. In addition, the voltage regulator according to the invention has a lower intrinsic power requirement because, of course, the additional shunt current is only caused to flow in particular phases. 
     Moreover, the stabilization circuit can be simply configured and implemented and can be matched without problems to the respective circumstances. In addition, it can be used essentially unchanged in all types of voltage regulators, the output voltage of which depends on the drive to a transistor. 
     In accordance with an added feature of the invention, the current flowing through the transistor is changed by changing a load driven by the transistor. The load driven by the transistor is changed by reconfiguring the voltage regulator. The stabilization circuit has a switch coupled to the transistor, and the reconfiguration is effected by opening or closing the switch, and through the switch the transistor can be connected to a component acting as a load element or a current sink. 
     In accordance with an additional feature of the invention, the stabilization circuit has a component disposed in a circuit branch containing the transistor. The current flowing through the transistor is changed by changing a drive to the component. 
     In accordance with another feature of the invention, the component is a second transistor connected in series with the transistor. The current flowing through the transistor is changed by changing the drive to the second transistor. 
     In accordance with a further feature of the invention, the stabilizing circuit has a third transistor interconnected with the second transistor to form a current mirror. A current flowing through the second transistor depends on a current flowing through the third transistor. 
     In accordance with a further added feature of the invention, the stabilization circuit initiates a change in the current flowing through the transistor when and as long as the current flowing through the transistor has a magnitude at which stable operation of the voltage regulator cannot be guaranteed. 
     In accordance with a further additional feature of the invention, the stabilizing circuit does not change the current flowing through the transistor when and as long as the current flowing through the transistor has a magnitude at which stable operation of the voltage regulator is guaranteed. 
     In accordance with another further feature of the invention, the stabilization circuit has a reference current generator outputting a reference current, and the stabilization circuit generates a further current. A magnitude of the further current is a measure of the current flowing through the transistor and changes the current flowing through the transistor when the further current or an additional current depending on the further current is less than the reference current. 
     In accordance with another added feature of the invention, the stabilization circuit has a fourth transistor driven like the transistor and generates the further current. The fourth transistor is dimensioned to be smaller than the transistor. The stabilization circuit ensures that the fourth transistor is operated at a same operating point as the first transistor. The stabilization circuit has a fifth transistor connected in series with the fourth transistor. The stabilization circuit has a sixth transistor interconnected with the fifth transistor to form a further current mirror. The sixth transistor has a source terminal receiving the reference current, and the source terminal of the sixth transistor is further connected to a primary transistor of the current mirror. 
     In accordance with a concomitant feature of the invention, the current flowing through the transistor is changed via a hysteresis loop. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a voltage regulator, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a series voltage regulator with a stabilization circuit according to the invention; 
     FIG. 2 is a schematic diagram of a low drop output regulator with the stabilization circuit; 
     FIG. 3 is a graph showing variations with time of selected currents and voltages in the configuration shown in FIG. 1; 
     FIG. 4 is a schematic diagram of the series voltage regulator with a modified stabilization circuit; 
     FIG. 5 is a schematic diagram of a conventional series voltage regulator according to the prior art; and 
     FIG. 6 shows a simplified small-signal equivalent circuit of the configuration shown in FIG.  5 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The voltage regulators described in the text that follows are direct voltage regulators. However, it should be pointed out even at this point that the characteristic features of the voltage regulators described in the text which follows can also be used in voltage regulators for voltages varying with time. 
     Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a configuration which contains a particularly stabilized voltage regulator and the load impedance Zout connected thereto. 
     The voltage regulator is a series voltage regulator which, like the voltage regulator shown in FIG.  5  and described initially with reference thereto, contains the differential amplifier (a differential transconductance amplifier) OTA 1 , the NMOS transistor MN 1 , the first resistor Rfb and the second resistor Re which are also interconnected and cooperate as in the voltage regulator shown in FIG.  5 . The voltage regulator shown in FIG. 1 additionally contains a stabilization circuit that, however, is constructed and operates completely differently from the elements Rs 1 , Cs 1 , Cs 2  and Cs 3  used for stabilization of the voltage regulator according to FIG.  5 . 
     The stabilization circuit consists of a second differential amplifier (a second differential transconductance amplifier) OTA 2 , NMOS transistors MN 2 , MN 3 , MN 4 , MN 5  and MN 6 , and a PMOS transistor MP 3 . 
     To a drain terminal of the transistor MN 2 , a supply voltage supplying the voltage regulator with power is applied, its gate terminal is connected to the output terminal of the first transconductance amplifier OTA 1 , and its source terminal is connected to a node x 3 . 
     A source terminal of the transistor MP 3  is connected to the node x 3 , its gate terminal is connected to the output terminal of the second transconductance amplifier OTA 2 , and its drain terminal is connected to the source terminal of the transistor MN 4 . 
     The transconductance amplifier OTA 2  has two input terminals, one of which is supplied with the voltage occurring at the node x 3  and the other of which is supplied with the voltage Vout. The transconductance amplifier OTA 2  forms a difference between these voltages and outputs it to a gate terminal of the transistor MP 3 . 
     The transistor MN 4  (the source of which is connected to ground) is interconnected with the transistor MN 3  to form a current mirror, a current Irep flowing through the transistor MN 4  causes a current Irep′ to flow through the transistor MN 3 . 
     A drain terminal of the transistor MN 3  (the source of which is also connected to ground) is connected to a node x 1 . The node x 1  is also connected to a reference current source outputting a current Iref and to the drain terminal of transistor MN 5 . 
     The transistor MN 5  (the source of which is connected to ground) is interconnected with the transistor MN 6  to form a current mirror, a current Ic flowing through the transistor MN 5  causing a current Ic′ to flow through the transistor MN 6 . 
     A drain terminal of the transistor MN 6  (the source of which is also connected to ground) is connected to the drain terminal of transistor MN 1 . The transistor MN 6  represents for the transistor MN 1  an additional load by which the magnitude of the current Is 1  flowing through the transistor MN 1  can be changed, the drive to the transistor MN 1  remaining the same. 
     Through the transistor MN 1 , a current flows which corresponds to the sum of the currents Ic′, Iq and Iout. Ic′ being the current flowing through the transistor MN 6 , Iq being the current flowing through the voltage divider Rfb, Re, and Iout being the current flowing through the load Zout. 
     The transconductance amplifier OTA 2  and the transistor MP 3  ensure that at the source terminal of the transistor MN 2  (at node x 3 ), the same potential occurs as at the source terminal of transistor MN 1 , i.e. that the potential Vout also occurs at node x 3 . Simplified, the configuration of the transconductance amplifier OTA 2  and the transistor MP 3  can be considered to be a voltage follower that generates a replica of the output voltage Vout at the node x 3 . With respect to voltage, transistors MN 1  and MN 2  are thus at the same operating point, which improves the tracking of the two transistors with respect to one another. 
     For this reason, and because the gate of the transistor MN 2  is driven by the same signal as the gate of the transistor MN 1 , a current flows through the transistor MN 2  which is specifically related to the current flowing through the transistor MN 1 . The transistor is preferably constructed to be very much weaker than the transistor MN 1  so that the current Irep flowing through the transistor MN 2  is very much smaller than the current Ic′+Iq+Iout flowing through the transistor MN 1 . The transistor MN 2  thus produces a replica current Irep to the current Ic′+Iq+Iout flowing through the transistor MN 1 . 
     The current Irep flowing through the transistor MN 2  also flows through the transistor MP 3  and the transistor MN 4 . The current Irep flowing through the transistor MN 4  has the effect that a current Irep′, which is specifically related to the current Irep, flows through the transistor MN 3 . 
     If the current Irep′ is greater than or equal to the magnitude of the current Iref, the node x 1  is pulled to ground potential, as a result of which the current Ic flowing from node x 1  to the source terminal of the transistor MN 5  and thus also the mirrored current Ic′ become 0 and no additional shunt current flows through the transistor MN 1 . This is the case when the load impedance Zout is small enough, i.e. the load current Iout is large enough. 
     If, on the other hand, the current Irep′ is less than the current Iref, a current Ic corresponding to the difference between Irep′ and Iref flows from the node x 1  through the transistor MN 5 . The current Ic flowing through the transistor MN 5  has the effect that the current Ic′, which is specifically related to the current Ic, flows through the transistor MN 6 . As a result, an additional shunt current Ic′ flows through the transistor MN 1 . This is the case if the load impedance Zout is large, i.e. the load current Iout is small. 
     The stabilization circuit can thus have the effect that an additional shunt current Ic′ flows through the transistor MN 1  if the sum of the currents Iout and Iq is small, and that no additional shunt current Ic′ flows through the transistor MN 1  if the sum of the currents Iout and Iq is large or, more precisely, is large enough for guaranteeing stable operation of the voltage regulator. 
     In addition, the voltage regulator according to FIG. 1 also contains capacitors Cm 1  and Cm 2  via which the output terminals of the transconductance amplifiers OTA 1  and OTA 2  are connected to ground and which are used for frequency compensation of the transconductance amplifiers OTA 1  and OTA 2 . 
     Essentially the same stabilization circuit can be used in a so-called low drop output regulator. FIG. 2 shows the low drop output regulator with a stabilization circuit that corresponds to the stabilization circuit described above. 
     The configuration shown in FIG. 2 differs from the configuration shown in FIG. 1 only in that instead of the common-drain NMOS driver transistor MN 1 , a common-source PMOS driver transistor MP 1  is used, and the frequency compensation of the first transconductance amplifier OTA 1  is effected by a series circuit of the capacitor Cm 1  and a resistor Rm 1  (key word: Miller compensation or pole splitting, respectively) disposed between the output terminal of the transconductance amplifier OTA 1  and the output terminal of the voltage regulator (the drain terminal of transistor MP 1 ). 
     In the text that follows, the operation of the configurations shown in FIGS. 1 and 2 and their dimensioning will be described again in greater detail. 
     Neglecting non-ideal features, the output voltage Vout of the voltage regulator is obtained as:              Vout   ≅     Vin   *       Rfb   +   Re     Re               (   1.3   )                                
     When the load changes, the output voltage Vout changes. The transconductance amplifier OTA 1  (also called error amplifier) corrects the gate-source voltage of the transistor MN 1  (MP 1 ) until the voltage has returned to the nominal value at the output. 
     If the load current Iout is above a lower threshold Ioutmin, the current Ic′ is equal to 0 and the following holds true for the sum of the currents at the pickup point of Vout, called node Vout in the text which follows: 
     
       
           Iout+Iq−Is   1 =0  (1.4) 
       
     
     Neglecting non-ideal features (mismatch etc.), the current flowing through the transistor MN 2  is obtained as:              Irep   ≅         β                   n   MN2     *     W   MN2     *     L   MN1         B                   n   MN1     *     W   MN1     *     L   MN2         *   Is1             (   1.5   )                                
     where W is a width of the transistor mentioned in the respective index, L is a length of the transistor mentioned in the respective index, and β is the process constant of the transistor and transistor type mentioned in the respective index. To simplify, it is assumed that the process constants are identical for transistors of the same type, and they will thus not be mentioned in the text that follows unless required. 
     The current Is 1  is minimum when Iout and Ic′ are equal to 0 and is                      Is1   min     =     Vout     Rfb   +   Re                   =     Vin   *       (     Rfb   +   Re     )     Re     *     1     (     Rfb   +   Re     )                     =     Vin   Re                   (   1.6   )                                
     The current Irep occurring with Is 1 =Is 1 min is (see equations 1.5 and 1.6)                Irep   min     =           W   MN2     *     L   MN1           W   MN1     *     L   MN2         *     Vin   Re               (   1.7   )                                
     It also holds true that 
     
       
         Iref−Ic−Irep′=0  (1.8) 
       
     
     
       
         
           
             
               
                 
                   
                     Irep 
                     ′ 
                   
                   ≅ 
                   
                     
                       
                         W 
                         MN3 
                       
                       * 
                       
                         L 
                         MN4 
                       
                     
                     
                       
                         W 
                         MN4 
                       
                       * 
                       
                         L 
                         MN3 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1.9 
                   ) 
                 
               
             
             
               
                 
                   
                     Ic 
                     ′ 
                   
                   ≅ 
                   
                     
                       
                         
                           W 
                           MN6 
                         
                         * 
                         
                           L 
                           MN5 
                         
                       
                       
                         
                           W 
                           MN5 
                         
                         * 
                         
                           L 
                           MN6 
                         
                       
                     
                     * 
                     Ic 
                   
                 
               
               
                 
                   ( 
                   1.10 
                   ) 
                 
               
             
           
         
                 
         
             
         
      
     
     If the load current Iout decreases, starting from a maximum value, the current Is 1  in the transistor MN 1  (MP 1 ) drops, as does the current in the transistor MN 2 , as well. If the current Irep′ becomes less than Iref, the potential at node x 1  rises. If the voltage V(x 1 ) occurring at node x 1  becomes greater than Vthn (threshold voltage of transistor MN 5 ), the current Ic flows through the transistor MN 5 , and the current Ic′ flows through the transistor MN 6 . At this instant, the current in the node Vout is composed as follows: 
     
       
           Iout+Iq+Ic′−Is   1 =0  (1.11) 
       
     
     From equations 1.3 to 1.11, the following is obtained                Irep   ′     ≅       [       (         W   MN2     *     L   MN1           W   MN1     *     L   MN2         )     *     (     Iout   +     Vin   Re       )       ]     *         W   MN3     *     L   MN4           W   MN4     *     L   MN3                   (   1.12   )                 Ic   ′     ≅       (     Iref   -       [       (         W   MN2     *     L   MN1           W   MN1     *     L   MN2         )     *     (     Iout   +     Vin   Re       )       ]     *         W   MN3     *     L   MN4           W   MN4     *     L   MN3             )     *         W   MN6     *     L   MN5           W   MN5     *     L   MN6                   (   1.13   )                                
     This then produces the conditions for current Ic′:                  for                 Iout     &lt;       Iref   *         W   MN1     *     L   MN2           W   MN2     *     L   MN1         *         W   MN4     *     L   MN3           W   MN3     *     L   MN4           -   Iq       ⇒       Ic   ′     &gt;   0             (1.14a)                     for                 Iout     &gt;       Iref   *         W   MN1     *     L   MN2           W   MN2     *     L   MN1         *         W   MN4     *     L   MN3           W   MN3     *     L   MN4           -   Iq       ⇒     Ic   ′       =   0           (1.14b)                                
     Using equation 1.14a and 1.14b, the circuit can now be dimensioned, taking into consideration the transconductance of the transistor MN 1  (MP 1 ), which is necessary for stability. 
     First, a description is given of how the necessary current Ic′ can be determined from the requirement for stability and thus a minimum phase margin. The assumption is that the transconductance amplifier OTA 1  has a simplified transfer function with a dominant pole. Parasitic poles and zeroes will not be taken into consideration. 
     The Laplace transfer function in the frequency range of the transconductance amplifier is then                    A   OTA1          (   s   )       ≅     1     1   +     s   *     C   m1     *     1   /     gm   OTA1                    
          and                 its                 pole                 frequency                 is             (   1.15   )                 f   p1     =     1     2   *   π   *     C   m1     *     1   /     gm   OTA1                   (   1.16   )                                
     where gm OTA1 , designates the transconductance of the transconductance amplifier OTA 1 . 
     For the rest of the analysis, the frequency response compensation circuit consisting of Cm 1  and Rm 1  will be ignored initially. The following determinations can be made for the transconductance amplifier OTA 1  and the output stage:              R1   =       1   gdsp     +     1   gdsn               (   1.17   )                                C 1 =Cgs   MP1   +Cgd   MP1 *(1 +|Av   11   MP1 |)  (1.18)                R2   =       1     gds   MP1                 R      out             R                 min       ;       R                 min     =       V      in       Is   min                 (   1.19   )                                 C 2 =C 1 +Cgd   MP1 *(1 +|Av   11   MP1 |)  (1.20)              Av11   =       gm   MP1     *       (       1     gds   MP1                 R                 min           )               (   1.21   )                                 
     where 
     R 1  is an output resistance of the transconductance amplifier OTA 1 , 
     gdsp is an output conductance of a P-channel MOS transistor, 
     gdsn is an output conductance of an N-channel MOS transistor, 
     C 1  is a sum of the load capacitances at the node X 4  (OTA 1  output), 
     Cgs MP1  is a gate-source capacitance of transistor MP 1 , 
     Cgd MP1  is a gate-drain capacitance of transistor MP 1 , 
     Av 11  is a direct-voltage gain of the output stage (e.g. transistor MP 1 ), 
     R 2  is an output resistance of the driver configuration, 
     gds MP1  is an output conductance of the transistor MP 1 , 
     Rout is a purely resistive load impedance at the node Vout, 
     Rmin is a most minimum aggregate resistivity of Rfb and Re as auxiliary quantity for dimensioning, 
     C 2  is a transformed load capacitance for calculating the second pole fp 2 ′, and 
     gm MP1  is the transconductance of the output transistor MP 1 . 
     For series-shunt feedback configurations such as the voltage regulators shown in FIGS. 1 and 2, two poles can be specified, neglecting the frequency compensation:                fp1   ′     =     1     2   *   π   *   R1   *   C1               (   1.22   )                 fp2   ′     =     1     2   *   π   *   R2   *   C2               (   1.23   )                                
     From general stability theory, it is known that fp 2 ′&gt;&gt;fp 1 ′ must apply in order to guarantee a sufficiently large phase margin. If the load current Iout then tends toward 0 (if R 1  tends toward infinity), the pole fp 2 ′ migrates toward the pole fp 1 ′. The phase margin decreases, and the system becomes unstable. 
     Taking into consideration the frequency response compensation, the poles are obtained as follows:              fc1   =     1           2   *   π   *   R1   *     [       Cgs   MP1     +                       (       Cgd   MP1     +     C   m1       )     *     [     1   +        Av11          ]       ]                     (   1.24   )               fc2   =     1     2   *   π   *   R2   *     (     C1   +   Cm1   +     Cgs   MP1       )                 (   1.25   )                                
     From equations 1.22 and 1.23, the total transfer function in the frequency plane can then be represented as a second-order system.                Avtot        (   s   )       =           V      out          (   s   )           V      in          (   s   )         =         gm   OTA1     *   R1   *   Av11         (     1   +     s   *     f   /   fc1         )     *     (     1   +     s   *     f   /   fc2         )                   (   1.26   )                                
     Assuming that f 1 c&lt;&lt;f 2 c and considering that the absolute value of the gain is |Avtot(s)|=1 at a frequency of fu, the following is obtained:                     Avtot        (   s   )            =           gm   OTA1     *   R1   *   Av11         1   +       (     f   /   fc1     )     2           =   1             (   1.27   )                                fu=fc 1 *gm   OTA1   *R   1   *Av   11   (1.27a) 
     Assuming that the load capacitance, the maximum load current and minimum load current are known, either the compensation capacitance Cm 1  and/or the minimum shunt current Is 1  in the transistor MP 1 /MN 1  can now be calculated. To guarantee stability, the following determination should apply: 
     
       
           fc   2 &gt;10* fufc   2 &gt;10* fc   1   *gm   OTA1   *R   1   *Av   11   (1.28) 
       
     
     Thus, the following relationships are obtained for Rmin and for Cm 1  (taking into consideration equation 1.25):                      R                 min     =       V                 in       Iq   +     Ic   ′                     =           1   /     [     2      π   *   10      fc1   *     gm   OTA1     *   R1   *   Av11   *                       (     C1   +   Cm1   +     Cgd   MP1       )     -     gds   MP1     -     1     R                 out         ]                                         (   1.29   )                                
     Using equations 1.29, 1.14 and 1.15, the circuit can now be appropriately dimensioned. A structure and a value for the transconductance gm OTA1  of OTA 1  must be determined at the beginning of the design process. This can be done from an input for the bandwidth of the OTA in accordance with equation 1.16. For the gain of the driving transistor, the assumption can be made that the minimum current Iq flows as Is 1 . The circuit is thus provided with an appropriate stability margin. 
     As can be seen from the above equations, they were created partially for the low drop output voltage regulator shown in FIG.  2 . The relationships derived in this way can be transferred to the series voltage regulator shown in FIG. 1, taking into consideration the following formulae:              Av12   =         gm   MN1     *   R                 out           gm   MN1     *   R                 out     +   1               (   1.30   )                 R2   ′     =       1       gm   MN1     +     gmb   MN1     +     gds   MN1                   R                 out             R                 min             (   1.31   )                                C 2 ′=C 1 +Cdb   1   (1.32)                C1   ′     =     Cgs1   *   Cgd1   *     (     1   +              gm   MN1     *   R                 out           gm   MN1     *   R                 out     +   1              )               (   1.33   )                 fc1   ′     =     1     2   *   π   *   R1   *     [       Cgs   MN1     +       (       Cgd   MN1     +   Cm1     )     *     [     1   +        Av12          ]         ]                 (   1.34   )                                 
     With the same assumptions as for the LDO configuration, an Rmin′ is obtained for the series voltage regulator:                      R                   min   ′       =     Vin     Iq   +     Ic   ′                     =           1   /     [     2      π   *   10        fcl   ′     *     gm   OTA1     *   R1   *   Av12   *                     (     C1   +   Cm1   +     Cgs   MN1       )     -     gm   MN1     +                   gmb   MN1     +     gds   MN1     -     1   Rout       ]                         (   1.35   )                                
     Using equations 1.35 and 1.29, the minimum shunt current which must flow through the output transistor MN 1  and MP 1 , respectively, in order to guarantee stability with a given load capacitance, can then be determined for the configurations shown in FIGS. 1 and 2. It should be pointed out again that the resistance Rmin (Rmin′) is used as auxiliary quantity for the design process. The current through an assumed resistance Rmin (Rmin′) can then be divided correspondingly between the current Iq through voltage divider Rfb and Re and current Ic′. The circuit can thus be completely dimensioned. 
     To check the mathematical results, the transfer function in the frequency domain of the closed control loop can be derived from the small-signal equivalent circuit shown in FIG.  6 .                  Gav   ac          (   s   )       =     20   *     log        (           Zin        (   s   )               Zin        (   s   )       +   Re             Rfb       *     Avtot        (   s   )       *           (     Re   +   Rfb     )             C1             (     Re   +   Rfb     )             C1     +   Rout           1   +       Re     Re   +   Rfb       *     (         Zin        (   s   )               Zin        (   s   )       +   Re             Rfb       *     Avtot        (   s   )       *           (     Re   +   Rfb     )             C1               (     Re   +   Rfb     )             C1     +   Rout     )         )           )                 (   1.36   )                 Gav   dc     ≅     20   *     log        (       Re   +   Rf     Re     )                 (   1.37   )                                
     If the transfer function has a peak in the frequency domain with respect to the expected DC gain, instability or at least ringing must be assumed. 
     Using the abovementioned equations, the circuit can be configured appropriately. 
     FIG. 3 shows by way of example current and voltage variations in a properly dimensioned voltage regulator with a stabilizing circuit of the type described above. 
     FIG. 4 shows a stabilization circuit in which a hysteresis is provided for switching the additional shunt current Ic′ on and off. 
     The configuration shown in FIG. 4 corresponds closely to the configuration shown in FIG. 1; elements designated with the same reference symbols are identical or corresponding elements. 
     The stabilization circuit shown in FIG. 4 additionally contains NMOS transistors MN 7  and MN 8  and a current source supplying a reference current Iref 2 . 
     Transistors MN 7  and MN 8  are interconnected to form a current mirror, a drain terminal of the transistor MN 7  and gate terminals of the transistors MN 7  and MN 8  are connected to node x 1 . The drain terminal of the transistor MN 8  is connected to the drain terminal of the transistor MN 4 , the gate terminals of transistors MN 3  and MN 4  and the current source supplying the reference current Iref 2 , and the source terminals of the transistors MN 7  and MN 8  are connected to ground. 
     The additional measures have the result that the threshold value, below which Irep must drop for the additional shunt current Ic′ to flow, is lower than the threshold value which must be exceeded by Irep for no additional shunt current Ic′ to flow. 
     The hysteresis is characterized by:                I   hys     =       (           W   MN4     *     L   MN3           W   MN3     *     L   MN4         -         W   MN7     *     L   MN8           W   MN8     *     L   MN7           )     *   Iref1             (   1.38   )                                
     The stabilization circuits described can be modified in many different ways. 
     For example, the magnitude of the additional shunt current Ic′ could be set in such a manner that the current flowing through the transistor MN 1  and MP 1 , respectively, is in each case just large enough, i.e. not much greater than required, for guaranteeing stable operation of the voltage regulator. 
     The magnitude of the additional shunt current Ic′ could also be made variable in a number of steps. 
     The shunt current flowing through the transistor could also be made large as a standard measure, and the stabilization circuit could ensure that the shunt current is reduced when the magnitude of the current flowing through the transistor (or a current depending on the magnitude of this current) exceeds a particular threshold value. 
     Independently of this, the current flowing through the transistor MN 1  or MP 1 , respectively, can be changed by reconfiguring the configuration, for example by opening, closing or switching over switches via which the transistor can be connected to components or current sinks acting as load elements. Irrespective of the details of the practical implementation, the stabilization circuits of the voltage regulators described can be simply configured and implemented and can guarantee stabilization which is reliable under all circumstances with minimum intrinsic power requirement of the voltage regulators.
A voltage regulator is described, the output voltage of which depends on a drive to a transistor contained in the voltage regulator. The voltage regulator described is distinguished by the fact that it contains a stabilization circuit that can change the current flowing through the transistor. Such a voltage regulator is simple to configure and to implement and, with minimum intrinsic power requirement, is stable under all circumstances.