BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a dual FET differential voltage controlled attenuator, and more particularly to a dual FET differential voltage controlled attenuator having an improved linear attenuation characteristic over a control voltage range. 
     2. Description of the Background Art 
     A signal attenuator is a device that, as the name implies, reduces the magnitude and therefore the electrical energy of an incoming waveform signal. The removed electrical energy is dissipated as heat. 
     Attenuation is commonly used in electrical circuits. For example, signal attenuators are commonly used in audio circuits, radio frequency (RF) circuits, automatic gain control (AGC) circuits, etc. Generally, a waveform signal is initially amplified to a desired maximum level and then attenuated at points where a lower energy level is desired. Attenuation is generally preferred because during amplification of a signal, any noise on the signal is also amplified. It may therefore be desired to amplify a signal only once, and perform any subsequent actions on the amplified signal. 
     In the prior art, voltage controlled FETs have been commonly used in attenuators in order to attenuate an input signal. The prior art has applied voltage controlled FETs in a variety of ways, as shown in U.S. Pat. No. 5,745,634 to Garrett et al., U.S. Pat. No. 4,334,195 to Luce, U.S. Pat. No. 4,155,047 to Rubens et al., and U.S. Pat. No. 3,581,222 to Dunwoodie. 
     However, a common drawback of prior art attenuators is distortion. This distortion may be defined as unwanted changes to a waveform amplitude, especially localized changes, phase shifts, changes in waveform shape, etc. In addition, the prior art attenuators suffer from distortion that varies over a range of control voltage used to set the attenuation level. As a result, the input waveform is changed by the attenuator in undesirable and unpredictable ways. 
     What is needed, therefore, is an improved attenuator that provides a very linear attenuation over an available control voltage range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by making reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and wherein: 
     FIG. 1 shows a voltage controlled attenuator of the present invention; 
     FIG. 2 shows a graph of input-to-output attenuation levels versus frequency response for a variety of levels of control voltages; and 
     FIGS. 3-8 show graphs of periodic steady state test results for IIP 3  at three different power levels. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The distortion problem of the prior art is addressed by the dual FET differential voltage controlled attenuator of the present invention. The dual FET differential voltage controlled attenuator enjoys reduced distortion across the attenuation range by employing a differential dual FET approach. This provides a very linear attenuation characteristic and a substantially constant IIP 3  across the control voltage range. The IIP 3  is the input intercept point, a point where a theoretical third order distortion component meets the first order component. A high IIP 3  value is desirable, indicating that the attenuator can handle more input RF power without causing distortion, hence a high dynamic attenuation range. 
     FIG. 1 shows a voltage controlled attenuator  100  according to a preferred embodiment of the present invention. The voltage controlled FET attenuator includes resistors R 1 -R 4 , bipolar transistors Q 1 -Q 4 , voltage controlled FET transistors M 1  and M 2 , and current sources S 1 -S 4 . 
     The transistors Q 1 -Q 4  are bipolar junction transistors (BJTs). The voltage controlled resistors M 1  and M 2  are preferably field effect transistors (FETs). Any suitable type of FET may be used, such as a JFET, a MOSFET, etc. The two FETs M 1  and M 2  are biased in the triode region using a common mode signal V G . 
     One end of each of the resistors R 1 -R 4  is connected to a DC supply voltage V cc  (voltage supply bus  101 ). The other ends of the resistors R 1 -R 4  are connected to corresponding collector terminals of transistors Q 1 -Q 4 . The emitter terminals of transistors Q 1 -Q 4  are connected to corresponding current sources S 1 -S 4 . The current sources S 1 -S 4  are further connected to a ground bus  104 . Voltage controlled FET transistor M 1  is connected across the emitter terminals of transistors Q 1  and Q 2 , while voltage controlled FET transistor M 2  is connected across the emitter terminals of transistors Q 3  and Q 4 . 
     The base terminals of transistors Q 1  and Q 4  comprise a positive RF input terminal V CM +V in , where the input signal is composed of the input signal V in  plus the common mode voltage V CM . The base terminals of transistors Q 2  and Q 3  comprise a negative RF input terminal V CM −V in . The transistors Q 1 -Q 4  are biased in class A mode when V CM  is applied. 
     Two attenuator control voltage inputs are connected to the gate terminals of the two voltage controlled FET transistors M 1  and M 2 . As for the signal inputs, the control voltage inputs are formed of a common mode voltage V G  and a differential control signal v g . Therefore, the voltage at the positive control voltage terminal is V G +v g  while the voltage at the negative control voltage terminal is V G -v g . 
     The attenuator output is the voltage signal available at the collector terminals of transistors Q 2  and Q 3 . 
     In operation, the input voltages V CM +V in  and V CM −V in  are applied to the positive and negative input terminals. The voltage controlled FET transistor M 1  attenuates the voltage output at +V out  by acting as a variable resistor and regulating a shunt current i d1 . As a result, the current going through resistor R 2  may be increased by adding an additional current component i d1  to the current I EE  flowing through resistor R 2 . This can increase the voltage +V out  across resistor R 2 , where 
     
       
         +V out =V cc −I 2 R 2 =V cc −R 2 (I EE +i d1 ). 
       
     
     Likewise, the input voltages +V in  and −V in  applied to the positive and negative input terminals cause transistors Q 3  and Q 4  to turn on. The voltage controlled FET transistor M 2  also contributes to the attenuation at the output terminal −V out  by regulating a shunt current i d2 . As a result, the current going through resistor R 3  may be decreased by subtracting an additional current component i d2  from the current I EE  flowing through resistor R 3 . This can decrease the voltage −V out  across resistor R 3 , where 
     
       
         −V out =V cc −I EE R 3 =V cc −R 3 (I EE −i d2 ) 
       
     
     The differential control voltages V G +v g /2 and V G −v g /2 therefore control the two currents id 1  and i d2  and add to and subtract from the currents I EE  flowing through transistors Q 2  and Q 3 . The drain currents i d1  and i d2  are out of phase and combine differentially at the load, resulting in the cancellation of the higher order terms and yielding a constant IIP 3  across the attenuation range. The result is that the two voltage controlled FET transistors M 1  and M 2  control the amplitude of the differential output waveform seen at the output V out =(+V out )−(−V out ). Attenuation is thereby achieved. 
     The use of a pair of voltage controlled FET transistors as described above may be confirmed through examination of applicable equations. A FET operated in a triode region is given as:                I   D     =         μ                   C   ox       2                     W   L          (         {       V   GS     -     V   t       }          V   DS       -       1   2                     V   DS   2         )               (   1   )                                
     Applying equation 1 to the FETs yields:                i   d1     =         μ                   C   ox       2                       W   L          [         (       V   G     +       V   g     2     -     V   ic     +       v   i     2     -     V   t       )          v   i       -       1   2          v   i   2         ]                 (   2   )                 i   d2     =         μ                   C   ox       2                       W   L          [         (       V   G     -       v   g     2     -     V   ic     -       v   i     2     -     V   t       )          (     -     v   i       )       -       1   2          v   i   2         ]                 (   3   )                                
     where V G  is a DC bias voltage and v g  is an input waveform (instantaneous) voltage. At the output:                  i   d1     +     i   d2       =       I   EE     +     i   d1     -     (       I   EE     -     i   d2       )               (   4   )                       i   out     =                  i   d1     +     i   d2                   =                μ                   C   ox                       W   L     [         v   g          v   i       +     (         V   G          v   i       -       V   G          v   i         )     +     (         V   ic          v   i       -       V   ic          v   i         )     +                                    (         V   t          v   i       -       V   t          v   i         )     +     (       v   i   2     -     v   i   2       )       ]                 (   5   )                                
     simplifies as 
     
       
         i out =μC ox (W/L) (v g v i )  (6) 
       
     
     This yields a very linear equation, with attenuation being varied by varying v g . The attenuation range can be accurately controlled by v g  and the circuit provides a constant IIP 3  versus attenuation range. 
     From the equations it can be seen that the circuit may be used as a baseband modulator or analog multiplier, for example. 
     One very important feature of this circuit is the ability to control and determine IIP 3  through choice of the (W/L) ratio corresponding to the physical size of a channel region of a FET. 
     On expanding equation (6) as a power series it can be seen that: 
     
       
         IM 3 ∝(W/L) 2   (7) 
       
     
     Therefore, the dual FET differential voltage controlled attenuator has the ability to increase IIP 3  by decreasing the (W/L) FET characteristic. This tradeoff of attenuation control range versus IIP 3  has been verified through simulation. An additional feature of the present invention is that the IIP 3  of the dual FET differential voltage controlled attenuator is independent of the current I EE , with the current I EE  being adjusted to keep the BJTs at the appropriate bias point. 
     Note that if the voltage controlled FET transistors M 1  and M 2  were replaced with ideal resistors, the output would not be differential. The differential combination of phase inversion that occurs in the drain currents is unique to the dual FET differential voltage controlled attenuator of the present invention. A possible limitation may occur due to mismatch in the FET devices. 
     FIG. 2 shows a graph of input-to-output (S 21 ) attenuation levels versus frequency response for a variety of levels of control voltages v g . This graph illustrates a wide bandwidth from about 100 megahertz (MHz) to about 2 gigahertz (GHz), and a wide range of control voltages v g , producing an attenuation range of about 50 dB at 100 MHz. As can be seen from the figure, the attenuation range is somewhat decreased at higher frequencies, having an attenuation range of about 40 dB at an operating frequency of 1 GHz, and an attenuation range of about 35 dB at an operating frequency of 2 GHz. 
     It should be noted that the attenuation range may be increased by decreasing FET device sizes, thereby reducing parasitic capacitances. In addition, the attenuation range may be increased by increasing the (W/L) characteristic through the choice of FETs (see equation (6)). 
     FIGS. 3-8 show graphs of periodic steady state test results for IIP 3  at three different power levels. An average IIP 3  value greater than 5 dBm is obtained across the attenuation range for a current drain of less than 5 mA. Previous designs, using FETs as variable resistors, had significant degradation of IIP 3  values as the FET devices approached their cutoff region. The dual FET differential voltage controlled attenuator of the present invention and the differential cancellation technique employed herein circumvents the problem and yields a constant IIP 3  across the attenuation range. 
     The IIP 3  results shown in FIGS. 3-8 are summarized below in Table 1. 
     
       
         
               
               
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 ATTEN- 
                   
                   
                   
               
               
                 UATION 
                 Pinput = −20 dBm 
                 Pinput = −10 dBm 
                 Pinput = 0 dBm 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Low 
                  5.6 dBm 
                  8.85 dBm 
                 5.345 dBm 
               
               
                 Medium 
                 5.33 dBm 
                  11.0 dBm 
                 11.08 dBm 
               
               
                 High 
                   9 dBm 
                 9.695 dBm 
                 10.64 dBm 
               
               
                   
               
             
          
         
       
     
     In summary, the invented circuit provides an attenuation range greater than or equal to about 40 dB at 1 GHz, a wide bandwidth of about 100 MHz to about 2 GHz, and a consistent IIP 3  greater than or equal to about 5 dBm across the attenuation range. This is achieved with a current drain of less than about 5 milliamps. 
     While the invention has been described in detail above, the invention is not intended to be limited to the specific embodiments as described. It is evident that those skilled in the art may now make numerous uses and modifications of and departures from the specific embodiments described herein without departing from the inventive concepts.
A dual FET differential voltage controlled attenuator includes a first voltage controlled FET transistor (M 1), corresponding to a first control voltage terminal, and a second voltage controlled FET transistor (M 2), corresponding to a second control voltage terminal. The first voltage controlled FET transistor attenuates a voltage at an attenuator output by regulating current through a first resistor (R 2) connected between an attenuator output and a voltage supply node (Vcc), and the second voltage controlled FET transistor attenuates the voltage at the attenuator output by regulating current through a second resistor (R 3) connected between the attenuator output and the voltage supply node. The first and second voltage controlled FET transistors attenuate the voltage at the attenuator output by generating differential currents in the first and second resistors, the differential currents giving a linear transfer function from an attenuator input to the attenuator output of the dual FET differential voltage controlled attenuator.