FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor transistors and more particularly to semiconductor transistors having reduced distances between their gate electrode regions. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a conventional semiconductor chip, transistors are formed on the same semiconductor substrate. In order to increase the number of transistors that can be formed on a certain area of the semiconductor substrate, the gate electrode regions of the transistors can be formed closer together. Therefore, there is a need for a method for forming the gate electrode regions of the transistors closer together than those of the prior art. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, wherein the semiconductor substrate comprises a first semiconductor body region and a second semiconductor body region; (b) a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; (c) a first gate electrode region and a second gate electrode region, wherein the first gate electrode region is on top of the semiconductor substrate and the first gate dielectric region, and wherein the second gate electrode region is on top of the semiconductor substrate and the second gate dielectric region; (d) a gate divider region, wherein the gate divider region is in direct physical contact with the first and second gate electrode regions, and wherein the gate divider region does not overlap the first and second gate electrode regions in the reference direction. 
         [0004]    The present invention provides a method for forming the gate electrode regions of the transistors closer together than those of the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    FIGS.  1 A- 1 H″ illustrate a fabrication process of a semiconductor structure, in accordance with embodiments of the present invention. 
           [0006]    FIGS.  2 A- 2 B′ illustrate a fabrication process of another semiconductor structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0007]    FIGS.  1 A- 1 H″ illustrate a fabrication process of a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the semiconductor structure  100  starts with a silicon substrate  110  (top-down view). 
         [0008]    Next, with reference to  FIG. 1B  (top-down view), in one embodiment, an STI (shallow trench isolation) region  120  is formed in the substrate  110  resulting in active silicon regions  110   a ,  110   b ,  110   c ,  110   d . The STI region  120  can comprise silicon dioxide. The STI region  120  can be formed by (i) forming shallow trenches in the substrate  110  using lithographic and etching processes and then (ii) filling the shallow trenches with silicon dioxide by a conventional method resulting in the STI region  120 . FIG.  1 B′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1B  along a line  1 B′- 1 B′. 
         [0009]    Next, with reference to  FIG. 1C  (top-down view), in one embodiment, gate divider regions  130   a ,  130   b ,  130   c , and  130   d  are formed on top of the semiconductor structure  100  of  FIG. 1B . The gate divider regions  130   a ,  130   b ,  130   c , and  130   d  can comprise silicon nitride. The gate divider regions  130   a ,  130   b ,  130   c , and  130   d  can be formed by (i) depositing a silicon nitride layer (not shown) on top of the semiconductor structure  100  of  FIG. 1B  and then (ii) patterning the silicon nitride layer resulting in the gate divider regions  130   a ,  130   b ,  130   c , and  130   d.    
         [0010]    Next, in one embodiment, the thicknesses  134   a ,  134   b ,  134   c , and  134   d  of the gate divider regions  130   a ,  130   b ,  130   c , and  130   d , respectively, are reduced by isotropically etching the gate divider regions  130   a ,  130   b ,  130   c , and  130   d  until the thicknesses  134   a ,  134   b ,  134   c , and  134   d  have desired values. This etching of the gate divider regions  130   a ,  130   b ,  130   c , and  130   d  is essentially selective to the STI region  120  and the active silicon regions  110   a ,  110   b ,  110   c , and  110   d . In other words, the recipe of the etching of the gate divider regions  130   a ,  130   b ,  130   c , and  130   d  (e.g., chemicals used, temperature, pressure, etc.) is such that the STI region  120  and the active silicon regions  110   a ,  110   b ,  110   c , and  110   d  are essentially not affected by the etching of the gate divider regions  130   a ,  130   b ,  130   c , and  130   d . FIG.  1 C′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1C  along a line  1 C′- 1 C′. 
         [0011]    Next, with reference to FIGS.  1 D and  1 D′ (wherein FIG.  1 D′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1D  along a line  1 D′- 1 D′), in one embodiment, gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  are formed on the active silicon regions  111   a ,  110   b ,  110   c , and  110   d , respectively. The gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  can comprise silicon dioxide. The gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  can be formed by thermally oxidizing exposed-to-ambient silicon surfaces of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d  resulting in the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d , respectively. 
         [0012]    Next, in one embodiment, a gate electrode layer  140  is formed on top of the semiconductor structure  100 . The gate electrode layer  140  can be formed by CVD (Chemical Vapor Deposition) of poly-silicon on top of the semiconductor structure  100 . 
         [0013]    Next, with reference to FIGS.  1 E and  1 E′ (wherein FIG.  1 E′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1E  along a line  1 E′- 1 E′), in one embodiment, a photoresist layer  150  is formed on top of the gate electrode layer  140  such that the top surface  152  of the photoresist layer  150  is planar. The photoresist layer  150  can be formed by a spin-on process. 
         [0014]    Next, in one embodiment, a CMP (Chemical Mechanical Polishing) process is performed on the top surface  152  of the photoresist layer  150  until (i) the top surfaces  130   a ′,  130   b ′,  130   c ′, and  130   d ′ ( FIG. 1F ) of the gate divider regions  130   a ,  130   b ,  130   c , and  130   d  are exposed to the surrounding ambient and (ii) the entire photoresist layer  150  is completely removed, resulting in the structure  100  of  FIG. 1F  (top-down view). Because the top surface  152  of the photoresist layer  150  is planar, the CMP process can be performed more easily. FIG.  1 F′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1F  along a line  1 F′- 1 F′. 
         [0015]    Next, in one embodiment, the gate divider regions  130   a ,  130   b ,  130   c ,  130   d  are completely removed such that the top surface  122  ( FIG. 1G ) of the STI region  120  is exposed to the surrounding ambient through the spaces of the removed gate divider regions  130   a ,  130   b ,  130   c , and  130   b  resulting in the structure  100  of  FIG. 1G  (top-down view). The gate divider regions  130   a ,  130   b ,  130   c , and  130   d  can be removed by wet etching. FIG.  1 G′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1G  along a line  1 G′- 1 G′. 
         [0016]    Next, in one embodiment, the gate electrode layer  140  is patterned resulting in gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  of  FIG. 1H  (top-down view). The gate electrode layer  140  can be patterned by lithographic and etching processes. With reference to  FIG. 1H , it should be noted that, at this time, because of the formation of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  by the lithographic process, the distance  134   b ′ between the gate electrode regions  142   a  and  142   b  is greater than the thickness  134   b  of the gate divider region  130   b  ( FIG. 1F ). Similarly, because of the formation of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  by the lithographic process, the distance  134   c ′ between the gate electrode regions  142   c  and  142   d  is greater than the thickness  134   c  of the gate divider region  130   c  ( FIG. 1F ). It should be noted that, at this time, the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  (shown in  FIG. 1G ) remain on top of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d , respectively, but will be later removed (therefore not shown in  FIG. 1H ) as described below. 
         [0017]    Next, in one embodiment, the thicknesses  144   a ,  144   b ,  144   c , and  144   d  of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d , respectively, are reduced by isotropically etching the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  until the thicknesses  144   a ,  144   b ,  144   c , and  144   d  have desired values. Also as a result of the etching of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d , the distance  134   b ′ between the gate electrode regions  142   a  and  142   b  and the distance  134   c ′ between the gate electrode regions  142   c  and  142   d  are increased. Therefore, as a result of the formation of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  by the lithographic process and as a result of the subsequent etching of the resulting gate electrode regions  142   a ,  142   b ,  142   c , and  142   d , the distances  134   b ′ and  134   c ′ are greater than the thicknesses  134   b  and  134   c  of the gate divider regions  130   b  and  130   c , respectively ( FIG. 1F ). The etching of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  can be wet etching. 
         [0018]    Next, in one embodiment, portions of the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  not covered by the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  are removed by a conventional anisotropic etching step with the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  as blocking masks resulting in the structure  100  of  FIG. 1H . As a result, the top surfaces of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d  are exposed to the surrounding ambient. Also as a result, portions of the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  which are directly beneath the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  remain on top of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d . FIG.  1 H′ shows a cross-section view of the semiconductor structure  100  of  FIG. 1H  along a line  1 H′- 1 H′. FIG.  1 H″ shows a cross-section view of the semiconductor structure  100  of  FIG. 1H  along a line H″- 1 H″. 
         [0019]    Next, with reference to  FIG. 1H , in one embodiment, transistors are formed on the active silicon regions  110   a ,  110   b ,  110   c , and  110   d . More specifically, each of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  crossing over an active silicon region can form a transistor in which the gate electrode region serves as the gate electrode region of the transistor. For example, the gate electrode region  142   b  crossing over the active silicon region  110   d  can form a transistor in which the gate electrode region  142   b  serves as the gate electrode region of the transistor. Source/Drain regions of the transistor are subsequently formed in the active silicon region  110   d . In total, six transistors can be formed on the semiconductor structure  100  of  FIG. 1H . 
         [0020]    In summary, with reference to  FIGS. 1F and 1H , the distance  134   b ′ between the gate electrode regions  142   a  and  142   b  depends on the thickness  134   b  of the gate divider region  130   b , whereas the distance  134   c ′ between the gate electrode regions  142   c  and  142   b  depends on the thickness  134   c  of the gate divider region  130   c . As a result, the reductions of the thicknesses  134   b  and  134   c  of the gate divider region  130   b  and  130   c  result in the reductions of the distances  134   b ′ and  134   c ′, respectively. The reductions of the thicknesses  134   b  and  134   c  of the gate divider regions  130   b  and  130   c  can be easily performed by an anisotropic etching step as described above. 
         [0021]    FIGS.  2 A- 2 B′ illustrate a fabrication process of a semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 2A  (top-down view), the fabrication process of the semiconductor structure  200  starts with the structure  200  of  FIG. 2A . The structure  200  of  FIG. 2A  is similar to the structure  100  of  FIG. 1F . The formation of the structure  200  of  FIG. 2A  is similar to the formation of the structure  100  of  FIG. 1F . 
         [0022]    Next, in one embodiment, with the gate divider regions  130   a ,  130   b ,  130   c , and  130   d  in place (not removed as in the embodiments described above with respect to FIGS.  1 A- 1 H″), the gate electrode layer  140  is patterned resulting in the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  of  FIG. 2B  (top-down view). The gate electrode layer  140  can be patterned by lithographic and etching processes. 
         [0023]    Next, in one embodiment, the thicknesses  144   a ,  144   b ,  144   c , and  144   d  of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d , respectively, are reduced by isotropically etching the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  until the thicknesses  144   a ,  144   b ,  144   c , and  144   d  have desired values. 
         [0024]    Because the side walls  146   a  and  146   b  of the gate electrode regions  142   a  and  142   b , respectively, are in direct physical contact with the gate divider region  130   b , the side walls  146   a  and  146   b  are not affected (i) by the patterning of the gate electrode layer  140  to create the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  and (ii) by the subsequent etching of the resulting gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  to reduce their thicknesses. As a result, the distance  134   b  between the gate electrode regions  142   a  and  142   b  is equal to the thickness  134   b  of the gate divider region  130   b . Similarly, because the side walls  146   c  and  146   d  of the gate electrode regions  142   c  and  142   d , respectively, are in direct physical contact with the gate divider region  130   c , the side walls  146   c  and  146   d  are not affected (i) by the patterning of the gate electrode layer  140  to create the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  and (ii) by the subsequent etching of the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  to reduce their thicknesses. As a result, the distance  134   c  between the gate electrode regions  142   c  and  142   d  is equal to the thickness  134   c  of the gate divider region  130   c.    
         [0025]    Next, in one embodiment, portions of the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  not covered by the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  are removed by a conventional anisotropic etching step with the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  as blocking masks resulting in the structure  100  of  FIG. 2B . As a result, the top surfaces of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d  are exposed to the surrounding ambient. Also as a result, portions of the gate dielectric regions  112   a ,  112   b ,  112   c , and  112   d  which are directly beneath the gate electrode regions  142   a ,  142   b ,  142   c , and  142   d  remain on top of the active silicon regions  110   a ,  110   b ,  110   c , and  110   d . FIG.  2 B′ shows a cross-section view of the semiconductor structure  200  of  FIG. 2B  along a line  2 B′- 2 B′. 
         [0026]    In summary, with reference to  FIG. 2B , the distance  134   b  between the gate electrode regions  142   a  and  142   b  is equal to the thickness  134   b  of the gate divider region  130   b , whereas the distance  134   c  between the gate electrode regions  142   c  and  142   b  is equal to the thickness  134   c  of the gate divider region  130   c . As a result, the reductions of the thicknesses  134   b  and  134   c  of the gate divider region  130   b  and  130   c  result in the reductions of the distances  134   b  and  134   c , respectively. The reductions of the thicknesses  134   b  and  134   c  of the gate divider regions  130   b  and  130   c  can be easily performed by an anisotropic etching step as described above. 
         [0027]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.