BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally relates to memory circuits, and more particularly, the present invention relates circuits and methods for isolating memory cells of a memory device. 
   2. Description of the Related Art 
   A conventional memory device, such as a dynamic random access memory (DRAM) device, is schematically illustrated in  FIG. 1 . As shown, a plurality of memory cell arrays  10  and sense amplifiers  20  are alternately arranged. Each memory cell array  10  is associated with a row decoder  30  which generates word line signals (WL) for selection of word lines of the corresponding memory cell array  10 . Likewise, a column decoder  50  generates column select signals (CSL) for selection of bits lines of the memory cells arrays  10 . Also, as shown, each sense amplifier  20  is controlled by control signals (CONTROL) generated by respective a control circuit  40 . 
   The memory device of  FIG. 1  is characterized by the sharing of each sense amplifier  20  between two adjacent memory cell arrays  10 . Isolation circuitry contained in each sense amplifier  20  is utilized to isolate one of the adjacent memory cell arrays  10  while the sense amplifier  20  is being used in conjunction with the other of adjacent memory cell arrays. This is explained in more detail with reference to the circuit diagram of  FIG. 2 . 
   Referring to  FIG. 2 , a sense amplifier region is operatively connected between a first memory cell array block  1  (BLOCK 1 ) and a second memory cell array block  2  (BLOCK 2 ). Each block contains complimentary memory cells C 0  and C 1  connected between source voltage VP and complimentary bit lines BLn and BLBn (where n=0, 1, 2, . . . ), respectively. A column decoder  50  receives a pre-decoded column address signal DCA and generates corresponding column select signals CSLn for selection of the complimentary bit lines BLn and BLBn. Also, as shown, the complimentary memory cells C 0  and C 1  are respectively read/write enabled by word lines WL 0  and WL 1  (or word lines WL 510  and  511 ), which in turn are connected to a row decoder  30  which decodes pre-decoded row address signals DRA. As one skilled in the art will appreciate,  FIG. 2  only shows a small portion of a typical memory block, and in reality each memory block includes numerous pairs of word lines and bit lines connected to numerous pairs of complimentary memory cells. 
   The sense amplifier region of  FIG. 2  includes equalization transistors E 1 , E 2  and E 3  which form an equalization circuit connected as shown between each pair of bit lines BL 0  and BLB 0 . This equalization circuit is responsive to an equalization control signal PEQL (or PEQR) generated by an equalization control signal generator  41  (PEQL GEN. and PEQR GEN.) to equalize, or pre-charge, the bit lines BL 0  and BLB 0  to VCC/2 (=VBL). Generally, this is done prior to accessing (e.g., reading) the memory cells connected to the bit lines. 
   Transistors P 1 , P 2  and N 1 , N 2  are connected as shown to form a sense amplifier which functions in a well know manner to amplify a voltage differential across the bit lines BL 0  and BLB 0 . The sense amplifier is enabled by sense enable voltages LA and LAB generated by amplification voltage generators  43  and  44  (LA GEN. and LAB GEN.). 
   Transistors S 1  and S 2  are isolation transistors which are responsive to isolation control signals PISOL and PISOR generated by an isolation control signal generator  42  (PISOL GEN. and PISOR GEN.) in response to block selection signals PBLOCK 1  and PBLOCK 2 . The isolation transistors S 1  and S 2  are controlled to selectively isolate one of the blocks  1  or  2  while the sense amplifier is being used for the other of the blocks  1  or  2 . 
   Transistors L 1  and L 2  are column select transistors which are used to selectively couple the bit lines BL 0  and BLB 0  to input/output lines IO and IOB, respectively. These transistors L 1  and L 2  are activated in response to the column select signals generated by the column decoder  50 . For example, column select signal CSL 0  controls coupling of the bit lines BL 0  and BLB 0  to the input/output lines IO and IOB, column select signal CSL 1  controls coupling of the bit lines BL 1  and BLB 1  to the input/output lines IO and IOB, and so on. 
     FIG. 3  is a block diagram for explaining the generation of the word line signals WL and the column select signals CSL. Externally supplied command and address signals are applied to terminals of the memory device as shown. A command decoder  60  is response to the command signals to generate a row access master signal PR and a column access master signal PC. An address buffer  70  receives the externally supplied address, and outputs a row address RA and a column address CA according to the externally supplied address and the row and column access master signals PR and PC. Pre-decoders  80  and  85  convert the row and column address signals RA and CA to pre-decoded row and column address signals DRA and DCA, respectively. These pre-decoded signals are then decoded by main decoders  90  and  95  to generate the word line signal WL and the column select signal CSL, respectively. 
     FIG. 4  is a schematic block diagram showing the generation of the isolation control signals, the equalization signals, and the sense enable signals of the memory device shown in  FIG. 2 . As described above in connection with  FIG. 3 , the pre-decoder  80  outputs pre-decoded row address signals DRA. Bits DRAij of the pre-decoded row address signal DRA are applied to the main decoder  90  which, as described above, outputs a corresponding word line signal WL. The remaining bits DRAkl of the pre-decoded row address signal DRA (typically, the most-significant bits of DRA) are used for block selection and applied to the block generator  100 . The block generator  100  outputs a block selection signal PBLOCK 1 , 2  which is indicative of one of the two memory array blocks  1  and  2  of the memory device. Although two blocks are described in this example, the memory device may include many more memory array blocks (e.g., 16 or more). 
   Still referring also to  FIG. 4 , the isolation control signal generator  42  controls isolation control signals PISOL and PISOR in accordance with the block selection signal PBLOCK 1 , 2 . Likewise, the equalization control signal generator  41  controls equalization control signals PEQL and PEQR in accordance with the block selection signal PBBLOCK 1 , 2 . 
   Meanwhile, the sense control circuit  110  of  FIG. 4  outputs a sense enable master signal PS in accordance with the row access master signal PR (see  FIG. 3 ) and the row address signal bits DRAij or DRAkl. The sense enable master signal PS is received by sense amplifier control circuits  120  and  130 , which respectively output sense amplifier control signals PS_PSA and PS_NSA. These control signals PS_PSA and PS_NSA are used to respectively control the voltage level of the sense enable voltages LA and LAB illustrated in  FIG. 2  (see, e.g.,  FIG. 9  discussed below). 
     FIG. 5  is an exemplary circuit diagram of the isolation control circuit generator  42  illustrated in  FIG. 4 , and  FIG. 6  is a logic table of the same. Generally, at least one of the block signals PBLOCK 1  and PBLOCK 2  is isolation enabled (Low) at all times. Here, isolation enabled means that the corresponding memory block is isolated from the sense amplifier. As is apparent from  FIG. 5 , and as shown in the table of  FIG. 6 , when PBLOCK 1  is enabled (Low) and PBLOCK 2  is non-enabled (High), isolation signal PISOL becomes VSS (Low) and isolation signal PISOR becomes VPP (High). As such, referring to  FIG. 2 , the cell array block  1  is isolated from the sense amplifier circuitry, while cell array block  2  is coupled to the sense amplifier circuitry. In contrast, when PBLOCK 1  is non-enabled (High) and PBLOCK 2  is enabled (Low), isolation signal PISOL becomes VPP (High) and isolation signal PISOR becomes VSS (Low). Thus, the cell array block  1  becomes coupled to the sense amplifier circuitry, and cell array block  2  is isolated from the sense amplifier circuitry. When both PBLOCK 1  and PBLOCK 2  are non-enabled (Low), for example during a standby mode, then the circuit block identified by reference number  150  functions to pre-charged and equalized PISOL and PISOR to voltage VCC. 
     FIG. 7  is a simplified circuit diagram for explaining a charge sharing operation of a conventional memory device. The bit lines BL and BLB of the device include pre-charged capacitors CBL_CELL and CBL_SA (CBLB_CELL and CBLB_SA). As examples, CBL_CELL is about 3 times the size of CCELL of the memory cell, and CBL_CELL is greater than the size of CBL_SA of the sense amplifier. In operation, assume the capacitor of memory cell C 0  contains a data “1”. When the word line WL is enabled, the charges stored in the various capacitors of bit line BL are “shared” as depicted by the two-headed arrow. The result is a small increase (e.g., 100 mV or more) in the voltage of bit line BL which is to be detected by the sense amplifier. 
     FIG. 8  is a timing diagram of the charge sharing operation of the circuit of  FIG. 5 , again in the case where cell C 0  contains data “1”. In an isolation (ISO) activation period, isolation control signal PISOL is increased from VCC to VPP, and isolation control signal PISOR is decreased from VCC to VSS. At the end of the ISO activation period, the voltage of word line WL is increased from VSS to VPP. As such, the capacitor CCELL becomes coupled to the bit line BL, and the resultant charge sharing operation causes the voltage of bit line BL to increase from VBL to VBL+ΔVBL. Note that the voltage of bit line BLB remains at VBL. 
   In order to speed up the bit line sense operation, it is generally necessary to lower the threshold voltages of the sense amplifier transistors. However, a trade-off situation arises in that lower threshold voltages result in increased leakage current, which in turn reduces an effective sense interval of the sense operation. The dashed lines shown in the circuit diagram of  FIG. 9  depict sense amplifier leakage current paths in the case where bit line BL is at voltage VBL+ΔVBL, and bit line BLB is at voltage VBL. The result of this leakage is illustrated in  FIG. 10 . After the charge sharing operation which follows activation of the isolation control signal PISO, the voltage level of bit line BL gradually decreases as a result of the sense amplifier leakage. The line identified by circle- 2  of the figure shows the bit line voltage characteristic in the case where the VCC voltage (i.e., the sense amplifier transistor thresholds) is reduced relative to that of the line identified by circle- 1  of the figure. The leakage is more pronounced at lower thresholds, and accordingly, the voltage drop is more rapid. As shown, the result is a significantly reduced sensing interval. As the trend in the industry is for lower and lower VCC operating voltages, sense amplifier leakage is becoming increasingly problematic. 
   In the meantime, a number of bit line bridge defects tend to occur in the manufacture of the memory device. Turning now to  FIG. 12 , these defects are generally of two types. The first type (circle- 1 ) results from a short or leakage between bit lines of the same bit line pair (e.g., BL 0  and BLB 0 ). The second type (circle- 2 ) results from a short or leakage between bit lines of adjacent bit line pairs (e.g., BLB 0  and BL 1 ). As is schematically shown, the bit lines of the memory cell array are packed more densely than those in the sense amplifier regions, and accordingly, bit line bridge defects are relatively common. As such, the memory device is thoroughly tested after manufacture for the presence of bit line bridge defects, and techniques are known for replacing defective bit lines with spare bit lines. 
   One problem with testing for bit line bridge defects, however, is that it is becoming increasingly difficult to distinguish bit line leakage from the leakage of the sense amplifier. As mentioned above, sense amplifier leakage causes a gradual drop in ΔVBL. The leakage attended by a bit line bridge defect can similarly reduce ΔVBL. Accordingly, it has become to difficult identify bit line bridge defects, particularly in the case where low threshold sense amplifier transistors are utilized. 
   SUMMARY OF THE INVENTION 
   According to one aspect of the present invention, a semiconductor memory device is provided which is operative in a read mode to read a memory cell of the device and which includes first and second memory cell arrays, a sense amplifier, and first and second isolation circuits. The first memory cell array includes a first memory cell to be read, a first bit line pair and a first word line, where a charge contained in the first memory cell to be read is applied to the first bit line pair when a word line select signal applied to the first word line becomes active during the read mode. The second memory cell array includes a second memory cell, a second bit line pair and a second word line. The sense amplifier is operatively interposed between the first and second memory cell arrays. The first isolation circuit isolates the sense amplifier from the first bit line pair when a first isolation signal is active, and couples the first bit line pair and the sense amplifier when the first isolation signal is inactive. The second isolation circuit isolates the sense amplifier from the second bit line pair when a second isolation signal is active, and couples the second bit line pair and the sense amplifier when the second isolation signal is inactive. During the read mode, the first isolation signal is held active and the second isolation signal is held inactive prior to the word line select signal becoming active. 
   According to another aspect of the present invention, a semiconductor device is provided which includes first and second memory cell arrays, a sense amplifier operatively interposed between the first and second memory cell arrays, first and second isolation circuits, an external terminal, and a logic circuit. The first isolation circuit isolates the sense amplifier from the first bit line pair when a first isolation signal is active, and couples the first bit line pair and the sense amplifier when the first isolation signal is inactive. The second isolation circuit isolates the sense amplifier from the second bit line pair when a second isolation signal is active, and couples the second bit line pair and the sense amplifier when the second isolation signal is inactive. The external terminal receives an external isolation control signal, and the logic circuit receives the external isolation control signal and outputs the first and second isolation signals. 
   According to yet another aspect of the present invention, a semiconductor memory device is provided which includes a first memory cell array including a first bit line pair, a first equalization circuit coupled to the first bit line pair, a second memory cell array including a second bit line pair, a second equalization circuit coupled to the second bit line pair, a sense amplifier operatively interposed between the first and second bit line pairs, first and second isolation circuits, an external terminal, a control circuit, and a logic circuit. The first isolation circuit isolates the sense amplifier from the first bit line pair when a first isolation signal is active, and couples the sense amplifier to the first bit line pair when the first isolation signal is inactive. The second isolation circuit isolates the sense amplifier from the second bit line pair when a second isolation signal is active, and couples the second bit line pair to the sense amplifier when the second isolation signal is inactive. The external terminal receives an external isolation control signal, the control circuit which outputs a memory array selection signal, and the logic circuit which receives the external isolation control signal and the memory array selection signal and which outputs the first and second isolation signals. 
   According to another aspect of the present invention, a semiconductor memory is provided which includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and means for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier. 
   According to still another aspect of the present invention, a method of reading a memory cell in a semiconductor memory is provided. The semiconductor memory include a first bit line pair and a first memory cell to be read, a second memory cell array including a second bit line pair, a sense amplifier operatively interposed between the first and second bit line pairs, a first isolation circuit which isolates the sense amplifier from the first bit line pair when a first isolation signal is active, and which couples the first bit line pair and the sense amplifier when the first isolation signal is inactive, and a second isolation circuit which isolates the sense amplifier from the second bit line when a second isolation signal is active, and which couples the first bit line and the sense amplifier when the second isolation signal is inactive. The method includes causing the first isolation signal to be active and the second isolation signal to be inactive, applying a charge contained in the first memory cell to be read to the first bit line pair while the first isolation signal is active and the second isolation signal is inactive, and causing the first isolation signal to be inactive and the second isolation signal to be active after the charge is applied to the first bit line pair, where the charge is applied to the sense amplifier via the first isolation circuit. 
   According to another aspect of the present invention, a method of reading a semiconductor memory is provided. The semiconductor memory a memory cell array, a sense amplifier, and an isolation device interposed between the sense amplifier and a bit line of the memory cell array. The method includes transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, causing the isolation device to electrically connect the bit line to the sense amplifier. 


   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a conventional memory device; 
       FIG. 2  is a circuit diagram of a portion of the memory device illustrated in  FIG. 1 ; 
       FIG. 3  is a block diagram of conventional circuitry used to generate word line and column select signals; 
       FIG. 4  is a block diagram of conventional circuitry used to generate isolation, equalization and sense enable signals; 
       FIGS. 5 and 6  are a circuit diagram and logic table, respectively, for explaining the generation of isolation control signals in a conventional memory device; 
       FIGS. 7 and 8  are a circuit diagram and a timing diagram, respectively, for explaining a conventional charge sharing operation; 
       FIG. 9  is a circuit diagram for explaining leakage which occurs in the case of a conventional sense amplifier; 
       FIG. 10  is a waveform diagram for explaining the relationship between bit line voltage and the sense interval of a conventional memory device; 
       FIG. 11  is a waveform diagram for explaining the control of the bit line voltage according to an isolation technique of an embodiment of the present invention; 
       FIG. 12  is a block diagram illustrating bit line bridge defects which can occur in a conventional memory device; 
       FIG. 13  is a circuit diagram of an isolation control signal generator according to an embodiment of the present invention; 
       FIGS. 14 and 15  are logic tables for describing the operation of the circuit illustrated in  FIG. 13 ; 
       FIG. 16  is a timing diagram for describing a first operational mode of a memory device according to an embodiment of the present invention; 
       FIG. 17  is a timing diagram for describing a second operational mode of a memory device according to an embodiment of the present invention; 
       FIG. 18  is a logic circuit diagram showing the generation of a sense enable signal and control signals according to an embodiment of the present invention; 
       FIG. 19  is a timing diagram for explaining the operation of the logic circuit illustrated in  FIG. 20 ; 
       FIG. 20  is an operational block diagram of the first operational mode of a memory device according to an embodiment of the present invention; and 
       FIG. 21  is an operational block diagram of the second operational mode of a memory device according to an embodiment of the present invention. 
   


   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The present invention will now be described in detail with reference to preferred but non-limiting embodiments. 
     FIG. 13  is a circuit diagram of an isolation control signal generator according to one embodiment of the present invention. Inputs to the generator include the block selection signals PBLOCK 1  and PBLOCK 2 , and control signals CON 0 , CON 1  and CON 2 . The block selection signals PBLOCK 1  and PBLOCK 2  may, for example, be generated in the same manner as discussed previously in connection with the related art. The control signals CON 0 , CON 1  and CON 2  may, for example, be externally generated and applied to one or more pin terminals or pad terminals of the memory device. 
   As shown in  FIG. 13 , the logic OR of control signal CON 0  and inverted block selection signal PBPLOCK 1  is applied to the gate of transistor P 3 , and the inverted signal thereof is applied to the gate of transistor N 4 . Similarly, the logic OR of control signal CON 0  and inverted block selection signal PBPLOCK 2  is applied to the gate of transistor P 4 , and the inverted signal thereof is applied to the gate of transistor N 3 . Accordingly, when the control signal CON 0  is Low, the isolation control signals PISOL and PISOR are dependent on the block selection signals PBLOCK 1  and PBLOCK 2  in the same manner as described previously in connection with  FIGS. 5 and 6 . 
   On the other hand, when CON 0  is High, the transistors P 3 , N 3 , P 4  and N 4  are all maintained in an OFF state regardless of the block selection signals PBLOCK 1  and PBLOCK 2 . As such, the isolation control signals PISOL and PISOR become dependent on the control signals CON 1  and CON 2 . That is, when CON 1  is High and CON 2  is Low, transistors P 5  and N 6  are OFF, and transistors N 5  and P 6  are ON. The isolation control signal PISOL thus becomes VSS, and the isolation control signal PISOR becomes VCC or VPP 2 . Here, VPP&gt;VPP 2 &gt;VCC. As examples only, VPP≈2.1v, VPP 2 ≈1.4v, and VCC≈1.0v. In contrast, when CON 1  is Low and CON 2  is High, transistors P 5  and N 6  are ON, and transistors N 5  and P 6  are Off. The isolation control signal PISOL thus becomes VCC or VPP 2 , and the isolation control signal PISOR becomes VSS. 
   The operation of the isolation control signal generator of  FIG. 13  is summarized in the logic tables of  FIGS. 14 and 15 . As shown in  FIG. 14 , when the control signal CON 0  is Low, the circuit operates in a normal operating mode which may, for example, be the same as that of the conventional memory device already discussed. On the other hand, when the control signal CON 0  is High, the normal operational mode is effectively blocked, and the external control mode is activated. That is, as shown in  FIG. 15 , when CON 0  is High, and CON 1  is Low and CON 2  is High, the isolation control signal PISOL is enabled (High at VCC or VPP 2 ). In contrast, when CON 0  is High, and CON 1  is High and CON 2  is Low, the isolation control signal PISOR is enabled (High at VCC or VPP 2 ). 
   A timing diagram of the normal operational mode (where control signal CON 0  is Low) is illustrated in  FIG. 16 . Initially, in a standby state, signals PBLOCK 1  and PBLOCK 2  are Low (VSS), which means that isolation control signals PISOL and PISOR are at VCC (see the table of  FIG. 6 ). Also, in this state, equalization control signals PEQL and PEQR are held at VCC. 
   Then, block selection signal PBLOCK 1  goes to VCC. Referring to  FIG. 13 , this causes isolation control signal PISOL to go High (VPP) and isolation control signal PISOR to go Low (VSS). As such, the memory array block  1  is connected to the sense amplifier (see  FIG. 2 ), and the memory array block  2  is isolated from the sense amplifier. In addition, equalization control signal PEQL goes Low (VSS), thus deactivating the equalization and pre-charge circuit on the side of the memory array block  1 . 
   Next, the word line signal WL is raised from Low (VSS) to High (VPP). As a result, a charge sharing operation causes the voltage of bit line BL to be raised to VBL+ΔVBL (it is assumed here that a memory cell connected to bit line BL contains a charge representing a data “1”). During this state, the sense interval of the sensing operation occurs as discussed previously. 
   Then, the sense enable voltage LA is increased from VBL to VCC and the sense enable voltage LAB is decreased from VBL to VSS. As such, the voltage of bit line BL becomes VCC and the voltage of bit line BLB becomes VSS. 
   The normal operational mode of  FIG. 16  is the same as that found in the conventional memory device as discussed previously. However, when screening for defective bit lines, it is difficult to discriminate the voltage behavior of defective bit lines from the voltage characteristics resulting from leakage in the sense amplifier circuitry. Accordingly, this embodiment of the present invention is configured to run in the externally controlled operational mode as shown in the timing diagram of  FIG. 17 . 
   Referring to  FIG. 17 , in an initial state, block selection signals PBLOCK 1  and PBLOCK 2  are at VSS (Low), control signal CON 0  is at VSS (Low), control signals CON 1  and CON 2  are at VPP (High), isolation control signals PISOL and PISOR are at VCC, and equalization control signals PEQL and PEQR are at VCC. 
   Then, upon the selection of memory block  1 , the block selection signal PBLOCK 1  goes to VCC, control signal CON 0  goes to VPP, control signal CON 2  goes to VSS, and PISOL goes to VSS. See  FIG. 13 . In this state, referring to  FIG. 2 , the memory block  1  is isolated from the sense amplifier by the isolation transistor (connected to PISOL) on the left side of the sense amplifier region, and the equalization circuit (connected to PEQL) connected ton the left side of the sense amplifier region is deactivated. Further, the sense amplifier is allowed to be pre-charged by the equalization circuit (connected to PEQR) on the right side of the sense amplifier region via the other isolation transistor (connected to PISOR). 
   Next, the word line signal WL is raised from Low (VSS) to High (VPP). As a result, a charge sharing operation causes the voltage of bit line BL of the memory block to be raised to VBL+ΔVBL (it is assumed here that a memory cell connected to bit line BL contains a charge representing a data “1”). Note, however, that since the sense amplifier is isolated from the memory block  1 , the voltage of the bit line BL of the memory block does not fall as a result of leakage of the sense amplifier. This is illustrated in  FIG. 11 , where the bit line BL voltage is maintained until the isolation control signal PISO is increased to a high voltage level. In the meantime, the voltage of the bit line BL at the sense amplifier remains at VBL as shown in  FIG. 17 . 
   After the charge is transferred to the bit line BL in the cell region of the memory block  1 , but prior to enabling of the sense amplifier, the control signal CON 0  goes to VSS (Low) and the control signal CON 2  goes to VPP (High). This causes the isolation control signal PISOL to become VPP (High) and the isolation control signal PISOR to become VSS. As such, again referring to  FIG. 2 , the isolation transistor (connected to PISOL) electrically connects the bit line BL of the memory block  1  to the sense amplifier, and the other isolation transistor (connected to PISOR) electrically isolates the second memory block  2  from the sense amplifier. As such, the memory cell charge previously transferred to the bit line BL of the memory block is further transferred to the sense amplifier. Charge sharing results in an increase of the voltage of the bit line BL in the sense amplifier region to increase to VBL+ΔVBL 2 . Likewise, the voltage of the bit line BL in the cell region of the memory block  1  decreases to VBL+ΔVBL 2 . 
   Next, the sense amplifier is enabled by the sense enable signal LA increasing from VBL to VCC, and by the sense enable signal LAB decreasing from VBL to VSS. As a result, the voltage of the bit line BL becomes VCC, and the voltage of the bit line BLB becomes VSS. 
   The operational mode of  FIG. 17  is at least partially characterized by the delayed activation of the isolation transistor after charge has been transferred to the bit line BL within the memory block  1 . As a result, the amount of time in which the leakage current of the sense amplifier can impact the bit line voltage is substantially reduced. In other words, the short time period between activation of the isolation transistor and enablement of the sense amplifier does not allow for the sense amplifier leakage to be a factor when testing the bit line. 
     FIG. 18  is a diagram of a circuit which may be used to generate the control signals CON 0 , CON 1  and CON 2 , and the sense enable signal SES, and  FIG. 19  is a timing diagram showing the operation of the same. When the first block  1  is selected (i.e., PBLOCK 1  is High, and PBLOCK 2  is Low), and control signal CON 0  becomes High, then CON 1  becomes Low and CON 2  remains High. As a result, node A becomes High. Then, sense enable signal PS goes High and inverted sense enable signal PSB goes Low. Thereafter, when control signal CON 0  goes Low, the control signal CON 1  goes High, causing node A to become Low. Then, after a delay caused by the NOR gate of  FIG. 18 , the sense enable signal SES goes High. This delay corresponds to the timing between the two vertical dashed lines appearing in  FIG. 17 . 
     FIG. 20  is a functional block diagram of the normal operation mode of an embodiment of the present invention. As explained previously, the normal operational mode may be the same as that of the related art. In this case, the address DRA is used to control the PBLOCK signal generation and to enable the word WL. The PBLOCK signals are used to control the isolation control signal PISO generation. In addition, the PBLOCK signals, together with the row active command PR, are used to control the sensing control circuit. The sensing control circuit includes a sensing control block which is responsive to the row active command PR, and a PSA/NSA control circuit that is responsive to the sensing control block. Finally, the bit line sense amplifier BLSA is controlled according to the sense amplification lines LA and LAB, the isolation control signal PISO, and the word line signal WL. 
     FIG. 21  is a functional block diagram of the externally controlled operational mode of an embodiment of the present invention. As illustrated, this mode is similar to that of  FIG. 20 , except that the isolation control signal PISO generation is selectively controlled base on an external control signal received from a PAD or PIN terminal. In addition, the sensing control circuit is selectively controlled according to this external control signal. 
   As described above, embodiments of the present invention delay activation of the isolation transistor until after a memory charge has already been transferred to the bit line within the memory block of the memory cell. As a result, the amount of time in which the leakage current of the sense amplifier can impact the bit line voltage is substantially reduced. The short time period between activation of the isolation transistor and enablement of the sense amplifier does not allow for sense amplifier leakage to be a factor when testing the bit line. 
   In addition, embodiments of the present invention include an external pad terminal or pin terminal control of the isolation control signal. This allows for user-friendly isolation and sensing control. 
   Although the present invention has been described above in connection with the preferred embodiments thereof, the present invention is not so limited. Rather, various changes to and modifications of the preferred embodiments will become readily apparent to those of ordinary skill in the art. Accordingly, the present invention is not limited to the preferred embodiments described above. Rather, the true spirit and scope of the invention is defined by the accompanying claims.
A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.