CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation, under 35 U.S.C. §120, of copending international application No. PCT/JP2013/070588, filed Jul. 30, 2013, which designated the United States; the prior application is herewith incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor integrated circuits have recently become larger in scale. As for the leading-edge micro-processing units (MPUs), a semiconductor chip including as many as one giga transistors has been developed. In a so-called planar transistor according to the related art, an n-well region that forms PMOS and a p-type silicon substrate (or p-well region) that forms NMOS need to be completely isolated from each other, as described in “CMOS OP anpu kairo jitsumu sekkei no kiso,” written by Yoshizawa Hirokazu, CQ Publishing, page 23. Each of the n-well region and the p-type silicon substrate needs a body terminal for applying a potential thereto, which increases the area. 
         [0006]    To approach this issue, a surrounding gate transistor (SGT) has been suggested in which a source, gate, and drain are disposed in the vertical direction relative to a substrate, and the gate surrounds an island-shaped semiconductor layer. A method for manufacturing the SGT, and a CMOS inverter, NAND circuit, or SRAM cell using the SGT have been disclosed in, for example, Japanese Patent No. 5130596, Japanese Patent No. 5031809, Japanese Patent No. 4756221, and International Publication WO2009/096465. 
         [0007]      FIG. 17  is a circuit diagram of an inverter using SGTs, and  FIGS. 18A and 18B  are layout diagrams of the inverter. 
         [0008]      FIG. 17  is a circuit diagram of the inverter. Qp denotes a p-channel MOS transistor (hereinafter referred to as a PMOS transistor), Qn denotes an n-channel MOS transistor (hereinafter referred to as an NMOS transistor), IN denotes an input signal, OUT denotes an output signal, Vcc denotes a power supply voltage, and Vss denotes a reference voltage. 
         [0009]      FIG. 18A  illustrates, as an example, a plan view of the layout of the inverter illustrated in  FIG. 17  including SGTs.  FIG. 18B  illustrates a cross-sectional view taken along a cut line A-A′ in the plan view in  FIG. 18A . 
         [0010]    Referring to  FIGS. 18A and 18B , planar silicon layers  2   p  and  2   n  are disposed on an insulating film, such as a buried oxide (BOX) layer disposed on a substrate. The planar silicon layers  2   p  and  2   n  are formed of a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like.  3  denotes a silicide layer disposed on surfaces of the planar silicon layers  2   p  and  2   n , which connects the planar silicon layers  2   p  and  2   n  to each other.  4   n  denotes an n-type  silicon pillar;  4   p  denotes a p-type silicon pillar;  5  denotes a gate insulating film surrounding the n-type silicon pillar  4   n  and the p-type silicon pillar  4   p;    6  denotes a gate electrode; and  6   a  denotes a gate line. A p+ diffusion layer  7   p  and an n+ diffusion layer  7   n  are formed at the tops of the n-type silicon pillar  4   n  and the p-type silicon pillar  4   p,  respectively, through impurity implantation or the like.  8  denotes a silicon nitride film for protecting the gate insulating film  5  and so forth;  9   p  and  9   n  denote silicide layers connected to the p+ diffusion layer  7   p  and the n+ diffusion layer  7   n,  respectively;  10   p  and  10   n  denote contacts that connect the silicide layers  9   p  and  9   n  to metal lines  13   a  and  13   b;  and  11  denotes a contact that connects the gate line  6   a  and a metal line  13   c  to each other. 
         [0011]    The n-type silicon pillar  4   n,  the planar silicon layer  2   p,  the p+ diffusion layer  7   p,  the gate insulating film  5 , and the gate electrode  6  constitute the PMOS transistor Qp. The p-type silicon pillar  4   p,  the planar silicon layer  2   n,  the n+ diffusion layer  7   n,  the gate insulating film  5 , and the gate electrode  6  constitute the NMOS transistor Qn. The p+ diffusion layer  7   p  and the n+ diffusion layer  7   n  serve as a source, and the planar silicon layers  2   p  and  2   n  serve as a drain. The power supply voltage Vcc is supplied to the metal line  13   a,  the reference voltage Vss is supplied to the metal line  13   b,  and the input signal IN is connected to the metal line  13   c.  The silicide layer  3  that connects the planar silicon layer  2   p  of the PMOS transistor Qp and the planar silicon layer  2   n  of the NMOS transistor Qn corresponds to the output OUT. 
         [0012]    In the inverter using SGTs illustrated in  FIGS. 17 ,  18 A, and  18 B, the PMOS transistor and the NMOS transistor are completely isolated from each other in the structure, and thus well isolation is not necessary unlike in a planar transistor. Further, the silicon pillars serve as floating bodies, and thus a body terminal for supplying a potential to the wells is not necessary unlike in a planar transistor. Accordingly, a very compact layout (arrangement) is realized. 
         [0013]    As described above, the greatest feature of an SGT is that, in terms of a structural principle, a lower line formed of a silicide layer existing on a substrate side relative to a silicon pillar and an upper line connected to a contact at an upper portion of the silicon pillar can be used. 
       SUMMARY OF THE INVENTION 
       [0014]    An object of the present invention is to provide a low-cost logic semiconductor device by minimizing the area of the device by arranging two-input NAND circuits that are used most often in a logic circuit in a line to realize a compact arrangement by utilizing the feature of an SGT. 
         [0015]    According to an aspect of the present invention, there is provided a semiconductor device including a NAND circuit including four transistors that are arranged in a line on a substrate. A source, a drain, and a gate of each of the four transistors are hierarchically disposed in a direction perpendicular to the substrate. Each of the four transistors includes a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region disposed at an upper portion or lower portion of the silicon pillar, and a drain region disposed at the upper portion or lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar. The four transistors include a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor, and a second n-channel MOS transistor. The gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to each other. The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars. The source region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a silicide region. The source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to each other via a contact. The source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact. The source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a silicide region. 
         [0016]    The four transistors may be arranged in a line in order of the first n-channel MOS transistor, the first p-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor. 
         [0017]    The four transistors may be arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor. 
         [0018]    The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor may be connected to each other via a contact. 
         [0019]    The four transistors may be arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor. 
         [0020]    According to another aspect of the present invention, there is provided a semiconductor device including a NAND circuit including four transistors that are arranged in a line on a substrate. A source, a drain, and a gate of each of the four transistors are hierarchically disposed in a direction perpendicular to the substrate. Each of the four transistors includes a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region disposed at an upper portion or lower portion of the silicon pillar, and a drain region disposed at the upper portion or lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar. The four transistors include a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor, and a second n-channel MOS transistor. The gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to each other. The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, the drain region of the first n-channel MOS transistor, and the drain region of the second n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are connected to one another via a silicide region. The source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to each other via a contact and a silicide region. The source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact. The source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact. 
         [0021]    The four transistors may be arranged in a line in order of the first n-channel MOS transistor, the first p-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor. 
         [0022]    The four transistors may be arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor. 
         [0023]    The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor may be connected to each other via a contact. 
         [0024]    According to another aspect of the present invention, there is provided a semiconductor device including a NAND circuit including four transistors that are arranged in a line on a substrate. A source, a drain, and a gate of each of the four transistors are hierarchically disposed in a direction perpendicular to the substrate. Each of the four transistors includes a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region disposed at an upper portion or lower portion of the silicon pillar, and a drain region disposed at the upper portion or lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar. The four transistors include a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor, and a second n-channel MOS transistor. The gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to each other. The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars. The source region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a silicide region. The source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to each other via a contact and a silicide region. The source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a contact. The source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact. The four transistors are arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second p-channel MOS transistor, and the second n-channel MOS transistor. 
         [0025]    According to another aspect of the present invention, there is provided a semiconductor device including a NAND circuit including four transistors that are arranged in a line on a substrate. A source, a drain, and a gate of each of the four transistors are hierarchically disposed in a direction perpendicular to the substrate. Each of the four transistors includes a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region disposed at an upper portion or lower portion of the silicon pillar, and a drain region disposed at the upper portion or lower portion of the silicon pillar and disposed on an opposite side of the source region relative to the silicon pillar. The four transistors include a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor, and a second n-channel MOS transistor. The gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor are connected to each other. The gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor are connected to each other. The source region of the first p-channel MOS transistor, the source region of the second p-channel MOS transistor, and the source region of the first n-channel MOS transistor are disposed on a side of the substrate relative to the silicon pillars. The drain region of the second n-channel MOS transistor is disposed on the side of the substrate relative to the silicon pillar. The drain region of the first p-channel MOS transistor, the drain region of the second p-channel MOS transistor, and the drain region of first n-channel MOS transistor are connected to one another via a contact. The source region of the first n-channel MOS transistor and the drain region of the second n-channel MOS transistor are connected to each other via a silicide region. The source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor are connected to a power supply terminal via a silicide region. The source region of the second n-channel MOS transistor is connected to a reference power supply terminal via a contact. 
         [0026]    The four transistors may be arranged in a line in order of the first p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the second p-channel MOS transistor. 
         [0027]    The source region of the first p-channel MOS transistor and the source region of the second p-channel MOS transistor may be connected to the power supply terminal via a silicide region and a contact, the silicide region extending in a direction perpendicular to a direction in which the four transistors are arranged in a line. 
         [0028]    The NAND circuit may be one of a plurality of NAND circuits that are arranged in a direction perpendicular to the direction in which the four transistors are arranged in a line. The extended silicide regions are connected to one another, and one of the plurality of NAND circuits is connected to the power supply terminal via the extended silicide regions and a contact. 
         [0029]    The four transistors may be arranged in a line in order of the second p-channel MOS transistor, the first p-channel MOS transistor, the first n-channel MOS transistor, and the second n-channel MOS transistor. 
         [0030]    A gate line of the second p-channel MOS transistor and a gate line of the second n-channel MOS transistor may be supplied with signals through different signal lines via contacts. 
         [0031]    Other features which are considered as characteristic for the invention are set forth in the appended claims. 
         [0032]    Although the invention is illustrated and described herein as embodied in a semiconductor device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
         [0033]    The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0034]      FIG. 1  is a first equivalent circuit diagram illustrating a NAND circuit according to an embodiment of the present invention. 
           [0035]      FIG. 2A  is a plan view of a NAND circuit according to a first embodiment of the present invention. 
           [0036]      FIG. 2B  is a cross-sectional view of the NAND circuit according to the first embodiment of the present invention. 
           [0037]      FIG. 3A  is a plan view of a NAND circuit according to a second embodiment of the present invention. 
           [0038]      FIG. 3B  is a cross-sectional view of the NAND circuit according to the second embodiment of the present invention. 
           [0039]      FIG. 4A  is a plan view of a NAND circuit according to a third embodiment of the present invention. 
           [0040]      FIG. 4B  is a cross-sectional view of the NAND circuit according to the third embodiment of the present invention. 
           [0041]      FIG. 5A  is a plan view of a NAND circuit according to a fourth embodiment of the present invention. 
           [0042]      FIG. 5B  is a cross-sectional view of the NAND circuit according to the fourth embodiment of the present invention. 
           [0043]      FIG. 6A  is a plan view of a NAND circuit according to a fifth embodiment of the present invention. 
           [0044]      FIG. 6B  is a cross-sectional view of the NAND circuit according to the fifth embodiment of the present invention. 
           [0045]      FIG. 7A  is a plan view of a NAND circuit according to a sixth embodiment of the present invention. 
           [0046]      FIG. 7B  is a cross-sectional view of the NAND circuit according to the sixth embodiment of the present invention. 
           [0047]      FIG. 8  is a second equivalent circuit diagram illustrating the NAND circuit according to the embodiment of the present invention. 
           [0048]      FIG. 9A  is a plan view of a NAND circuit according to a seventh embodiment of the present invention. 
           [0049]      FIG. 9B  is a cross-sectional view of the NAND circuit according to the seventh embodiment of the present invention. 
           [0050]      FIG. 10A  is a plan view of a NAND circuit according to an eighth embodiment of the present invention. 
           [0051]      FIG. 10B  is a cross-sectional view of the NAND circuit according to the eighth embodiment of the present invention. 
           [0052]      FIG. 11A  is a plan view of a NAND circuit according to a ninth embodiment of the present invention. 
           [0053]      FIG. 11B  is a cross-sectional view of the NAND circuit according to the ninth embodiment of the present invention. 
           [0054]      FIG. 11C  is a cross-sectional view of the NAND circuit according to the ninth embodiment of the present invention. 
           [0055]      FIG. 12A  is a plan view of a NAND circuit according to a tenth embodiment of the present invention. 
           [0056]      FIG. 12B  is a cross-sectional view of the NAND circuit according to the tenth embodiment of the present invention. 
           [0057]      FIG. 12C  is a cross-sectional view of the NAND circuit according to the tenth embodiment of the present invention. 
           [0058]      FIG. 13A  is a plan view of a NAND circuit according to an eleventh embodiment of the present invention. 
           [0059]      FIG. 13B  is a cross-sectional view of the NAND circuit according to the eleventh embodiment of the present invention. 
           [0060]      FIG. 14  is a third equivalent circuit diagram illustrating the NAND circuit according to the embodiment of the present invention. 
           [0061]      FIG. 15A  is a plan view of a NAND circuit according to a twelfth embodiment of the present invention. 
           [0062]      FIG. 15B  is a cross-sectional view of the NAND circuit according to the twelfth embodiment of the present invention. 
           [0063]      FIG. 16A  is a plan view of a NAND circuit according to another embodiment of the present invention. 
           [0064]      FIG. 16B  is a cross-sectional view of the NAND circuit according to the other embodiment of the present invention. 
           [0065]      FIG. 17  is an equivalent circuit diagram of an inverter according to the prior art. 
           [0066]      FIG. 18A  is a plan view of the inverter according to the prior art. 
           [0067]      FIG. 18B  is a cross-sectional view of the inverter according to the prior art. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     First Embodiment  
       [0068]      FIG. 1  is an equivalent circuit diagram of a two-input NAND circuit applied to the present invention. Qp 1  and Qp 2  denote PMOS transistors each constituted by an SGT, and Qn 1  and Qn 2  denote NMOS transistors each constituted by an SGT. The sources of the PMOS transistors Qp 1  and Qp 2  are connected to a common power supply voltage Vcc, and the drains thereof are connected to a common node N 1 . The drain of the NMOS transistor Qn 1  is connected to the node N 1 , the source thereof is connected to the drain of the NMOS transistor Qn 2  via a node N 2 , and the source of the NMOS transistor Qn 2  is connected to a reference voltage Vss. An input signal IN 1  is connected to the gates of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 , and an input signal IN 2  is connected to the gates of the PMOS transistor Qp 2  and the NMOS transistor Qn 2 . 
         [0069]      FIGS. 2A and 2B  illustrate a first embodiment.  FIG. 2A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 2B  is a cross-sectional view taken along a cut line A-A′. 
         [0070]    Referring to  FIG. 2A , the NMOS transistor Qn 1 , the PMOS transistor Qp 1 , the PMOS transistor Qp 2 , and the NMOS transistor Qn 2  of the NAND circuit illustrated in  FIG. 1  are arranged in a line from the right. In  FIGS. 2A and 2B , the components having the same structure as that in  FIGS. 18A and 18B  are denoted by equivalent reference numerals in the 100s. 
         [0071]    Planar silicon layers  102   na ,  102   p,  and  102   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  101  disposed on a substrate. The planar silicon layers  102   na ,  102   p,  and  102   nb  are formed of an n+ diffusion layer, a p+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  103  denotes a silicide layer disposed on surfaces of the planar silicon layers  102   na ,  102   p,  and  102   nb , which connects the planar silicon layers  102   na  and  102   p  to each other.  104   n   1  and  104   n   2  denote n-type silicon pillars;  104   p   1  and  104   p   2  denote p-type silicon pillars;  105  denotes a gate insulating film surrounding the silicon pillars  104   n   1 ,  104   n   2 ,  104   p   1 , and  104   p   2 ;  106  denotes a gate electrode; and  106   a  and  106   b  denote gate lines. P+ diffusion layers  107   p   1  and  107   p   2  are formed at the tops of the n-type silicon pillars  104   n   1  and  104   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  107   n   1  and  107   n   2  are formed at the tops of the p-type silicon pillars  104   p   1  and  104   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  108  denotes a silicon nitride film for protecting the gate insulating film  105 ;  109   p   1 ,  109   p   2 ,  109   n   1 , and  109   n   2  denote silicide layers connected to the p+ diffusion layers  107   p   1  and  107   p   2  and the n+ diffusion layers  107   n   1  and  107   n   2 , respectively;  110   p   1 ,  110   p   2 ,  110   n   1 , and  110   n   2  denote contacts that connect the silicide layers  109   p   1 ,  109   p   2 ,  109   n   1 , and  109   n   2  to first metal lines  113   c,    113   c,    113   a,  and  113   e , respectively;  111   a  denotes a contact that connects the gate line  106   a  and a first metal line  113   b  to each other; and  111  b denotes a contact that connects the gate line  106   b  and a first metal line  113   d  to each other.  112  denotes a contact that connects the silicide layer  103  connected to the planar silicon layer  102   nb  and a first metal line  113   f  to each other.  114   n   1  denotes a contact that connects the first metal line  113   a  and a second metal line  115  to each other; and  114   n   2  denotes a contact that connects the first metal line  113   e  and the second metal line  115  to each other. 
         [0072]    The n-type silicon pillar  104   n   1 , the planar silicon layer  102   p,  the p+ diffusion layer  107   p   1 , the gate insulating film  105 , and the gate electrode  106  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  104   n   2 , the planar silicon layer  102   p,  the p+ diffusion layer  107   p   2 , the gate insulating film  105 , and the gate electrode  106  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  104   p   1 , the planar silicon layer  102   na , the n+ diffusion layer  107   n   1 , the gate insulating film  105 , and the gate electrode  106  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  104   p   2 , the planar silicon layer  102   nb , the n+ diffusion layer  107   n   2 , the gate insulating film  105 , and the gate electrode  106  constitute the NMOS transistor Qn 2 . 
         [0073]    The gate line  106   a  is connected to the gate electrode  106  of the PMOS transistor Qp 1 . The gate line  106   b  is connected to the gate electrode  106  of the PMOS transistor Qp 2 . The gate line  106   a  is connected to the gate electrode  106  of the NMOS transistor Qn 1 . The gate line  106   b  is connected to the gate electrode  106  of the NMOS transistor Qn 2 . 
         [0074]    The planar silicon layers  102   na and  102   p  serve as a common drain of the NMOS transistor Qn 1  and the PMOS transistors Qp 1  and Qp 2 , and are connected to an output OUT 1 . The p+ diffusion layer  107   p   1 , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  113   c  via the silicide layer  109   p   1  and the contact  110   p   1 , and the power supply voltage Vcc is supplied to the first metal line  113   c.  The p+ diffusion layer  107   p   2 , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  113   c  via the silicide layer  109   p   2  and the contact  110   p   2 . The n+ diffusion layer  107   n   1 , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  113   a  via the silicide layer  109   n   1  and the contact  110   n   1 , and the first metal line  113   a  is connected to the second metal line  115  via the contact  114   n   1 . The n+ diffusion layer  107   n   2 , which serves as the drain of the NMOS transistor Qn 2 , is connected to the first metal line  113   e  via the silicide layer  109   n   2  and the contact  110   n   2 , and the first metal line  113   e  is connected to the second metal line  115  via the contact  114   n   2 . Here, the source of the NMOS transistor Qn 1  and the drain of the NMOS transistor Qn 2  are connected to each other via the second metal line  115 . The planar silicon layer  102   nb  serves as the source of the NMOS transistor Qn 2  and is connected to the first metal line  113   f  via the silicide layer  103  and the contact  112 . The reference voltage Vss is supplied to the first metal line  113   f.    
         [0075]    The input signal IN 1  is supplied to the first metal line  113   b,  is supplied to the gate line  106   a  via the contact  111   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  113   d,  is supplied to the gate line  106   b  via the contact  111   b , and is supplied to the gate electrodes of the PMOS transistor Qp 2  and the NMOS transistor Qn 2 . 
         [0076]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
       Second Embodiment  
       [0077]      FIGS. 3A and 3B  illustrate a second embodiment.  FIG. 3A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 3B  is a cross-sectional view taken along a cut line A-A′. 
         [0078]    Referring to  FIG. 3A , the PMOS transistors Qp 2  and Qp 1  and the NMOS transistors Qn 1  and Qn 2  of the NAND circuit illustrated in  FIG. 1  are arranged in a line from the right. In  FIGS. 3A and 3B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 200s. 
         [0079]    Planar silicon layers  202   p,    202   na , and  202   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  201  disposed on a substrate. The planar silicon layers  202   p,    202   na , and  202   nb  are formed of a p+ diffusion layer, an n+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  203  denotes a silicide layer disposed on surfaces of the planar silicon layers  202   p,    202   na , and  202   nb , which connects the planar silicon layers  202   p  and  202   na  to each other.  204   n   1  and  204   n   2  denote n-type silicon pillars;  204   p   1  and  204   p   2  denote p-type silicon pillars;  205  denotes a gate insulating film surrounding the silicon pillars  204   n   1 ,  204   n   2 ,  204   p   1 , and  204   p   2 ;  206  denotes a gate electrode; and  206   a,    206   b,  and  206   c  denote gate lines. P+ diffusion layers  207   p   1  and  207   p   2  are formed at the tops of the n-type silicon pillars  204   n   1  and  204   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  207   n   1  and  207   n   2  are formed at the tops of the p-type silicon pillars  204   p   1  and  204   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  208  denotes a silicon nitride film for protecting the gate insulating film  205 ;  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  denote silicide layers connected to the p+ diffusion layers  207   p   1  and  207   p   2  and the n+ diffusion layers  207   n   1  and  207   n   2 , respectively;  210   p   1 ,  210   p   2 ,  210   n   1 , and  210   n   2  denote contacts that connect the silicide layers  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  to first metal lines  213   b,    213   b ,  213   d,  and  213   d,  respectively;  211   a  denotes a contact that connects the gate line  206   a  and a first metal line  213   c  to each other; and  211   c  denotes a contact that connects the gate line  206   c  and a first metal line  213   e  to each other.  212  denotes a contact that connects the silicide layer  203  connected to the planar silicon layer  202   nb  and a first metal line  213   f  to each other. The gate line  206   b  is a line that connects the gate electrode  206  of the PMOS transistor Qp 2  and the gate electrode  206  of the NMOS transistor Qn 2  to each other, which will be described below. 
         [0080]    The n-type silicon pillar  204   n   1 , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   1 , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  204   n   2 , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   2 , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  204   p   1 , the planar silicon layer  202   na , the n+ diffusion layer  207   n   1 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  204   p   2 , the planar silicon layer  202   nb , the n+ diffusion layer  207   n   2 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 2 . 
         [0081]    The gate line  206   a  is connected to the gate electrode  206  of the PMOS transistor Qp 1 . The gate line  206   b  is connected to the gate electrode  206  of the PMOS transistor Qp 2 . The gate line  206   a  is connected to the gate electrode  206  of the NMOS transistor Qn 1 . The gate lines  206   b  and  206   c  are connected to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0082]    The planar silicon layers  202   p  and  202   na serve as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1 , and are connected to an output OUT 1 . The p+ diffusion layer  207   p   1 , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  213   b  via the silicide layer  209   p   1  and the contact  210   p   1 , and the power supply voltage Vcc is supplied to the first metal line  213   b.  The p+ diffusion layer  207   p   2 , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  213   b  via the silicide layer  209   p   2  and the contact  210   p   2 . The n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  213   d  via the silicide layer  209   n   1  and the contact  210   n   1 . 
         [0083]    The n+ diffusion layer  207   n   2 , which serves as the drain of the NMOS transistor Qn 2 , is connected to the first metal line  213   d  via the silicide layer  209   n   2  and the contact  210   n   2 . Here, the n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , and the n+ diffusion layer  207   n   2 , which serves as the drain of the NMOS transistor Qn 2 , are connected to each other via the first metal line  213   d.  The planar silicon layer  202   nb  serves as the source of the NMOS transistor Qn 2 , and is connected to the first metal line  213   f  via the silicide layer  203  and the contact  212 . The reference voltage Vss is supplied to the first metal line  213   f.    
         [0084]    The input signal IN 1  is supplied to the first metal line  213   c,  is supplied to the gate line  206   a  via the contact  211   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to first metal line  213   e,  is supplied to the gate line  206   c  via the contact  211   c , and is supplied to the gate electrode of the NMOS transistor Qn 2 . Also, the input signal IN 2  is supplied to the gate electrode of the PMOS transistor Qp 2  via the gate line  206   b.  In this embodiment, the gate electrodes of the NMOS transistor Qn 2  and the PMOS transistor Qp 2  are connected to each other by using the extended gate line  206   b  in order to omit a metal line. However, the gate line  206   b  extends between diffusion layers in a free region, and thus an increase in the area does not occur. 
         [0085]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. Further, with the gate line  206   b  being extended, connections can be made using only the first metal lines, and thus the second metal line can be effectively used. Further, the first metal line  213   b  for the power supply voltage Vcc is disposed at the right end and the first metal line  213   f  for the reference voltage Vss is disposed at the left end. Accordingly, the power supply can be shared in a case where a plurality of circuits are arranged side by side, and thus the area can be further reduced. 
       Third Embodiment  
       [0086]      FIGS. 4A and 4B  illustrate a third embodiment.  FIG. 4A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 4B  is a cross-sectional view taken along a cut line A-A′. 
         [0087]    The arrangement of the transistors illustrated in  FIGS. 4A and 4B  is the same as that illustrated in  FIGS. 3A and 3B , that is, the PMOS transistors Qp 2  and Qp 1  and the NMOS transistors Qn 1  and Qn 2  are arranged in a line from the right. A difference from  FIGS. 3A and 3B  is a connection method for a gate input signal between the PMOS transistor Qp 2  and the NMOS transistor Qn 2 . In  FIGS. 4A and 4B , the components having the same structure as that in  FIGS. 3A and 3B  are denoted by equivalent reference numerals in the 200s. 
         [0088]    Planar silicon layers  202   p,    202   na , and  202   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  201  disposed on a substrate. The planar silicon layers  202   p,    202   na , and  202   nb  are formed of a p+ diffusion layer, an n+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  203  denotes a silicide layer disposed on surfaces of the planar silicon layers  202   p,    202   na , and  202   nb , which connects the planar silicon layers  202   p  and  202   na  to each other.  204   n   1  and  204   n   2  denote n-type silicon pillars;  204   p   1  and  204   p   2  denote p-type silicon pillars;  205  denotes a gate insulating film surrounding the silicon pillars  204   n   1 ,  204   n   2 ,  204   p   1 , and  204   p   2 ;  206  denotes a gate electrode; and  206   a,    206   b,  and  206   c  denote gate lines. P+ diffusion layers  207   p   1  and  207   p   2  are formed at the tops of the n-type silicon pillars  204   n   1  and  204   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  207   n   1  and  207   n   2  are formed at the tops of the p-type silicon pillars  204   p   1  and  204   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  208  denotes a silicon nitride film for protecting the gate insulating film  205 ;  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  denote silicide layers connected to the p+ diffusion layers  207   p   1  and  207   p   2  and the n+ diffusion layers  207   n   1  and  207   n   2 , respectively;  210   p   1 ,  210   p   2 ,  210   n   1 , and  210   n   2  denote contacts that connect the silicide layers  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  to first metal lines  213   b,    213   b ,  213   d,  and  213   d,  respectively;  211   a  denotes a contact that connects the gate line  206   a  and a first metal line  213   c  to each other;  211   b  denotes a contact that connects the gate line  206   b  and a first metal line  213   a  to each other; and  211   c  denotes a contact that connects the gate line  206   c  and a first metal line  213   e  to each other.  214   b  denotes a contact that connects the first metal line  213   a  and a second metal line  215  to each other; and  214   c  denotes a contact that connects the first metal line  213   e  and the second metal line  215  to each other.  212  denotes a contact that connects the silicide layer  203  connected to the planar silicon layer  202   nb  and a first metal line  213   f  to each other. 
         [0089]    The n-type silicon pillar  204   n   1 , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   1 , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  204   n   2 , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   2 , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  204   p   1 , the planar silicon layer  202   na , the n+ diffusion layer  207   n   1 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  204   p   2 , the planar silicon layer  202   nb , the n+ diffusion layer  207   n   2 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 2 . 
         [0090]    The gate line  206   a  is connected to the gate electrode  206  of the PMOS transistor Qp 1 . The gate line  206   b  is connected to the gate electrode  206  of the PMOS transistor Qp 2 . The gate line  206   a  is connected to the gate electrode  206  of the NMOS transistor Qn 1 . The gate line  206   c  is connected to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0091]    The planar silicon layers  202   p  and  202   na  serve as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1 , and are connected to an output OUT 1 . The p+ diffusion layer  207   p   1 , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  213   b  via the silicide layer  209   p   1  and the contact  210   p   1 , and the power supply voltage Vcc is supplied to the first metal line  213   b.  The p+ diffusion layer  207   p   2 , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  213   b  via the silicide layer  209   p   2  and the contact  210   p   2 . The n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  213   d  via the silicide layer  209   n   1  and the contact  210   n   1 . 
         [0092]    The n+ diffusion layer  207   n   2 , which serves as the drain of the NMOS transistor Qn 2 , is connected to the first metal line  213   d  via the silicide layer  209   n   2  and the contact  210   n   2 . Here, the source of the NMOS transistor Qn 1  and the drain of the NMOS transistor Qn 2  are connected to each other via the first metal line  213   d.  The planar silicon layer  202   nb  serves as the source of the NMOS transistor Qn 2  and is connected to the first metal line  213   f  via the silicide layer  203  and the contact  212 . The reference voltage Vss is supplied to the first metal line  213   f.    
         [0093]    The input signal IN 1  is supplied to the first metal line  213   c,  is supplied to the gate line  206   a  via the contact  211   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  213   a,  is supplied to the gate line  206   b  via the contact  211   b , and is supplied to the gate electrode  206  of the PMOS transistor Qp 2 . Also, the input signal IN 2  is supplied to the second metal line  215  via the contact  214   b,  is supplied to the gate line  206   c  via the contact  214   c,  the first metal line  213   e,  and the contact  211   c , and is supplied to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0094]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. Further, with use of the second metal line, the gate line  206   b  according to the second embodiment can be omitted. 
       Fourth Embodiment 
       [0095]      FIGS. 5A and 5B  illustrate a fourth embodiment.  FIG. 5A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 5B  is a cross-sectional view taken along a cut line A-A′. 
         [0096]    The arrangement of the transistors illustrated in  FIGS. 5A and 5B  is the same as that illustrated in  FIGS. 2A and 2B , that is, the NMOS transistor Qn 1 , the PMOS transistors Qp 1  and Qp 2 , and the NMOS transistor Qn 2  are arranged in a line from the right. A difference from  FIGS. 2A and 2B  is that the connection of the source and drain of the NMOS transistor Qn 2  is changed. In  FIGS. 5A and 5B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 100s. 
         [0097]    In an SGT, the drain and source are located in a lower layer portion and an upper layer portion, respectively, and the physical positions thereof are different. The drain and source are made so as to be as equivalent as possible, but the orientations of the drain and source are different and thus both of them may have different current characteristics in some cases. The present invention addresses this issue. 
         [0098]    Planar silicon layers  102   na ,  102   p,  and  102   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  101  disposed on a substrate. The planar silicon layers  102   na ,  102   p,  and  102   nb  are formed of an n+ diffusion layer, a p+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  103  denotes a silicide layer disposed on surfaces of the planar silicon layers  102   na ,  102   p,  and  102   nb  , which connects the planar silicon layers  102   na and  102   p  to each other.  104   n   1  and  104   n   2  denote n-type silicon pillars;  104   p   1  and  104   p   2  denote p-type silicon pillars;  105  denotes a gate insulating film surrounding the silicon pillars  104   n   1 ,  104   n   2 ,  104   p   1 , and  104   p   2 ;  106  denotes a gate electrode; and  106   a  and  106   b  denote gate lines. P+ diffusion layers  107   p   1  and  107   p   2  are formed at the tops of the n-type silicon pillars  104   n   1  and  104   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  107   n   1  and  107   n   2  are formed at the tops of the p-type silicon pillars  104   p   1  and  104   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  108  denotes a silicon nitride film for protecting the gate insulating film  105 ;  109   p   1 ,  109   p   2 ,  109   n   1 , and  109   n   2  denote silicide layers connected to the p+ diffusion layers  107   p   1  and  107   p   2  and the n+ diffusion layers  107   n   1  and  107   n   2  , respectively;  110   p   1 ,  110   p   2 ,  110   n   1 , and  110   n   2  denote contacts that connect the silicide layers  109   p   1 ,  109   p   2 ,  109   n   1 , and  109   n   2  to first metal lines  113   c,    113   c,    113   a,  and  113   e , respectively;  111   a  denotes a contact that connects the gate line  106   a  and a first metal line  113   b  to each other; and  111   b  denotes a contact that connects the gate line  106   b  and a first metal line  113   d  to each other.  112  denotes a contact that connects the silicide layer  103  connected to the planar silicon layer  102   nb  and a first metal line  113   f  to each other.  114   n   1  denotes a contact that connects the first metal line  113   a  and a second metal line  115  to each other; and  114  denotes a contact that connects the first metal line  113   f  and the second metal line  115  to each other. 
         [0099]    The n-type silicon pillar  104   n   1 , the planar silicon layer  102   p,  the p+ diffusion layer  107   p   1  , the gate insulating film  105 , and the gate electrode  106  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  104   n   2 , the planar silicon layer  102   p,  the p+ diffusion layer  107   p   2  , the gate insulating film  105 , and the gate electrode  106  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  104   p   1 , the planar silicon layer  102   na , the n+ diffusion layer  107   n   1  , the gate insulating film  105 , and the gate electrode  106  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  104   p   2 , the planar silicon layer  102   nb  , the n+ diffusion layer  107   n   2  , the gate insulating film  105 , and the gate electrode  106  constitute the NMOS transistor Qn 2 . 
         [0100]    The gate line  106   a  is connected to the gate electrode  106  of the PMOS transistor Qp 1 . The gate line  106   b  is connected to the gate electrode  106  of the PMOS transistor Qp 2 . The gate line  106   a  is connected to the gate electrode  106  of the NMOS transistor Qn 1 . The gate line  106   b  is connected to the gate electrode  106  of the NMOS transistor Qn 2 . 
         [0101]    The planar silicon layers  102   na and  102   p  serve as a common drain of the NMOS transistor Qn 1  and the PMOS transistors Qp 1  and Qp 2 , and are connected to an output OUT 1 . The p+ diffusion layer  107   p   1  , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  113   c  via the silicide layer  109   p   1  and the contact  110   p   1 , and the power supply voltage Vcc is supplied to the first metal line  113   c.  The p+ diffusion layer  107   p   2  , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  113   c  via the silicide layer  109   p   2  and the contact  110   p   2 . The n+ diffusion layer  107   n   1  , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  113   a  via the silicide layer  109   n   1  and the contact  110   n   1 , and the first metal line  113   a  is connected to the second metal line  115  via the contact  114   n   1 . The planar silicon layer  102   nb  , which serves as the drain of the NMOS transistor Qn 2 , is connected to the second metal line  115  via the silicide layer  103 , the contact  112 , the first metal line  113   f,  and the contact  114 , and the n+ diffusion layer  107   n   1  , which serves as the source of the NMOS transistor Qn 1 , and the planar silicon layer  102   nb  , which serves as the drain of the NMOS transistor Qn 2 , are connected to each other via the second metal line  115 . The n+ diffusion layer  107   n   2  , which serves as the source of the NMOS transistor Qn 2 , is connected to the first metal line  113   e  via the silicide layer  109   n   2  and the contact  110   n   2 , and the reference voltage Vss is supplied to the first metal line  113   e.  With such connections, the orientations of the drains and sources of the NMOS transistors Qn 1  and Qn 2  can be the same, that is, the directions in which currents flow therethrough can be the same, and accordingly the same current characteristic can be obtained. 
         [0102]    The input signal IN 1  is supplied to the first metal line  113   b,  is supplied to the gate line  106   a  via the contact  111   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  113   d,  is supplied to the gate line  106   b  via the contact  111   b , and is supplied to the gate electrodes of the PMOS transistor Qp 2  and the NMOS transistor Qn 2 . 
         [0103]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. Further, the current flow directions of the NMOS transistor Qn 1  and the NMOS transistor Qn 2  (the orientations of the drains and sources) can be the same. Accordingly, the same current characteristic can be obtained and a favorable characteristic can be obtained. 
       Fifth Embodiment  
       [0104]      FIGS. 6A and 6B  illustrate a fifth embodiment.  FIG. 6A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 6B  is a cross-sectional view taken along a cut line A-A′. 
         [0105]    The arrangement of the transistors illustrated in  FIGS. 6A and 6B  is the same as that illustrated in  FIGS. 3A and 3B , that is, the PMOS transistors Qp 2  and Qp 1  and the NMOS transistors Qn 1  and Qn 2  are arranged in a line from the right. A difference from  FIGS. 3A and 3B  is that the connection of the source and drain of the NMOS transistor Qn 2  is changed. In  FIGS. 6A and 6B , the components having the same structure as that in  FIGS. 3A and 3B  are denoted by equivalent reference numerals in the 200s. 
         [0106]    In an SGT, the drain and source are located in a lower layer portion and an upper layer portion, respectively, and the physical positions thereof are different. The drain and source are made so as to be as equivalent as possible, but the orientations of the drain and source are different and thus both of them may have different current characteristics in some cases. The present invention addresses this issue. 
         [0107]    Planar silicon layers  202   p,    202   na , and  202   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  201  disposed on a substrate. The planar silicon layers  202   p,    202   na , and  202   nb  are formed of a p+ diffusion layer, an n+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  203  denotes a silicide layer disposed on surfaces of the planar silicon layers  202   p,    202   na , and  202   nb  , which connects the planar silicon layers  202   p  and  202   na to each other.  204   n   1  and  204   n   2  denote n-type silicon pillars;  204   p   1  and  204   p   2  denote p-type silicon pillars;  205  denotes a gate insulating film surrounding the silicon pillars  204   n   1  ,  204   n   2  ,  204   p   1 , and  204   p   2 ;  206  denotes a gate electrode; and  206   a  and  206   b  denote gate lines. P+ diffusion layers  207   p   1  and  207   p   2  are formed at the tops of the n-type silicon pillars  204   n   1  and  204   n   2  , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  207   n   1  and  207   n   2  are formed at the tops of the p-type silicon pillars  204   p   1  and  204   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  208  denotes a silicon nitride film for protecting the gate insulating film  205 ;  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  denote silicide layers connected to the p+ diffusion layers  207   p   1  and  207   p   2  and the n+ diffusion layers  207   n   1  and  207   n   2 , respectively;  210   p   1 ,  210   p   2 ,  210   n   1 , and  210   n   2  denote contacts that connect the silicide layers  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  to first metal lines  213   b,    213   b,    213   d,  and  213   f , respectively;  211   a  denotes a contact that connects the gate line  206   a  and a first metal line  213   c  to each other; and  211   c  denotes a contact that connects the gate line  206   b  and a first metal line  213   e  to each other.  212  denotes a contact that connects the silicide layer  203  connected to the planar silicon layer  202   nb  and the first metal line  213   d  to each other. The gate line  206   b  is a line that connects the gate electrode  206  of the PMOS transistor Qp 2  and the gate electrode  206  of the NMOS transistor Qn 2  to each other, which will be described below. 
         [0108]    The n-type silicon pillar  204   n   1  , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   1  , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  204   n   2  , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   2  , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  204   p   1 , the planar silicon layer  202   na , the n+ diffusion layer  207   n   1 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  204   p   2 , the planar silicon layer  202   nb  , the n+ diffusion layer  207   n   2 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 2 . 
         [0109]    The gate line  206   a  is connected to the gate electrode  206  of the PMOS transistor Qp 1 . The gate line  206   b  is connected to the gate electrode  206  of the PMOS transistor Qp 2 . The gate line  206   a  is connected to the gate electrode  206  of the NMOS transistor Qn 1 . The gate line  206   b  is connected to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0110]    The planar silicon layers  202   p  and  202   na serve as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1 , and are connected to an output OUT 1 . The p+ diffusion layer  207   p   1  , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  213   b  via the silicide layer  209   p   1  and the contact  210   p   1 , and the power supply voltage Vcc is supplied to the first metal line  213   b.  The p+ diffusion layer  207   p   2  , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  213   b  via the silicide layer  209   p   2  and the contact  210   p   2 . The n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  213   d  via the silicide layer  209   n   1  and the contact  210   n   1 . 
         [0111]    The planar silicon layer  202   nb  , which serves as the drain of the NMOS transistor Qn 2 , is connected to the first metal line  213   d  via the silicide layer  203  and the contact  212 . Here, the n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , and the planar silicon layer  202   nb  , which serves as the drain of the NMOS transistor Qn 2 , are connected to each other via the first metal line  213   d.  The n+ diffusion layer  207   n   2  of the NMOS transistor Qn 2  serves as the source and is connected to the first metal line  213   f  via the silicide layer  209   n   2  and the contact  210   n   2 . The reference voltage Vss is supplied to the first metal line  213   f.    
         [0112]    The input signal IN 1  is supplied to the first metal line  213   c,  is supplied to the gate line  206   a  via the contact  211   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  213   e,  is supplied to the gate line  206   b  via the contact  211   c , and is supplied to the gate electrode of the NMOS transistor Qn 2 . The gate line  206   b  is connected to the gate electrode of the PMOS transistor Qp 2 . 
         [0113]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. Further, connections can be made using only the first metal lines, and the second metal line can be effectively used. Further, the current flow directions of the NMOS transistor Qn 1  and the NMOS transistor Qn 2  (the orientations of the drains and sources) can be the same. Accordingly, the same current characteristic can be obtained and a favorable characteristic can be obtained. 
       Sixth Embodiment  
       [0114]      FIGS. 7A and 7B  illustrate a sixth embodiment.  FIG. 7A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 7B  is a cross-sectional view taken along a cut line A-A′. 
         [0115]    The arrangement of the transistors illustrated in  FIGS. 7A and 7B  is the same as that illustrated in  FIGS. 4A and 4B , that is, the PMOS transistors Qp 2  and Qp 1  and the NMOS transistors Qn 1  and Qn 2  are arranged in a line from the right. A difference from  FIGS. 4A and 4B  is that the connection of the source and drain of the NMOS transistor Qn 2  is changed. In  FIGS. 7A and 7B , the components having the same structure as that in  FIGS. 4A and 4B  are denoted by equivalent reference numerals in the 200s. 
         [0116]    In an SGT, the drain and source are located in a lower layer portion and an upper layer portion, respectively, and the physical positions thereof are different. The drain and source are made so as to be as equivalent as possible, but the orientations of the drain and source are different and thus both of them may have different current characteristics in some cases. The present invention addresses this issue. 
         [0117]    Planar silicon layers  202   p,    202   na , and  202   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  201  disposed on a substrate. The planar silicon layers  202   p,    202   na , and  202   nb  are formed of a p+ diffusion layer, an n+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  203  denotes a silicide layer disposed on surfaces of the planar silicon layers  202   p,    202   na , and  202   nb  , which connects the planar silicon layers  202   p  and  202   na to each other.  204   n   1  and  204   n   2  denote n-type silicon pillars;  204   p   1  and  204   p   2  denote p-type silicon pillars;  205  denotes a gate insulating film surrounding the silicon pillars  204   n   1  ,  204   n   2  ,  204   p   1 , and  204   p   2 ;  206  denotes a gate electrode; and  206   a,    206   b,  and  206   c  denote gate lines. P+ diffusion layers  207   p   1  and  207   p   2  are formed at the tops of the n-type silicon pillars  204   n   1  and  204   n   2  , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  207   n   1  and  207   n   2  are formed at the tops of the p-type silicon pillars  204   p   1  and  204   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  208  denotes a silicon nitride film for protecting the gate insulating film  205 ;  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  denote silicide layers connected to the p+ diffusion layers  207   p   1  and  207   p   2  and the n+ diffusion layers  207   n   1  and  207   n   2 , respectively;  210   p   1 ,  210   p   2 ,  210   n   1 , and  210   n   2  denote contacts that connect the silicide layers  209   p   1 ,  209   p   2 ,  209   n   1 , and  209   n   2  to first metal lines  213   b,    213   b ,  213   d,  and  213   f,  respectively;  211   a  denotes a contact that connects the gate line  206   a  and a first metal line  213   c  to each other;  211   b  denotes a contact that connects the gate line  206   b  and a first metal line  213   a  to each other; and  211   c  denotes a contact that connects the gate line  206   c  and a first metal line  213   e  to each other.  214   b  denotes a contact that connects the first metal line  213   a  and a second metal line  215  to each other; and  214   c  denotes a contact that connects the first metal line  213   e  and the second metal line  215  to each other.  212  denotes a contact that connects the silicide layer  203  connected to the planar silicon layer  202   nb  and the first metal line  213   d  to each other. 
         [0118]    The n-type silicon pillar  204   n   1  , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   1  , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  204   n   2  , the planar silicon layer  202   p,  the p+ diffusion layer  207   p   2  , the gate insulating film  205 , and the gate electrode  206  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  204   p   1 , the planar silicon layer  202   na , the n+ diffusion layer  207   n   1 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  204   p   2 , the planar silicon layer  202   nb  , the n+ diffusion layer  207   n   2 , the gate insulating film  205 , and the gate electrode  206  constitute the NMOS transistor Qn 2 . 
         [0119]    The gate line  206   a  is connected to the gate electrode  206  of the PMOS transistor Qp 1 . The gate line  206   b  is connected to the gate electrode  206  of the PMOS transistor Qp 2 . The gate line  206   a  is connected to the gate electrode  206  of the NMOS transistor Qn 1 . The gate line  206   c  is connected to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0120]    The planar silicon layers  202   p  and  202   na serve as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1 , and are connected to an output OUT 1 . The p+ diffusion layer  207   p   1  , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  213   b  via the silicide layer  209   p   1  and the contact  210   p   1 , and the power supply voltage Vcc is supplied to the first metal line  213   b.  The p+ diffusion layer  207   p   2  , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  213   b  via the silicide layer  209   p   2  and the contact  210   p   2 . The n+ diffusion layer  207   n   1 , which serves as the source of the NMOS transistor Qn 1 , is connected to the first metal line  213   d  via the silicide layer  209   n   1  and the contact  210   n   1 . 
         [0121]    The planar silicon layer  202   nb  , which serves as the drain of the NMOS transistor Qn 2 , is connected to the first metal line  213   d  via the silicide layer  203  and the contact  212 . Here, the source of the NMOS transistor Qn 1  and the drain of the NMOS transistor Qn 2  are connected to each other via the first metal line  213   d.  The n+ diffusion layer  207   n   2  serves as the source of the NMOS transistor Qn 2  and is connected to the first metal line  213   f  via the silicide layer  209   n   2  and the contact  210   n   2 . The reference voltage Vss is supplied to the first metal line  213   f.    
         [0122]    The input signal IN 1  is supplied to the first metal line  213   c,  is supplied to the gate line  206   a  via the contact  211   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  213   a,  is supplied to the gate line  206   b  via the contact  211   b , and is supplied to the gate electrode  206  of the PMOS transistor Qp 2 . Also, the input signal IN 2  is supplied to the second metal line  215  via the contact  214   b,  is supplied to the gate line  206   c  via the contact  214   c,  the first metal line  213   e,  and the contact  211   c , and is supplied to the gate electrode  206  of the NMOS transistor Qn 2 . 
         [0123]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. Further, with use of the second metal line, the gate line  206   b  according to the second embodiment can be omitted. Further, the current flow directions of the NMOS transistor Qn 1  and the NMOS transistor Qn 2  (the orientations of the drains and sources) can be the same. Accordingly, the same current characteristic can be obtained and a favorable characteristic can be obtained. 
       Seventh Embodiment 
       [0124]      FIG. 8  illustrates a modification example of the two-input NAND circuit illustrated in  FIG. 1 . In  FIG. 1 , a common power supply voltage Vcc is supplied to the sources of the PMOS transistors Qp 1  and Qp 2 . In  FIG. 8 , power supply voltages Vcc are supplied to the sources of the PMOS transistors Qp 10  and Qp 20 , respectively. The operation of the NAND circuit illustrated in  FIG. 8  is the same as that of the NAND circuit illustrated in  FIG. 1 , but the wiring method for power supply lines in the case of arranging transistors is different. In a seventh embodiment, an arrangement based on  FIG. 8  will be described. 
         [0125]      FIGS. 9A and 9B  illustrate an arrangement according to the seventh embodiment.  FIG. 9A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 9B  is a cross-sectional view taken along a cut line A-A′. 
         [0126]    Referring to  FIG. 9A , the PMOS transistor Qp 10 , the NMOS transistor Qn 10 , the PMOS transistor Qp 20 , and the NMOS transistor Qn 20  of the NAND circuit illustrated in  FIG. 8  are arranged in a line from the right. In  FIGS. 9A and 9B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 300s. 
         [0127]    Planar silicon layers  302   pa ,  302   na ,  302   pb , and  302   nb  are disposed on an insulating film, such as a buried oxide (BOX) layer  301  disposed on a substrate. The planar silicon layers  302   pa ,  302   na ,  302   pb , and  302   nb  are formed of a p+ diffusion layer, an n+ diffusion layer, a p+ diffusion layer, and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  303  denotes a silicide layer disposed on surfaces of the planar silicon layers  302   pa ,  302   na ,  302   pb , and  302   nb , which connects the planar silicon layers  302   pa ,  302   na , and  302   pb to one another.  304   n   1  and  304   n   2  denote n-type silicon pillars;  304   p   1  and  304   p   2  denote p-type silicon pillars;  305  denotes a gate insulating film surrounding the silicon pillars  304   n   1 ,  304   n   2  ,  304   p   1 , and  304   p   2  ;  306  denotes a gate electrode; and  306   a  and  306   b  denote gate lines. P+ diffusion layers  307   p   1  and  307   p   2  are formed at the tops of the n-type silicon pillars  304   n   1  and  304   n   2  , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  307   n   1  and  307   n   2  are formed at the tops of the p-type silicon pillars  304   p   1  and  304   p   2  , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  308  denotes a silicon nitride film for protecting the gate insulating film  305 ;  309   p   1 ,  309   p   2 ,  309   n   1 , and  309   n   2  denote silicide layers connected to the p+ diffusion layers  307   p   1  and  307   p   2  and the n+ diffusion layers  307   n   1  and  307   n   2 , respectively;  310   p   1 ,  310   p   2 ,  310   n   1 , and  310   n   2  denote contacts that connect the silicide layers  309   p   1 ,  309   p   2 ,  309   n   1 , and  309   n   2  to first metal lines  313   a,    313   d,    313   c,  and  313   f,  respectively;  311   a  denotes a contact that connects the gate line  306   a  and a first metal line  313   b  to each other; and  311  b denotes a contact that connects the gate line  306   b  and a first metal line  313   e  to each other.  312  denotes a contact that connects the silicide layer  303  connected to the planar silicon layer  302   nb  and a first metal line  313   g  to each other.  314   n   1  denotes a contact that connects the first metal line  313   c  and a second metal line  315  to each other; and  314   n   2  denotes a contact that connects the first metal line  313   f  and the second metal line  315  to each other. 
         [0128]    The n-type silicon pillar  304   n   1 , the planar silicon layer  302   pa , the p+ diffusion layer  307   p   1 , the gate insulating film  305 , and the gate electrode  306  constitute the PMOS transistor Qp 10 . The n-type silicon pillar  304   n   2  , the planar silicon layer  302   pb , the p+ diffusion layer  307   p   2  , the gate insulating film  305 , and the gate electrode  306  constitute the PMOS transistor Qp 20 . The p-type silicon pillar  304   p   1 , the planar silicon layer  302   na , the n+ diffusion layer  307   n   1 , the gate insulating film  305 , and the gate electrode  306  constitute the NMOS transistor Qn 10 . The p-type silicon pillar  304   p   2  , the planar silicon layer  302   nb , the n+ diffusion layer  307   n   2 , the gate insulating film  305 , and the gate electrode  306  constitute the NMOS transistor Qn 20 . 
         [0129]    The gate line  306   a  is connected to the gate electrode  306  of the PMOS transistor Qp 10 . The gate line  306   b  is connected to the gate electrode  306  of the PMOS transistor Qp 20 . The gate line  306   a  is connected to the gate electrode  306  of the NMOS transistor Qn 10 . The gate line  306   b  is connected to the gate electrode  306  of the NMOS transistor Qn 20 . 
         [0130]    The planar silicon layers  302   pa ,  302   na , and  302   pb serve as a common drain of the PMOS transistors Qn 10  and Qp 20  and the NMOS transistor Qn 10 , and are connected to an output OUT 10 . The p+ diffusion layer  307   p   1 , which serves as the source of the PMOS transistor Qp 10 , is connected to the first metal line  313   a  via the silicide layer  309   p   1  and the contact  310   p   1 , and the power supply voltage Vcc is supplied to the first metal line  313   a.  The p+ diffusion layer  307   p   2  , which serves as the source of the PMOS transistor Qp 20 , is connected to the first metal line  313   d  via the silicide layer  309   p   2  and the contact  310   p   2 , and the power supply voltage Vcc is supplied to the first metal line  313   d.  The n+ diffusion layer  307   n   1 , which serves as the source of the NMOS transistor Qn 10 , is connected to the first metal line  313   c  via the silicide layer  309   n   1  and the contact  310   n   1 , and the first metal line  313   c  is connected to the second metal line  315  via the contact  314   n   1 . The n+ diffusion layer  307   n   2 , which serves as the drain of the NMOS transistor Qn 20 , is connected to the first metal line  313   f  via the silicide layer  309   n   2  and the contact  310   n   2 , and the first metal line  313   f  is connected to the second metal line  315  via the contact  314   n   2 . Here, the source of the NMOS transistor Qn 10  and the drain of the NMOS transistor Qn 20  are connected to each other via the second metal line  315 . The planar silicon layer  302   nb  serves as the source of the NMOS transistor Qn 20 , and is connected to the first metal line  313   g  via the silicide layer  303  and the contact  312 . The reference voltage Vss is supplied to the first metal line  313   g . 
         [0131]    The input signal IN 1  is supplied to the first metal line  313   b,  is supplied to the gate line  306   a  via the contact  311   a,  and is supplied to the gate electrodes of the PMOS transistor Qp 10  and the NMOS transistor Qn 10 . The input signal IN 2  is supplied to the first metal line  313   e,  is supplied to the gate line  306   b  via the contact  311   b , and is supplied to the gate electrodes of the PMOS transistor Qp 20  and the NMOS transistor Qn 20 . 
         [0132]    The power supply voltage Vcc supplied to the first metal line  313   a  and the power supply voltage Vcc supplied to the first metal line  313   d  are connected to each other at a position that is not illustrated, and are supplied as the same power supply voltage.  FIG. 9A  illustrates the power supply voltages Vcc that are supplied to the first metal line  313   a  and the first metal line  313   d,  respectively, but they are disposed in upper portions of the PMOS transistors Qp 10  and QP 20 . Thus, an increase in the area does not occur, and the area for disposition can be reduced by utilizing the feature of the SGTs. 
         [0133]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
         [0134]    Although not illustrated, the connection of the source and drain of the NMOS transistor Qn 20  may be changed so that the current direction becomes the same as in the NMOS transistor Qn 10 , as in  FIGS. 5A and 5B  or  FIGS. 6A and 6B . 
         [0135]    Although not illustrated, in  FIGS. 9A and 9B , the first metal line  313   e,  the contact  311   b , and the gate line  306   b  for supplying a gate signal of the NMOS transistor Qn 20  and the PMOS transistor Qp 20  may be disposed on the left side of the NMOS transistor Qn 20 , that is, on the outer side of the second metal line  315 . Accordingly, the first metal line  313   e  for supplying the input signal IN 2  can be disposed without restriction of the second metal line, and therefore the degree of freedom in disposition is increased. 
       Eighth Embodiment 
       [0136]      FIGS. 10A and 10B  illustrate still another embodiment. The equivalent circuit diagram of this embodiment is based on  FIG. 8 . 
         [0137]    This embodiment is greatly different from the above-described first to seventh embodiments in that the orientations of the sources and drains of the PMOS transistors Qp 10  and Qp 20  and the NMOS transistors Qn 10  and Qn 20  are reversed upside down.  FIG. 10A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 10B  is a cross-sectional view taken along a cut line A-A′. 
         [0138]    Referring to  FIG. 10A , the PMOS transistor Qp 10 , the NMOS transistors Qn 10  and Qn 20 , and the PMOS transistor Qp 20  of the NAND circuit illustrated in  FIG. 8  are arranged in a line from the right. In  FIGS. 10A and 10B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 400s. 
         [0139]    Planar silicon layers  402   pa  ,  402   n,  and  402   pb  are disposed on an insulating film, such as a buried oxide (BOX) layer  401  disposed on a substrate. The planar silicon layers  402   pa  ,  402   n,  and  402   pb  are formed of a p+ diffusion layer, an n+ diffusion layer, and a p+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  403  denotes a silicide layer disposed on surfaces of the planar silicon layers  402   pa  ,  402   n,  and  402   pb  .  404   n   1  and  404   n   2  denote n-type silicon pillars;  404   p   1  and  404   p   2  denote p-type silicon pillars;  405  denotes a gate insulating film surrounding the silicon pillars  404   n   1 ,  404   n   2 ,  404   p   1 , and  404   p   2 ;  406  denotes a gate electrode; and  406   a  and  406   b  denote gate lines. P+ diffusion layers  407   p   1  and  407   p   2  are formed at the tops of the n-type silicon pillars  404   n   1  and  404   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  407   n   1  and  407   n   2  are formed at the tops of the p-type silicon pillars  404   p   1  and  404   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  408  denotes a silicon nitride film for protecting the gate insulating film  405 ;  409   p   1 ,  409   p   2 ,  409   n   1 , and  409   n   2  denote silicide layers connected to the p+ diffusion layers  407   p   1  and  407   p   2  and the n+ diffusion layers  407   n   1  and  407   n   2 , respectively;  410   p   1 ,  410   p   2 ,  410   n   1 , and  410   n   2  denote contacts that connect the silicide layers  409   p   1 ,  409   p   2 ,  409   n   1 , and  409   n   2  to first metal lines  413   b,    413   g ,  413   d,  and  413   e,  respectively;  411   a  denotes a contact that connects the gate line  406   a  and a first metal line  413   c  to each other; and  411   b  denotes a contact that connects the gate line  406   b  and a first metal line  413   f  to each other.  412   a  denotes a contact that connects the silicide layer  403  connected to the planar silicon layer  402   pa  and a first metal line  413   a  to each other; and  412   b  denotes a contact that connects the silicide layer  403  connected to the p+ diffusion layer  402   pb  and a first metal line  413   h  to each other.  414   p   1  denotes a contact that connects the first metal line  413   b  and a second metal line  415  to each other;  414   p   2  denotes a contact that connects the first metal line  413   g  and the second metal line  415  to each other; and  414   n   1  denotes a contact that connects the first metal line  413   d  and the second metal line  415  to each other. 
         [0140]    The n-type silicon pillar  404   n   1 , the planar silicon layer  402   pa  , the p+ diffusion layer  407   p   1 , the gate insulating film  405 , and the gate electrode  406  constitute the PMOS transistor Qp 10 . The n-type silicon pillar  404   n   2 , the planar silicon layer  402   pb  , the p+ diffusion layer  407   p   2 , the gate insulating film  405 , and the gate electrode  406  constitute the PMOS transistor Qp 20 . The p-type silicon pillar  404   p   1 , the planar silicon layer  402   n,  the n+ diffusion layer  407   n   1 , the gate insulating film  405 , and the gate electrode  406  constitute the NMOS transistor Qn 10 . The p-type silicon pillar  404   p   2 , the planar silicon layer  402   n,  the n+ diffusion layer  407   n   2 , the gate insulating film  405 , and the gate electrode  406  constitute the NMOS transistor Qn 20 . 
         [0141]    The gate line  406   a  is connected to the gate electrode  406  of the PMOS transistor Qp 10 . The gate line  406   b  is connected to the gate electrode  406  of the PMOS transistor Qp 20 . The gate line  406   a  is connected to the gate electrode  406  of the NMOS transistor Qn 10 . The gate line  406   b  is connected to the gate electrode  406  of the NMOS transistor Qn 20 . 
         [0142]    The second metal line  415  serves as a common drain of the PMOS transistors Qp 10  and Qp 20  and the NMOS transistor Qn 10 , and are connected to an output OUT 10 . The planar silicon layer  402   pa  , which serves as the source of the PMOS transistor Qp 10 , is connected to the first metal line  413   a  via the silicide layer  403  and the contact  412   a,  and the power supply voltage Vcc is supplied to the first metal line  413   a.  The planar silicon layer  402   pb  , which serves as the source of the PMOS transistor Qp 20 , is connected to the first metal line  413   h  via the silicide layer  403  and the contact  412   b,  and the power supply voltage Vcc is supplied to the first metal line  413   h.  The planar silicon layer  402   n,  which serves as the source of the NMOS transistor Qn 10 , serves as the drain of the NMOS transistor Qn 20 . The n+ diffusion layer  407   n   2 , which serves as the source of the NMOS transistor Qn 20 , is connected to the first metal line  413   e  via the silicide layer  409   n   2  and the contact  410   n   2 , and the reference voltage Vss is supplied to the first metal line  413   e.    
         [0143]    The input signal IN 1  is supplied to the first metal line  413   c,  is supplied to the gate line  406   a  via the contact  411   a,  and is supplied to the gate electrodes  406  of the PMOS transistor Qp 10  and the NMOS transistor Qn 10 . The input signal IN 2  is supplied to the first metal line  413   f,  is supplied to the gate line  406   b  via the contact  411   b , and is supplied to the gate electrodes  406  of the PMOS transistor Qp 20  and the NMOS transistor Qn 20 . 
         [0144]    In this embodiment, power supply voltages Vcc are respectively supplied to the first metal lines  413   a  and  413   h,  but they are disposed at the right and left ends in the figure. Thus, the power supply voltages Vcc can be shared in the case of arranging the circuits according to the embodiment of the present invention side by side (not illustrated) without causing an increase in the area. Accordingly, the area for arrangement can be reduced by utilizing the feature of the SGTs. 
         [0145]    Further, in this embodiment, the output OUT 10  is connected to the second metal line, and thus there is a degree of freedom in obtaining an output. For example, the second metal line  415 , which serves as an output line, can be freely extended in the right direction or left direction in  FIG. 10A . 
         [0146]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
       Ninth Embodiment 
       [0147]      FIGS. 11A ,  11 B, and  11 C illustrate a ninth embodiment, which is a modification example of the eighth embodiment.  FIG. 11A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention,  FIG. 11B  is a cross-sectional view taken along a cut line A-A′, and FIG.  11 C is a cross-sectional view taken along a cut line B-B′. A common power supply voltage Vcc is supplied, on the basis of the circuit diagram illustrated in  FIG. 1 . 
         [0148]    Referring to  FIG. 11A , the PMOS transistor Qp 1 , the NMOS transistors Qn 1  and Qn 2 , and the PMOS transistor Qp 2  of the NAND circuit illustrated in  FIG. 1  are arranged in a line from the right. In  FIGS. 11A and 11B , the components having the same structure as that in  FIGS. 10A and 10B  are denoted by equivalent reference numerals in the 500s. 
         [0149]    A difference between this embodiment and the eighth embodiment ( FIGS. 10A and 10B ) is that contacts  512   a  and  512   b  for supplying the power supply voltage Vcc to the PMOS transistors Qp 1  and Qp 2  are disposed on the upper and lower sides in  FIG. 11A  (right and left sides in  FIG. 11C ), whereas they are disposed on the right and left sides in  FIGS. 10A and 10B . 
         [0150]    Planar silicon layers  502   pa ,  502   n,  and  502   pb  are disposed on an insulating film, such as a buried oxide (BOX) layer  501  disposed on a substrate. The planar silicon layers  502   pa ,  502   n,  and  502   pb  are formed of a p+ diffusion layer, an n+ diffusion layer, and a p+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  503  denotes a silicide layer disposed on surfaces of the planar silicon layers  502   pa ,  502   n,  and  502   pb .  504   n   1  and  504   n   2  denote n-type silicon pillars;  504   p   1  and  504   p   2  denote p-type silicon pillars;  505  denotes a gate insulating film surrounding the silicon pillars  504   n   1 ,  504   n   2 ,  504   p   1 , and  504   p   2 ;  506  denotes a gate electrode; and  506   a,    506   b ,  506   c,  and  506   d  denote gate lines. P+ diffusion layers  507   p   1  and  507   p   2  are formed at the tops of the n-type silicon pillars  504   n   1  and  504   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  507   n   1  and  507   n   2  are formed at the tops of the p-type silicon pillars  504   p   1  and  504   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  508  denotes a silicon nitride film for protecting the gate insulating film  505 ;  509   p   1 ,  509   p   2 ,  509   n   1 , and  509   n   2  denote silicide layers connected to the p+ diffusion layers  507   p   1  and  507   p   2  and the n+ diffusion layers  507   n   1  and  507   n   2 , respectively;  510   p   1 ,  510   p   2 ,  510   n   1 , and  510   n   2  denote contacts that connect the silicide layers  509   p   1 ,  509   p   2 ,  509   n   1 , and  509   n   2  to first metal lines  513   b,    513   e,    513   c,  and  513   d,  respectively;  511   a  denotes a contact that connects the gate line  506   a  and a first metal line  513   a  to each other; and  511  b denotes a contact that connects the gate line  506   d  and a first metal line  513   f  to each other. In  FIGS. 11A and 11C ,  512   a  denotes a contact that connects the silicide layer  503  connected to the planar silicon layer  502   pa  and a first metal line  513   g  to each other. In  FIG. 11A ,  512   b  denotes a contact that connects the silicide layer  503  connected to the planar silicon layer  502   pb  and a first metal line  513   h  to each other.  514   p   1  denotes a contact that connects the first metal line  513   b  and a second metal line  515  to each other;  514   p   2  denotes a contact that connects the first metal line  513   e  and the second metal line  515  to each other; and  514   n   1  denotes a contact that connects the first metal line  513   c  and the second metal line  515  to each other. 
         [0151]    The n-type silicon pillar  504   n   1 , the planar silicon layer  502   pa , the p+ diffusion layer  507   p   1 , the gate insulating film  505 , and the gate electrode  506  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  504   n   2 , the planar silicon layer  502   pb , the p+ diffusion layer  507   p   2 , the gate insulating film  505 , and the gate electrode  506  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  504   p   1 , the planar silicon layer  502   n,  the n+ diffusion layer  507   n   1 , the gate insulating film  505 , and the gate electrode  506  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  504   p   2 , the planar silicon layer  502   n,  the n+ diffusion layer  507   n   2 , the gate insulating film  505 , and the gate electrode  506  constitute the NMOS transistor Qn 2 . 
         [0152]    The gate line  506   a  is connected to the gate electrode  506  of the PMOS transistor Qp 1 . The gate line  506   d  is connected to the gate electrode  506  of the PMOS transistor Qp 2 . The gate line  506   a  is connected to the gate electrode  506  of the NMOS transistor Qn 1  via the gate line  506   b.  The gate line  506   d  is connected to the gate electrode  506  of the NMOS transistor Qn 2  via the gate line  506   c.    
         [0153]    The second metal line  515  serves as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1  and is connected to an output OUT 1 . The planar silicon layer  502   pa , which serves as the source of the PMOS transistor Qp 1 , is connected to the first metal line  513   g  via the silicide layer  503  and the contact  512   a,  and is further connected to a second metal line  516  via a contact  514   a.  The power supply voltage Vcc is supplied to the second metal line  516 . The planar silicon layer  502   pb , which serves as the source of the PMOS transistor Qp 2 , is connected to the first metal line  513   h  via the silicide layer  503  and the contact  512   b,  and is further connected to the second metal line  516  via a contact  514   b.  The planar silicon layer  502   n,  which serves as the source of the NMOS transistor Qn 1 , serves as the drain of the NMOS transistor Qn 2 . The n+ diffusion layer  507   n   2 , which serves as the source of the NMOS transistor Qn 2 , is connected to the first metal line  513   d  via the silicide layer  509   n   2  and the contact  510   n   2 , and the reference voltage Vss is supplied to the first metal line  513   d.    
         [0154]    The input signal IN 1  is supplied to the first metal line  513   a,  is supplied to the gate line  506   a  via the contact  511   a,  and is supplied to the gate electrodes  506  of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  513   f,  is supplied to the gate line  506   b  via the contact  511   b , and is supplied to the gate electrodes  506  of the PMOS transistor Qp 2  and the NMOS transistor Qn 2 . 
         [0155]    A basic unit of the layout of this circuit is referred to as a unit block (UB). A UB  500  is represented by a chained line. In a case where a plurality of NAND circuits are arranged in the vertical direction in units of the unit blocks, the contacts  512   a  and  512   b  for supplying the power supply voltage Vcc can be shared, and an increase in the area can be suppressed. 
         [0156]    In this embodiment, in contrast to the eighth embodiment, the contacts  512   a  and  512   b  for supplying the power supply voltage Vcc to the PMOS transistors Qp 1  and Qp 2  are disposed on the upper and lower sides in the figure. Accordingly, the width in the horizontal direction can be greatly reduced. According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
       Tenth Embodiment  
       [0157]      FIGS. 12A ,  12 B, and  12 C illustrate a tenth embodiment, which is a modification example of the ninth embodiment.  FIG. 12A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention,  FIG. 12B  is a cross-sectional view taken along a cut line A-A′, and  FIG. 12C  is a cross-sectional view taken along a cut line B-B′. 
         [0158]      FIG. 12A  illustrates an example in which four NAND circuits, each being the NAND circuit illustrated in  FIG. 1 , are arranged. From the upper right of  FIG. 12A , a PMOS transistor Qp 11 , NMOS transistors Qn 11  and Qn 12 , and a PMOS transistor Qp 12  are arranged in a line. Also, a PMOS transistor Qp 21 , NMOS transistors Qn 21  and Qn 22 , and a PMOS transistor Qp 22  are arranged in a line in the second row. Further, a PMOS transistor Qp 31 , NMOS transistors Qn 31  and Qn 32 , and a PMOS transistor Qp 32  are arranged in a line in the third row. Further, a PMOS transistor Qp 41 , NMOS transistors Qn 41  and Qn 42 , and a PMOS transistor Qp 42  are arranged in a line in the fourth row. These four sets of NAND circuits integrally constitute a NAND circuit unit block UB 600 . 
         [0159]    In  FIGS. 12A ,  12 B, and  12 C, the components having the same structure as that in  FIGS. 11A ,  11 B, and  11 C are denoted by equivalent reference numerals in the 600s, and the description thereof is omitted. Hereinafter, a difference from the ninth embodiment will be described. 
         [0160]    In this embodiment, the four sets of NAND circuits are provided with a pair of contacts  612   a  and  612   b.  The contact  612   a  supplies the power supply voltage Vcc to the PMOS transistors Qp 11 , Qp 21 , Qp 31 , and QP 41 . The contact  612   b  supplies the power supply voltage Vcc to the PMOS transistors Qp 12 , Qp 22 , Qp 32 , and Qp 42 . Further, as a metal line for supplying the power supply voltage Vcc, a second metal line  616  is provided so as to extend in the horizontal direction in  FIG. 12A . In  FIG. 12C , the sources of the PMOS transistors Qp 11 , QP 21 , Qp 31 , and Qp 41  are connected to a planar silicon layer  602   pa , and are connected to a first metal line  613   k  via a silicide layer  603  connected to the planar silicon layer  602   pa  and the contact  612   a.  The first metal line  613   k  is connected to the second metal line  616  via a contact  614   k.  As illustrated in  FIG. 12A , the second metal line  616  extends in the horizontal direction on the upper side, the horizontal direction on the lower side, and the vertical direction on the left side, so that the power supply voltage Vcc can be freely supplied from the right and left. Further, with the power supply voltage Vcc being supplied in units of blocks, the NAND circuits can be arranged with a minimum interval in the vertical direction in  FIG. 12A , relative to the embodiment illustrated in  FIGS. 11A to 11C , and thus the entire size can be reduced. 
         [0161]    In this embodiment, a pair of contacts are provided for four sets of NAND circuits. However, in a power supply path, current flows via the silicide layer  603 , and thus the resistance of a silicide line may cause voltage drop. Thus, the number of sets may be determined in consideration of the amount of current consumption and a resistance value. According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
       Eleventh Embodiment 
       [0162]      FIGS. 13A and 13B  illustrate the arrangement according to an eleventh embodiment.  FIG. 13A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 13B  is a cross-sectional view taken along a cut line A-A′. 
         [0163]    Referring to  FIG. 13A , the PMOS transistors Qp 2  and Qp 1  and the NMOS transistors Qn 1  and Qn 2  of the NAND circuit illustrated in  FIG. 1  are arranged in a line from the right. In  FIGS. 13A and 13B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 700s. 
         [0164]    Planar silicon layers  702   p  and  702   n  are disposed on an insulating film, such as a buried oxide (BOX) layer  701  disposed on a substrate. The planar silicon layers  702   p  and  702   n  are formed of a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  703  denotes a silicide layer disposed on surfaces of the planar silicon layers  702   p  and  702   n.    704   n   1  and  704   n   2  denote n-type silicon pillars;  704   p   1  and  704   p   2  denote p-type silicon pillars;  705  denotes a gate insulating film surrounding the silicon pillars  704   n   1 ,  704   n   2 ,  704   p   1 , and  704   p   2 ;  706  denotes a gate electrode; and  706   a,    706   b,  and  706   c  denote gate lines. P+ diffusion layers  707   p   1  and  707   p   2  are formed at the tops of the n-type silicon pillars  704   n   1  and  704   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  707   n   1  and  707   n   2  are formed at the tops of the p-type silicon pillars  704   p   1  and  704   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  708  denotes a silicon nitride film for protecting the gate insulating film  705 ;  709   p   1 ,  709   p   2 ,  709   n   1 , and  709   n   2  denote silicide layers connected to the p+ diffusion layers  707   p   1  and  707   p   2  and the n+ diffusion layers  707   n   1  and  707   n   2 , respectively;  710   p   1 ,  710   p   2 ,  710   n   1 , and  710   n   2  denote contacts that connect the silicide layers  709   p   1 ,  709   p   2 ,  709   n   1 , and  709   n   2  to first metal lines  713   d,    713   c,    713   f,  and  713   g,  respectively;  711   a  denotes a contact that connects the gate line  706   a  and a first metal line  713   e  to each other; and  711  b denotes a contact that connects the gate line  706   b  and a first metal line  713   b  to each other.  712  denotes a contact that connects the silicide layer  703  connected to the planar silicon layer  702   p  and a first metal line  713   a  to each other.  714   p   1  denotes a contact that connects the first metal line  713   d  and a second metal line  715  to each other;  714   p   2  denotes a contact that connects the first metal line  713   c  and the second metal line  715  to each other; and  714   n   1  denotes a contact that connects the first metal line  713   f  and the second metal line  715  to each other. 
         [0165]    The n-type silicon pillar  704   n   1 , the planar silicon layer  702   p,  the p+ diffusion layer  707   p   1 , the gate insulating film  705 , and the gate electrode  706  constitute the PMOS transistor Qp 1 . The n-type silicon pillar  704   n   2 , the planar silicon layer  702   p,  the p+ diffusion layer  707   p   2 , the gate insulating film  705 , and the gate electrode  706  constitute the PMOS transistor Qp 2 . The p-type silicon pillar  704   p   1 , the planar silicon layer  702   n,  the n+ diffusion layer  707   n   1 , the gate insulating film  705 , and the gate electrode  706  constitute the NMOS transistor Qn 1 . The p-type silicon pillar  704   p   2 , the planar silicon layer  702   n,  the n+ diffusion layer  707   n   2 , the gate insulating film  705 , and the gate electrode  706  constitute the NMOS transistor Qn 2 . 
         [0166]    The gate line  706   a  is connected to the gate electrode  706  of the PMOS transistor Qp 1 . The gate line  706   b  is connected to the gate electrode  706  of the PMOS transistor Qp 2 . The gate line  706   a  is connected to the gate electrode  706  of the NMOS transistor Qn 1 . The gate line  706   b  is connected to the gate electrode  706  of the NMOS transistor Qn 2  via the gate line  706   c.    
         [0167]    The second metal line  715  serves as a common drain of the PMOS transistors Qp 1  and Qp 2  and the NMOS transistor Qn 1  and is connected to an output OUT 1 . The planar silicon layer  702   p,  which serves as the sources of the PMOS transistors Qp 1  and Qp 2 , is connected to the first metal line  713   a  via the silicide layer  703  and the contact  712 , and the power supply voltage Vcc is supplied to the first metal line  713   a.  The planar silicon layer  702   n,  which serves as the source of the NMOS transistor Qn 1 , serves as the drain of the NMOS transistor Qn 2 . The n+ diffusion layer  707   n   2 , which serves as the source of the NMOS transistor Qn 2 , is connected to the first metal line  713   g  via the silicide layer  709   n   2  and the contact  710   n   2 , and the reference voltage Vss is supplied to the first metal line  713   g.    
         [0168]    The input signal IN 1  is supplied to the first metal line  713   e,  is supplied to the gate line  706   a  via the contact  711   a,  and is supplied to the gate electrodes  706  of the PMOS transistor Qp 1  and the NMOS transistor Qn 1 . The input signal IN 2  is supplied to the first metal line  713   d,  is supplied to the gate line  706   b  via the contact  711   b , and is supplied to the gate electrode  706  of the PMOS transistor Qp 2 . Also, the input signal IN 2  is supplied to the gate electrode  706  of the NMOS transistor Qn 2  via the gate line  706   c.    
         [0169]    In this embodiment, the power supply voltage Vcc can be supplied from the rightmost side in the figure, and the reference voltage Vss can be supplied from the leftmost side in the figure. Thus, in a case where a plurality of circuits (not illustrated) are arranged side by side, the power supply voltage Vcc and the reference voltage Vss can be shared by the circuits, and the area can be further reduced. 
         [0170]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
         [0171]    Twelfth Embodiment 
         [0172]      FIG. 14  illustrates another NAND circuit. A difference from the NAND circuit illustrated in  FIG. 1  is that an input signal for a PMOS transistor Qp 200  and an input signal for an NMOS transistor Qn 200  are supplied through different lines. An input signal IN 2   a  is input to the gate of the PMOS transistor Qp 200 , and an input signal IN 2   b  is input to the gate of the NMOS transistor Qn 200 . As illustrated in  FIG. 14 , the input signals IN 2   a  and IN 2   b  are connected to a common input signal IN 2  at another position, and thus the operation is the same as in  FIG. 1 . Here, the lines for the input signals IN 2   a  and IN 2   b  are individually provided for the convenience of arrangement. 
         [0173]    An embodiment based on the connections illustrated in  FIG. 14  is illustrated in  FIGS. 15A and 15B .  FIGS. 15A and 15B  illustrate a modification example of the embodiment illustrated in  FIGS. 13A and 13B . 
         [0174]      FIGS. 15A and 15B  illustrate the arrangement according to a twelfth embodiment.  FIG. 15A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 15B  is a cross-sectional view taken along a cut line A-A′. 
         [0175]    Referring to  FIG. 15A , the PMOS transistors Qp 200  and Qp 100  and the NMOS transistors Qn 100  and Qn 200  of the NAND circuit illustrated in  FIG. 14  are arranged in a line from the right. In  FIGS. 15A and 15B , the components having the same structure as that in  FIGS. 13A and 13B  are denoted by equivalent reference numerals in the 700s. 
         [0176]    Planar silicon layers  702   p  and  702   n  are disposed on an insulating film, such as a buried oxide (BOX) layer  701  disposed on a substrate. The planar silicon layers  702   p  and  702   n  are formed of a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like, and serve as lower diffusion layers.  703  denotes a silicide layer disposed on surfaces of the planar silicon layers  702   p  and  702   n.    704   n   1  and  704   n   2  denote n-type silicon pillars;  704   p   1  and  704   p   2  denote p-type silicon pillars;  705  denotes a gate insulating film surrounding the silicon pillars  704   n   1 ,  704   n   2 ,  704   p   1 , and  704   p   2 ;  706  denotes a gate electrode; and  706   a,    706   b,  and  706   c  denote gate lines. P+ diffusion layers  707   p   1  and  707   p   2  are formed at the tops of the n-type silicon pillars  704   n   1  and  704   n   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers. N+ diffusion layers  707   n   1  and  707   n   2  are formed at the tops of the p-type silicon pillars  704   p   1  and  704   p   2 , respectively, through impurity implantation or the like, and serve as upper diffusion layers.  708  denotes a silicon nitride film for protecting the gate insulating film  705 ;  709   p   1 ,  709   p   2 ,  709   n   1 , and  709   n   2  denote silicide layers connected to the p+ diffusion layers  707   p   1  and  707   p   2  and the n+ diffusion layers  707   n   1  and  707   n   2 , respectively;  710   p   1 ,  710   p   2 ,  710   n   1 , and  710   n   2  denote contacts that connect the silicide layers  709   p   1 ,  709   p   2 ,  709   n   1 , and  709   n   2  to first metal lines  713   d,    713   c,    713   f,  and  713   g,  respectively;  711   a  denotes a contact that connects the gate line  706   a  and a first metal line  713   e  to each other;  711  b denotes a contact that connects the gate line  706   b  and a first metal line  713   b  to each other; and  711   c  denotes a contact that connects the gate line  706   c  and a first metal line  713   h  to each other.  712  denotes a contact that connects the silicide layer  703  connected to the planar silicon layer  702   p  and a first metal line  713   a  to each other.  714   p   1  denotes a contact that connects the first metal line  713   d  and a second metal line  715  to each other;  714   p   2  denotes a contact that connects the first metal line  713   c  and the second metal line  715  to each other; and  714   n   1  denotes a contact that connects the first metal line  713   f  and the second metal line  715  to each other. 
         [0177]    The n-type silicon pillar  704   n   1 , the planar silicon layer  702   p,  the p+ diffusion layer  707   p   1 , the gate insulating film  705 , and the gate electrode  706  constitute the PMOS transistor Qp 100 . The n-type silicon pillar  704   n   2 , the planar silicon layer  702   p,  the p+ diffusion layer  707   p   2 , the gate insulating film  705 , and the gate electrode  706  constitute the PMOS transistor Qp 200 . The p-type silicon pillar  704   p   1 , the planar silicon layer  702   n,  the n+ diffusion layer  707   n   1 , the gate insulating film  705 , and the gate electrode  706  constitute the NMOS transistor Qn 100 . The p-type silicon pillar  704   p   2 , the planar silicon layer  702   n,  the n+ diffusion layer  707   n   2 , the gate insulating film  705 , and the gate electrode  706  constitute the NMOS transistor Qn 200 . 
         [0178]    The gate line  706   a  is connected to the gate electrode  706  of the PMOS transistor Qp 100 . The gate line  706   b  is connected to the gate electrode  706  of the PMOS transistor Qp 200 . The gate line  706   a  is connected to the gate electrode  706  of the NMOS transistor Qn 100 . The gate line  706   c  is connected to the gate electrode  706  of the NMOS transistor Qn 200 . 
         [0179]    The second metal line  715  serves as a common drain of the PMOS transistors Qp 100  and Qp 200  and the NMOS transistor Qn 100  and is connected to an output OUT 100 . The planar silicon layer  702   p,  which serves as the sources of the PMOS transistors Qp 100  and Qp 200 , is connected to the first metal line  713   a  via the silicide layer  703  and the contact  712 , and the power supply voltage Vcc is supplied to the first metal line  713   a.  The planar silicon layer  702   n,  which serves as the source of the NMOS transistor Qn 100 , serves as the drain of the NMOS transistor Qn 200 . The n+ diffusion layer  707   n   2 , which serves as the source of the NMOS transistor Qn 200 , is connected to the first metal line  713   g  via the silicide layer  709   n   2  and the contact  710   n   2 , and the reference voltage Vss is supplied to the first metal line  713   g.    
         [0180]    The input signal IN 1  is supplied to the first metal line  713   e,  is supplied to the gate line  706   a  via the contact  711   a,  and is supplied to the gate electrodes  706  of the PMOS transistor Qp 100  and the NMOS transistor Qn 100 . The input signal IN 2   a  is supplied to the first metal line  713   b,  is supplied to the gate line  706   b  via the contact  711   b , and is supplied to the gate electrode  706  of the PMOS transistor Qp 200 . The input signal IN 2   b  is supplied to the first metal line  713   h,  is supplied to the gate line  706   c  via the contact  711   c,  and is supplied to the gate electrode  706  of the NMOS transistor Qn 200 . 
         [0181]    Note that the input signals IN 2   a  and IN 2   b  are equivalent to the input signal IN 2  illustrated in  FIG. 1 , but the names of the signals are different for convenience because the connection positions of the first metal lines are different. 
         [0182]    In this embodiment, a line for an input signal (the first metal line  713   c ) is added to the configuration illustrated in  FIGS. 13A and 13B . However, the gate line  706   c  illustrated in  FIG. 13A  can be omitted. Thus, in a case where a plurality of circuits (not illustrated) are arranged in the vertical direction in the figure, the circuits can be arranged with a minimum pitch, and thus the entire size in the vertical direction can be reduced. 
         [0183]    According to this embodiment, four SGTs constituting a two-input NAND circuit can be arranged in a line without providing wasteful lines and contact regions, and a semiconductor device with a reduced area can be provided. 
         [0184]    In the above-described embodiments, a description has been given of arrangements by using examples of a process in which planar silicon layers are disposed on an insulating film, such as a buried oxide (BOX) layer disposed on a substrate. The same applies to a bulk CMOS process. As an example,  FIGS. 16A and 16B  illustrate an embodiment in which the embodiment illustrated in  FIGS. 2A and 2B  is implemented with a bulk CMOS process. 
         [0185]      FIG. 16A  is a plan view illustrating the layout (arrangement) of a two-input NAND circuit according to the present invention, and  FIG. 16B  is a cross-sectional view taken along a cut line A-A′. In  FIG. 16A , the arrangement of the transistors is the same as that in  FIG. 2A , that is, the NMOS transistor Qn 1 , the PMOS transistors Qp 1  and Qp 2 , and the NMOS transistor Qn 2  of the NAND circuit illustrated in  FIG. 1  are arranged in a line from the right. In  FIGS. 16A and 16B , the components having the same structure as that in  FIGS. 2A and 2B  are denoted by equivalent reference numerals in the 100s. 
         [0186]    With reference to Japanese Patent No. 4756221, no difference is seen in the plan view in  FIG. 16A  between the BOX process illustrated in  FIGS. 2A and 2B  and the bulk CMOS process illustrated in  FIGS. 16A and 16B . However, a difference therebetween can be seen in the cross-sectional view in  FIG. 16B . Referring to  FIG. 16B ,  150  denotes a p-type silicon substrate.  160  denotes an insulator for element isolation.  170  denotes an n-region serving as an isolation layer for preventing leakage. The manufacturing process and structure of the lower diffusion layer and the upper side thereof, that is, the portion other than the p-type silicon substrate  150 , the insulator  160  for element isolation, and the leakage preventing isolation layer  170 , are completely the same as those of the embodiment illustrated in  FIGS. 2A and 2B , and the first to twelfth embodiments of the present invention can be implemented through a bulk CMOS process. However, the insulator  160  and the leakage preventing isolation layer  170  are provided, and thus the area increases accordingly. 
         [0187]    In the description of the embodiments, the silicon pillar of a PMOS transistor is defined as an n-type silicon layer, and the silicon pillar of an NMOS transistor is defined as a p-type silicon layer. However, in a fine process, it is difficult to control the density obtained through impurity implantation. Thus, a so-called neutral (intrinsic) semiconductor with no impurity implantation may be used for silicon pillars of the PMOS transistor and the NMOS transistor, and a difference in work function unique to a metal gate material may be used for control of a channel, that is, thresholds of PMOS and NMOS. 
         [0188]    The primarily important aspect of the present invention is the definition of the optimum arrangement of four transistors. In a case where the transistors are arranged in the optimum order, a wiring method and wiring positions for gate lines and a wiring method and wiring positions for metal lines that are not illustrated in the figures of the embodiments are also included in the technical scope of the present invention.
A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area.