Researchers have also constructed the CMOS inverter (logic circuit) by combining a phosphorene PMOS transistor with a MoS NMOS transistor, achieving high heterogeneous integration of semiconducting phosphorene crystals as a new channel material for potential electronic applications. In the inverter, the power supply voltage is set to be 1 V. The output voltage shows a clear transition from VDD to 0 within the input voltage range from −10 to −2 V. A maximum gain of ~1.4 is attained.