In the array storage, the value of 170 ns/integral in the random access case is typical of the latency to fetch a value in the RAM modules, telling that the requested integral is almost never present in any level of cache. When the data is accessed with a stride of one (i, j, l, k storage), the hierarchical architecture of the cache levels accelerates the access by a factor of 18, down to 9.71 ns/integral, corresponding mostly to the overhead of the function call, the retrieval of the data being negligible.