Silicon Chip fabrication was undertaken as described in previous publications , , , , , , . In brief, four-inch silicon wafer substrates bearing a 300 nm thermally grown silicon dioxide layer were used. Working electrodes were first fabricated using optical lithography, metal evaporation (Ti 10 nm /Au 50 nm Temescal FC-2000 beam evaporator) and lift-off techniques to yield well-defined, stacked metallic (Ti/Au) microband (1 µm width, 50 nm height, 45 µm length) structures.