With an interface centered at position 10, there is a 1500 µm distance between the top of the TCS (position 20) and the interface. Assuming a homogeneous polishing procedure, it means that the TCS angle is at best 0.015° or even below, if we use an alternative methodology as described in Figure . This time, three polishing steps were used with an angle between the sample holder and the polishing plate of 0.1°, 0.06°, and 0.06°. Up to now, there is no unique polishing procedure that can be applied to all sample architectures. For each device, a polishing methodology needs to be developed. For the measurements of the perovskite solar cells, it was important to prepare the TCS by limiting water exposure, but for the III-V semiconductors it seems that the main issue is the polishing induced defects. As before, the TCS-PES can lead to a relative concentration profile that helped to set the limit between the two materials and position the interface (see Figure ). BE shifts were also monitored over the TCS (see Figure ). When moving closer to the interface, a shift to higher BE for the elements composing the n-GaAs, and a shift to lower BE for the ones composing the n-GaInP are observed. These shifts can either come from Fermi level alignment or from chemical modifications induced by surface states.