For all correlated computations, the frozen-core approximation is used. All timings are performed on 16 cores of an Intel Xeon 6136 CPU (3.0 GHz processing speed with 1 TB of RAM) unless otherwise stated. The code can currently be found in a developmental branch of the freely available Psi4. For the average user, it is not required to have such high amounts of RAM for routine DLPNO-CCSD(T) calculations. A high amount of RAM is only used here in order to benchmark the largest systems.