Materials with high permittivities are important research and development targets, as gate components in metal-oxide semiconductor transistors and high energy density capacitors. Industry demands ever-increasing performance in these devices, with capacitance increased most often by decreasing dielectric layer thicknesses. However, the thicknesses of traditional SiO 2 gate layers can not be decreased below ∼ 1 nm, because increasing leakage currents negate capacitance improvements. Using thicker dielectrics with larger permittivities allows device footprints to continue to shrink while maintaining low leakage currents.