Simulations were carried out on the Dutch national supercomputer, Snellius. For the 3D simulations, we made use of 3 nodes, 80 cores each, each node holding CPUs with a clock speed of 2.6 GHz, with 672 GB of the total available memory. In order to obtain the scaling behavior and the parallel efficiency of the developed model in an HPC environment, a strong scaling test was performed in which we made use of up to 10 nodes, 80 cores each. 2D simulations were performed using 16 CPU cores on Snellius. The run for translating the optimization results to TPMS structures was carried out using 64 CPU cores on an exclusive Snellius node with 224 GB of memory.