DRAM device scaling has gotten aggressive with each progressing node . This aggressive scaling of DRAM array results in significant bottleneck for DRAM device fabrication. Over the years, this has resulted in disruptive memory technologies to take shape . In the current DRAM technology, there are several places where we are required to use n-type Polysilicon, using Phosphorus doping . For example: The contact regions between the middle-of-the-line (MOL) and the front-end-of-line (FEOL) require the use of Polycrystalline Si:P to design optimal contacts. But DRAM scaling has rendered Polysilicon deposition difficult due to its non-selective nature. There is a natural tendency to deviate into a monocrystalline selective deposition to enable such aggressive scaling. Selective epitaxy is one of the most obvious candidates for monocrystalline Si:P deposition . Furthermore, advanced CMOS devices also require the use of n-type Si to enable doped source/drain regions for DRAM peripheries .