As the size of transistors continue to shrink in size, following Moore's Law, the ability to downscale the lowest level device interconnects has become a bottleneck in further device miniaturisation. The current metal of choice for the interconnects is copper (Cu), however as the interconnect size shrinks, the resistivity of Cu increases, limiting its use at the smallest scales. This problem is increased as Cu needs a diffusion barrier to hinder it from contaminating the dielectric and a liner (or glue layer) to make it adhere to the substrate, and to form a smooth film. Without a liner layer, the Cu forms non-conductive 3D islands instead of a 2D smooth film during deposition. Common barrier materials are metal nitrides such as tantalum nitride (TaN), titanium nitride (TiN) or tungsten nitride (WN) while the liner often consist of a metal, such as tantalum, cobalt or ruthenium. These additional layers take up valuable and already limited available volume in the small vias. The deposition of the barrier and liner is also a challenge in the high-aspect ratio vias, as uniform and smooth films needs to be deposited without any pinch off that is typically seen in physical vapour deposition. Different approaches have been proposed to circumvent these challenges. One method is to replace the barrier/liner bilayer structure with a single material, thus freeing up space in the via allowing Cu interconnects to be used in even smaller devices. An approach we have explored is to dope the common barrier material TaN with cobalt, ruthenium or tungsten to increase the wettability of Cu to the barrier and promoting a 2D morphology. Another approach is to replace the Cu with other metals to improve conductivity at smaller scales. Multiple different metals have emerged as possible replacements, of which cobalt (Co) and ruthenium (Ru) have been considered as some of the most promising alternatives. Compared to Cu these metals show lower resistivity at nm-length scales. A smooth 2D film is preferred for the interconnects as this allows for a high conductivity in the interconnects, the metals should form a smooth 2D film with a low amount of grain boundaries. Despite their status as critical materials the relatively small amounts used may overcome this issue. Although both these metals have been shown to adhere better to the substrate and form a more continuous film with better conductivity, there has only been limited studies on how the morphology and structure of metals is determined by the substrate on which they are deposited.