SERS sensors were fabricated on four-inch silicon wafer substrates with a 300 nm layer of thermally grown silicon dioxide as previously described. Briefly, the working electrodes were patterned using photolithography and physical vapor deposition (PVD) (50 nm of Au, with 10 nm of Ti adhesion layer) followed by a lift-off step. A second optical lithographic and metal deposition process (Au 100 nm/Ti 10 nm) was undertaken to define micro-SD pin-out, interconnection tracks, as well as the on-chip counter electrode (500 μm wide × 6 mm long). A third lithographic step was employed to define the Pt (Pt 100 nm/ Ti 10 nm) on-chip reference electrode (500 μm wide × 6 mm long). Finally, 500 nm of Plasma-enhanced chemical vapor deposition (PECVD) Si3N4 was blanket deposited on the whole wafer, the openings were over the working/counter/reference electrodes and the electrical contacts were defined by lithography and dry etching process. See Figure in SI.