Fabrication and functionalization of silicon oxide microchips with GSH probes. The silicon oxide microchips (SOµC) were fabricated using microelectronics techniques summarized in, Figure , over a 100-mm-Φ silicon wafer, Figure . First, a 1-µm-thick silicon oxide layer was thermally grown (Figure ). This layer will be the structural material of the microchips. The next processes were performed to define the lateral dimensions of the chips. For that purpose, a photoresist layer was spun on the wafer (Figure ), and a photolithographic process was performed to define the lateral dimensions of the chips to 3×3 µm 2 (Figure ). Then, the silicon oxide layer was patterned by a dry etching process (Figure ). At this stage the devices were defined and the next processes were performed to prepare the release of the chips from the wafer.