Silicon chip based devices were fabricated using methods similar to those described by Creedon et al and Barry et al. [23] Each chip consisted of two combs of gold working IDEs. A platinum pseudo reference and gold counter electrode were also employed on-chip. In brief, chips were designed to interface with external electronics via a microSD port to facilitate facile electrical connection. Devices were batch fabricated on 4-inch silicon wafers bearing a thermally grown 300 nm silicon dioxide layer. Blanket metal evaporations of titanium (10 nm) and gold (100 nm) was undertaken using a Temescal FC-2000 E-beam evaporator and lift-off technique yields interdigitated microband (L 55 µm x W, 1 µm x H 110 nm) structures with separations between the tines of each comb maintained at 1 µm. 1 µm is defined by the mask, but this can result in electrode widths of 0.75 µm and gaps of 1.25 µm. A second metal evaporation and lift-off process was undertaken to define the interconnection tracks, contact pads and the gold counter electrode (90 µm x 7 mm). To prevent unwanted interactions along the connection tracks, silicon nitride, which acts as an insulating layer, was deposited by plasma enhanced chemical vapor deposition. Photolithography and dry etching were utilized to selectively open windows (45 μm x 100 μm) in the insulating SiN3 layer over the microband electrodes for electrolyte access. Openings were also created over the counter and reference electrodes and the contact pads. Each chip contains six IDE (sensors) which are separated by 0.94 mm to prevent cross talk between the sensors. Once sensor fabrication was completed, each wafer was diced to yield 28 separate chips.