Fabrication of GFET Arrays. Figure shows experimental procedures, including the fabrication process, Raman analysis, and electrical measurement of GFET arrays (see Experimental Details). First, CVD-grown graphene/Cu was coated with polymethyl methacrylate (PMMA). The Cu film was subsequently etched away, and the PMMA/graphene films were wettransferred onto SiO2/Si substrates, where the source/drain electrode lines were pre-deposited. The films were patterned using oxygen plasma etching, followed by PMMA layer removal. The resulting GFETs were arranged in an array of six rows and nine columns, comprising 54 GFETs per chip, with both the channel length and width set to 100 μm (Figure (a) and Figure in Supporting Information). After fabrication, the GFET arrays were examined using slit-scanning Raman microscopy, where a patented line illumination excites Raman scattered light along the line-illuminated area. The laser line was scanned in one direction to acquire Raman images. Finally, the GFETs were electrically tested in a solution-gated configuration.