Analogue to digital conversion and digital signal processing is carried out on a Teensy 4.0 microcontroller development board (PJRC). The Teensy 4.0 has a fast 600-MHz ARM processor with on-board Floating Point Unit (FPU), allowing it to efficiently carry out the calculations needed to implement digital lock-in detection. In brief, a sampled periodic signal 𝑆 of frequency 𝑓 0 is multiplied by sinusoidal and cosinusoidal reference signals of matching frequency 𝑓 0 , and the resulting output signals are passed through separate digital low-pass filters to remove non-DC components (see the block diagram in Fig. ). Following low-pass filtering we obtain two scalar outputs 𝑋 and 𝑌 derived from the two reference signals. 𝑋 and 𝑌 are vectorially combined to obtain an output signal 𝑅 = √(𝑋 2 + 𝑌 2 ) that is directly proportional to the amplitude of 𝑆. (Formally, 𝑅 corresponds to the amplitude of the first harmonic of 𝑆). The process repeats every time a new sample is acquired, so the lock-in outputs 𝑋, 𝑌 and 𝑅 are updated at the sample rate of the ADC. 𝑅 is affected only by input signals that are very close in frequency to 𝑓 0 so the target signal 𝑆 may be reliably measured even if it is corrupted by significant noise and/or interferences at other frequencies. A detailed description of the lock-in method is provided in the Supporting Information. Computationally, the lock-in procedure is carried out as follows. The low-pass filtering step is carried out by exponentially averaging 𝑋 0 (𝑛) and 𝑌 0 (𝑛), which yields two intermediate outputs 𝑋 1 (𝑛) and 𝑌 1 (𝑛):