The first setup involved creating three OR gates, known as the OR configuration (Figure ), and three AND gates, known as the AND configuration (Figure ). The truth tables for each configuration are provided in Table . In the OR configuration, input signals A and B are set to 25 mHz, while inputs C and D are set to 50 mHz (Figure ). The outputs from the first two gates, F (output of A and B) and E (output of C and D), serve as inputs to a third gate. The output signal followed the design of the electronic circuit, matching the expected results outlined in the truth table (Table ). It was noted that the baseline for the OR connection shifted to a more negative value. Figure shows the output signal for the OR gate when 0V was applied as the input, indicating a negative shift. A similar shift occurred in the AND gate output, but in a positive direction. These shifts are likely attributed to the internal resistance of the electrochemical devices and their connections. Nonetheless, the output signal across the three OR connections aligned with the expected design. . When the input frequency ratios between A and C, and B and D, were set to 1:2, the output signal (Figure ) matched the theoretical calculations. Similarly, with a frequency ratio of 1:3, the output achieved the expected results (Figure ). As the frequency difference between the inputs increased, cross-talk between the channels became more pronounced. This effect is likely due to one of the devices charging and discharging multiple times (three times) while the other devices remained under the same conditions. For another configuration, where two AND gates were connected to an OR gate (Figure ), the output signals at different frequencies (Figure , i) also matched the theoretical values outlined in Table . Furthermore, the efficiency of constructed devices was further tested under different input frequencies (Figure ). The constructed logic gates under the configurations (Figure , d, g, and S26) were tested under four different frequencies for input signals of (0.5, 0.25, 0.167, and 0.125 Hz). The output signal of all constructed logic gates with different configurations fits theoretical calculations (Table ). Furthermore, Figure presents the output when both inputs A, and B are 0 for OR and AND gate, respectively.