Heavy scaling of DRAM nodes requires unique propositions to improve electrical performances . Bit contact region is one of the most heavily affected regions due to the scaling down of DRAM nodes. The resistance increases exponentially with smaller critical dimensions (CDs) . The current junction for BC is made with a polycrystalline Si plug, followed by metallic silicidation using Ti deposition and rapid thermal annealing . This technique, called poly bit con (PBC) has been the standard process/structure for making BCs .