2.3. Chips fabrication IDEs with 10 µm gaps were fabricated on silicon chip substrates. Each silicon chip comprised six sensors containing two IDEs, a gold counter electrode, and a platinum pseudo-reference electrode. Gold contact pads and interconnection metallisation on two sides of the chip allowed electrical connection to both IDEs. The method of chip fabrication was described previously . In brief, fourinch silicon wafer substrates bearing a ~300 nm layer of thermally grown silicon dioxide were used. IDEs were first fabricated using optical lithography, metal evaporation (Ti 10 nm /Au 150 nm Temescal FC-2000 E-beam evaporator) and lift-off techniques to yield well-defined, stacked metallic (Ti/Au) microband (1 µm width, 50 nm height, 45 µm length) structures. Each chip comprised six independent sensors. A second optical lithographic and metal deposition (Ti 10 nm/Ni 70 nm/Au 200 nm) process was then undertaken to define a MicroSD pin-out, interconnection tracks, as well as counter electrodes (500 µm wide x 10 mm long). Finally, a passivation SiNX layer was deposited on the chip by PECVD, with windows opened in this layer directly above the working, reference and counter electrodes. The windows defined the length of the working electrode to be 45 µm. In this work, an on-chip microSD style electrical pin-out was included to permit a facile electrical connection to external electronics. In this manner, chips could be easily swapped in and out with the potentiostat, enabling rapid analysis of multiple samples. A custom-built cell was designed and fabricated so that when screwed together, the microSD primary contact pads protruded out of the holder to allow connection with a PCB mounted microSD port.