Interdigitated microelectrodes (IDE) array chips were designed and fabricated in Tyndall National Institute semiconductor cleanroom facilities using microfabrication techniques of photolithography, metal deposition, lift-off and etching. The process of chip fabrication was akin to the methods outlined in prior studies . 4-inch silicon wafers were cleaned by sequentially washing in acetone, isopropyl alcohol (IPA), and deionized (DI) water for 5 min each. Wafers contained a pre-deposited, ∼300 nm thick silicon dioxide (SiO2) passivation layer, deposited thermally on the substrate via plasma enhanced chemical vapor deposition (PECVD). S1813 photoresist (PR) was then spin coated on the wafer and patterned for the six individual sensor IDEs by using Metal mask-1. The Titanium:Gold (Ti:Au) was deposited by electron beam evaporator (E-Beam) with a thickness of 20:150 nm and subsequent lift-off process to yield well defined comb structure (Ti/Au) microband IDEs (1 μm width, 150 nm height, 80 μm length). Then the photolithographic process was carried away by using Metal mask-2 to transfer the pattern of contact pads, interconnection tracks (leads), reference and counter electrodes (500 μm in width and 10 mm in length) areas and sonicated for 2-3 s for lift-off operation. After that, a Metal mask-3 was utilized in the process flow which involved two phases of Ti:Au deposition for the sensing IDEs, contacts, leads, and both the CE and RE. This was followed by the sequential deposition of Titanium (Ti), Nickel (Ni), and Platinum (Pt) metals to form a RE, after which a lift-off process was implemented. The silicon wafer was then passivated using a silicon nitride (Si3N4) with a thickness of 500 nm and by using reactive-ion etching (RIE), the windows for the six sensing IDEs, counter-reference electrodes and contact pads were etched away. For the etching process, a passivation mask was employed. Lastly, the wafer was obscured with a protective photoresists layer (AR-PC 500) to ensure no physical damage while doing the mechanical dicing process to the chips. The overall fabrication process are depicted in Fig. .