def resolve_memory_access(self, tb, x86_mem_operand):
        """Return operand memory access translation.
        """
        size = self.__get_memory_access_size(x86_mem_operand)

        addr = None

        if x86_mem_operand.base:
            addr = ReilRegisterOperand(x86_mem_operand.base, size)

        if x86_mem_operand.index and x86_mem_operand.scale != 0x0:
            index = ReilRegisterOperand(x86_mem_operand.index, size)
            scale = ReilImmediateOperand(x86_mem_operand.scale, size)
            scaled_index = tb.temporal(size)

            tb.add(tb._builder.gen_mul(index, scale, scaled_index))

            if addr:
                tmp = tb.temporal(size)

                tb.add(tb._builder.gen_add(addr, scaled_index, tmp))

                addr = tmp
            else:
                addr = scaled_index

        if x86_mem_operand.displacement != 0x0:
            disp = ReilImmediateOperand(x86_mem_operand.displacement, size)

            if addr:
                tmp = tb.temporal(size)

                tb.add(tb._builder.gen_add(addr, disp, tmp))

                addr = tmp
            else:
                addr = disp
        else:
            if not addr:
                disp = ReilImmediateOperand(x86_mem_operand.displacement, size)

                addr = disp

        # TODO Improve this code and add support for the rest of the segments.
        if x86_mem_operand.segment in ["gs", "fs"]:
            seg_base_addr_map = {
                "gs": "gs_base_addr",
                "fs": "fs_base_addr",
            }

            seg_base = ReilRegisterOperand(seg_base_addr_map[x86_mem_operand.segment], size)

            if addr:
                tmp = tb.temporal(size)

                tb.add(tb._builder.gen_add(addr, seg_base, tmp))

                addr = tmp
            else:
                addr = seg_base

        return addr
Return operand memory access translation.