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peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd | 4 | 2011 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2948.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02948ent IS
END c02s02b00x00p08n02i02948ent;
ARCHITECTURE c02s02b00x00p08n02i02948arch OF c02s02b00x00p08n02i02948ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
I2 <= '1';
I3 <= 6;
end PX; -- No_failure_here
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert NOT(S3='1' and S2=6)
report "***PASSED TEST: c02s02b00x00p08n02i02948"
severity NOTE;
assert (S3='1' and S2=6)
report "***FAILED TEST: c02s02b00x00p08n02i02948 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02948arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2213.vhd | 4 | 1942 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2213.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02213ent IS
END c07s02b06x00p01n01i02213ent;
ARCHITECTURE c07s02b06x00p01n01i02213arch OF c07s02b06x00p01n01i02213ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- Local declarations.
variable SWITCHV : SWITCH_LEVEL := '0';
variable LOGICV : LOGIC_SWITCH := '0';
variable k : integer;
BEGIN
k := LOGICV rem SWITCHV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02213 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02213arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd | 4 | 1832 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1292.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p05n01i01292ent IS
END c08s04b00x00p05n01i01292ent;
ARCHITECTURE c08s04b00x00p05n01i01292arch OF c08s04b00x00p05n01i01292ent IS
signal done : integer;
BEGIN
TESTING: PROCESS
BEGIN
done <= 1 after 10 ns,
0 after 20 ns,
5 after 35 ns;
wait for 70 ns;
assert NOT( done=5 )
report "***PASSED TEST: c08s04b00x00p05n01i01292"
severity NOTE;
assert (done=5)
report "***FAILED TEST: c08s04b00x00p05n01i01292 - The waveform consists of one or more waveform elements separated with commas(,)."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p05n01i01292arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1095.vhd | 4 | 2068 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1095.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01095ent IS
END c06s05b00x00p03n01i01095ent;
ARCHITECTURE c06s05b00x00p03n01i01095arch OF c06s05b00x00p03n01i01095ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V2 := (1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
-- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01095 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01095arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd | 4 | 1884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01307ent IS
END c08s04b00x00p06n01i01307ent;
ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
type UA is array (NATURAL range <>) of BIT;
subtype ARAY_1 is UA (0 to 500);
signal S2 : ARAY_1;
signal S1 : BIT := '1';
BEGIN
TESTING: PROCESS
BEGIN
S2(200) <= S1;
wait for 1 ns;
assert NOT(S2(200) = '1')
report "***PASSED TEST: c08s04b00x00p06n01i01307"
severity NOTE;
assert (S2(200) = '1')
report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01307arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd | 4 | 1600 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity quad_opamp_wa is
port (terminal n1, n2, output : electrical_vector(1 to 4));
end entity quad_opamp_wa ;
----------------------------------------------------------------
architecture slew_limited of quad_opamp_wa is
quantity vin across n1 to n2;
quantity vout across iout through output;
quantity vamp1 : real;
quantity vamp2 : real;
quantity vamp3 : real;
quantity vamp4 : real;
constant gain : real := 50.0;
begin
vamp1 == gain*vin(1);
vamp2 == gain*vin(2);
vamp3 == gain*vin(3);
vamp4 == gain*vin(4);
vout(1) == vamp1'slew(1.0e6,-1.0e6);
vout(2) == vamp2'slew(1.0e6,-1.0e6);
vout(3) == vamp3'slew(1.0e6,-1.0e6);
vout(4) == vamp4'slew(1.0e6,-1.0e6);
end architecture slew_limited ;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd | 4 | 1948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02412ent IS
END c07s03b02x00p09n01i02412ent;
ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
type T1 is array (1 to 5) of integer;
constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***PASSED TEST: c07s03b02x00p09n01i02412"
severity NOTE;
assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4)
report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02412arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc372.vhd | 4 | 1879 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00372ent IS
END c03s02b01x01p03n02i00372ent;
ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A5 is array (FALSE to FALSE,
BFALSE range <>,
1 to 2) of BIT; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00372arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd | 4 | 2379 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package random is
type distribution_type is (fixed, uniform, exponential);
subtype probability is real range 0.0 to 1.0;
type probability_vector is array (positive range <>) of probability;
type seed_type is record
seed1, seed2 : positive;
end record seed_type;
type seed_array is array ( natural range <> ) of seed_type;
constant sample_seeds : seed_array(0 to 50);
type random_info_record is record
seed : seed_type;
distribution : distribution_type;
mean : real;
lower_bound, upper_bound : real;
end record random_info_record;
procedure init_fixed ( random_info : out random_info_record;
mean : in real );
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type );
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type );
procedure generate_random ( random_info : inout random_info_record;
random_number : out real );
end package random;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd | 4 | 17205 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-b.vhd,v 1.4 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.4 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
library work;
use work.dlx_instr.all;
architecture behavior of dlx is
begin
interpreter : process
is
type reg_array is array (reg_index) of dlx_bv_word;
variable reg : reg_array;
variable fp_reg : reg_array;
variable PC : dlx_bv_word;
constant PC_incr : dlx_bv_word := X"0000_0004";
variable IR : dlx_bv_word;
alias IR_opcode : dlx_opcode is IR(0 to 5);
alias IR_sp_func : dlx_sp_func is IR(26 to 31);
alias IR_fp_func : dlx_fp_func is IR(27 to 31);
alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
alias IR_immed16 : dlx_immed16 is IR(16 to 31);
alias IR_immed26 : dlx_immed26 is IR(6 to 31);
variable disassembled_instr : string(1 to 40);
variable disassembled_instr_len : positive;
variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
variable mem_addr_reg : dlx_bv_address;
variable mem_data_reg : dlx_bv_word;
variable overflow : boolean;
-- lookup table for result of set instructions
type set_result_table is array (boolean) of dlx_bv_word;
constant set_if : set_result_table := ( false => X"0000_0000",
true => X"0000_0001" );
variable instr_count : natural;
-- local procedures for use within the interpreter
procedure bus_read ( address : in dlx_bv_address;
data_width : in dlx_mem_width;
instr_fetch : in std_logic;
data : out dlx_bv_word ) is
begin
wait until rising_edge(phi1);
if To_bit(reset) = '1' then
return;
end if;
a <= To_X01(address) after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
ifetch <= instr_fetch after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
assert not Is_X(d) report "Bus read data contains unknown bits";
data := To_bitvector(d);
mem_enable <= '0' after Tpd_clk_out;
end procedure bus_read;
procedure bus_write ( address : in dlx_bv_address;
data_width : in dlx_mem_width;
data : in dlx_bv_word ) is
begin
wait until rising_edge(phi1);
if To_bit(reset) = '1' then
return;
end if;
a <= To_X01(address) after Tpd_clk_out;
ifetch <= '0' after Tpd_clk_out;
width <= data_width after Tpd_clk_out;
d <= To_X01Z(data) after Tpd_clk_out;
write_enable <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
loop
wait until falling_edge(phi2);
if To_bit(reset) = '1' then
return;
end if;
exit when To_bit(ready) = '1';
end loop;
d <= disabled_dlx_word after Tpd_clk_out;
write_enable <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end procedure bus_write;
procedure execute_op_special is
begin
case IR_sp_func is
when sp_func_nop =>
null;
when sp_func_add =>
bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_addu =>
bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sub =>
bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_subu =>
bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
when sp_func_sll =>
reg(Rtype_rd) := reg(rs1) sll bv_to_natural(reg(rs2)(27 to 31));
when sp_func_srl =>
reg(Rtype_rd) := reg(rs1) srl bv_to_natural(reg(rs2)(27 to 31));
when sp_func_sra =>
reg(Rtype_rd) := reg(rs1) sra bv_to_natural(reg(rs2)(27 to 31));
when sp_func_and =>
reg(Rtype_rd) := reg(rs1) and reg(rs2);
when sp_func_or =>
reg(Rtype_rd) := reg(rs1) or reg(rs2);
when sp_func_xor =>
reg(Rtype_rd) := reg(rs1) xor reg(rs2);
when sp_func_sequ =>
reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
when sp_func_sneu =>
reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
when sp_func_sltu =>
reg(Rtype_rd) := set_if( reg(rs1) < reg(rs2) );
when sp_func_sgtu =>
reg(Rtype_rd) := set_if( reg(rs1) > reg(rs2) );
when sp_func_sleu =>
reg(Rtype_rd) := set_if( reg(rs1) <= reg(rs2) );
when sp_func_sgeu =>
reg(Rtype_rd) := set_if( reg(rs1) >= reg(rs2) );
when sp_func_seq =>
reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
when sp_func_sne =>
reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
when sp_func_slt =>
reg(Rtype_rd) := set_if( bv_lt(reg(rs1), reg(rs2)) );
when sp_func_sgt =>
reg(Rtype_rd) := set_if( bv_gt(reg(rs1), reg(rs2)) );
when sp_func_sle =>
reg(Rtype_rd) := set_if( bv_le(reg(rs1), reg(rs2)) );
when sp_func_sge =>
reg(Rtype_rd) := set_if( bv_ge(reg(rs1), reg(rs2)) );
when sp_func_movi2s | sp_func_movs2i
| sp_func_movf | sp_func_movd
| sp_func_movfp2i | sp_func_movi2fp =>
report sp_func_names(bv_to_natural(IR_sp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined special instruction function" severity error;
end case;
end procedure execute_op_special;
procedure execute_op_fparith is
begin
case IR_fp_func is
when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
| fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
| fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
| fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
| fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
| fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
| fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
| fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
report fp_func_names(bv_to_natural(IR_fp_func))
& " instruction not implemented" severity warning;
when others =>
report "undefined floating point instruction function" severity error;
end case;
end procedure execute_op_fparith;
procedure execute_load ( data_width : dlx_mem_width; unsigned : boolean ) is
variable temp : dlx_bv_word;
-- type for least-significant two bits of address
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
bus_read(mem_addr_reg, data_width, '0', mem_data_reg);
if To_bit(reset) = '1' then
return;
end if;
case data_width is
when dlx_mem_width_byte =>
case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
when B"00" =>
temp(0 to 7) := mem_data_reg(0 to 7);
when B"01" =>
temp(0 to 7) := mem_data_reg(8 to 15);
when B"10" =>
temp(0 to 7) := mem_data_reg(16 to 23);
when B"11" =>
temp(0 to 7) := mem_data_reg(24 to 31);
end case;
if unsigned then
reg(Itype_rd) := bv_zext(temp(0 to 7), 32);
else
reg(Itype_rd) := bv_sext(temp(0 to 7), 32);
end if;
when dlx_mem_width_halfword =>
if mem_addr_reg(1) = '0' then
temp(0 to 15) := mem_data_reg(0 to 15);
else
temp(0 to 15) := mem_data_reg(16 to 31);
end if;
if unsigned then
reg(Itype_rd) := bv_zext(temp(0 to 15), 32);
else
reg(Itype_rd) := bv_sext(temp(0 to 15), 32);
end if;
when dlx_mem_width_word =>
reg(Itype_rd) := mem_data_reg;
when others =>
null;
end case;
end procedure execute_load;
procedure execute_store ( data_width : dlx_mem_width ) is
variable temp : dlx_bv_word;
-- type for least-significant two bits of address
subtype ls_2_addr_bits is bit_vector(1 downto 0);
begin
mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
mem_data_reg := X"0000_0000";
case data_width is
when dlx_mem_width_byte =>
case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
when B"00" =>
mem_data_reg(0 to 7) := reg(Itype_rd)(0 to 7);
when B"01" =>
mem_data_reg(8 to 15) := reg(Itype_rd)(0 to 7);
when B"10" =>
mem_data_reg(16 to 23) := reg(Itype_rd)(0 to 7);
when B"11" =>
mem_data_reg(24 to 31) := reg(Itype_rd)(0 to 7);
end case;
when dlx_mem_width_halfword =>
if mem_addr_reg(1) = '0' then
mem_data_reg(0 to 15) := reg(Itype_rd)(0 to 15);
else
mem_data_reg(16 to 31) := reg(Itype_rd)(0 to 15);
end if;
when dlx_mem_width_word =>
mem_data_reg := reg(Itype_rd);
when others =>
null;
end case;
bus_write(mem_addr_reg, data_width, mem_data_reg);
end procedure execute_store;
begin -- interpreter
-- reset the processor
d <= disabled_dlx_word;
halt <= '0';
write_enable <= '0';
mem_enable <= '0';
reg(0) := X"0000_0000";
PC := X"0000_0000";
instr_count := 0;
wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
-- fetch-decode-execute loop
while To_bit(reset) /= '1' loop
-- fetch next instruction
instr_count := instr_count + 1;
if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
report "instruction count = " & natural'image(instr_count);
end if;
if debug >= msg_each_instruction then
report "fetching instruction";
end if;
bus_read( address => PC, data_width => dlx_mem_width_word,
instr_fetch => '1', data => IR );
exit when To_bit(reset) = '1';
if debug >= trace_each_instruction then
disassemble(IR, disassembled_instr, disassembled_instr_len);
report disassembled_instr(1 to disassembled_instr_len);
end if;
wait until rising_edge(phi1);
-- increment the PC to point to the following instruction
if debug = trace_each_step then
report "incrementing PC";
end if;
PC := bv_addu(PC, PC_incr);
-- decode the instruction
if debug = trace_each_step then
report "decoding instruction";
end if;
rs1 := bv_to_natural(IR_rs1);
rs2 := bv_to_natural(IR_rs2);
Itype_rd := bv_to_natural(IR_Itype_rd);
Rtype_rd := bv_to_natural(IR_Rtype_rd);
-- execute the instruction
if debug = trace_each_step then
report "executing instruction";
end if;
overflow := false;
case IR_opcode is
when op_special =>
execute_op_special;
when op_fparith =>
execute_op_fparith;
when op_j =>
PC := PC + bv_sext(IR_immed26, 32);
when op_jal =>
reg(link_reg) := PC;
PC := PC + bv_sext(IR_immed26, 32);
when op_jr =>
PC := reg(rs1);
when op_jalr =>
reg(link_reg) := PC;
PC := reg(rs1);
when op_beqz =>
if reg(rs1) = X"0000_0000" then
PC := PC + bv_sext(IR_immed16, 32);
end if;
when op_bnez =>
if reg(rs1) /= X"0000_0000" then
PC := PC + bv_sext(IR_immed16, 32);
end if;
when op_addi =>
bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_addui =>
bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subi =>
bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_subui =>
bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
when op_slli =>
reg(Itype_rd) := reg(rs1) sll bv_to_natural(IR_immed16(11 to 15));
when op_srli =>
reg(Itype_rd) := reg(rs1) srl bv_to_natural(IR_immed16(11 to 15));
when op_srai =>
reg(Itype_rd) := reg(rs1) sra bv_to_natural(IR_immed16(11 to 15));
when op_andi =>
reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
when op_ori =>
reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
when op_xori =>
reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
when op_lhi =>
reg(Itype_rd) := IR_immed16 & X"0000";
when op_sequi =>
reg(Itype_rd) := set_if( reg(rs1) = bv_zext(IR_immed16, 32) );
when op_sneui =>
reg(Itype_rd) := set_if( reg(rs1) /= bv_zext(IR_immed16, 32) );
when op_sltui =>
reg(Itype_rd) := set_if( reg(rs1) < bv_zext(IR_immed16, 32) );
when op_sgtui =>
reg(Itype_rd) := set_if( reg(rs1) > bv_zext(IR_immed16, 32) );
when op_sleui =>
reg(Itype_rd) := set_if( reg(rs1) <= bv_zext(IR_immed16, 32) );
when op_sgeui =>
reg(Itype_rd) := set_if( reg(rs1) >= bv_zext(IR_immed16, 32) );
when op_seqi =>
reg(Itype_rd) := set_if( reg(rs1) = bv_sext(IR_immed16, 32) );
when op_snei =>
reg(Itype_rd) := set_if( reg(rs1) /= bv_sext(IR_immed16, 32) );
when op_slti =>
reg(Itype_rd) := set_if( bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_sgti =>
reg(Itype_rd) := set_if( bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_slei =>
reg(Itype_rd) := set_if( bv_le(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_sgei =>
reg(Itype_rd) := set_if( bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) );
when op_trap =>
report "TRAP instruction encountered, execution halted" severity note;
halt <= '1' after Tpd_clk_out;
wait until To_bit(reset) = '1';
exit;
when op_lb =>
execute_load(data_width => dlx_mem_width_byte, unsigned => false);
exit when To_bit(reset) = '1';
when op_lh =>
execute_load(data_width => dlx_mem_width_halfword, unsigned => false);
exit when To_bit(reset) = '1';
when op_lw =>
execute_load(data_width => dlx_mem_width_word, unsigned => false);
exit when To_bit(reset) = '1';
when op_lbu =>
execute_load(data_width => dlx_mem_width_byte, unsigned => true);
exit when To_bit(reset) = '1';
when op_lhu =>
execute_load(data_width => dlx_mem_width_halfword, unsigned => true);
exit when To_bit(reset) = '1';
when op_sb =>
execute_store ( data_width => dlx_mem_width_byte );
exit when To_bit(reset) = '1';
when op_sh =>
execute_store ( data_width => dlx_mem_width_halfword );
exit when To_bit(reset) = '1';
when op_sw =>
execute_store ( data_width => dlx_mem_width_word );
exit when To_bit(reset) = '1';
when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd =>
report opcode_names(bv_to_natural(IR_opcode))
& " instruction not implemented" severity warning;
when others =>
report "undefined instruction" severity error;
end case;
-- fix up R0 in case it was overwritten
reg(0) := X"0000_0000";
-- overflow and divide-by-zero exception handing
-- (not implemented)
if debug = trace_each_step then
report "end of execution";
end if;
end loop;
-- loop is only exited when reset active:
-- process interpreter starts again from beginning
end process interpreter;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd | 4 | 1981 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_20_types is
-- code from book:
type FIFO_status is record
nearly_full, nearly_empty, full, empty : bit;
end record FIFO_status;
-- end of code from book
end package inline_20_types;
----------------------------------------------------------------
use work.inline_20_types.all;
entity FIFO is
port ( status : out FIFO_status;
other_ports : out bit );
end entity FIFO;
----------------------------------------------------------------
entity inline_20 is
end entity inline_20;
----------------------------------------------------------------
use work.inline_20_types.all;
architecture test of inline_20 is
signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
begin
-- code from book:
DMA_buffer : entity work.FIFO
port map ( -- . . .,
status.nearly_full => start_flush,
status.nearly_empty => end_flush,
status.full => DMA_buffer_full,
status.empty => DMA_buffer_empty, -- . . . );
-- not in book
other_ports => open );
-- end not in book
-- end of code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | libraries/ieee/math_complex.vhdl | 4 | 40109 | ------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common COMPLEX
-- constants and common COMPLEX mathematical functions and
-- operators.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to provide a guideline for
-- implementations to verify their implementation of MATH_COMPLEX.
-- Tool developers may choose to implement the package body in
-- the most efficient manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package MATH_COMPLEX is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Type Definitions
--
type COMPLEX is
record
RE: REAL; -- Real part
IM: REAL; -- Imaginary part
end record;
subtype POSITIVE_REAL is REAL range 0.0 to REAL'HIGH;
subtype PRINCIPAL_VALUE is REAL range -MATH_PI to MATH_PI;
type COMPLEX_POLAR is
record
MAG: POSITIVE_REAL; -- Magnitude
ARG: PRINCIPAL_VALUE; -- Angle in radians; -MATH_PI is illegal
end record;
--
-- Constant Definitions
--
constant MATH_CBASE_1: COMPLEX := COMPLEX'(1.0, 0.0);
constant MATH_CBASE_J: COMPLEX := COMPLEX'(0.0, 1.0);
constant MATH_CZERO: COMPLEX := COMPLEX'(0.0, 0.0);
--
-- Overloaded equality and inequality operators for COMPLEX_POLAR
-- (equality and inequality operators for COMPLEX are predefined)
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is equal to R and returns FALSE otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) = COMPLEX_POLAR'(0.0, Y) returns TRUE
-- regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "="(L,R) is either TRUE or FALSE
-- Notes:
-- None
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN;
-- Purpose:
-- Returns TRUE if L is not equal to R and returns FALSE
-- otherwise
-- Special values:
-- COMPLEX_POLAR'(0.0, X) /= COMPLEX_POLAR'(0.0, Y) returns
-- FALSE regardless of the value of X and Y.
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- "/="(L,R) is either TRUE or FALSE
-- Notes:
-- None
--
-- Function Declarations
--
function CMPLX(X: in REAL; Y: in REAL:= 0.0 ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX number X + iY
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- CMPLX(X,Y) is mathematically unbounded
-- Notes:
-- None
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns principal value of angle X; X in radians
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < GET_PRINCIPAL_VALUE(X) <= MATH_PI
-- Notes:
-- None
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value COMPLEX_POLAR of Z
-- Special values:
-- COMPLEX_TO_POLAR(MATH_CZERO) = COMPLEX_POLAR'(0.0, 0.0)
-- COMPLEX_TO_POLAR(Z) = COMPLEX_POLAR'(ABS(Z.IM),
-- SIGN(Z.IM)*MATH_PI_OVER_2) if Z.RE = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX;
-- Purpose:
-- Returns COMPLEX value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- POLAR_TO_COMPLEX(Z) is mathematically unbounded
-- Notes:
-- None
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(Z) is mathematically unbounded
-- Notes:
-- ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL;
-- Purpose:
-- Returns absolute value (magnitude) of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- ABS(Z) >= 0.0
-- Notes:
-- ABS(Z) = Z.MAG
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- ARG(Z) = 0.0 if Z.RE >= 0.0 and Z.IM = 0.0
-- ARG(Z) = SIGN(Z.IM)*MATH_PI_OVER_2 if Z.RE = 0.0
-- ARG(Z) = MATH_PI if Z.RE < 0.0 and Z.IM = 0.0
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = ARCTAN(Z.IM, Z.RE)
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE;
-- Purpose:
-- Returns argument (angle) in radians of the principal
-- value of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- -MATH_PI < ARG(Z) <= MATH_PI
-- Notes:
-- ARG(Z) = Z.ARG
function "-" (Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns unary minus of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- Returns -x -jy for Z= x + jy
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of unary minus of Z
-- Special values:
-- "-"(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, Z.ARG - SIGN(Z.ARG)*MATH_PI) if
-- Z.ARG /= 0.0
function CONJ (Z: in COMPLEX) return COMPLEX;
-- Purpose:
-- Returns complex conjugate of Z
-- Special values:
-- None
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- CONJ(Z) is mathematically unbounded
-- Notes:
-- Returns x -jy for Z= x + jy
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of complex conjugate of Z
-- Special values:
-- CONJ(Z) = COMPLEX_POLAR'(Z.MAG, MATH_PI) if Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- Returns COMPLEX_POLAR'(Z.MAG, -Z.ARG) if Z.ARG /= MATH_PI
function SQRT(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(MATH_CZERO) = MATH_CZERO
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- SQRT(Z) is mathematically unbounded
-- Notes:
-- None
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns square root of Z with positive real part
-- or, if the real part is zero, the one with nonnegative
-- imaginary part
-- Special values:
-- SQRT(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function EXP(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns exponential of Z
-- Special values:
-- EXP(MATH_CZERO) = MATH_CBASE_1
-- EXP(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and ABS(Z.IM) = MATH_PI
-- EXP(Z) = SIGN(Z.IM)*MATH_CBASE_J if Z.RE = 0.0 and
-- ABS(Z.IM) = MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- EXP(Z) is mathematically unbounded
-- Notes:
-- None
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of exponential of Z
-- Special values:
-- EXP(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG =0.0 and
-- Z.ARG = 0.0
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- ABS(Z.ARG) = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = MATH_PI_OVER_2
-- EXP(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if
-- Z.MAG = MATH_PI_OVER_2 and
-- Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns natural logarithm of Z
-- Special values:
-- LOG(MATH_CBASE_1) = MATH_CZERO
-- LOG(-MATH_CBASE_1) = COMPLEX'(0.0, MATH_PI)
-- LOG(MATH_CBASE_J) = COMPLEX'(0.0, MATH_PI_OVER_2)
-- LOG(-MATH_CBASE_J) = COMPLEX'(0.0, -MATH_PI_OVER_2)
-- LOG(Z) = MATH_CBASE_1 if Z = COMPLEX'(MATH_E, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG(Z) is mathematically unbounded
-- Notes:
-- None
function LOG2(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 2 of Z
-- Special values:
-- LOG2(MATH_CBASE_1) = MATH_CZERO
-- LOG2(Z) = MATH_CBASE_1 if Z = COMPLEX'(2.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG2(Z) is mathematically unbounded
-- Notes:
-- None
function LOG10(Z: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns logarithm base 10 of Z
-- Special values:
-- LOG10(MATH_CBASE_1) = MATH_CZERO
-- LOG10(Z) = MATH_CBASE_1 if Z = COMPLEX'(10.0, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Range:
-- LOG10(Z) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of natural logarithm of Z
-- Special values:
-- LOG(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2) if
-- Z.MAG = 1.0 and Z.ARG = -MATH_PI_OVER_2
-- LOG(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = MATH_E and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 2 of Z
-- Special values:
-- LOG2(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG2(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 2.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base 10 of Z
-- Special values:
-- LOG10(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG10(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 10.0 and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function LOG(Z: in COMPLEX; BASE: in REAL) return COMPLEX;
-- Purpose:
-- Returns logarithm base BASE of Z
-- Special values:
-- LOG(MATH_CBASE_1, BASE) = MATH_CZERO
-- LOG(Z,BASE) = MATH_CBASE_1 if Z = COMPLEX'(BASE, 0.0)
-- Domain:
-- Z in COMPLEX and ABS(Z) /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if ABS(Z) = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(Z,BASE) is mathematically unbounded
-- Notes:
-- None
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of logarithm base BASE of Z
-- Special values:
-- LOG(Z, BASE) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 1.0 and
-- Z.ARG = 0.0
-- LOG(Z, BASE) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = BASE and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Z.MAG /= 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Error if Z.MAG = 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SIN (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns sine of Z
-- Special values:
-- SIN(MATH_CZERO) = MATH_CZERO
-- SIN(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(Z)) <= SQRT(SIN(Z.RE)*SIN(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function SIN (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of sine of Z
-- Special values:
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SIN(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = 0.0
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COS (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns cosine of Z
-- Special values:
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(MATH_PI_OVER_2, 0.0)
-- COS(Z) = MATH_CZERO if Z = COMPLEX'(-MATH_PI_OVER_2, 0.0)
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COS(Z)) <= SQRT(COS(Z.RE)*COS(Z.RE) +
-- SINH(Z.IM)*SINH(Z.IM))
-- Notes:
-- None
function COS (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of cosine of Z
-- Special values:
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = 0.0
-- COS(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI_OVER_2
-- and Z.ARG = MATH_PI
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function SINH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic sine of Z
-- Special values:
-- SINH(MATH_CZERO) = MATH_CZERO
-- SINH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI
-- SINH(Z) = MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = MATH_PI_OVER_2
-- SINH(Z) = -MATH_CBASE_J if Z.RE = 0.0 and
-- Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(SINH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- SIN(Z.IM)*SIN(Z.IM))
-- Notes:
-- None
function SINH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic sine of Z
-- Special values:
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- SINH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- SINH(Z) = COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function COSH (Z : in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns hyperbolic cosine of Z
-- Special values:
-- COSH(MATH_CZERO) = MATH_CBASE_1
-- COSH(Z) = -MATH_CBASE_1 if Z.RE = 0.0 and Z.IM = MATH_PI
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = MATH_PI_OVER_2
-- COSH(Z) = MATH_CZERO if Z.RE = 0.0 and Z.IM = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX
-- Error conditions:
-- None
-- Range:
-- ABS(COSH(Z)) <= SQRT(SINH(Z.RE)*SINH(Z.RE) +
-- COS(Z.IM)*COS(Z.IM))
-- Notes:
-- None
function COSH (Z : in COMPLEX_POLAR ) return COMPLEX_POLAR;
-- Purpose:
-- Returns principal value of hyperbolic cosine of Z
-- Special values:
-- COSH(Z) = COMPLEX_POLAR'(1.0, 0.0) if Z.MAG = 0.0 and
-- Z.ARG = 0.0
-- COSH(Z) = COMPLEX_POLAR'(1.0, MATH_PI) if Z.MAG = MATH_PI and
-- Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2
-- COSH(Z) = COMPLEX_POLAR'(0.0, 0.0) if Z.MAG =
-- MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2
-- Domain:
-- Z in COMPLEX_POLAR and Z.ARG /= -MATH_PI
-- Error conditions:
-- Error if Z.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "+"(Z) is mathematically unbounded
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic addition of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "-"(Z) is mathematically unbounded
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic subtraction of L minus R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL
-- Error conditions:
-- None
-- Range:
-- "*"(Z) is mathematically unbounded
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- Error conditions:
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic multiplication of L and R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in REAL
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX and R /= MATH_CZERO
-- Error conditions:
-- Error if R = MATH_CZERO
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX
-- R in REAL and R /= 0.0
-- Error conditions:
-- Error if R = 0.0
-- Range:
-- "/"(Z) is mathematically unbounded
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if L.ARG = -MATH_PI
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in REAL
-- R in COMPLEX_POLAR and R.ARG /= -MATH_PI
-- R.MAG > 0.0
-- Error conditions:
-- Error if R.MAG <= 0.0
-- Error if R.ARG = -MATH_PI
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR;
-- Purpose:
-- Returns arithmetic division of L by R
-- Special values:
-- None
-- Domain:
-- L in COMPLEX_POLAR and L.ARG /= -MATH_PI
-- R /= 0.0
-- Error conditions:
-- Error if L.ARG = -MATH_PI
-- Error if R = 0.0
-- Range:
-- result.MAG >= 0.0
-- -MATH_PI < result.ARG <= MATH_PI
-- Notes:
-- None
end MATH_COMPLEX;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd | 4 | 1884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1461.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01461ent IS
END c08s07b00x00p04n01i01461ent;
ARCHITECTURE c08s07b00x00p04n01i01461arch OF c08s07b00x00p04n01i01461ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
end if;
assert NOT(k = 1)
report "***PASSED TEST: c08s07b00x00p04n01i01461"
severity NOTE;
assert (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01461 - the condition after the IF statement is TRUE in 'if-end if' format"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01461arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd | 4 | 3051 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity nor_gate is
generic ( width : positive;
Tpd01, Tpd10 : delay_length );
port ( input : in std_logic_vector(0 to width - 1);
output : out std_logic );
end entity nor_gate;
architecture primitive of nor_gate is
function max ( a, b : delay_length ) return delay_length is
begin
if a > b then
return a;
else
return b;
end if;
end function max;
begin
reducer : process (input) is
variable result : std_logic;
begin
result := '0';
for index in input'range loop
result := result or input(index);
end loop;
if not result = '1' then
output <= not result after Tpd01;
elsif not result = '0' then
output <= not result after Tpd10;
else
output <= not result after max(Tpd01, Tpd10);
end if;
end process reducer;
end architecture primitive;
library ieee; use ieee.std_logic_1164.all;
library cell_lib;
entity interlock_control is
end entity interlock_control;
-- code from book
architecture detailed_timing of interlock_control is
component nor_gate is
generic ( input_width : positive );
port ( input : in std_logic_vector(0 to input_width - 1);
output : out std_logic );
end component nor_gate;
for ex_interlock_gate : nor_gate
use entity cell_lib.nor_gate(primitive)
generic map ( width => input_width,
Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
-- . . .
-- not in book
signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
-- end not in book
begin
ex_interlock_gate : component nor_gate
generic map ( input_width => 2 )
port map ( input(0) => reg_access_hazard,
input(1) => load_hazard,
output => stall_ex_n);
-- . . .
-- not in book
reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
'0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
'0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
'0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
-- end not in book
end architecture detailed_timing;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc363.vhd | 4 | 1932 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc363.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n01i00363ent IS
END c03s02b01x01p03n01i00363ent;
ARCHITECTURE c03s02b01x01p03n01i00363arch OF c03s02b01x01p03n01i00363ent IS
type week is array (positive range <>) of integer;
type a is access week;
subtype weekend1 is week (10 to 20);
subtype weekend2 is a (10 to 20);
type week2 is array (1 to 10) of integer;
type b is access week2;
subtype weekend3 is week2 (1 to 2); -- Failure_here
subtype weekend4 is b (1 to 2); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n01i00363 - Index constraint not allowed in the subtype declaration of weekend3."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n01i00363arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug16/repro1.vhdl | 3 | 416 | entity repro is
end repro;
entity comp is
port (s : bit);
end comp;
architecture behav of repro is
component comp is
port (s : bit);
end component;
signal s : bit;
begin
c : comp port map (s);
end behav;
use work.pkg.all;
entity comp2 is
port (s : bit);
end comp2;
architecture behav of comp is
component comp2 is
port (s : bit);
end component;
begin
c2: comp2 port map (s);
end behav;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd | 4 | 1568 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_SR_flipflop is
end entity tb_SR_flipflop;
----------------------------------------------------------------
architecture test_checking of tb_SR_flipflop is
signal S, R, Q : bit := '0';
begin
dut : entity work.SR_flipflop(checking)
port map ( S => S, R => R, Q => Q );
stumulus : process is
begin
wait for 10 ns;
S <= '1'; wait for 10 ns;
S <= '0'; wait for 10 ns;
S <= '1'; wait for 10 ns;
S <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
S <= '1'; R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
S <= '0'; wait for 10 ns;
wait;
end process stumulus;
end architecture test_checking;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc153.vhd | 4 | 1961 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc153.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n01i00153pkg is
procedure P1 (a : in integer; b: inout integer);
end ch04030202_p01601_03_pkg;
package body c04s03b02x02p16n01i00153pkg is
procedure P1 (a: in integer; b: inout integer) is
begin
b := a;
end;
end c04s03b02x02p16n01i00153pkg;
use work.c04s03b02x02p16n01i00153pkg.all;
ENTITY c04s03b02x02p16n01i00153ent IS
END c04s03b02x02p16n01i00153ent;
ARCHITECTURE c04s03b02x02p16n01i00153arch OF c04s03b02x02p16n01i00153ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00153 - Type mismatch."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00153arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd | 3 | 1827 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc43.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00043ent IS
END c04s03b01x01p02n01i00043ent;
ARCHITECTURE c04s03b01x01p02n01i00043arch OF c04s03b01x01p02n01i00043ent IS
-- constant integer:integer := 1; -- No_failure_here
-- According to scopes and visibility rules, this test is not correct.
constant integer:natural := 1;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(integer = 1)
report "***PASSED TEST: c04s03b01x01p02n01i00043"
severity NOTE;
assert (integer = 1)
report "***FAILED TEST:c04s03b01x01p02n01i00043 - Constant declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00043arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd | 4 | 1903 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1634.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01634ent IS
END c08s12b00x00p05n01i01634ent;
ARCHITECTURE c08s12b00x00p05n01i01634arch OF c08s12b00x00p05n01i01634ent IS
BEGIN
TESTING: PROCESS
type E is (A,B,C,D);
subtype E1 is E range C to D;
function F return E is
variable V : E1 := C;
begin
return V;
end F;
variable k : E := A;
BEGIN
k := F;
assert NOT(k = C)
report "***PASSED TEST: c08s12b00x00p05n01i01634"
severity NOTE;
assert (k = C)
report "***FAILED TEST: c08s12b00x00p05n01i01634 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01634arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2624.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02624ent IS
END c13s03b01x00p02n01i02624ent;
ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
BEGIN
TESTING: PROCESS
variable k{k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02624arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd | 4 | 2319 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc658.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00658ent IS
END c03s04b01x00p01n01i00658ent;
ARCHITECTURE c03s04b01x00p01n01i00658arch OF c03s04b01x00p01n01i00658ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type time_vector is array (natural range <>) of time;
subtype time_vector_range is time_vector(hi_to_low_range);
constant C1 : time_vector_range := (others => 3 ns);
type time_vector_range_file is file of time_vector_range;
BEGIN
TESTING: PROCESS
file filein : time_vector_range_file open write_mode is "iofile.07";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00658 - The output file will be verified by test s010108.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00658arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00333ent IS
END c03s02b01x00p06n01i00333ent;
ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
type bit_vctor is array (1 to 8, 1 to 8) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1,8) := 56;
assert NOT(k(1,8)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00333"
severity NOTE;
assert (k(1,8)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00333arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-rightof.vhdl | 4 | 438 | entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'rightof(1) = 2 report "TEST FAILED. rightof 1 = 2" severity FAILURE;
report "TEST PASSED rightof 1 = 2" severity NOTE;
assert small'rightof(2) = 3 report "TEST FAILED. rightof 2 = 3" severity FAILURE;
report "TEST PASSED rightof 2 = 3" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd | 4 | 2028 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc637.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:50 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00637ent IS
END c03s04b01x00p01n01i00637ent;
ARCHITECTURE c03s04b01x00p01n01i00637arch OF c03s04b01x00p01n01i00637ent IS
subtype word is bit_vector(0 to 15);
type word_file is file of word;
constant C38 : word := (others => '1');
BEGIN
TESTING: PROCESS
file filein : word_file open write_mode is "iofile.41";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00637 - The output file will be verified by test s010284.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00637arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1041.vhd | 4 | 1656 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01041ent IS
END c06s04b00x00p03n01i01041ent;
ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if k(1) = 1 then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01041arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd | 4 | 23127 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc751.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00751ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00751ent;
ARCHITECTURE c01s01b01x01p05n02i00751arch OF c01s01b01x01p05n02i00751ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) ;
variable V2 : severity_level_vector(zero to fifteen);
variable V3 : integer_vector(zero to fifteen) ;
variable V4 : real_vector(zero to fifteen) ;
variable V5 : time_vector (zero to fifteen);
variable V6 : natural_vector(zero to fifteen);
variable V7 : positive_vector(zero to fifteen);
variable V8 : boolean_cons_vector;
variable V9 : severity_level_cons_vector ;
variable V10 : integer_cons_vector;
variable V11 : real_cons_vector;
variable V12 : time_cons_vector ;
variable V13 : natural_cons_vector ;
variable V14 : positive_cons_vector ;
variable V15 : boolean_cons_vectorofvector ;
variable V16 : severity_level_cons_vectorofvector;
variable V17 : integer_cons_vectorofvector;
variable V18 : real_cons_vectorofvector;
variable V19 : time_cons_vectorofvector;
variable V20 : natural_cons_vectorofvector;
variable V21 : positive_cons_vectorofvector;
variable V22 : record_std_package;
variable V23 : record_cons_array ;
variable V24 : record_cons_arrayofarray ;
variable V25 : boolean_vector_st ;
variable V26 : severity_level_vector_st ;
variable V27 : integer_vector_st ;
variable V28 : real_vector_st ;
variable V29 : time_vector_st ;
variable V30 : natural_vector_st ;
variable V31 : positive_vector_st ;
variable V32 : record_array_st ;
variable V33 : record_array_st ;
variable V34 : record_array_new ;
variable V35 : record_of_records ;
variable V36 : byte ;
variable V37 : word ;
variable V41 : boolean_vector_range ;
variable V42 : severity_level_vector_range ;
variable V43 : integer_vector_range ;
variable V44 : real_vector_range ;
variable V45 : time_vector_range ;
variable V46 : natural_vector_range ;
variable V47 : positive_vector_range ;
variable V48 : array_rec_std(zero to seven) ;
variable V49 : array_rec_cons(zero to seven) ;
variable V50 : array_rec_rec(zero to seven) ;
variable V51 : record_of_arr_of_record ;
BEGIN
V1 := (zero to fifteen => C1);
V2 := (zero to fifteen => C4);
V3 := (zero to fifteen => C5);
V4 := (zero to fifteen => C6);
V5 := (zero to fifteen => C7);
V6 := (zero to fifteen => C8);
V7 := (zero to fifteen => C9);
V8 := C19;
V9 := C20;
V10 := C21;
V11 := C22;
V12 := C23;
V13 := C24;
V14 := C25;
V15 := C26;
V16 := C27;
V17 := C28;
V18 := C29;
V19 := C30;
V20 := C31;
V21 := C32;
V22 := C50;
V23 := C51;
V24 := C53;
V25 := C70;
V26 := C71;
V27 := C72;
V28 := C73;
V29 := C74;
V30 := C75;
V31 := C76;
V32 := C54a;
V33 := C54a;
V34 := C54b;
V35 := C55;
V36 := C60;
V37 := C61;
V41 := C78;
V42 := C79;
V43 := C80;
V44 := C81;
V45 := C82;
V46 := C83;
V47 := C84;
V48 := C85;
V49 := C86;
V50 := C88;
V51 := C102;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00751"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00751 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00751arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd | 4 | 1764 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1923.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01923ent IS
END c07s02b01x00p01n01i01923ent;
ARCHITECTURE c07s02b01x00p01n01i01923arch OF c07s02b01x00p01n01i01923ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 nand b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01923"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01923 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01923arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd | 4 | 5629 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
package body random is
use math.math_real;
constant sample_seeds : seed_array(0 to 50)
:= ( 0 => (1, 1),
1 => (1919456777, 2006618587),
2 => (928906921, 476680813),
3 => (715788085, 762347824),
4 => (366002668, 1804336679),
5 => (1866585254, 247488051),
6 => (1342990589, 1539624735),
7 => (677313287, 1675609237),
8 => (644816519, 2026475269),
9 => (1654953611, 564421524),
10 => (1020104619, 712556314),
11 => (609798541, 1592526288),
12 => (1106087470, 1468242308),
13 => (1378844312, 646793513),
14 => (966261604, 481733031),
15 => (1407842093, 1316990206),
16 => (1705378215, 1930221363),
17 => (206887499, 1810320799),
18 => (1681633030, 2114795480),
19 => (71194926, 1642522201),
20 => (663275331, 1947299255),
21 => (224432387, 944962866),
22 => (1156075861, 1866435087),
23 => (1670357576, 1247152991),
24 => (846934138, 1673364736),
25 => (1972636955, 1404522710),
26 => (533484185, 592078395),
27 => (1989468008, 1409246301),
28 => (697086615, 1975145057),
29 => (111393259, 1673620688),
30 => (1352201163, 872947497),
31 => (1342844190, 877696585),
32 => (938770066, 1222894811),
33 => (1144599578, 661919919),
34 => (1750521407, 269946538),
35 => (457892500, 1256953520),
36 => (1678589945, 356027520),
37 => (1484458924, 2103068828),
38 => (1296978761, 2124096638),
39 => (1702642440, 1161000593),
40 => (1244690090, 2016422304),
41 => (1858682943, 1053836731),
42 => (1496964676, 701079294),
43 => (432696952, 602526767),
44 => (2097684438, 1264032473),
45 => (2115456834, 298917738),
46 => (432301768, 232430346),
47 => (1929812456, 758157910),
48 => (1655564027, 1062345086),
49 => (1116121051, 538424126),
50 => (844396720, 821616997) );
procedure init_fixed ( random_info : out random_info_record;
mean : in real ) is
begin
random_info.distribution := fixed;
random_info.mean := mean;
end procedure init_fixed;
procedure init_uniform ( random_info : out random_info_record;
lower_bound, upper_bound : in real;
seed : in seed_type ) is
begin
assert lower_bound <= upper_bound
report "init_uniform: lower_bound > upper_bound" severity failure;
random_info.distribution := uniform;
random_info.lower_bound := lower_bound;
random_info.upper_bound := upper_bound;
random_info.seed := seed;
end procedure init_uniform;
procedure init_exponential ( random_info : out random_info_record;
mean : in real;
seed : in seed_type ) is
begin
assert mean > 0.0
report "init_exponential: mean not positive" severity failure;
random_info.distribution := exponential;
random_info.mean := mean;
random_info.seed := seed;
end procedure init_exponential;
procedure generate_uniform ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
random_number := random_info.lower_bound
+ tmp * (random_info.upper_bound - random_info.lower_bound);
end procedure generate_uniform;
procedure generate_exponential ( random_info : inout random_info_record;
random_number : out real ) is
variable tmp : real;
begin
loop
math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
exit when tmp /= 0.0;
end loop;
random_number := - random_info.mean * math_real.log(tmp);
end procedure generate_exponential;
procedure generate_random ( random_info : inout random_info_record;
random_number : out real ) is
begin
case random_info.distribution is
when fixed =>
random_number := random_info.mean;
when uniform =>
generate_uniform(random_info, random_number);
when exponential =>
generate_exponential(random_info, random_number);
end case;
end procedure generate_random;
end package body random;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd | 4 | 2387 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2132.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02132ent IS
END c07s02b04x00p21n01i02132ent;
ARCHITECTURE c07s02b04x00p21n01i02132arch OF c07s02b04x00p21n01i02132ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_5 is record_v (1 to 5);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : record_5;
variable l_operand : simple_record := (12,34) ;
variable r_operand : record_4 := ((12,34), (56,78), (12,34), (56,78));
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
report "***PASSED TEST: c07s02b04x00p21n01i02132"
severity NOTE;
assert ( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
report "***FAILED TEST:c07s02b04x00p21n01i02132 - Concatenation of element and RECORD array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02132arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd | 4 | 2150 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p01n01i02736ent IS
END c13s06b00x00p01n01i02736ent;
ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
BEGIN
TESTING: PROCESS
variable S45 : STRING (1 to 44);
variable S50 : STRING (1 to 50);
BEGIN
S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
wait for 5 ns;
assert NOT( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***PASSED TEST: c13s06b00x00p01n01i02736"
severity NOTE;
assert ( S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p01n01i02736arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc979.vhd | 4 | 1927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc979.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00979ent IS
END c06s03b00x00p05n01i00979ent;
ARCHITECTURE c06s03b00x00p05n01i00979arch OF c06s03b00x00p05n01i00979ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
function F1 return R1 is
begin
return (RE1=>TRUE);
end F1;
variable V1: R1 ;
variable V2: R2 ;
variable V10: BOOLEAN;
BEGIN
V10 := F1.RE2;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00979 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00979arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd | 4 | 1813 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n01i02697ent IS
END c13s04b01x00p05n01i02697ent;
ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
constant a : real := 2.34;
constant b : real := 2.3_4;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a=b )
report "***PASSED TEST: c13s04b01x00p05n01i02697"
severity NOTE;
assert ( a=b )
report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n01i02697arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2050.vhd | 4 | 1671 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2050.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02050ent IS
END c07s02b04x00p01n01i02050ent;
ARCHITECTURE c07s02b04x00p01n01i02050arch OF c07s02b04x00p01n01i02050ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := STRINGV - "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02050 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02050arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd | 4 | 10183 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc856.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00856pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00856pkg_b;
package body c01s03b01x00p12n01i00856pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00856pkg_b;
use work.c01s03b01x00p12n01i00856pkg_b.all;
package c01s03b01x00p12n01i00856pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010";
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00856pkg_a;
use work.c01s03b01x00p12n01i00856pkg_a.all;
use work.c01s03b01x00p12n01i00856pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00856pkg_a.all;
use work.c01s03b01x00p12n01i00856pkg_b.all;
ENTITY c01s03b01x00p12n01i00856ent IS
END c01s03b01x00p12n01i00856ent;
ARCHITECTURE c01s03b01x00p12n01i00856arch OF c01s03b01x00p12n01i00856ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00856"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00856 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00856arch;
configuration c01s03b01x00p12n01i00856cfg of c01s03b01x00p12n01i00856ent is
for c01s03b01x00p12n01i00856arch
for K
for T5:test use configuration work.testbench;
end for;
for G(hi_to_low_range)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1966.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01966ent IS
END c07s02b01x00p02n02i01966ent;
ARCHITECTURE c07s02b01x00p02n02i01966arch OF c07s02b01x00p02n02i01966ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := FALSE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a nand b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01966"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01966 - Logical operation of 'NAND'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01966arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1937.vhd | 4 | 1944 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1937.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01937ent IS
END c07s02b01x00p01n04i01937ent;
ARCHITECTURE c07s02b01x00p01n04i01937arch OF c07s02b01x00p01n04i01937ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a and b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01937 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01937arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2247.vhd | 4 | 1927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2247.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02247ent IS
END c07s02b06x00p01n01i02247ent;
ARCHITECTURE c07s02b06x00p01n01i02247arch OF c07s02b06x00p01n01i02247ent IS
BEGIN
TESTING: PROCESS
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
variable RECV : DATE;
variable k : integer;
BEGIN
k := RECV rem ( DAY => 14, MONTH => 2, YEAR => 1988 );
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02247 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02247arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2571.vhd | 4 | 1732 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2571.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n02i02571ent IS
END c07s05b00x00p16n02i02571ent;
ARCHITECTURE c07s05b00x00p16n02i02571arch OF c07s05b00x00p16n02i02571ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E26 = (2E13*1E13))
report "***PASSED TEST: c07s05b00x00p16n02i02571"
severity NOTE;
assert (2E26 = (2E13*1E13))
report "***FAILED TEST: c07s05b00x00p16n02i02571 - The values of the operands and the result lie within the range of the integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n02i02571arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd | 4 | 1088 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovect.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity to_vector_test is
end entity to_vector_test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1379.vhd | 4 | 1812 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1379.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01379ent IS
END c08s05b00x00p03n01i01379ent;
ARCHITECTURE c08s05b00x00p03n01i01379arch OF c08s05b00x00p03n01i01379ent IS
BEGIN
TESTING: PROCESS
variable v1, v2 : integer := 0;
function add (v1, v2 : integer) return integer is
begin
return v1 + v2;
end add;
BEGIN
v1 := 1;
add := v1 + v2; -- illegal assignment to function name
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01379 - Target of a variable assignment can not be an operator name."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01379arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2053.vhd | 4 | 1866 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2053.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02053ent IS
END c07s02b04x00p01n01i02053ent;
ARCHITECTURE c07s02b04x00p01n01i02053arch OF c07s02b04x00p01n01i02053ent IS
BEGIN
TESTING: PROCESS
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
variable RECV : DATE;
BEGIN
RECV := RECV + (DAY=>14, MONTH=>2, YEAR=>1988);
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02053 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02053arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd | 4 | 1305 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, count => count );
stimulus : process is
begin
for cycle_count in 1 to 100 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd | 4 | 1758 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2513.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p02n01i02513ent IS
END c07s03b05x00p02n01i02513ent;
ARCHITECTURE c07s03b05x00p02n01i02513arch OF c07s03b05x00p02n01i02513ent IS
BEGIN
TESTING: PROCESS
variable k1 : integer := 65;
variable k2 : real := 1.2;
BEGIN
k1 := integer(k2);
wait for 1 ns;
assert NOT(k1 = 1)
report "***PASSED TEST: c07s03b05x00p02n01i02513"
severity NOTE;
assert (k1 = 1)
report "***FAILED TEST: c07s03b05x00p02n01i02513 - Missing expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p02n01i02513arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1248.vhd | 4 | 1705 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1248.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01248ent IS
END c08s02b00x00p04n01i01248ent;
ARCHITECTURE c08s02b00x00p04n01i01248arch OF c08s02b00x00p04n01i01248ent IS
BEGIN
TESTING: PROCESS
type BYTE_T is array (1 to 8) of BIT;
variable N2 : BYTE_T;
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01248 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01248arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd | 4 | 1957 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3005.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03005pkg is
constant t: time;
end c02s06b00x00p07n01i03005pkg;
package body c02s06b00x00p07n01i03005pkg is
constant t: time:= 5 ns;
end c02s06b00x00p07n01i03005pkg;
ENTITY c02s06b00x00p07n01i03005ent IS
END c02s06b00x00p07n01i03005ent;
ARCHITECTURE c02s06b00x00p07n01i03005arch OF c02s06b00x00p07n01i03005ent IS
use work.c02s06b00x00p07n01i03005pkg.all;
BEGIN
TESTING: PROCESS
variable x: time;
BEGIN
x := t;
wait for 5 ns;
assert NOT( x = 5 ns )
report "***PASSED TEST: c02s06b00x00p07n01i03005"
severity NOTE;
assert ( x = 5 ns )
report "***FAILED TEST: c02s06b00x00p07n01i03005 - Deferred constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03005arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd | 4 | 1887 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2404.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02404ent IS
END c07s03b02x00p08n05i02404ent;
ARCHITECTURE c07s03b02x00p08n05i02404arch OF c07s03b02x00p08n05i02404ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
constant y: arr := (1 => 12, others => 0);
BEGIN
assert NOT(y(1)=12 and y(2)=0 and y(3)=0)
report "***PASSED TEST: c07s03b02x00p08n05i02404"
severity NOTE;
assert (y(1)=12 and y(2)=0 and y(3)=0)
report "***FAILED TEST: c07s03b02x00p08n05i02404 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02404arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd | 4 | 2222 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02150ent IS
END c07s02b04x00p21n01i02150ent;
ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real_4 := ( 12.34, 56.78, 12.34, 56.78 );
variable r_operand : real := 12.34;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***PASSED TEST: c07s02b04x00p21n01i02150"
severity NOTE;
assert ((result = (12.34, 56.78, 12.34, 56.78, 12.34)) and (result(1) = 12.34))
report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02150arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd | 4 | 3399 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc470.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00470ent IS
END c03s02b01x01p19n01i00470ent;
ARCHITECTURE c03s02b01x01p19n01i00470arch OF c03s02b01x01p19n01i00470ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_range is positive_vector(hi_to_low_range);
constant C66: positive_vector_range := (others => 1);
function complex_scalar(s : positive_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return positive_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : positive_vector_range;
signal S2 : positive_vector_range;
signal S3 : positive_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00470"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00470 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00470arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd | 4 | 3572 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_ch_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_09_01 is
end entity ch_09_01;
----------------------------------------------------------------
architecture test of ch_09_01 is
begin
process_09_1_a : process is
-- code from book:
type register_array is array (0 to 15) of bit_vector(31 downto 0);
type register_set is record
general_purpose_registers : register_array;
program_counter : bit_vector(31 downto 0);
program_status : bit_vector(31 downto 0);
end record;
variable CPU_registers : register_set;
-- code revised to work around MTI bugs mt015 and mt016
-- alias PSW is CPU_registers.program_status;
-- alias PC is CPU_registers.program_counter;
-- alias GPR is CPU_registers.general_purpose_registers;
alias PSW : bit_vector(31 downto 0) is CPU_registers.program_status;
alias PC : bit_vector(31 downto 0) is CPU_registers.program_counter;
alias GPR : register_array is CPU_registers.general_purpose_registers;
-- alias SP is CPU_registers.general_purpose_registers(15);
alias SP : bit_vector(31 downto 0) is CPU_registers.general_purpose_registers(15);
-- alias interrupt_level is PSW(30 downto 26);
alias interrupt_level : bit_vector(30 downto 26) is PSW(30 downto 26);
-- end revision
-- end of code from book
procedure procedure_09_1_b is
-- code from book:
-- code revised to work around MTI bug mt016
-- alias SP is GPR(15);
alias SP : bit_vector(31 downto 0) is GPR(15);
-- end revision
alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
-- end of code from book
begin
end procedure procedure_09_1_b;
begin
wait;
end process process_09_1_a;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd | 4 | 1182 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of mux2 is
begin
with To_bit(sel) select
y <= i0 after Tpd when '0',
i1 after Tpd when '1';
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd | 4 | 3762 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_19 is
end entity fg_05_19;
architecture test of fg_05_19 is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd | 4 | 2032 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2390.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02390ent IS
END c07s03b02x00p07n01i02390ent;
ARCHITECTURE c07s03b02x00p07n01i02390arch OF c07s03b02x00p07n01i02390ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
type RECORD_TYPE is record
E1,E2 : BOOLEAN;
end record;
signal S2 : RECORD_TYPE;
BEGIN
TESTING: PROCESS
BEGIN
S2 <= ( E1=>TRUE, E2=>TRUE);
-- positional and named associations are legal.
wait for 1 ns;
assert NOT(S2.E1=TRUE and S2.E2=TRUE)
report "***PASSED TEST: c07s03b02x00p07n01i02390"
severity NOTE;
assert (S2.E1=TRUE and S2.E2=TRUE)
report "***FAILED TEST: c07s03b02x00p07n01i02390 - Both named and positional associations can be used in the same aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02390arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd | 4 | 1800 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_05_11 is
end entity ch_05_11;
----------------------------------------------------------------
architecture test of ch_05_11 is
signal line_in, line_out : bit := '0';
begin
-- code from book:
transmission_line : process (line_in) is
begin
line_out <= transport line_in after 500 ps;
end process transmission_line;
-- end of code from book
----------------
stimulus : process is
begin
line_in <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps,
'1' after 8000 ps,
'0' after 8200 ps,
'1' after 8300 ps,
'0' after 8400 ps;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd | 4 | 4342 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity nor_gate is
generic ( width : positive;
Tpd01, Tpd10 : delay_length );
port ( input : in std_logic_vector(0 to width - 1);
output : out std_logic );
end entity nor_gate;
architecture primitive of nor_gate is
function max ( a, b : delay_length ) return delay_length is
begin
if a > b then
return a;
else
return b;
end if;
end function max;
begin
reducer : process (input) is
variable result : std_logic;
begin
result := '0';
for index in input'range loop
result := result or input(index);
end loop;
if not result = '1' then
output <= not result after Tpd01;
elsif not result = '0' then
output <= not result after Tpd10;
else
output <= not result after max(Tpd01, Tpd10);
end if;
end process reducer;
end architecture primitive;
library ieee; use ieee.std_logic_1164.all;
library cell_lib;
entity interlock_control is
end entity interlock_control;
-- code from book
architecture detailed_timing of interlock_control is
component nor_gate is
generic ( input_width : positive );
port ( input : in std_logic_vector(0 to input_width - 1);
output : out std_logic );
end component nor_gate;
for ex_interlock_gate : nor_gate
use entity cell_lib.nor_gate(primitive)
generic map ( width => input_width,
Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
-- . . .
-- not in book
signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
-- end not in book
begin
ex_interlock_gate : component nor_gate
generic map ( input_width => 2 )
port map ( input(0) => reg_access_hazard,
input(1) => load_hazard,
output => stall_ex_n);
-- . . .
-- not in book
reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
'0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
'0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
'0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
-- end not in book
end architecture detailed_timing;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd | 4 | 2111 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2719.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p03n01i02719ent IS
END c13s04b02x00p03n01i02719ent;
ARCHITECTURE c13s04b02x00p03n01i02719arch OF c13s04b02x00p03n01i02719ent IS
constant T1 : Integer := 16#E#E1;
constant T2 : Real := 5#1234.4321#; --- No_Failure_here
constant T3 : Integer := 2#1111_1111#;
constant T4 : Integer := 16#FF#;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( T1 = 16#E#E1 and
T2 = 5#1234.4321# and
T3 = 2#1111_1111# and
T4 = 16#FF# )
report "***PASSED TEST: c13s04b02x00p03n01i02719"
severity NOTE;
assert ( T1 = 16#E#E1 and
T2 = 5#1234.4321# and
T3 = 2#1111_1111# and
T4 = 16#FF# )
report "***FAILED TEST: c13s04b02x00p03n01i02719 - Base literal as an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p03n01i02719arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd | 4 | 1202 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration architectural of computer_system is
for block_level
-- . . . -- component configurations for cpu and memory, etc
for instrumentation
for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
use entity work.bus_monitor(general_purpose)
generic map ( verbose => true, dump_stats => true );
end for;
end for;
end for;
end configuration architectural;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc808.vhd | 4 | 1585 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc808.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b00x00p02n01i00808ent IS
END c01s02b00x00p02n01i00808ent;
ARCHITECTURE c01s02b00x00p02n01i00808arch OF c01s02b00x00p02n01i00808ent --failure here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p02n01i00808 - Reserved word is has to follow reserved word for."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p02n01i00808arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug04/test.vhdl | 3 | 1424 | library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function EQ_BUT_NOT_META(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function EQ_BUT_NOT_META(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= 'X';
wait for 1 ns;
b <= '1';
wait for 1 ns;
a <= '0';
wait for 1 ns;
b <= '0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert EQ_BUT_NOT_META(a,b) = TRUE
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd | 4 | 2095 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc603.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00603ent IS
END c03s04b01x00p01n01i00603ent;
ARCHITECTURE c03s04b01x00p01n01i00603arch OF c03s04b01x00p01n01i00603ent IS
type natural_cons_vector is array (15 downto 0) of natural;
type natural_cons_vector_file is file of natural_cons_vector;
constant C19 : natural_cons_vector := (others => 3);
BEGIN
TESTING: PROCESS
file filein : natural_cons_vector_file open write_mode is "iofile.30";
BEGIN
for i in 1 to 100 loop
write(filein, C19);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00603 - The output file will be verified by test s010248.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00603arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd | 4 | 4804 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p07n01i01348ent IS
END c08s04b01x00p07n01i01348ent;
ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS
-- Local signals.
signal S : BIT := '0';
BEGIN
TESTING: PROCESS
-- local variables.
variable S_INITIAL : BIT;
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- 0. Keep around the initial value of S.
S_INITIAL := S;
-- 1. When no preemption necessary, verify the results.
S <= transport (not S) after 10 ns, (S) after 20 ns;
-- a. Wait for first transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Wait for second transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- 2. Preempt a transaction which is to occur at the same time as second one.
S_INITIAL := S;
S <= transport (S) after 10 ns;
S <= transport (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 3. Preempt a transaction which is to occur at a later time than second one.
S_INITIAL := S;
S <= transport (S) after 15 ns;
S <= transport (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 4. Preempt multiple transactions.
S_INITIAL := S;
S <= transport (S) after 15 ns, (not S) after 30 ns;
S <= transport (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p07n01i01348"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p07n01i01348arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc20.vhd | 4 | 1720 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc20.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n03i00020ent IS
END c04s02b00x00p09n03i00020ent;
ARCHITECTURE c04s02b00x00p09n03i00020arch OF c04s02b00x00p09n03i00020ent IS
type A2 is range 50.0 to 100.0;
subtype B2 is A2 range 1.0 to 60.0; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p09n03i00020 - Range constraints for the subtype declarations contradict the range of the subtype indication.(real)"
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s02b00x00p09n03i00020arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd | 4 | 1878 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd | 4 | 1899 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_11.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_11 is
end entity fg_07_11;
architecture test of fg_07_11 is
subtype word32 is bit_vector(31 downto 0);
-- code from book
procedure increment ( a : inout word32; by : in word32 := X"0000_0001" ) is
variable sum : word32;
variable carry : bit := '0';
begin
for index in a'reverse_range loop
sum(index) := a(index) xor by(index) xor carry;
carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
end loop;
a := sum;
end procedure increment;
-- end code from book
begin
stimulus : process is
variable count : word32 := X"0001_1100";
begin
-- code from book (in text)
increment(count, X"0000_0004");
increment(count);
increment(count, by => open);
-- end code from book
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd | 4 | 1918 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3064.vhd | 4 | 2232 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3064.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s03b02x02p05n01i03064ent IS
port(con : in BIT := '1'; clk : out BIT);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
BEGIN
TESTING: PROCESS
begin
clk <= con;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch_a;
ENTITY c12s03b02x02p05n01i03064ent IS
port (C : out bit);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
component c12s03b02x02p05n01i03064ent_aa
port(con : in bit:='1'; clk : out bit);
end component;
for all: c12s03b02x02p05n01i03064ent_aa use entity work.fail(c12s03b02x02p05n01i03064arch_a); -- Failure_here
BEGIN
T1: test port map(open,C);
TESTING: PROCESS
BEGIN
assert FAILED
report "***FAILED TEST: c12s03b02x02p05n01i03064 - Entity declaration and the corresponding body implied by the binding indication do not exist within the specified library."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1660.vhd | 4 | 1682 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1660.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01660ent IS
END c09s01b00x00p02n01i01660ent;
ARCHITECTURE c09s01b00x00p02n01i01660arch OF c09s01b00x00p02n01i01660ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end; -- Failure_here
-- The reserved word block expected.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01660 - The reserved word block expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01660arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd | 4 | 2232 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_adc is
end tb_adc;
architecture tb_adc of tb_adc is
-- Component declarations
-- Signal declarations
signal clk_in : bit;
signal clk_in_tmp : std_logic;
signal dig_out1, dig_out2 : bit;
terminal sine_in : electrical;
quantity gain : real;
begin
-- Signal assignments
clk_in <= To_bit(clk_in_tmp); -- convert std_logic to bit
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 5.0
)
port map(
pos => sine_in,
neg => ELECTRICAL_REF
);
adc25 : entity work.adc(struct)
port map(
gain => gain,
a => sine_in,
d_out => dig_out1,
clk => clk_in
);
adc26 : entity work.adc(ideal)
port map(
gain => gain,
a => sine_in,
d_out => dig_out2,
clk => clk_in
);
clock1 : entity work.clock_duty(ideal)
generic map(
on_time => 1 ms,
off_time => 0.5 ms
)
port map(
CLOCK_OUT => clk_in_tmp
);
src1 : entity work.src_constant(ideal)
generic map(
level => 1.0
)
port map(
output => gain
);
end tb_adc;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd | 4 | 1934 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity circuit is
generic ( inpad_delay, outpad_delay : delay_length );
port ( in1, in2, in3 : in bit; out1, out2 : out bit );
end entity circuit;
--------------------------------------------------
architecture with_pad_delays of circuit is
component subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end component subcircuit;
signal delayed_in1, delayed_in2, delayed_in3 : bit;
signal undelayed_out1, undelayed_out2 : bit;
begin
input_delays : block is
begin
delayed_in1 <= in1 after inpad_delay;
delayed_in2 <= in2 after inpad_delay;
delayed_in3 <= in3 after inpad_delay;
end block input_delays;
functionality : block is
signal intermediate : bit;
begin
cell1 : component subcircuit
port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
cell2 : component subcircuit
port map ( intermediate, delayed_in3, undelayed_out2, open );
end block functionality;
output_delays : block is
begin
out1 <= undelayed_out1 after outpad_delay;
out2 <= undelayed_out2 after outpad_delay;
end block output_delays;
end architecture with_pad_delays;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd | 4 | 1838 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00298ent IS
END c03s01b03x01p01n03i00298ent;
ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***PASSED TEST: c03s01b03x01p01n03i00298"
severity NOTE;
assert ( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00298arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd | 4 | 2057 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2004.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p08n02i02004ent IS
END c07s02b02x00p08n02i02004ent;
ARCHITECTURE c07s02b02x00p08n02i02004arch OF c07s02b02x00p08n02i02004ent IS
BEGIN
TESTING: PROCESS
type array_x is array (positive range <>) of integer;
subtype array_three is array_x (1 to 6) ;
subtype array_four is array_x (6 downto 1) ;
variable x : array_four := (1,2,3,4,5,6);
variable y : array_three := (1,2,3,4,5,6);
BEGIN
assert NOT(x=y)
report "***PASSED TEST: c07s02b02x00p08n02i02004"
severity NOTE;
assert ( x=y )
report "***FAILED TEST: c07s02b02x00p08n02i02004 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p08n02i02004arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd | 4 | 3263 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc426.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00426ent IS
END c03s02b01x01p19n01i00426ent;
ARCHITECTURE c03s02b01x01p19n01i00426arch OF c03s02b01x01p19n01i00426ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
constant C1 : time_cons_vectorofvector := (others => (others => 3 ns));
function complex_scalar(s : time_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_cons_vectorofvector;
signal S2 : time_cons_vectorofvector;
signal S3 : time_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00426"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00426 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00426arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd | 4 | 2152 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1394.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01394ent IS
END c08s05b00x00p04n01i01394ent;
ARCHITECTURE c08s05b00x00p04n01i01394arch OF c08s05b00x00p04n01i01394ent IS
BEGIN
TESTING: PROCESS
type AT2 is array (0 to 1, 0 to 1) of CHARACTER;
type AT1 is array (0 to 1) of CHARACTER;
variable v1, v2 : AT1;
variable av : AT2 := (('a', 'b'), ('c', 'd'));
BEGIN
assert v1 = (NUL, NUL);
assert v2 = (NUL, NUL);
v1(0) := av(0,0);
v1(1) := av(0,1);
v2(0) := av(1,0);
v2(1) := av(1,1);
assert v1 = ('a', 'b');
assert v2 = ('c', 'd');
wait for 1 ns;
assert NOT( v1 = ('a','b') and v2 = ('c', 'd') )
report "***PASSED TEST: c08s05b00x00p04n01i01394"
severity NOTE;
assert ( v1 = ('a','b') and v2 = ('c', 'd') )
report "***FAILED TEST: c08s05b00x00p04n01i01394 - Aggregate (2-d array type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01394arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd | 4 | 2378 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2133.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02133ent IS
END c07s02b04x00p21n01i02133ent;
ARCHITECTURE c07s02b04x00p21n01i02133arch OF c07s02b04x00p21n01i02133ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_5 is record_v (1 to 5);
SUBTYPE record_4 is record_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : record_5;
variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
variable r_operand : simple_record := (12,34);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ((12,34),(56,78),(12,34),(56,78),(12,34)))
report "***PASSED TEST: c07s02b04x00p21n01i02133"
severity NOTE;
assert ( result = ((12,34),(56,78),(12,34),(56,78),(12,34)))
report "***FAILED TEST: c07s02b04x00p21n01i02133 - Concatenation of element and RECORD array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02133arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc835.vhd | 4 | 1808 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p06n01i00835ent IS
END c01s03b00x00p06n01i00835ent;
ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p06n01i00835arch;
configuration C of c01s03b00x00p06n01i00835ent is
for c01s03b00x00p06n01i00835arch
use WORK.all ;
end for ;
end C2; -- Failure_here
-- ERROR: name given at the end must be the same as that given beginning.
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd | 4 | 1903 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1174.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01174ent IS
END c06s06b00x00p06n01i01174ent;
ARCHITECTURE c06s06b00x00p06n01i01174arch OF c06s06b00x00p06n01i01174ent IS
signal POS : Integer;
attribute PIO : positive;
attribute PIO of POS : signal is 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT(POS'PIO = 10)
report "***PASSED TEST: c06s06b00x00p06n01i01174"
severity NOTE;
assert (POS'PIO = 10)
report "***FAILED TEST: c06s06b00x00p06n01i01174 - If the attribute designator does not denote a predefined attribute, the static expression in the attribute name must not be present."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01174arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd | 4 | 1899 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1442.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01442ent IS
END c08s07b00x00p02n01i01442ent;
ARCHITECTURE c08s07b00x00p02n01i01442arch OF c08s07b00x00p02n01i01442ent IS
begin
TESTING: process
variable k : integer := 0;
variable m : integer := 6;
variable j : boolean := TRUE;
begin
if m > 5 then
case j is
when TRUE => k := 1;
when FALSE => NULL;
end case;
end if;
assert NOT(k = 1)
report "***PASSED TEST: c08s07b00x00p02n01i01442"
severity NOTE;
assert (k = 1)
report "***FAILED TEST: c08s07b00x00p02n01i01442 - CASE statement to be sequence statements of IF statement"
severity ERROR;
wait;
end process TESTING;
END c08s07b00x00p02n01i01442arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd | 4 | 2123 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2094.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02094ent IS
END c07s02b04x00p20n01i02094ent;
ARCHITECTURE c07s02b04x00p20n01i02094arch OF c07s02b04x00p20n01i02094ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4 is boolean_v (1 to 4);
SUBTYPE boolean_8 is boolean_v (1 to 8);
FUNCTION return_array RETURN boolean_4 is
constant l_operand : boolean_4 := (true,false,true,false);
begin
RETURN l_operand;
end return_array;
BEGIN
l : block
generic ( info : boolean_8 );
generic map ( return_array & return_array );
begin
assert NOT(info = (true,false,true,false,true,false,true,false))
report "***PASSED TEST: c07s02b04x00p20n01i02094"
severity NOTE;
assert (info = (true,false,true,false,true,false,true,false))
report "***FAILED TEST: c07s02b04x00p20n01i02094 - Function array concatenation did not succeed."
severity ERROR;
end block;
END c07s02b04x00p20n01i02094arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd | 4 | 2112 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02138ent IS
END c07s02b04x00p21n01i02138ent;
ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive := 1 ;
variable r_operand : positive_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02138"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02138arch;
| gpl-2.0 |
peteut/ghdl | libraries/ieee2008/fixed_generic_pkg.vhdl | 4 | 66882 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package fixed_generic_pkg is
generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false
);
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright 2008 by IEEE. All rights reserved.";
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
alias U_ufixed is UNRESOLVED_ufixed;
alias U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is (resolved) UNRESOLVED_ufixed;
subtype sfixed is (resolved) UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNRESOLVED_UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
end package fixed_generic_pkg;
| gpl-2.0 |
123gmax/Digital-Lab | AES128/building_blocks/addRoundKey.vhd | 2 | 1076 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:22:58 PM
-- Design Name:
-- Module Name: addRoundKey - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end addRoundKey;
architecture Behavioral of addRoundKey is
begin
process(CLK, RESET, wordIn, keyIn)
begin
if RESET = '1' then
wordOut <= (others => '0');
elsif rising_edge(CLK) then
wordOut <= wordIn XOR keyIn;
end if;
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc975.vhd | 4 | 1940 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc975.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00975ent IS
END c06s03b00x00p05n01i00975ent;
ARCHITECTURE c06s03b00x00p05n01i00975arch OF c06s03b00x00p05n01i00975ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
type ONE is range 1 to 1;
type A1 is array (ONE) of BOOLEAN;
variable V1: R1 ;
variable V2: R2 ;
variable V5: A1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V5.ONE;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00975 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00975arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd | 4 | 2127 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2297.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p33n01i02297ent IS
END c07s02b06x00p33n01i02297ent;
ARCHITECTURE c07s02b06x00p33n01i02297arch OF c07s02b06x00p33n01i02297ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 min / 60) = 1 sec);
assert ((1 sec / 1000) = 1 ms);
assert ((1 ms / 1000) = 1 us);
wait for 5 us;
assert NOT( ((1 min / 60) = 1 sec) and
((1 sec / 1000) = 1 ms) and
((1 ms / 1000) = 1 us) )
report "***PASSED TEST: c07s02b06x00p33n01i02297"
severity NOTE;
assert ( ((1 min / 60) = 1 sec) and
((1 sec / 1000) = 1 ms) and
((1 ms / 1000) = 1 us) )
report "***FAILED TEST: c07s02b06x00p33n01i02297 - Division of an user-defined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p33n01i02297arch;
| gpl-2.0 |
peteut/ghdl | libraries/ieee2008/float_pkg.vhdl | 4 | 2608 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Floating-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
package float_pkg is new IEEE.float_generic_pkg
generic map (
float_exponent_width => 8, -- float32'high
float_fraction_width => 23, -- -float32'low
float_round_style => IEEE.fixed_float_types.round_nearest, -- round nearest algorithm
float_denormalize => true, -- Use IEEE extended floating
float_check_error => true, -- Turn on NAN and overflow processing
float_guard_bits => 3, -- number of guard bits
no_warning => false, -- show warnings
fixed_pkg => IEEE.fixed_pkg
);
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd | 4 | 1446 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_19 is
end entity inline_19;
----------------------------------------------------------------
architecture test of inline_19 is
subtype data_type is integer;
signal transmit_data : data_type := 0;
begin
-- code from book:
transmit_element : process (transmit_data) is
-- . . . -- variable declarations
begin
report "transmit_element: data = "
& data_type'image(transmit_data);
-- . . .
end process transmit_element;
-- end of code from book
stimulus : process is
begin
transmit_data <= 10 after 10 ns, 20 after 20 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2670.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2670.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02670ent IS
END c13s03b01x00p02n01i02670ent;
ARCHITECTURE c13s03b01x00p02n01i02670arch OF c13s03b01x00p02n01i02670ent IS
BEGIN
TESTING: PROCESS
variable ^k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02670 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02670arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.vhdl | 3 | 1853 |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity character_read is
end character_read;
architecture test0 of character_read is
type character_file is file of character;
signal k : integer := 0;
begin
doit: process
file filein : character_file open read_mode is "character.file";
variable v : character;
begin
assert(endfile(filein) = false)
report "End of file reached before expected."
severity failure;
read(filein,v);
assert(v = '1') severity failure;
read(filein,v);
assert(v = 'A') severity failure;
read(filein,v);
assert(v = '$') severity failure;
read(filein,v);
assert(v = '+') severity failure;
assert(endfile(filein));
report "PASSED TEST: character_read."
severity NOTE;
wait;
end process;
end test0;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1904.vhd | 4 | 3502 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1904.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01904pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01904pkg;
use work.c07s01b00x00p08n01i01904pkg.all;
ENTITY c07s01b00x00p08n01i01904ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01904ent_a;
ARCHITECTURE c07s01b00x00p08n01i01904arch_a OF c07s01b00x00p08n01i01904ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01904arch_a;
use work.c07s01b00x00p08n01i01904pkg.all;
ENTITY c07s01b00x00p08n01i01904ent IS
END c07s01b00x00p08n01i01904ent;
ARCHITECTURE c07s01b00x00p08n01i01904arch OF c07s01b00x00p08n01i01904ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width - 1));
signal out_bus : out cmd_bus (0 to small_int(bus_width - 1)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01904ent_a(c07s01b00x00p08n01i01904arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, s ); -- signal assignment label illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "signal assignment label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01904 - Signal assignment labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01904arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket44/file1.vhd | 3 | 594 | package pkg is
type protected_t is protected
end protected protected_t;
procedure proc(variable prot : inout protected_t; variable result : out boolean);
end package;
package body pkg is
type protected_t is protected body
end protected body protected_t;
procedure proc(variable prot : inout protected_t; variable result : out boolean) is
begin
end;
end package body pkg;
use work.pkg.all;
package other_pkg is
procedure other_proc(variable result : out boolean);
alias other_proc is proc[protected_t, boolean];
impure function other_proc return boolean;
end package;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd | 4 | 16579 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1947.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01947pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01947pkg.all;
ENTITY c07s02b01x00p01n02i01947ent IS
END c07s02b01x00p01n02i01947ent;
ARCHITECTURE c07s02b01x00p01n02i01947arch OF c07s02b01x00p01n02i01947ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
--
-- Test NANDoperator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01947"
severity NOTE;
assert ( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01947 - Logical operator NAND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01947arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc774.vhd | 4 | 2254 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc774.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p09n01i00774ent_a IS
port ( c1 : buffer integer ;
c2 : in integer );
END c01s01b01x02p09n01i00774ent_a;
ARCHITECTURE c01s01b01x02p09n01i00774arch_a OF c01s01b01x02p09n01i00774ent_a IS
BEGIN
c1 <= c2;
END c01s01b01x02p09n01i00774arch_a;
ENTITY c01s01b01x02p09n01i00774ent IS
port ( p1 : in integer ;
p2 : in integer );
END c01s01b01x02p09n01i00774ent;
ARCHITECTURE c01s01b01x02p09n01i00774arch OF c01s01b01x02p09n01i00774ent IS
component c01s01b01x02p09n01i00774ent_b
port ( c1 : buffer integer ;
c2 : in integer );
end component;
for L : c01s01b01x02p09n01i00774ent_b use entity work.c01s01b01x02p09n01i00774ent_a(c01s01b01x02p09n01i00774arch_a);
BEGIN
L : c01s01b01x02p09n01i00774ent_b port map (p1, p2);
--Failure here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p09n01i00774 - An actual of mode in cannot be associated with a formal port of mode buffer."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p09n01i00774arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-event-attribute.vhdl | 3 | 704 | entity test is
end test;
architecture only of test is
signal s : bit;
begin
s <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
p: process
begin
wait for 1 ns;
assert not(s'event) report "TEST FAILED - 'event active" severity failure;
wait for 25 ns;
-- s <= '1';
-- wait for 0 ns;
assert s = '0' report "TEST FAILED - s has not changed to 0 yet!" severity failure;
--wait for 10 ns;
wait for 4 ns;
assert s = '1' report "TEST FAILED - s has not changed to 1 yet!" severity failure;
assert (s'event) report "TEST FAILED - 'event not tripped" severity failure;
report "TEST PASSED";
wait;
end process;
end architecture only;
| gpl-2.0 |
123gmax/Digital-Lab | AES128/building_blocks/invMixColumn.vhd | 2 | 50061 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 04:30:29 PM
-- Design Name:
-- Module Name: invMixColumn - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- x9, x11, x13, x14 are the Gallois Multiplication Lookup Tables
-- Source: https://en.wikipedia.org/wiki/Rijndael_mix_columns#Galois_Multiplication_lookup_tables
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x9 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x9;
architecture Behavioral of x9 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"09";
when x"02" => byteOut <= x"12";
when x"03" => byteOut <= x"1B";
when x"04" => byteOut <= x"24";
when x"05" => byteOut <= x"2D";
when x"06" => byteOut <= x"36";
when x"07" => byteOut <= x"3F";
when x"08" => byteOut <= x"48";
when x"09" => byteOut <= x"41";
when x"0A" => byteOut <= x"5A";
when x"0B" => byteOut <= x"53";
when x"0C" => byteOut <= x"6C";
when x"0D" => byteOut <= x"65";
when x"0E" => byteOut <= x"7E";
when x"0F" => byteOut <= x"77";
when x"10" => byteOut <= x"90";
when x"11" => byteOut <= x"99";
when x"12" => byteOut <= x"82";
when x"13" => byteOut <= x"8B";
when x"14" => byteOut <= x"B4";
when x"15" => byteOut <= x"BD";
when x"16" => byteOut <= x"A6";
when x"17" => byteOut <= x"AF";
when x"18" => byteOut <= x"D8";
when x"19" => byteOut <= x"D1";
when x"1A" => byteOut <= x"CA";
when x"1B" => byteOut <= x"C3";
when x"1C" => byteOut <= x"FC";
when x"1D" => byteOut <= x"F5";
when x"1E" => byteOut <= x"EE";
when x"1F" => byteOut <= x"E7";
when x"20" => byteOut <= x"3B";
when x"21" => byteOut <= x"32";
when x"22" => byteOut <= x"29";
when x"23" => byteOut <= x"20";
when x"24" => byteOut <= x"1F";
when x"25" => byteOut <= x"16";
when x"26" => byteOut <= x"0D";
when x"27" => byteOut <= x"04";
when x"28" => byteOut <= x"73";
when x"29" => byteOut <= x"7A";
when x"2A" => byteOut <= x"61";
when x"2B" => byteOut <= x"68";
when x"2C" => byteOut <= x"57";
when x"2D" => byteOut <= x"5E";
when x"2E" => byteOut <= x"45";
when x"2F" => byteOut <= x"4C";
when x"30" => byteOut <= x"AB";
when x"31" => byteOut <= x"A2";
when x"32" => byteOut <= x"B9";
when x"33" => byteOut <= x"B0";
when x"34" => byteOut <= x"8F";
when x"35" => byteOut <= x"86";
when x"36" => byteOut <= x"9D";
when x"37" => byteOut <= x"94";
when x"38" => byteOut <= x"E3";
when x"39" => byteOut <= x"EA";
when x"3A" => byteOut <= x"F1";
when x"3B" => byteOut <= x"F8";
when x"3C" => byteOut <= x"C7";
when x"3D" => byteOut <= x"CE";
when x"3E" => byteOut <= x"D5";
when x"3F" => byteOut <= x"DC";
when x"40" => byteOut <= x"76";
when x"41" => byteOut <= x"7F";
when x"42" => byteOut <= x"64";
when x"43" => byteOut <= x"6D";
when x"44" => byteOut <= x"52";
when x"45" => byteOut <= x"5B";
when x"46" => byteOut <= x"40";
when x"47" => byteOut <= x"49";
when x"48" => byteOut <= x"3E";
when x"49" => byteOut <= x"37";
when x"4A" => byteOut <= x"2C";
when x"4B" => byteOut <= x"25";
when x"4C" => byteOut <= x"1A";
when x"4D" => byteOut <= x"13";
when x"4E" => byteOut <= x"08";
when x"4F" => byteOut <= x"01";
when x"50" => byteOut <= x"E6";
when x"51" => byteOut <= x"EF";
when x"52" => byteOut <= x"F4";
when x"53" => byteOut <= x"FD";
when x"54" => byteOut <= x"C2";
when x"55" => byteOut <= x"CB";
when x"56" => byteOut <= x"D0";
when x"57" => byteOut <= x"D9";
when x"58" => byteOut <= x"AE";
when x"59" => byteOut <= x"A7";
when x"5A" => byteOut <= x"BC";
when x"5B" => byteOut <= x"B5";
when x"5C" => byteOut <= x"8A";
when x"5D" => byteOut <= x"83";
when x"5E" => byteOut <= x"98";
when x"5F" => byteOut <= x"91";
when x"60" => byteOut <= x"4D";
when x"61" => byteOut <= x"44";
when x"62" => byteOut <= x"5F";
when x"63" => byteOut <= x"56";
when x"64" => byteOut <= x"69";
when x"65" => byteOut <= x"60";
when x"66" => byteOut <= x"7B";
when x"67" => byteOut <= x"72";
when x"68" => byteOut <= x"05";
when x"69" => byteOut <= x"0C";
when x"6A" => byteOut <= x"17";
when x"6B" => byteOut <= x"1E";
when x"6C" => byteOut <= x"21";
when x"6D" => byteOut <= x"28";
when x"6E" => byteOut <= x"33";
when x"6F" => byteOut <= x"3A";
when x"70" => byteOut <= x"DD";
when x"71" => byteOut <= x"D4";
when x"72" => byteOut <= x"CF";
when x"73" => byteOut <= x"C6";
when x"74" => byteOut <= x"F9";
when x"75" => byteOut <= x"F0";
when x"76" => byteOut <= x"EB";
when x"77" => byteOut <= x"E2";
when x"78" => byteOut <= x"95";
when x"79" => byteOut <= x"9C";
when x"7A" => byteOut <= x"87";
when x"7B" => byteOut <= x"8E";
when x"7C" => byteOut <= x"B1";
when x"7D" => byteOut <= x"B8";
when x"7E" => byteOut <= x"A3";
when x"7F" => byteOut <= x"AA";
when x"80" => byteOut <= x"EC";
when x"81" => byteOut <= x"E5";
when x"82" => byteOut <= x"FE";
when x"83" => byteOut <= x"F7";
when x"84" => byteOut <= x"C8";
when x"85" => byteOut <= x"C1";
when x"86" => byteOut <= x"DA";
when x"87" => byteOut <= x"D3";
when x"88" => byteOut <= x"A4";
when x"89" => byteOut <= x"AD";
when x"8A" => byteOut <= x"B6";
when x"8B" => byteOut <= x"BF";
when x"8C" => byteOut <= x"80";
when x"8D" => byteOut <= x"89";
when x"8E" => byteOut <= x"92";
when x"8F" => byteOut <= x"9B";
when x"90" => byteOut <= x"7C";
when x"91" => byteOut <= x"75";
when x"92" => byteOut <= x"6E";
when x"93" => byteOut <= x"67";
when x"94" => byteOut <= x"58";
when x"95" => byteOut <= x"51";
when x"96" => byteOut <= x"4A";
when x"97" => byteOut <= x"43";
when x"98" => byteOut <= x"34";
when x"99" => byteOut <= x"3D";
when x"9A" => byteOut <= x"26";
when x"9B" => byteOut <= x"2F";
when x"9C" => byteOut <= x"10";
when x"9D" => byteOut <= x"19";
when x"9E" => byteOut <= x"02";
when x"9F" => byteOut <= x"0B";
when x"A0" => byteOut <= x"D7";
when x"A1" => byteOut <= x"DE";
when x"A2" => byteOut <= x"C5";
when x"A3" => byteOut <= x"CC";
when x"A4" => byteOut <= x"F3";
when x"A5" => byteOut <= x"FA";
when x"A6" => byteOut <= x"E1";
when x"A7" => byteOut <= x"E8";
when x"A8" => byteOut <= x"9F";
when x"A9" => byteOut <= x"96";
when x"AA" => byteOut <= x"8D";
when x"AB" => byteOut <= x"84";
when x"AC" => byteOut <= x"BB";
when x"AD" => byteOut <= x"B2";
when x"AE" => byteOut <= x"A9";
when x"AF" => byteOut <= x"A0";
when x"B0" => byteOut <= x"47";
when x"B1" => byteOut <= x"4E";
when x"B2" => byteOut <= x"55";
when x"B3" => byteOut <= x"5C";
when x"B4" => byteOut <= x"63";
when x"B5" => byteOut <= x"6A";
when x"B6" => byteOut <= x"71";
when x"B7" => byteOut <= x"78";
when x"B8" => byteOut <= x"0F";
when x"B9" => byteOut <= x"06";
when x"BA" => byteOut <= x"1D";
when x"BB" => byteOut <= x"14";
when x"BC" => byteOut <= x"2B";
when x"BD" => byteOut <= x"22";
when x"BE" => byteOut <= x"39";
when x"BF" => byteOut <= x"30";
when x"C0" => byteOut <= x"9A";
when x"C1" => byteOut <= x"93";
when x"C2" => byteOut <= x"88";
when x"C3" => byteOut <= x"81";
when x"C4" => byteOut <= x"BE";
when x"C5" => byteOut <= x"B7";
when x"C6" => byteOut <= x"AC";
when x"C7" => byteOut <= x"A5";
when x"C8" => byteOut <= x"D2";
when x"C9" => byteOut <= x"DB";
when x"CA" => byteOut <= x"C0";
when x"CB" => byteOut <= x"C9";
when x"CC" => byteOut <= x"F6";
when x"CD" => byteOut <= x"FF";
when x"CE" => byteOut <= x"E4";
when x"CF" => byteOut <= x"ED";
when x"D0" => byteOut <= x"0A";
when x"D1" => byteOut <= x"03";
when x"D2" => byteOut <= x"18";
when x"D3" => byteOut <= x"11";
when x"D4" => byteOut <= x"2E";
when x"D5" => byteOut <= x"27";
when x"D6" => byteOut <= x"3C";
when x"D7" => byteOut <= x"35";
when x"D8" => byteOut <= x"42";
when x"D9" => byteOut <= x"4B";
when x"DA" => byteOut <= x"50";
when x"DB" => byteOut <= x"59";
when x"DC" => byteOut <= x"66";
when x"DD" => byteOut <= x"6F";
when x"DE" => byteOut <= x"74";
when x"DF" => byteOut <= x"7D";
when x"E0" => byteOut <= x"A1";
when x"E1" => byteOut <= x"A8";
when x"E2" => byteOut <= x"B3";
when x"E3" => byteOut <= x"BA";
when x"E4" => byteOut <= x"85";
when x"E5" => byteOut <= x"8C";
when x"E6" => byteOut <= x"97";
when x"E7" => byteOut <= x"9E";
when x"E8" => byteOut <= x"E9";
when x"E9" => byteOut <= x"E0";
when x"EA" => byteOut <= x"FB";
when x"EB" => byteOut <= x"F2";
when x"EC" => byteOut <= x"CD";
when x"ED" => byteOut <= x"C4";
when x"EE" => byteOut <= x"DF";
when x"EF" => byteOut <= x"D6";
when x"F0" => byteOut <= x"31";
when x"F1" => byteOut <= x"38";
when x"F2" => byteOut <= x"23";
when x"F3" => byteOut <= x"2A";
when x"F4" => byteOut <= x"15";
when x"F5" => byteOut <= x"1C";
when x"F6" => byteOut <= x"07";
when x"F7" => byteOut <= x"0E";
when x"F8" => byteOut <= x"79";
when x"F9" => byteOut <= x"70";
when x"FA" => byteOut <= x"6B";
when x"FB" => byteOut <= x"62";
when x"FC" => byteOut <= x"5D";
when x"FD" => byteOut <= x"54";
when x"FE" => byteOut <= x"4F";
when x"FF" => byteOut <= x"46";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x11 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x11;
architecture Behavioral of x11 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0B";
when x"02" => byteOut <= x"16";
when x"03" => byteOut <= x"1D";
when x"04" => byteOut <= x"2C";
when x"05" => byteOut <= x"27";
when x"06" => byteOut <= x"3A";
when x"07" => byteOut <= x"31";
when x"08" => byteOut <= x"58";
when x"09" => byteOut <= x"53";
when x"0A" => byteOut <= x"4E";
when x"0B" => byteOut <= x"45";
when x"0C" => byteOut <= x"74";
when x"0D" => byteOut <= x"7F";
when x"0E" => byteOut <= x"62";
when x"0F" => byteOut <= x"69";
when x"10" => byteOut <= x"B0";
when x"11" => byteOut <= x"BB";
when x"12" => byteOut <= x"A6";
when x"13" => byteOut <= x"AD";
when x"14" => byteOut <= x"9C";
when x"15" => byteOut <= x"97";
when x"16" => byteOut <= x"8A";
when x"17" => byteOut <= x"81";
when x"18" => byteOut <= x"E8";
when x"19" => byteOut <= x"E3";
when x"1A" => byteOut <= x"FE";
when x"1B" => byteOut <= x"F5";
when x"1C" => byteOut <= x"C4";
when x"1D" => byteOut <= x"CF";
when x"1E" => byteOut <= x"D2";
when x"1F" => byteOut <= x"D9";
when x"20" => byteOut <= x"7B";
when x"21" => byteOut <= x"70";
when x"22" => byteOut <= x"6D";
when x"23" => byteOut <= x"66";
when x"24" => byteOut <= x"57";
when x"25" => byteOut <= x"5C";
when x"26" => byteOut <= x"41";
when x"27" => byteOut <= x"4A";
when x"28" => byteOut <= x"23";
when x"29" => byteOut <= x"28";
when x"2A" => byteOut <= x"35";
when x"2B" => byteOut <= x"3E";
when x"2C" => byteOut <= x"0F";
when x"2D" => byteOut <= x"04";
when x"2E" => byteOut <= x"19";
when x"2F" => byteOut <= x"12";
when x"30" => byteOut <= x"CB";
when x"31" => byteOut <= x"C0";
when x"32" => byteOut <= x"DD";
when x"33" => byteOut <= x"D6";
when x"34" => byteOut <= x"E7";
when x"35" => byteOut <= x"EC";
when x"36" => byteOut <= x"F1";
when x"37" => byteOut <= x"FA";
when x"38" => byteOut <= x"93";
when x"39" => byteOut <= x"98";
when x"3A" => byteOut <= x"85";
when x"3B" => byteOut <= x"8E";
when x"3C" => byteOut <= x"BF";
when x"3D" => byteOut <= x"B4";
when x"3E" => byteOut <= x"A9";
when x"3F" => byteOut <= x"A2";
when x"40" => byteOut <= x"F6";
when x"41" => byteOut <= x"FD";
when x"42" => byteOut <= x"E0";
when x"43" => byteOut <= x"EB";
when x"44" => byteOut <= x"DA";
when x"45" => byteOut <= x"D1";
when x"46" => byteOut <= x"CC";
when x"47" => byteOut <= x"C7";
when x"48" => byteOut <= x"AE";
when x"49" => byteOut <= x"A5";
when x"4A" => byteOut <= x"B8";
when x"4B" => byteOut <= x"B3";
when x"4C" => byteOut <= x"82";
when x"4D" => byteOut <= x"89";
when x"4E" => byteOut <= x"94";
when x"4F" => byteOut <= x"9F";
when x"50" => byteOut <= x"46";
when x"51" => byteOut <= x"4D";
when x"52" => byteOut <= x"50";
when x"53" => byteOut <= x"5B";
when x"54" => byteOut <= x"6A";
when x"55" => byteOut <= x"61";
when x"56" => byteOut <= x"7C";
when x"57" => byteOut <= x"77";
when x"58" => byteOut <= x"1E";
when x"59" => byteOut <= x"15";
when x"5A" => byteOut <= x"08";
when x"5B" => byteOut <= x"03";
when x"5C" => byteOut <= x"32";
when x"5D" => byteOut <= x"39";
when x"5E" => byteOut <= x"24";
when x"5F" => byteOut <= x"2F";
when x"60" => byteOut <= x"8D";
when x"61" => byteOut <= x"86";
when x"62" => byteOut <= x"9B";
when x"63" => byteOut <= x"90";
when x"64" => byteOut <= x"A1";
when x"65" => byteOut <= x"AA";
when x"66" => byteOut <= x"B7";
when x"67" => byteOut <= x"BC";
when x"68" => byteOut <= x"D5";
when x"69" => byteOut <= x"DE";
when x"6A" => byteOut <= x"C3";
when x"6B" => byteOut <= x"C8";
when x"6C" => byteOut <= x"F9";
when x"6D" => byteOut <= x"F2";
when x"6E" => byteOut <= x"EF";
when x"6F" => byteOut <= x"E4";
when x"70" => byteOut <= x"3D";
when x"71" => byteOut <= x"36";
when x"72" => byteOut <= x"2B";
when x"73" => byteOut <= x"20";
when x"74" => byteOut <= x"11";
when x"75" => byteOut <= x"1A";
when x"76" => byteOut <= x"07";
when x"77" => byteOut <= x"0C";
when x"78" => byteOut <= x"65";
when x"79" => byteOut <= x"6E";
when x"7A" => byteOut <= x"73";
when x"7B" => byteOut <= x"78";
when x"7C" => byteOut <= x"49";
when x"7D" => byteOut <= x"42";
when x"7E" => byteOut <= x"5F";
when x"7F" => byteOut <= x"54";
when x"80" => byteOut <= x"F7";
when x"81" => byteOut <= x"FC";
when x"82" => byteOut <= x"E1";
when x"83" => byteOut <= x"EA";
when x"84" => byteOut <= x"DB";
when x"85" => byteOut <= x"D0";
when x"86" => byteOut <= x"CD";
when x"87" => byteOut <= x"C6";
when x"88" => byteOut <= x"AF";
when x"89" => byteOut <= x"A4";
when x"8A" => byteOut <= x"B9";
when x"8B" => byteOut <= x"B2";
when x"8C" => byteOut <= x"83";
when x"8D" => byteOut <= x"88";
when x"8E" => byteOut <= x"95";
when x"8F" => byteOut <= x"9E";
when x"90" => byteOut <= x"47";
when x"91" => byteOut <= x"4C";
when x"92" => byteOut <= x"51";
when x"93" => byteOut <= x"5A";
when x"94" => byteOut <= x"6B";
when x"95" => byteOut <= x"60";
when x"96" => byteOut <= x"7D";
when x"97" => byteOut <= x"76";
when x"98" => byteOut <= x"1F";
when x"99" => byteOut <= x"14";
when x"9A" => byteOut <= x"09";
when x"9B" => byteOut <= x"02";
when x"9C" => byteOut <= x"33";
when x"9D" => byteOut <= x"38";
when x"9E" => byteOut <= x"25";
when x"9F" => byteOut <= x"2E";
when x"A0" => byteOut <= x"8C";
when x"A1" => byteOut <= x"87";
when x"A2" => byteOut <= x"9A";
when x"A3" => byteOut <= x"91";
when x"A4" => byteOut <= x"A0";
when x"A5" => byteOut <= x"AB";
when x"A6" => byteOut <= x"B6";
when x"A7" => byteOut <= x"BD";
when x"A8" => byteOut <= x"D4";
when x"A9" => byteOut <= x"DF";
when x"AA" => byteOut <= x"C2";
when x"AB" => byteOut <= x"C9";
when x"AC" => byteOut <= x"F8";
when x"AD" => byteOut <= x"F3";
when x"AE" => byteOut <= x"EE";
when x"AF" => byteOut <= x"E5";
when x"B0" => byteOut <= x"3C";
when x"B1" => byteOut <= x"37";
when x"B2" => byteOut <= x"2A";
when x"B3" => byteOut <= x"21";
when x"B4" => byteOut <= x"10";
when x"B5" => byteOut <= x"1B";
when x"B6" => byteOut <= x"06";
when x"B7" => byteOut <= x"0D";
when x"B8" => byteOut <= x"64";
when x"B9" => byteOut <= x"6F";
when x"BA" => byteOut <= x"72";
when x"BB" => byteOut <= x"79";
when x"BC" => byteOut <= x"48";
when x"BD" => byteOut <= x"43";
when x"BE" => byteOut <= x"5E";
when x"BF" => byteOut <= x"55";
when x"C0" => byteOut <= x"01";
when x"C1" => byteOut <= x"0A";
when x"C2" => byteOut <= x"17";
when x"C3" => byteOut <= x"1C";
when x"C4" => byteOut <= x"2D";
when x"C5" => byteOut <= x"26";
when x"C6" => byteOut <= x"3B";
when x"C7" => byteOut <= x"30";
when x"C8" => byteOut <= x"59";
when x"C9" => byteOut <= x"52";
when x"CA" => byteOut <= x"4F";
when x"CB" => byteOut <= x"44";
when x"CC" => byteOut <= x"75";
when x"CD" => byteOut <= x"7E";
when x"CE" => byteOut <= x"63";
when x"CF" => byteOut <= x"68";
when x"D0" => byteOut <= x"B1";
when x"D1" => byteOut <= x"BA";
when x"D2" => byteOut <= x"A7";
when x"D3" => byteOut <= x"AC";
when x"D4" => byteOut <= x"9D";
when x"D5" => byteOut <= x"96";
when x"D6" => byteOut <= x"8B";
when x"D7" => byteOut <= x"80";
when x"D8" => byteOut <= x"E9";
when x"D9" => byteOut <= x"E2";
when x"DA" => byteOut <= x"FF";
when x"DB" => byteOut <= x"F4";
when x"DC" => byteOut <= x"C5";
when x"DD" => byteOut <= x"CE";
when x"DE" => byteOut <= x"D3";
when x"DF" => byteOut <= x"D8";
when x"E0" => byteOut <= x"7A";
when x"E1" => byteOut <= x"71";
when x"E2" => byteOut <= x"6C";
when x"E3" => byteOut <= x"67";
when x"E4" => byteOut <= x"56";
when x"E5" => byteOut <= x"5D";
when x"E6" => byteOut <= x"40";
when x"E7" => byteOut <= x"4B";
when x"E8" => byteOut <= x"22";
when x"E9" => byteOut <= x"29";
when x"EA" => byteOut <= x"34";
when x"EB" => byteOut <= x"3F";
when x"EC" => byteOut <= x"0E";
when x"ED" => byteOut <= x"05";
when x"EE" => byteOut <= x"18";
when x"EF" => byteOut <= x"13";
when x"F0" => byteOut <= x"CA";
when x"F1" => byteOut <= x"C1";
when x"F2" => byteOut <= x"DC";
when x"F3" => byteOut <= x"D7";
when x"F4" => byteOut <= x"E6";
when x"F5" => byteOut <= x"ED";
when x"F6" => byteOut <= x"F0";
when x"F7" => byteOut <= x"FB";
when x"F8" => byteOut <= x"92";
when x"F9" => byteOut <= x"99";
when x"FA" => byteOut <= x"84";
when x"FB" => byteOut <= x"8F";
when x"FC" => byteOut <= x"BE";
when x"FD" => byteOut <= x"B5";
when x"FE" => byteOut <= x"A8";
when x"FF" => byteOut <= x"A3";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x13 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x13;
architecture Behavioral of x13 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0D";
when x"02" => byteOut <= x"1A";
when x"03" => byteOut <= x"17";
when x"04" => byteOut <= x"34";
when x"05" => byteOut <= x"39";
when x"06" => byteOut <= x"2E";
when x"07" => byteOut <= x"23";
when x"08" => byteOut <= x"68";
when x"09" => byteOut <= x"65";
when x"0A" => byteOut <= x"72";
when x"0B" => byteOut <= x"7F";
when x"0C" => byteOut <= x"5C";
when x"0D" => byteOut <= x"51";
when x"0E" => byteOut <= x"46";
when x"0F" => byteOut <= x"4B";
when x"10" => byteOut <= x"D0";
when x"11" => byteOut <= x"DD";
when x"12" => byteOut <= x"CA";
when x"13" => byteOut <= x"C7";
when x"14" => byteOut <= x"E4";
when x"15" => byteOut <= x"E9";
when x"16" => byteOut <= x"FE";
when x"17" => byteOut <= x"F3";
when x"18" => byteOut <= x"B8";
when x"19" => byteOut <= x"B5";
when x"1A" => byteOut <= x"A2";
when x"1B" => byteOut <= x"AF";
when x"1C" => byteOut <= x"8C";
when x"1D" => byteOut <= x"81";
when x"1E" => byteOut <= x"96";
when x"1F" => byteOut <= x"9B";
when x"20" => byteOut <= x"BB";
when x"21" => byteOut <= x"B6";
when x"22" => byteOut <= x"A1";
when x"23" => byteOut <= x"AC";
when x"24" => byteOut <= x"8F";
when x"25" => byteOut <= x"82";
when x"26" => byteOut <= x"95";
when x"27" => byteOut <= x"98";
when x"28" => byteOut <= x"D3";
when x"29" => byteOut <= x"DE";
when x"2A" => byteOut <= x"C9";
when x"2B" => byteOut <= x"C4";
when x"2C" => byteOut <= x"E7";
when x"2D" => byteOut <= x"EA";
when x"2E" => byteOut <= x"FD";
when x"2F" => byteOut <= x"F0";
when x"30" => byteOut <= x"6B";
when x"31" => byteOut <= x"66";
when x"32" => byteOut <= x"71";
when x"33" => byteOut <= x"7C";
when x"34" => byteOut <= x"5F";
when x"35" => byteOut <= x"52";
when x"36" => byteOut <= x"45";
when x"37" => byteOut <= x"48";
when x"38" => byteOut <= x"03";
when x"39" => byteOut <= x"0E";
when x"3A" => byteOut <= x"19";
when x"3B" => byteOut <= x"14";
when x"3C" => byteOut <= x"37";
when x"3D" => byteOut <= x"3A";
when x"3E" => byteOut <= x"2D";
when x"3F" => byteOut <= x"20";
when x"40" => byteOut <= x"6D";
when x"41" => byteOut <= x"60";
when x"42" => byteOut <= x"77";
when x"43" => byteOut <= x"7A";
when x"44" => byteOut <= x"59";
when x"45" => byteOut <= x"54";
when x"46" => byteOut <= x"43";
when x"47" => byteOut <= x"4E";
when x"48" => byteOut <= x"05";
when x"49" => byteOut <= x"08";
when x"4A" => byteOut <= x"1F";
when x"4B" => byteOut <= x"12";
when x"4C" => byteOut <= x"31";
when x"4D" => byteOut <= x"3C";
when x"4E" => byteOut <= x"2B";
when x"4F" => byteOut <= x"26";
when x"50" => byteOut <= x"BD";
when x"51" => byteOut <= x"B0";
when x"52" => byteOut <= x"A7";
when x"53" => byteOut <= x"AA";
when x"54" => byteOut <= x"89";
when x"55" => byteOut <= x"84";
when x"56" => byteOut <= x"93";
when x"57" => byteOut <= x"9E";
when x"58" => byteOut <= x"D5";
when x"59" => byteOut <= x"D8";
when x"5A" => byteOut <= x"CF";
when x"5B" => byteOut <= x"C2";
when x"5C" => byteOut <= x"E1";
when x"5D" => byteOut <= x"EC";
when x"5E" => byteOut <= x"FB";
when x"5F" => byteOut <= x"F6";
when x"60" => byteOut <= x"D6";
when x"61" => byteOut <= x"DB";
when x"62" => byteOut <= x"CC";
when x"63" => byteOut <= x"C1";
when x"64" => byteOut <= x"E2";
when x"65" => byteOut <= x"EF";
when x"66" => byteOut <= x"F8";
when x"67" => byteOut <= x"F5";
when x"68" => byteOut <= x"BE";
when x"69" => byteOut <= x"B3";
when x"6A" => byteOut <= x"A4";
when x"6B" => byteOut <= x"A9";
when x"6C" => byteOut <= x"8A";
when x"6D" => byteOut <= x"87";
when x"6E" => byteOut <= x"90";
when x"6F" => byteOut <= x"9D";
when x"70" => byteOut <= x"06";
when x"71" => byteOut <= x"0B";
when x"72" => byteOut <= x"1C";
when x"73" => byteOut <= x"11";
when x"74" => byteOut <= x"32";
when x"75" => byteOut <= x"3F";
when x"76" => byteOut <= x"28";
when x"77" => byteOut <= x"25";
when x"78" => byteOut <= x"6E";
when x"79" => byteOut <= x"63";
when x"7A" => byteOut <= x"74";
when x"7B" => byteOut <= x"79";
when x"7C" => byteOut <= x"5A";
when x"7D" => byteOut <= x"57";
when x"7E" => byteOut <= x"40";
when x"7F" => byteOut <= x"4D";
when x"80" => byteOut <= x"DA";
when x"81" => byteOut <= x"D7";
when x"82" => byteOut <= x"C0";
when x"83" => byteOut <= x"CD";
when x"84" => byteOut <= x"EE";
when x"85" => byteOut <= x"E3";
when x"86" => byteOut <= x"F4";
when x"87" => byteOut <= x"F9";
when x"88" => byteOut <= x"B2";
when x"89" => byteOut <= x"BF";
when x"8A" => byteOut <= x"A8";
when x"8B" => byteOut <= x"A5";
when x"8C" => byteOut <= x"86";
when x"8D" => byteOut <= x"8B";
when x"8E" => byteOut <= x"9C";
when x"8F" => byteOut <= x"91";
when x"90" => byteOut <= x"0A";
when x"91" => byteOut <= x"07";
when x"92" => byteOut <= x"10";
when x"93" => byteOut <= x"1D";
when x"94" => byteOut <= x"3E";
when x"95" => byteOut <= x"33";
when x"96" => byteOut <= x"24";
when x"97" => byteOut <= x"29";
when x"98" => byteOut <= x"62";
when x"99" => byteOut <= x"6F";
when x"9A" => byteOut <= x"78";
when x"9B" => byteOut <= x"75";
when x"9C" => byteOut <= x"56";
when x"9D" => byteOut <= x"5B";
when x"9E" => byteOut <= x"4C";
when x"9F" => byteOut <= x"41";
when x"A0" => byteOut <= x"61";
when x"A1" => byteOut <= x"6C";
when x"A2" => byteOut <= x"7B";
when x"A3" => byteOut <= x"76";
when x"A4" => byteOut <= x"55";
when x"A5" => byteOut <= x"58";
when x"A6" => byteOut <= x"4F";
when x"A7" => byteOut <= x"42";
when x"A8" => byteOut <= x"09";
when x"A9" => byteOut <= x"04";
when x"AA" => byteOut <= x"13";
when x"AB" => byteOut <= x"1E";
when x"AC" => byteOut <= x"3D";
when x"AD" => byteOut <= x"30";
when x"AE" => byteOut <= x"27";
when x"AF" => byteOut <= x"2A";
when x"B0" => byteOut <= x"B1";
when x"B1" => byteOut <= x"BC";
when x"B2" => byteOut <= x"AB";
when x"B3" => byteOut <= x"A6";
when x"B4" => byteOut <= x"85";
when x"B5" => byteOut <= x"88";
when x"B6" => byteOut <= x"9F";
when x"B7" => byteOut <= x"92";
when x"B8" => byteOut <= x"D9";
when x"B9" => byteOut <= x"D4";
when x"BA" => byteOut <= x"C3";
when x"BB" => byteOut <= x"CE";
when x"BC" => byteOut <= x"ED";
when x"BD" => byteOut <= x"E0";
when x"BE" => byteOut <= x"F7";
when x"BF" => byteOut <= x"FA";
when x"C0" => byteOut <= x"B7";
when x"C1" => byteOut <= x"BA";
when x"C2" => byteOut <= x"AD";
when x"C3" => byteOut <= x"A0";
when x"C4" => byteOut <= x"83";
when x"C5" => byteOut <= x"8E";
when x"C6" => byteOut <= x"99";
when x"C7" => byteOut <= x"94";
when x"C8" => byteOut <= x"DF";
when x"C9" => byteOut <= x"D2";
when x"CA" => byteOut <= x"C5";
when x"CB" => byteOut <= x"C8";
when x"CC" => byteOut <= x"EB";
when x"CD" => byteOut <= x"E6";
when x"CE" => byteOut <= x"F1";
when x"CF" => byteOut <= x"FC";
when x"D0" => byteOut <= x"67";
when x"D1" => byteOut <= x"6A";
when x"D2" => byteOut <= x"7D";
when x"D3" => byteOut <= x"70";
when x"D4" => byteOut <= x"53";
when x"D5" => byteOut <= x"5E";
when x"D6" => byteOut <= x"49";
when x"D7" => byteOut <= x"44";
when x"D8" => byteOut <= x"0F";
when x"D9" => byteOut <= x"02";
when x"DA" => byteOut <= x"15";
when x"DB" => byteOut <= x"18";
when x"DC" => byteOut <= x"3B";
when x"DD" => byteOut <= x"36";
when x"DE" => byteOut <= x"21";
when x"DF" => byteOut <= x"2C";
when x"E0" => byteOut <= x"0C";
when x"E1" => byteOut <= x"01";
when x"E2" => byteOut <= x"16";
when x"E3" => byteOut <= x"1B";
when x"E4" => byteOut <= x"38";
when x"E5" => byteOut <= x"35";
when x"E6" => byteOut <= x"22";
when x"E7" => byteOut <= x"2F";
when x"E8" => byteOut <= x"64";
when x"E9" => byteOut <= x"69";
when x"EA" => byteOut <= x"7E";
when x"EB" => byteOut <= x"73";
when x"EC" => byteOut <= x"50";
when x"ED" => byteOut <= x"5D";
when x"EE" => byteOut <= x"4A";
when x"EF" => byteOut <= x"47";
when x"F0" => byteOut <= x"DC";
when x"F1" => byteOut <= x"D1";
when x"F2" => byteOut <= x"C6";
when x"F3" => byteOut <= x"CB";
when x"F4" => byteOut <= x"E8";
when x"F5" => byteOut <= x"E5";
when x"F6" => byteOut <= x"F2";
when x"F7" => byteOut <= x"FF";
when x"F8" => byteOut <= x"B4";
when x"F9" => byteOut <= x"B9";
when x"FA" => byteOut <= x"AE";
when x"FB" => byteOut <= x"A3";
when x"FC" => byteOut <= x"80";
when x"FD" => byteOut <= x"8D";
when x"FE" => byteOut <= x"9A";
when x"FF" => byteOut <= x"97";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x14 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x14;
architecture Behavioral of x14 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0E";
when x"02" => byteOut <= x"1C";
when x"03" => byteOut <= x"12";
when x"04" => byteOut <= x"38";
when x"05" => byteOut <= x"36";
when x"06" => byteOut <= x"24";
when x"07" => byteOut <= x"2A";
when x"08" => byteOut <= x"70";
when x"09" => byteOut <= x"7E";
when x"0A" => byteOut <= x"6C";
when x"0B" => byteOut <= x"62";
when x"0C" => byteOut <= x"48";
when x"0D" => byteOut <= x"46";
when x"0E" => byteOut <= x"54";
when x"0F" => byteOut <= x"5A";
when x"10" => byteOut <= x"E0";
when x"11" => byteOut <= x"EE";
when x"12" => byteOut <= x"FC";
when x"13" => byteOut <= x"F2";
when x"14" => byteOut <= x"D8";
when x"15" => byteOut <= x"D6";
when x"16" => byteOut <= x"C4";
when x"17" => byteOut <= x"CA";
when x"18" => byteOut <= x"90";
when x"19" => byteOut <= x"9E";
when x"1A" => byteOut <= x"8C";
when x"1B" => byteOut <= x"82";
when x"1C" => byteOut <= x"A8";
when x"1D" => byteOut <= x"A6";
when x"1E" => byteOut <= x"B4";
when x"1F" => byteOut <= x"BA";
when x"20" => byteOut <= x"DB";
when x"21" => byteOut <= x"D5";
when x"22" => byteOut <= x"C7";
when x"23" => byteOut <= x"C9";
when x"24" => byteOut <= x"E3";
when x"25" => byteOut <= x"ED";
when x"26" => byteOut <= x"FF";
when x"27" => byteOut <= x"F1";
when x"28" => byteOut <= x"AB";
when x"29" => byteOut <= x"A5";
when x"2A" => byteOut <= x"B7";
when x"2B" => byteOut <= x"B9";
when x"2C" => byteOut <= x"93";
when x"2D" => byteOut <= x"9D";
when x"2E" => byteOut <= x"8F";
when x"2F" => byteOut <= x"81";
when x"30" => byteOut <= x"3B";
when x"31" => byteOut <= x"35";
when x"32" => byteOut <= x"27";
when x"33" => byteOut <= x"29";
when x"34" => byteOut <= x"03";
when x"35" => byteOut <= x"0D";
when x"36" => byteOut <= x"1F";
when x"37" => byteOut <= x"11";
when x"38" => byteOut <= x"4B";
when x"39" => byteOut <= x"45";
when x"3A" => byteOut <= x"57";
when x"3B" => byteOut <= x"59";
when x"3C" => byteOut <= x"73";
when x"3D" => byteOut <= x"7D";
when x"3E" => byteOut <= x"6F";
when x"3F" => byteOut <= x"61";
when x"40" => byteOut <= x"AD";
when x"41" => byteOut <= x"A3";
when x"42" => byteOut <= x"B1";
when x"43" => byteOut <= x"BF";
when x"44" => byteOut <= x"95";
when x"45" => byteOut <= x"9B";
when x"46" => byteOut <= x"89";
when x"47" => byteOut <= x"87";
when x"48" => byteOut <= x"DD";
when x"49" => byteOut <= x"D3";
when x"4A" => byteOut <= x"C1";
when x"4B" => byteOut <= x"CF";
when x"4C" => byteOut <= x"E5";
when x"4D" => byteOut <= x"EB";
when x"4E" => byteOut <= x"F9";
when x"4F" => byteOut <= x"F7";
when x"50" => byteOut <= x"4D";
when x"51" => byteOut <= x"43";
when x"52" => byteOut <= x"51";
when x"53" => byteOut <= x"5F";
when x"54" => byteOut <= x"75";
when x"55" => byteOut <= x"7B";
when x"56" => byteOut <= x"69";
when x"57" => byteOut <= x"67";
when x"58" => byteOut <= x"3D";
when x"59" => byteOut <= x"33";
when x"5A" => byteOut <= x"21";
when x"5B" => byteOut <= x"2F";
when x"5C" => byteOut <= x"05";
when x"5D" => byteOut <= x"0B";
when x"5E" => byteOut <= x"19";
when x"5F" => byteOut <= x"17";
when x"60" => byteOut <= x"76";
when x"61" => byteOut <= x"78";
when x"62" => byteOut <= x"6A";
when x"63" => byteOut <= x"64";
when x"64" => byteOut <= x"4E";
when x"65" => byteOut <= x"40";
when x"66" => byteOut <= x"52";
when x"67" => byteOut <= x"5C";
when x"68" => byteOut <= x"06";
when x"69" => byteOut <= x"08";
when x"6A" => byteOut <= x"1A";
when x"6B" => byteOut <= x"14";
when x"6C" => byteOut <= x"3E";
when x"6D" => byteOut <= x"30";
when x"6E" => byteOut <= x"22";
when x"6F" => byteOut <= x"2C";
when x"70" => byteOut <= x"96";
when x"71" => byteOut <= x"98";
when x"72" => byteOut <= x"8A";
when x"73" => byteOut <= x"84";
when x"74" => byteOut <= x"AE";
when x"75" => byteOut <= x"A0";
when x"76" => byteOut <= x"B2";
when x"77" => byteOut <= x"BC";
when x"78" => byteOut <= x"E6";
when x"79" => byteOut <= x"E8";
when x"7A" => byteOut <= x"FA";
when x"7B" => byteOut <= x"F4";
when x"7C" => byteOut <= x"DE";
when x"7D" => byteOut <= x"D0";
when x"7E" => byteOut <= x"C2";
when x"7F" => byteOut <= x"CC";
when x"80" => byteOut <= x"41";
when x"81" => byteOut <= x"4F";
when x"82" => byteOut <= x"5D";
when x"83" => byteOut <= x"53";
when x"84" => byteOut <= x"79";
when x"85" => byteOut <= x"77";
when x"86" => byteOut <= x"65";
when x"87" => byteOut <= x"6B";
when x"88" => byteOut <= x"31";
when x"89" => byteOut <= x"3F";
when x"8A" => byteOut <= x"2D";
when x"8B" => byteOut <= x"23";
when x"8C" => byteOut <= x"09";
when x"8D" => byteOut <= x"07";
when x"8E" => byteOut <= x"15";
when x"8F" => byteOut <= x"1B";
when x"90" => byteOut <= x"A1";
when x"91" => byteOut <= x"AF";
when x"92" => byteOut <= x"BD";
when x"93" => byteOut <= x"B3";
when x"94" => byteOut <= x"99";
when x"95" => byteOut <= x"97";
when x"96" => byteOut <= x"85";
when x"97" => byteOut <= x"8B";
when x"98" => byteOut <= x"D1";
when x"99" => byteOut <= x"DF";
when x"9A" => byteOut <= x"CD";
when x"9B" => byteOut <= x"C3";
when x"9C" => byteOut <= x"E9";
when x"9D" => byteOut <= x"E7";
when x"9E" => byteOut <= x"F5";
when x"9F" => byteOut <= x"FB";
when x"A0" => byteOut <= x"9A";
when x"A1" => byteOut <= x"94";
when x"A2" => byteOut <= x"86";
when x"A3" => byteOut <= x"88";
when x"A4" => byteOut <= x"A2";
when x"A5" => byteOut <= x"AC";
when x"A6" => byteOut <= x"BE";
when x"A7" => byteOut <= x"B0";
when x"A8" => byteOut <= x"EA";
when x"A9" => byteOut <= x"E4";
when x"AA" => byteOut <= x"F6";
when x"AB" => byteOut <= x"F8";
when x"AC" => byteOut <= x"D2";
when x"AD" => byteOut <= x"DC";
when x"AE" => byteOut <= x"CE";
when x"AF" => byteOut <= x"C0";
when x"B0" => byteOut <= x"7A";
when x"B1" => byteOut <= x"74";
when x"B2" => byteOut <= x"66";
when x"B3" => byteOut <= x"68";
when x"B4" => byteOut <= x"42";
when x"B5" => byteOut <= x"4C";
when x"B6" => byteOut <= x"5E";
when x"B7" => byteOut <= x"50";
when x"B8" => byteOut <= x"0A";
when x"B9" => byteOut <= x"04";
when x"BA" => byteOut <= x"16";
when x"BB" => byteOut <= x"18";
when x"BC" => byteOut <= x"32";
when x"BD" => byteOut <= x"3C";
when x"BE" => byteOut <= x"2E";
when x"BF" => byteOut <= x"20";
when x"C0" => byteOut <= x"EC";
when x"C1" => byteOut <= x"E2";
when x"C2" => byteOut <= x"F0";
when x"C3" => byteOut <= x"FE";
when x"C4" => byteOut <= x"D4";
when x"C5" => byteOut <= x"DA";
when x"C6" => byteOut <= x"C8";
when x"C7" => byteOut <= x"C6";
when x"C8" => byteOut <= x"9C";
when x"C9" => byteOut <= x"92";
when x"CA" => byteOut <= x"80";
when x"CB" => byteOut <= x"8E";
when x"CC" => byteOut <= x"A4";
when x"CD" => byteOut <= x"AA";
when x"CE" => byteOut <= x"B8";
when x"CF" => byteOut <= x"B6";
when x"D0" => byteOut <= x"0C";
when x"D1" => byteOut <= x"02";
when x"D2" => byteOut <= x"10";
when x"D3" => byteOut <= x"1E";
when x"D4" => byteOut <= x"34";
when x"D5" => byteOut <= x"3A";
when x"D6" => byteOut <= x"28";
when x"D7" => byteOut <= x"26";
when x"D8" => byteOut <= x"7C";
when x"D9" => byteOut <= x"72";
when x"DA" => byteOut <= x"60";
when x"DB" => byteOut <= x"6E";
when x"DC" => byteOut <= x"44";
when x"DD" => byteOut <= x"4A";
when x"DE" => byteOut <= x"58";
when x"DF" => byteOut <= x"56";
when x"E0" => byteOut <= x"37";
when x"E1" => byteOut <= x"39";
when x"E2" => byteOut <= x"2B";
when x"E3" => byteOut <= x"25";
when x"E4" => byteOut <= x"0F";
when x"E5" => byteOut <= x"01";
when x"E6" => byteOut <= x"13";
when x"E7" => byteOut <= x"1D";
when x"E8" => byteOut <= x"47";
when x"E9" => byteOut <= x"49";
when x"EA" => byteOut <= x"5B";
when x"EB" => byteOut <= x"55";
when x"EC" => byteOut <= x"7F";
when x"ED" => byteOut <= x"71";
when x"EE" => byteOut <= x"63";
when x"EF" => byteOut <= x"6D";
when x"F0" => byteOut <= x"D7";
when x"F1" => byteOut <= x"D9";
when x"F2" => byteOut <= x"CB";
when x"F3" => byteOut <= x"C5";
when x"F4" => byteOut <= x"EF";
when x"F5" => byteOut <= x"E1";
when x"F6" => byteOut <= x"F3";
when x"F7" => byteOut <= x"FD";
when x"F8" => byteOut <= x"A7";
when x"F9" => byteOut <= x"A9";
when x"FA" => byteOut <= x"BB";
when x"FB" => byteOut <= x"B5";
when x"FC" => byteOut <= x"9F";
when x"FD" => byteOut <= x"91";
when x"FE" => byteOut <= x"83";
when x"FF" => byteOut <= x"8D";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end invMixColumn;
architecture Behavioral of invMixColumn is
signal t0_x1, t0_x9, t0_x11, t0_x13, t0_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t1_x1, t1_x9, t1_x11, t1_x13, t1_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t2_x1, t2_x9, t2_x11, t2_x13, t2_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t3_x1, t3_x9, t3_x11, t3_x13, t3_x14 : STD_LOGIC_VECTOR(7 downto 0);
component x9
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x11
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x13
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x14
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
begin
t0_x1 <= wordIn(31 downto 24);
t1_x1 <= wordIn(23 downto 16);
t2_x1 <= wordIn(15 downto 8);
t3_x1 <= wordIn(7 downto 0);
t0x9: x9 port map(byteIn => t0_x1, byteOut => t0_x9);
t1x9: x9 port map(byteIn => t1_x1, byteOut => t1_x9);
t2x9: x9 port map(byteIn => t2_x1, byteOut => t2_x9);
t3x9: x9 port map(byteIn => t3_x1, byteOut => t3_x9);
t0x11: x11 port map(byteIn => t0_x1, byteOut => t0_x11);
t1x11: x11 port map(byteIn => t1_x1, byteOut => t1_x11);
t2x11: x11 port map(byteIn => t2_x1, byteOut => t2_x11);
t3x11: x11 port map(byteIn => t3_x1, byteOut => t3_x11);
t0x13: x13 port map(byteIn => t0_x1, byteOut => t0_x13);
t1x13: x13 port map(byteIn => t1_x1, byteOut => t1_x13);
t2x13: x13 port map(byteIn => t2_x1, byteOut => t2_x13);
t3x13: x13 port map(byteIn => t3_x1, byteOut => t3_x13);
t0x14: x14 port map(byteIn => t0_x1, byteOut => t0_x14);
t1x14: x14 port map(byteIn => t1_x1, byteOut => t1_x14);
t2x14: x14 port map(byteIn => t2_x1, byteOut => t2_x14);
t3x14: x14 port map(byteIn => t3_x1, byteOut => t3_x14);
process(CLK, RESET, wordIn)
begin
if RESET = '1' then
wordOut <= (others => '0');
elsif rising_edge(CLK) then
wordOut(31 downto 24) <= t0_x14 XOR t1_x11 XOR t2_x13 XOR t3_x9;
wordOut(23 downto 16) <= t0_x9 XOR t1_x14 XOR t2_x11 XOR t3_x13;
wordOut(15 downto 8) <= t0_x13 XOR t1_x9 XOR t2_x14 XOR t3_x11;
wordOut(7 downto 0) <= t0_x11 XOR t1_x13 XOR t2_x9 XOR t3_x14;
end if;
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd | 4 | 3242 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00433ent IS
END c03s02b01x01p19n01i00433ent;
ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2integer_cons_vector is array (row,column) of integer;
constant C1 : s2integer_cons_vector := (others => (others => 3));
function complex_scalar(s : s2integer_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2integer_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2integer_cons_vector;
signal S2 : s2integer_cons_vector;
signal S3 : s2integer_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00433"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00433arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd | 4 | 2037 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1458.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01458ent IS
END c08s07b00x00p04n01i01458ent;
ARCHITECTURE c08s07b00x00p04n01i01458arch OF c08s07b00x00p04n01i01458ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 0 then
m := 1;
elsif delay = 4 then
n := 1;
else
k := 1;
end if;
assert NOT((m = 0) and (n = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01458"
severity NOTE;
assert (m = 0) and (n = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01458 - conditions after the if and elsif are evaluated to be FALSE, so should treat a final else as elsif TRUE then"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01458arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd | 4 | 4534 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_10 is
end entity fg_18_10;
architecture test of fg_18_10 is
signal temperature, setting : integer;
signal enable, heater_fail : bit;
begin
-- code from book
stimulus_interpreter : process is
use std.textio.all;
file control : text open read_mode is "control";
variable command : line;
variable read_ok : boolean;
variable next_time : time;
variable whitespace : character;
variable signal_id : string(1 to 4);
variable temp_value, set_value : integer;
variable on_value, fail_value : bit;
begin
command_loop : while not endfile(control) loop
readline ( control, command );
-- read next stimulus time, and suspend until then
read ( command, next_time, read_ok );
if not read_ok then
report "error reading time from line: " & command.all
severity warning;
next command_loop;
end if;
wait for next_time - now;
-- skip whitespace
while command'length > 0
and ( command(command'left) = ' ' -- ordinary space
or command(command'left) = ' ' -- non-breaking space
or command(command'left) = HT ) loop
read ( command, whitespace );
end loop;
-- read signal identifier string
read ( command, signal_id, read_ok );
if not read_ok then
report "error reading signal id from line: " & command.all
severity warning;
next command_loop;
end if;
-- dispatch based on signal id
case signal_id is
when "temp" =>
read ( command, temp_value, read_ok );
if not read_ok then
report "error reading temperature value from line: "
& command.all
severity warning;
next command_loop;
end if;
temperature <= temp_value;
when "set " =>
-- . . . -- similar to "temp"
-- not in book
read ( command, set_value, read_ok );
if not read_ok then
report "error reading setting value from line: "
& command.all
severity warning;
next command_loop;
end if;
setting <= set_value;
-- end not in book
when "on " =>
read ( command, on_value, read_ok );
if not read_ok then
report "error reading on value from line: "
& command.all
severity warning;
next command_loop;
end if;
enable <= on_value;
when "fail" =>
-- . . . -- similar to "on "
-- not in book
read ( command, fail_value, read_ok );
if not read_ok then
report "error reading fail value from line: "
& command.all
severity warning;
next command_loop;
end if;
heater_fail <= fail_value;
-- end not in book
when others =>
report "invalid signal id in line: " & signal_id
severity warning;
next command_loop;
end case;
end loop command_loop;
wait;
end process stimulus_interpreter;
-- end code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1002.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1002.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01002pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01002pkg;
use work.c06s03b00x00p09n01i01002pkg.all;
ENTITY c06s03b00x00p09n01i01002ent IS
END c06s03b00x00p09n01i01002ent;
ARCHITECTURE c06s03b00x00p09n01i01002arch OF c06s03b00x00p09n01i01002ent IS
BEGIN
TESTING: PROCESS
subtype ST7 is Q.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01002 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01002arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2557.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2557.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02557ent IS
END c07s03b06x00p02n01i02557ent;
ARCHITECTURE c07s03b06x00p02n01i02557arch OF c07s03b06x00p02n01i02557ent IS
BEGIN
TESTING: PROCESS
variable b : boolean;
BEGIN
b := new boolean;
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02557 - Not an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02557arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd | 4 | 1318 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package byte_swap_types is
subtype halfword is bit_vector(0 to 15);
end package byte_swap_types;
use work.byte_swap_types.all;
-- end not in book:
entity byte_swap is
port (input : in halfword; output : out halfword);
end entity byte_swap;
--------------------------------------------------
architecture behavior of byte_swap is
begin
swap : process (input)
begin
output(8 to 15) <= input(0 to 7);
output(0 to 7) <= input(8 to 15);
end process swap;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd | 4 | 2170 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc776.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p09n01i00776ent_a IS
port ( C1 : inout Bit ;
C2 : buffer Bit );
END c01s01b01x02p09n01i00776ent_a;
ARCHITECTURE c01s01b01x02p09n01i00776arch_a OF c01s01b01x02p09n01i00776ent_a IS
BEGIN
c1 <= c2;
END c01s01b01x02p09n01i00776arch_a;
ENTITY c01s01b01x02p09n01i00776ent IS
port ( p1 : inout Bit ;
p2 : buffer Bit );
END c01s01b01x02p09n01i00776ent;
ARCHITECTURE c01s01b01x02p09n01i00776arch OF c01s01b01x02p09n01i00776ent IS
component c01s01b01x02p09n01i00776ent_b
port ( C1 : inout Bit ;
C2 : buffer Bit );
end component;
for L : c01s01b01x02p09n01i00776ent_b use entity work.c01s01b01x02p09n01i00776ent_a(c01s01b01x02p09n01i00776arch_a);
BEGIN
L : c01s01b01x02p09n01i00776ent_b port map (p1, p2);
--Success here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p09n01i00776"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p09n01i00776arch;
| gpl-2.0 |
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