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systec-dk/openPOWERLINK_systec | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_burst_0.vhd | 3 | 41369 | --Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin
process (wrclock, clk) -- MG
VARIABLE rd_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
VARIABLE wr_address_internal : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
begin
-- Write data
if wrclock'event and wrclock = '1' then
wr_address_internal := wraddress;
if wren = '1' then
Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
end if;
end if;
-- read data
q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rd_address_internal)));
IF clk'event AND clk = '1' AND rdclken = '1' THEN
rd_address_internal := rdaddress;
END IF;
end process;
end europa;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--library altera;
--use altera.altera_europa_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--entity niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- port (
--
-- signal clk : IN STD_LOGIC;
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC;
-- signal reset_n : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wrclock : IN STD_LOGIC;
-- signal wren : IN STD_LOGIC;
--
--
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
-- );
--end entity niosII_openMac_burst_0_fifo_module_fifo_ram_module;
--
--
--architecture europa of niosII_openMac_burst_0_fifo_module_fifo_ram_module is
-- component lpm_ram_dp is
--GENERIC (
-- lpm_file : STRING;
-- lpm_hint : STRING;
-- lpm_indata : STRING;
-- lpm_outdata : STRING;
-- lpm_rdaddress_control : STRING;
-- lpm_width : NATURAL;
-- lpm_widthad : NATURAL;
-- lpm_wraddress_control : STRING;
-- suppress_memory_conversion_warnings : STRING
-- );
-- PORT (
-- signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal wren : IN STD_LOGIC;
-- signal rdclock : IN STD_LOGIC;
-- signal wrclock : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-- signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC
-- );
-- end component lpm_ram_dp;
-- signal internal_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- TYPE mem_array is ARRAY( 3 DOWNTO 0) of STD_LOGIC_VECTOR(31 DOWNTO 0);
-- signal read_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
--
--begin
--
-- process (rdaddress)
-- begin
-- read_address <= rdaddress;
--
-- end process;
--
-- lpm_ram_dp_component : lpm_ram_dp
-- generic map(
-- lpm_file => "UNUSED",
-- lpm_hint => "USE_EAB=OFF",
-- lpm_indata => "REGISTERED",
-- lpm_outdata => "UNREGISTERED",
-- lpm_rdaddress_control => "REGISTERED",
-- lpm_width => 32,
-- lpm_widthad => 2,
-- lpm_wraddress_control => "REGISTERED",
-- suppress_memory_conversion_warnings => "ON"
-- )
-- port map(
-- data => data,
-- q => internal_q,
-- rdaddress => read_address,
-- rdclken => rdclken,
-- rdclock => clk,
-- wraddress => wraddress,
-- wrclock => wrclock,
-- wren => wren
-- );
--
--
-- q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0_fifo_module;
architecture europa of niosII_openMac_burst_0_fifo_module is
component niosII_openMac_burst_0_fifo_module_fifo_ram_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component niosII_openMac_burst_0_fifo_module_fifo_ram_module;
signal estimated_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_dec : STD_LOGIC;
signal fifo_inc : STD_LOGIC;
signal fifo_ram_q : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_fifo_empty : STD_LOGIC;
signal internal_fifo_full : STD_LOGIC;
signal internal_p1_fifo_empty : STD_LOGIC;
signal last_write_collision : STD_LOGIC;
signal last_write_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal module_input : STD_LOGIC;
signal p1_estimated_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_fifo_full : STD_LOGIC;
signal p1_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rdaddress_reg : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_collision : STD_LOGIC;
begin
p1_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((fifo_write)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
wraddress <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
wraddress <= std_logic_vector'("00");
else
wraddress <= p1_wraddress;
end if;
end if;
end if;
end process;
rdaddress <= A_EXT (A_WE_StdLogicVector((std_logic'(flush_fifo) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(fifo_read) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001"))), (std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
rdaddress_reg <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
rdaddress_reg <= rdaddress;
end if;
end process;
fifo_datavalid <= NOT internal_fifo_empty;
fifo_inc <= fifo_write AND NOT fifo_read;
fifo_dec <= fifo_read AND NOT fifo_write;
estimated_rdaddress <= A_EXT (((std_logic_vector'("0000000000000000000000000000000") & (rdaddress_reg)) - std_logic_vector'("000000000000000000000000000000001")), 2);
p1_estimated_wraddress <= A_EXT (A_WE_StdLogicVector((std_logic'((inc_pending_data)) = '1'), ((std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("0000000000000000000000000000000") & (estimated_wraddress))), 2);
process (clk, reset_n)
begin
if reset_n = '0' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
if std_logic'(flush_fifo) = '1' then
estimated_wraddress <= A_REP(std_logic'('1'), 2);
else
estimated_wraddress <= p1_estimated_wraddress;
end if;
end if;
end if;
end process;
internal_p1_fifo_empty <= flush_fifo OR ((((NOT fifo_inc AND internal_fifo_empty)) OR ((fifo_dec AND to_std_logic(((wraddress = estimated_rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_empty <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_empty <= internal_p1_fifo_empty;
end if;
end if;
end process;
p1_fifo_full <= NOT flush_fifo AND ((((NOT fifo_dec AND internal_fifo_full)) OR ((inc_pending_data AND to_std_logic(((estimated_wraddress = rdaddress)))))));
process (clk, reset_n)
begin
if reset_n = '0' then
internal_fifo_full <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
internal_fifo_full <= p1_fifo_full;
end if;
end if;
end process;
write_collision <= fifo_write AND to_std_logic(((wraddress = rdaddress)));
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_data <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_data <= fifo_wr_data;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
last_write_collision <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(write_collision) = '1' then
last_write_collision <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(fifo_read) = '1' then
last_write_collision <= std_logic'('0');
end if;
end if;
end process;
fifo_rd_data <= A_WE_StdLogicVector((std_logic'(last_write_collision) = '1'), last_write_data, fifo_ram_q);
--niosII_openMac_burst_0_fifo_module_fifo_ram, which is an e_ram
niosII_openMac_burst_0_fifo_module_fifo_ram : niosII_openMac_burst_0_fifo_module_fifo_ram_module
port map(
q => fifo_ram_q,
clk => clk,
data => fifo_wr_data,
rdaddress => rdaddress,
rdclken => module_input,
reset_n => reset_n,
wraddress => wraddress,
wrclock => clk,
wren => fifo_write
);
module_input <= std_logic'('1');
--vhdl renameroo for output signals
fifo_empty <= internal_fifo_empty;
--vhdl renameroo for output signals
fifo_full <= internal_fifo_full;
--vhdl renameroo for output signals
p1_fifo_empty <= internal_p1_fifo_empty;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
--
--Burst adapter parameters:
--adapter is mastered by: powerlink_0/MAC_DMA
--adapter masters: SRAM_0/avalon_tristate_slave
--asp_debug: 0
--byteaddr_width: 23
--ceil_data_width: 32
--data_width: 32
--dbs_shift: -1
--dbs_upstream_burstcount_width: 3
--downstream_addr_shift: 2
--downstream_burstcount_width: 1
--downstream_max_burstcount: 1
--downstream_pipeline: 0
--dynamic_slave: 1
--master_always_burst_max_burst: 0
--master_burst_on_burst_boundaries_only: 0
--master_data_width: 16
--master_interleave: 0
--master_linewrap_bursts: 0
--nativeaddr_width: 21
--slave_always_burst_max_burst: 0
--slave_burst_on_burst_boundaries_only: 0
--slave_interleave: 0
--slave_linewrap_bursts: 0
--upstream_burstcount: upstream_burstcount
--upstream_burstcount_width: 3
--upstream_max_burstcount: 4
--zero_address_width: 0
entity niosII_openMac_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_burst_0;
architecture europa of niosII_openMac_burst_0 is
component niosII_openMac_burst_0_fifo_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal fifo_read : IN STD_LOGIC;
signal fifo_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : IN STD_LOGIC;
signal flush_fifo : IN STD_LOGIC;
signal inc_pending_data : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal fifo_datavalid : OUT STD_LOGIC;
signal fifo_empty : OUT STD_LOGIC;
signal fifo_full : OUT STD_LOGIC;
signal fifo_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal p1_fifo_empty : OUT STD_LOGIC
);
end component niosII_openMac_burst_0_fifo_module;
signal address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal atomic_counter : STD_LOGIC;
signal current_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal current_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal current_upstream_read : STD_LOGIC;
signal current_upstream_write : STD_LOGIC;
signal data_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal downstream_address_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal downstream_burstdone : STD_LOGIC;
signal enable_state_change : STD_LOGIC;
signal fifo_datavalid : STD_LOGIC;
signal fifo_empty : STD_LOGIC;
signal fifo_full : STD_LOGIC;
signal fifo_rd_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_read : STD_LOGIC;
signal fifo_wr_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_write : STD_LOGIC;
signal flush_fifo : STD_LOGIC;
signal full_width_rdv_counter : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal internal_downstream_burstcount : STD_LOGIC;
signal internal_downstream_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_downstream_read : STD_LOGIC;
signal internal_downstream_write : STD_LOGIC;
signal internal_upstream_readdatavalid : STD_LOGIC;
signal internal_upstream_waitrequest : STD_LOGIC;
signal max_burst_size : STD_LOGIC;
signal module_input1 : STD_LOGIC;
signal negative_dbs_rdv_counter : STD_LOGIC;
signal negative_dbs_read_expression : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_atomic_counter : STD_LOGIC;
signal p1_fifo_empty : STD_LOGIC;
signal p1_state_busy : STD_LOGIC;
signal p1_state_idle : STD_LOGIC;
signal pending_register_enable : STD_LOGIC;
signal pending_upstream_read : STD_LOGIC;
signal pending_upstream_read_reg : STD_LOGIC;
signal pending_upstream_write : STD_LOGIC;
signal pending_upstream_write_reg : STD_LOGIC;
signal quantized_burst_base : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal quantized_burst_limit : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal read_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal read_update_count : STD_LOGIC;
signal read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_read_write_dbs_adjusted_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_address : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal registered_upstream_burstcount : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal registered_upstream_nativeaddress : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal registered_upstream_read : STD_LOGIC;
signal registered_upstream_write : STD_LOGIC;
signal state_busy : STD_LOGIC;
signal state_idle : STD_LOGIC;
signal sync_nativeaddress : STD_LOGIC;
signal transactions_remaining : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal transactions_remaining_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal update_count : STD_LOGIC;
signal upstream_burstdone : STD_LOGIC;
signal upstream_read_run : STD_LOGIC;
signal upstream_write_run : STD_LOGIC;
signal write_address_offset : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal write_update_count : STD_LOGIC;
begin
sync_nativeaddress <= or_reduce(upstream_nativeaddress);
--downstream, which is an e_avalon_master
--upstream, which is an e_avalon_slave
upstream_burstdone <= A_WE_StdLogic((std_logic'(current_upstream_read) = '1'), ((to_std_logic(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))))) AND internal_downstream_read) AND NOT downstream_waitrequest), ((to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (transactions_remaining)) = (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + std_logic_vector'("000000000000000000000000000000001")))))) AND internal_downstream_write) AND NOT downstream_waitrequest));
p1_atomic_counter <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(atomic_counter))) + (std_logic_vector'("0") & ((A_WE_StdLogicVector((std_logic'(internal_downstream_read) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")))))));
downstream_burstdone <= (((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest) AND to_std_logic(((std_logic'(p1_atomic_counter) = std_logic'(internal_downstream_burstcount))));
quantized_burst_base <= A_EXT (((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000011")), 23);
quantized_burst_limit <= A_EXT (((std_logic_vector'("0") & ((((((std_logic_vector'("0") & (((std_logic_vector'("0") & ((((std_logic_vector'("000000000") & (upstream_address)) AND NOT std_logic_vector'("00000000000000000000000000000001"))))) + (std_logic_vector'("00000000000000000000000000000") & ((upstream_burstcount & A_ToStdLogicVector(std_logic'('0')))))))) - std_logic_vector'("0000000000000000000000000000000001"))) OR std_logic_vector'("0000000000000000000000000000000011"))))) + std_logic_vector'("00000000000000000000000000000000001")), 23);
negative_dbs_read_expression <= A_EXT (A_SRL((((std_logic_vector'("0") & (quantized_burst_limit)) - (std_logic_vector'("0") & (quantized_burst_base)))),std_logic_vector'("00000000000000000000000000000010")), 3);
dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), read_write_dbs_adjusted_upstream_burstcount, registered_read_write_dbs_adjusted_upstream_burstcount);
read_write_dbs_adjusted_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(upstream_read) = '1'), negative_dbs_read_expression, upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
registered_read_write_dbs_adjusted_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_read_write_dbs_adjusted_upstream_burstcount <= read_write_dbs_adjusted_upstream_burstcount;
end if;
end if;
end process;
p1_state_idle <= ((state_idle AND NOT upstream_read) AND NOT upstream_write) OR ((((state_busy AND to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000"))))) AND p1_fifo_empty) AND NOT pending_upstream_read) AND NOT pending_upstream_write);
p1_state_busy <= (state_idle AND ((upstream_read OR upstream_write))) OR (state_busy AND ((((to_std_logic(NOT (((std_logic_vector'("00000000000000000000000000000") & (data_counter)) = std_logic_vector'("00000000000000000000000000000000")))) OR NOT p1_fifo_empty) OR pending_upstream_read) OR pending_upstream_write)));
enable_state_change <= NOT ((internal_downstream_read OR internal_downstream_write)) OR NOT downstream_waitrequest;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_read_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((upstream_read AND state_idle)) = '1' then
pending_upstream_read_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
elsif std_logic'(downstream_readdatavalid) = '1' then
pending_upstream_read_reg <= std_logic'('0');
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
pending_upstream_write_reg <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(upstream_burstdone) = '1' then
pending_upstream_write_reg <= std_logic'('0');
elsif std_logic'((upstream_write AND ((state_idle OR NOT internal_upstream_waitrequest)))) = '1' then
pending_upstream_write_reg <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_idle <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_idle <= p1_state_idle;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
state_busy <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(enable_state_change) = '1' then
state_busy <= p1_state_busy;
end if;
end if;
end process;
pending_upstream_read <= pending_upstream_read_reg;
pending_upstream_write <= pending_upstream_write_reg AND NOT upstream_burstdone;
pending_register_enable <= state_idle OR ((((upstream_read OR upstream_write)) AND NOT internal_upstream_waitrequest));
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_read <= upstream_read;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_write <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_write <= upstream_write;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_burstcount <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_burstcount <= upstream_burstcount;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_address <= std_logic_vector'("00000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_address <= upstream_address;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
registered_upstream_nativeaddress <= std_logic_vector'("000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(pending_register_enable) = '1' then
registered_upstream_nativeaddress <= upstream_nativeaddress;
end if;
end if;
end process;
current_upstream_read <= registered_upstream_read AND NOT(internal_downstream_write);
current_upstream_write <= registered_upstream_write;
current_upstream_address <= registered_upstream_address;
current_upstream_burstcount <= A_WE_StdLogicVector((std_logic'(pending_register_enable) = '1'), upstream_burstcount, registered_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
atomic_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((internal_downstream_read OR internal_downstream_write)) AND NOT downstream_waitrequest)) = '1' then
atomic_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(downstream_burstdone) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(p1_atomic_counter)))));
end if;
end if;
end process;
read_update_count <= current_upstream_read AND NOT downstream_waitrequest;
write_update_count <= (current_upstream_write AND internal_downstream_write) AND downstream_burstdone;
update_count <= read_update_count OR write_update_count;
transactions_remaining <= A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), dbs_adjusted_upstream_burstcount, transactions_remaining_reg);
process (clk, reset_n)
begin
if reset_n = '0' then
transactions_remaining_reg <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
transactions_remaining_reg <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND ((upstream_read OR upstream_write))))) = '1'), (std_logic_vector'("0") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(update_count) = '1'), ((std_logic_vector'("0") & (transactions_remaining_reg)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (transactions_remaining_reg)))), 3);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
data_counter <= A_EXT (A_WE_StdLogicVector((std_logic'(((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (dbs_adjusted_upstream_burstcount)), A_WE_StdLogicVector((std_logic'(downstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (data_counter)) - std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (data_counter)))), 3);
end if;
end process;
max_burst_size <= std_logic'('1');
internal_downstream_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (std_logic_vector'("00000000000000000000000000000") & ((A_WE_StdLogicVector(((transactions_remaining>(std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))))), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(max_burst_size))), transactions_remaining)))), std_logic_vector'("00000000000000000000000000000001")));
downstream_arbitrationshare <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), (dbs_adjusted_upstream_burstcount), dbs_adjusted_upstream_burstcount);
process (clk, reset_n)
begin
if reset_n = '0' then
write_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
write_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_write)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((internal_downstream_write AND NOT downstream_waitrequest) AND downstream_burstdone) AND or_reduce(internal_downstream_byteenable(3 DOWNTO 2))))) = '1'), ((std_logic_vector'("0") & (write_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (write_address_offset)))))), 2);
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
read_address_offset <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
read_address_offset <= A_EXT (A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((internal_downstream_read AND NOT downstream_waitrequest))) = '1'), ((std_logic_vector'("0") & (read_address_offset)) + (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount)))), (std_logic_vector'("0") & (read_address_offset)))))), 2);
end if;
end process;
downstream_nativeaddress <= A_SRL(registered_upstream_nativeaddress,std_logic_vector'("00000000000000000000000000000001"));
address_offset <= A_WE_StdLogicVector((std_logic'(current_upstream_read) = '1'), read_address_offset, write_address_offset);
downstream_address_base <= current_upstream_address;
downstream_address <= A_EXT (((std_logic_vector'("0") & (downstream_address_base)) + (std_logic_vector'("00000000000000000000") & ((address_offset & std_logic_vector'("00"))))), 21);
process (clk, reset_n)
begin
if reset_n = '0' then
internal_downstream_read <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((NOT internal_downstream_read OR NOT downstream_waitrequest)) = '1' then
internal_downstream_read <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((state_idle AND upstream_read)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector(((transactions_remaining = (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(internal_downstream_burstcount))))), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_downstream_read))))));
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
negative_dbs_rdv_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
negative_dbs_rdv_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(upstream_address(1)))), A_WE_StdLogicVector((std_logic'(fifo_datavalid) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))));
end if;
end process;
fifo_read <= NOT fifo_empty AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))) = std_logic_vector'("00000000000000000000000000000001"))) OR (((((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001"))) = (std_logic_vector'("000000000000000000000000000000") & (current_upstream_burstcount)))))));
fifo_write <= downstream_readdatavalid;
fifo_wr_data <= downstream_readdata;
flush_fifo <= std_logic'('0');
--the_niosII_openMac_burst_0_fifo_module, which is an e_instance
the_niosII_openMac_burst_0_fifo_module : niosII_openMac_burst_0_fifo_module
port map(
fifo_datavalid => fifo_datavalid,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
fifo_rd_data => fifo_rd_data,
p1_fifo_empty => p1_fifo_empty,
clk => clk,
clk_en => module_input1,
fifo_read => fifo_read,
fifo_wr_data => fifo_wr_data,
fifo_write => fifo_write,
flush_fifo => flush_fifo,
inc_pending_data => fifo_write,
reset_n => reset_n
);
module_input1 <= std_logic'('1');
process (clk, reset_n)
begin
if reset_n = '0' then
full_width_rdv_counter <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
full_width_rdv_counter <= A_EXT (A_WE_StdLogicVector((std_logic'((((state_idle AND upstream_read) AND NOT internal_upstream_waitrequest))) = '1'), std_logic_vector'("000000000000000000000000000000000"), A_WE_StdLogicVector((std_logic'(internal_upstream_readdatavalid) = '1'), ((std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)) + std_logic_vector'("000000000000000000000000000000001")), (std_logic_vector'("000000000000000000000000000000") & (full_width_rdv_counter)))), 3);
end if;
end process;
internal_upstream_readdatavalid <= fifo_datavalid;
upstream_readdata <= A_WE_StdLogicVector(((std_logic_vector'("00000000000000000000000000000000") = (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(negative_dbs_rdv_counter))))), Std_Logic_Vector'(fifo_rd_data(15 DOWNTO 0) & fifo_rd_data(15 DOWNTO 0)), Std_Logic_Vector'(fifo_rd_data(31 DOWNTO 16) & fifo_rd_data(31 DOWNTO 16)));
internal_downstream_byteenable <= upstream_byteenable;
internal_downstream_write <= ((upstream_write AND state_busy) AND NOT(pending_upstream_read)) AND fifo_empty;
downstream_writedata <= upstream_writedata;
upstream_read_run <= state_idle AND upstream_read;
upstream_write_run <= ((state_busy AND upstream_write) AND NOT downstream_waitrequest) AND NOT(internal_downstream_read);
internal_upstream_waitrequest <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((upstream_read OR current_upstream_read))) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_read_run))), A_WE_StdLogicVector((std_logic'(current_upstream_write) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT upstream_write_run))), std_logic_vector'("00000000000000000000000000000001"))));
downstream_debugaccess <= upstream_debugaccess;
--vhdl renameroo for output signals
downstream_burstcount <= internal_downstream_burstcount;
--vhdl renameroo for output signals
downstream_byteenable <= internal_downstream_byteenable;
--vhdl renameroo for output signals
downstream_read <= internal_downstream_read;
--vhdl renameroo for output signals
downstream_write <= internal_downstream_write;
--vhdl renameroo for output signals
upstream_readdatavalid <= internal_upstream_readdatavalid;
--vhdl renameroo for output signals
upstream_waitrequest <= internal_upstream_waitrequest;
--synthesis translate_off
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'((fifo_full AND fifo_write)) = '1' then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("simulation assertion failed: niosII_openMac_burst_0: illegal write into full fifo."));
write(output, write_line.all);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/lib/src/req_ack.vhd | 3 | 3089 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
entity req_ack is
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
ack : out std_logic
);
end req_ack;
architecture rtl of req_ack is
constant iMaxCnt : integer := ack_delay_g;
constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0);
signal cnt_tc : std_logic;
begin
genDelay : if zero_delay_g = false generate
theCnter : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
end if;
end process;
cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0');
cnt_tc <= '1' when cnt = iMaxCnt else '0';
ack <= cnt_tc;
end generate;
genNoDelay : if zero_delay_g = true generate
ack <= enable;
end generate;
end rtl;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openHUB.vhd | 3 | 7075 | -------------------------------------------------------------------------------
-- OpenHUB
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK
-- ReceivePort return currently active Port
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenHUB IS
GENERIC ( Ports : integer := 3 );
PORT ( Rst : IN std_logic;
Clk : IN std_logic;
RxDv : IN std_logic_vector(Ports DOWNTO 1);
RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1);
TxEn : OUT std_logic_vector(Ports DOWNTO 1);
TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1);
internPort : IN integer RANGE 1 TO Ports := 1;
TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1');
ReceivePort : OUT integer RANGE 0 TO Ports
);
END ENTITY OpenHUB;
ARCHITECTURE struct OF OpenHUB IS
SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports;
SIGNAL HubActive : boolean;
SIGNAL CollStatus : boolean;
SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1);
BEGIN
RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0';
RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0';
RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0';
TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1);
TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1);
TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1);
do: PROCESS (Rst, Clk)
VARIABLE Active : boolean;
VARIABLE Master : integer RANGE 0 TO Ports;
VARIABLE Master_at_Coll : integer RANGE 0 TO Ports;
VARIABLE Coll : boolean;
VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0);
BEGIN
IF Rst = '1' THEN
RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0');
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
Active := false;
Master := 0;
Master_at_Coll := 0;
Coll := false;
TransmitMask_L <= (OTHERS => '1');
ELSIF rising_edge(Clk) THEN
RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1;
IF Active = false THEN
IF RxDvL /= 0 THEN
FOR i IN 1 TO Ports LOOP
IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN
Master := i;
Active := true;
EXIT;
END IF;
END LOOP;
END IF;
ELSE
IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN
Master := 0;
END IF;
IF RxDvL = 0 AND RxDvI = 0 THEN
Active := false;
END IF;
END IF;
IF Master = 0 THEN
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
-- Overtake new TransmitMask only, when there is no active frame.
TransmitMask_L <= TransmitMask;
ELSE
FOR i IN 1 TO Ports LOOP -- output received frame to every port
IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac)
IF TransmitMask_L(i) = '1' OR Master = internPort THEN
TxEnI(i) <= '1';
TxDatI0(i) <= RxDatL0(Master);
TxDatI1(i) <= RxDatL1(Master);
END IF;
-- If there is a frame received and another is sent => collision!
IF RxDvL(i) = '1' THEN
Coll := true;
Master_at_Coll := Master;
END IF;
END IF;
END LOOP;
END IF;
IF Coll = true THEN
TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0';
RxDvM := RxDvL;
RxDvM(Master_at_Coll) := '0';
IF RxDvM = 0 THEN
TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0';
Coll := false;
Master_at_Coll := 0;
END IF;
END IF;
END IF;
HubActive <= Active;
MasterAtCollNumber <= Master_at_Coll;
CollStatus <= Coll;
-- Output the Master Port - identifies the port (1...n) which has received the packet.
-- If Master is 0, the Hub is inactive.
ReceivePort <= Master;
END PROCESS do;
END struct;
| gpl-2.0 |
sjohann81/hf-risc | mips/platform/spartan3e_nexys2/spartan3e_nexys2.vhd | 2 | 4656 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 |
mossmann/hackrf | firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-2.0 |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/spi_sram_ctrl_tb.vhd | 1 | 1411 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, burst, bmode, hmode, wr, rd, data_ack, stall, spi_cs, spi_clk, spi_mosi, spi_miso, hold_n: std_logic := '0';
signal addr_in: std_logic_vector(23 downto 0);
signal data_in, data_out: std_logic_vector(31 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
wr <= '0', '1' after 1000 ns, '0' after 1100 ns;
rd <= '0', '1' after 15000 ns, '0' after 15200 ns;
addr_in <= x"001000";
data_in <= x"aa556699";
burst <= '0';
bmode <= '0';
hmode <= '0';
hold_n <= '1';
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock,
rst_i => reset,
addr_i => addr_in,
data_i => data_in,
data_o => data_out,
burst_i => burst,
bmode_i => bmode,
hmode_i => hmode,
wr_i => wr,
rd_i => rd,
data_ack_o => data_ack,
cpu_stall_o => stall,
spi_cs_n_o => spi_cs,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
end tb;
| gpl-2.0 |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2.vhd | 1 | 4864 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 |
jasonpeng/cg3207-proj | EX_MEM_BUFF.vhd | 1 | 3144 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:35 10/31/2013
-- Design Name:
-- Module Name: EX_MEM_BUFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EX_MEM_BUFF is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- states received from EX
-- state registers
IN_EX_MemWrite : in STD_LOGIC;
IN_EX_MemToReg : in STD_LOGIC;
IN_EX_MemRead : in STD_LOGIC;
IN_EX_RegWrite : in STD_LOGIC;
-- alu related
IN_EX_OVF : in STD_LOGIC;
IN_EX_Zero : in STD_LOGIC;
IN_EX_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_MULDIV : in STD_LOGIC;
IN_EX_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- for DM Write Data
IN_EX_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0); -- register address
OUT_MEM_MemWrite : out STD_LOGIC;
OUT_MEM_MemToReg : out STD_LOGIC;
OUT_MEM_MemRead : out STD_LOGIC;
OUT_MEM_RegWrite : out STD_LOGIC;
-- alu related
OUT_MEM_OVF : out STD_LOGIC;
OUT_MEM_Zero : out STD_LOGIC;
OUT_MEM_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_MULDIV : out STD_LOGIC;
OUT_MEM_Data2 : out STD_LOGIC_VECTOR(31 downto 0); -- for DM Write Data
OUT_MEM_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0) -- register address
);
end EX_MEM_BUFF;
architecture Behavioral of EX_MEM_BUFF is
begin
process(CLK, RESET)
begin
if (RESET = '1') then
OUT_MEM_MemWrite <= '0';
OUT_MEM_MemToReg <= '0';
OUT_MEM_MemRead <= '0';
OUT_MEM_RegWrite <= '0';
OUT_MEM_OVF <= '0';
OUT_MEM_Zero <= '0';
OUT_MEM_ALU_Result <= (others => '0');
OUT_MEM_ALU_Result_2 <= (others => '0');
OUT_MEM_MULDIV <= '0';
OUT_MEM_Data2 <= (others => '0');
OUT_MEM_REG_WriteAddr <= (others => '0');
elsif rising_edge(CLK) then
OUT_MEM_MemWrite <= IN_EX_MemWrite;
OUT_MEM_MemToReg <= IN_EX_MemToReg;
OUT_MEM_MemRead <= IN_EX_MemRead;
OUT_MEM_RegWrite <= IN_EX_RegWrite;
OUT_MEM_OVF <= IN_EX_OVF;
OUT_MEM_Zero <= IN_EX_Zero;
OUT_MEM_ALU_Result <= IN_EX_ALU_Result;
OUT_MEM_ALU_Result_2 <= IN_EX_ALU_Result_2;
OUT_MEM_MULDIV <= IN_EX_MULDIV;
OUT_MEM_Data2 <= IN_EX_Data2;
OUT_MEM_REG_WriteAddr <= IN_EX_REG_WriteAddr;
end if;
end process;
end Behavioral;
| gpl-2.0 |
Cognoscan/ctags | Test/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2_basic_soc.vhd | 1 | 4991 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 |
sjohann81/hf-risc | devices/controllers/spi_master_slave/spi_master_slave.vhd | 1 | 4871 | -- file: spi_master_slave.vhd
-- description: SPI master slave interface
-- date: 01/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- This is a simple SPI master / slave interface that works in SPI MODE 0.
-- Chip select logic is not included and selects the operating mode (spi_ssn_i <= '0'
-- for slave mode and spi_ssn_i <= '1' for master mode). The usual terminology of the
-- clock and data buses (SCK, MISO and MOSI) is changed because the interface can act
-- in both modes. So, the SPI clock bus works in either direction and MISO, MOSI data
-- buses are changed to DI and DO respectively.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_master_slave is
generic (
BYTE_SIZE: integer := 8
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
data_i: in std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data in (clocked on rising spi_clk after last bit)
data_o: out std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data output (clocked on rising spi_clk after last bit)
data_valid_o: out std_logic; -- data valid (read / write finished)
wren_i: in std_logic; -- data write enable, starts transmission when interface is idle
clk_div_i: in std_logic_vector(8 downto 0); -- SPI clock divider
-- SPI interface
spi_ssn_i: in std_logic; -- spi slave select negated input
spi_clk_i: in std_logic; -- spi slave clock input
spi_clk_o: out std_logic; -- spi master clock output
spi_do_o: out std_logic; -- spi mosi (master mode) or miso (slave mode)
spi_di_i: in std_logic -- spi miso (master mode) or mosi (slave mode)
);
end spi_master_slave;
architecture spi_master_slave_arch of spi_master_slave is
type states is (idle, data1, clock1, data2, clock2, sdata1, sdata2, done);
signal state: states;
signal data_reg: std_logic_vector(BYTE_SIZE-1 downto 0);
signal clk_cnt: std_logic_vector(8 downto 0);
signal counter: std_logic_vector(8 downto 0);
signal fsm_trigger: std_logic;
begin
process(clk_i, rst_i)
begin
if rst_i = '1' then
clk_cnt <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if (clk_cnt < clk_div_i) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= (others => '0');
end if;
end if;
end process;
fsm_trigger <= '1' when clk_cnt = "000000000" or spi_ssn_i = '0' else '0';
process(clk_i, rst_i, spi_clk_i, fsm_trigger)
begin
if rst_i = '1' then
data_reg <= (others => '0');
counter <= (others => '0');
data_valid_o <= '0';
spi_clk_o <= '0';
spi_do_o <= '0';
elsif clk_i'event and clk_i = '1' then
if (fsm_trigger = '1') then
case state is
when idle =>
counter <= (others => '0');
spi_clk_o <= '0';
spi_do_o <= '0';
data_valid_o <= '0';
data_reg <= data_i;
when data1 =>
data_valid_o <= '0';
spi_do_o <= data_reg(BYTE_SIZE-1);
when clock1 =>
spi_clk_o <= '1';
when data2 =>
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_di_i;
when clock2 =>
spi_clk_o <= '0';
counter <= counter + 1;
when sdata1 =>
data_valid_o <= '0';
spi_do_o <= data_reg(BYTE_SIZE-1);
when sdata2 =>
if (spi_clk_i = '0') then
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_di_i;
spi_do_o <= data_reg(BYTE_SIZE-1);
counter <= counter + 1;
end if;
when done =>
counter <= (others => '0');
data_valid_o <= '1';
spi_do_o <= '0';
when others => null;
end case;
end if;
end if;
end process;
data_o <= data_reg;
process(clk_i, rst_i, state, counter, wren_i, spi_ssn_i, spi_clk_i, fsm_trigger)
begin
if rst_i = '1' then
state <= idle;
elsif clk_i'event and clk_i = '1' then
if (fsm_trigger = '1') then
case state is
when idle =>
if (spi_ssn_i = '1') then
if (wren_i = '1') then
state <= data1;
end if;
else
state <= sdata1;
end if;
when data1 =>
state <= clock1;
when clock1 =>
state <= data2;
when data2 =>
state <= clock2;
when clock2 =>
if (counter < BYTE_SIZE-1) then
state <= data1;
else
state <= done;
end if;
when sdata1 =>
if (spi_clk_i = '1') then
state <= sdata2;
end if;
when sdata2 =>
if (spi_clk_i = '0') then
if (counter < BYTE_SIZE-1) then
state <= sdata1;
else
state <= done;
end if;
end if;
when done =>
if (spi_ssn_i = '1') then
if (wren_i = '0') then
state <= idle;
end if;
else
if (spi_clk_i = '1') then
state <= sdata1;
end if;
end if;
when others => null;
end case;
end if;
end if;
end process;
end spi_master_slave_arch;
| gpl-2.0 |
sjohann81/hf-risc | mips/platform/rams/ram.vhd | 2 | 1229 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end bram;
architecture memory of bram is
type ram is array(2 ** address_width -1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
begin
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
| gpl-2.0 |
jasonpeng/cg3207-proj | ID_EX_BUFF.vhd | 1 | 3970 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:19:27 10/31/2013
-- Design Name:
-- Module Name: ID_EX_BUFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EX_BUFF is
Port (
CLK : in STD_LOGIC; -- clock signal for synchronization
RESET : in STD_LOGIC;
-- IN --
IN_ID_ALUOp : in STD_LOGIC_VECTOR(2 downto 0);
IN_ID_SignExtended : in STD_LOGIC_VECTOR(31 downto 0); -- extended signed immediate value; also used for ALU opcode
IN_ID_ALUSrc : in STD_LOGIC; -- selects second operand for ALU
IN_ID_Data1 : in STD_LOGIC_VECTOR(31 downto 0); -- data1 from register
IN_ID_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- data2 from register
-- register writeback
IN_ID_RegDst : in STD_LOGIC; --selects writeback address
IN_ID_Instr_25_21 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_20_16 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_15_11 : in STD_LOGIC_VECTOR(4 downto 0);
-- states received from the previous stage
IN_ID_MemWrite : in STD_LOGIC;
IN_ID_MemToReg : in STD_LOGIC;
IN_ID_MemRead : in STD_LOGIC;
IN_ID_RegWrite : in STD_LOGIC;
-- OUT --
OUT_EX_ALUOp : out STD_LOGIC_VECTOR(2 downto 0);
OUT_EX_SignExtended : out STD_LOGIC_VECTOR(31 downto 0); -- extended signed immediate value; also used for ALU opcode
OUT_EX_ALUSrc : out STD_LOGIC; -- selects second operand for ALU
OUT_EX_Data1 : out STD_LOGIC_VECTOR(31 downto 0); -- data1 from register
OUT_EX_Data2 : out STD_LOGIC_VECTOR(31 downto 0); -- data2 from register
-- register writeback
OUT_EX_RegDst : out STD_LOGIC; --selects writeback address
OUT_EX_Instr_25_21 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_20_16 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_15_11 : out STD_LOGIC_VECTOR(4 downto 0);
-- states received from the previous stage
OUT_EX_MemWrite : out STD_LOGIC;
OUT_EX_MemToReg : out STD_LOGIC;
OUT_EX_MemRead : out STD_LOGIC;
OUT_EX_RegWrite : out STD_LOGIC
);
end ID_EX_BUFF;
architecture Behavioral of ID_EX_BUFF is
begin
process(CLK, RESET)
begin
if (RESET = '1') then
OUT_EX_ALUOp <= "000";
OUT_EX_SignExtended <= (others => '0');
OUT_EX_ALUSrc <= '0';
OUT_EX_Data1 <= (others => '0');
OUT_EX_Data2 <= (others => '0');
OUT_EX_RegDst <= '0';
OUT_EX_Instr_25_21 <= (others => '0');
OUT_EX_Instr_20_16 <= (others => '0');
OUT_EX_Instr_15_11 <= (others => '0');
OUT_EX_MemWrite <= '0';
OUT_EX_MemToReg <= '0';
OUT_EX_MemRead <= '0';
OUT_EX_RegWrite <= '0';
elsif(Clk'event and Clk='1') then
OUT_EX_ALUOp <= IN_ID_ALUop;
OUT_EX_SignExtended <= IN_ID_SignExtended;
OUT_EX_ALUSrc <= IN_ID_ALUSrc;
OUT_EX_Data1 <= IN_ID_Data1;
OUT_EX_Data2 <= IN_ID_Data2;
OUT_EX_RegDst <= IN_ID_RegDst;
OUT_EX_Instr_25_21 <= IN_ID_Instr_25_21;
OUT_EX_Instr_20_16 <= IN_ID_Instr_20_16;
OUT_EX_Instr_15_11 <= IN_ID_Instr_15_11;
OUT_EX_MemWrite <= IN_ID_MemWrite;
OUT_EX_MemToReg <= IN_ID_MemToReg;
OUT_EX_MemRead <= IN_ID_MemRead;
OUT_EX_RegWrite <= IN_ID_RegWrite;
end if;
end process;
end Behavioral;
| gpl-2.0 |
thasti/dvbs | hdl/mapper/mapper_tb.vhd | 1 | 1449 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mapper_tb is
end mapper_tb;
architecture tb of mapper_tb is
constant width : positive := 8;
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal d_valid : std_logic := '0';
signal d_i : std_logic := '0';
signal d_q : std_logic := '0';
signal q_i : std_logic_vector(width-1 downto 0);
signal q_q : std_logic_vector(width-1 downto 0);
begin
dut : entity work.mapper
generic map (width => width)
port map(clk => clk, rst => rst, clk_en => clk_en, d_valid => d_valid, d_i => d_i, d_q => d_q, q_i => q_i, q_q => q_q);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
clk_en <= '1';
d_valid <= '1';
d_i <= '0';
d_q <= '0';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '0';
d_q <= '1';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '1';
d_q <= '0';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
d_valid <= '1';
d_i <= '1';
d_q <= '1';
wait until rising_edge(clk);
d_valid <= '0';
wait until rising_edge(clk);
clk_en <= '0';
d_i <= '0';
d_q <= '0';
wait;
end process;
end tb;
| gpl-2.0 |
thasti/dvbs | hdl/network/eth_rx/eth_rx_tb.vhd | 1 | 1394 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity eth_rx_tb is
end eth_rx_tb;
architecture behav of eth_rx_tb is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal rxd : std_logic_vector(1 downto 0) := "00";
signal crsdv : std_logic := '0';
signal q : std_logic_vector(7 downto 0);
signal q_valid : std_logic;
begin
dut : entity work.eth_rx port map(clk, rst, rxd, crsdv, q, q_valid);
rst <= '1', '0' after 100 ns;
clk <= not clk after 10 ns;
rx_test : process
variable tmp : integer;
variable tmp_v : std_logic_vector(7 downto 0);
variable l : line;
file input_file : text is in "mpeg_packet.txt";
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
-- preamble
crsdv <= '1';
rxd <= "01";
for i in 0 to 10 loop
wait until rising_edge(clk);
end loop;
-- SFD
rxd <= "11";
wait until rising_edge(clk);
while not endfile(input_file) loop
readline(input_file, l);
read(l, tmp);
tmp_v := std_logic_vector(to_unsigned(tmp, 8));
for i in 0 to 3 loop
rxd <= tmp_v(2*i + 1) & tmp_v(2*i);
wait until rising_edge(clk);
end loop;
end loop;
for i in 0 to 1 loop
crsdv <= '0';
wait until rising_edge(clk);
crsdv <= '1';
wait until rising_edge(clk);
end loop;
crsdv <= '0';
wait;
end process;
end behav;
| gpl-2.0 |
thasti/dvbs | hdl/conv_coder/conv_coder_tb.vhd | 1 | 1829 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity conv_coder_tb is
end conv_coder_tb;
architecture tb of conv_coder_tb is
-- interface signals
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal clk_en : std_logic := '0';
signal d : std_logic := '0';
signal x : std_logic;
signal y : std_logic;
-- number of bits to check
constant n_bit : positive := 1000;
-- test vector
signal rand_vector : std_logic_vector(0 to n_bit + 6) := (others => '0');
signal x_test : std_logic;
signal y_test : std_logic;
begin
dut : entity work.conv_coder
port map(clk => clk, rst => rst, clk_en => clk_en, d => d, x => x, y => y);
clk <= not clk after 100 ns;
rst <= '0' after 500 ns;
prepare : process
variable seed1, seed2 : positive;
variable rand : real;
variable rand_unsigned : std_logic_vector(0 downto 0);
begin
for i in 0 to n_bit-1 loop
uniform(seed1, seed2, rand);
rand_unsigned := std_logic_vector(to_unsigned(integer(round(rand)),1));
rand_vector(6 + i) <= rand_unsigned(0);
end loop;
wait;
end process;
test : process
begin
wait until falling_edge(rst);
wait until rising_edge(clk);
wait until rising_edge(clk);
for i in 6 to n_bit + 6 - 1 loop
clk_en <= '1';
d <= rand_vector(i);
x_test <= (rand_vector(i) xor
rand_vector(i-1) xor
rand_vector(i-2) xor
rand_vector(i-3) xor
rand_vector(i-6));
y_test <= (rand_vector(i) xor
rand_vector(i-2) xor
rand_vector(i-3) xor
rand_vector(i-5) xor
rand_vector(i-6));
wait until rising_edge(clk);
wait until falling_edge(clk);
assert x = x_test
report "X output error."
severity failure;
assert y = y_test
report "Y output error."
severity failure;
end loop;
end process;
end tb;
| gpl-2.0 |
thasti/dvbs | hdl/scrambler/prbs.vhd | 1 | 1012 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- implements n-th order prbs with common polynomials y = x^n + x^(n-1) + 1
entity prbs is
generic (
n : positive;
width : positive
);
port (
clk : in std_logic;
clk_en : in std_logic;
rst : in std_logic;
q : out std_logic_vector(width-1 downto 0);
def_val : in std_logic_vector(n-1 downto 0)
);
end entity prbs;
architecture rtl of prbs is
signal sr : std_logic_vector(n-1 downto 0) := def_val;
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
sr <= def_val;
elsif clk_en = '1' then
for i in 0 to width-1 loop
sr(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end loop;
for i in 0 to n-width-1 loop
sr(width+i) <= sr(i);
end loop;
end if;
end process;
bla : for i in 0 to width-1 generate
q(width-1-i) <= sr(n-1-i) xor sr(n-2-i);
end generate bla;
assert (n>width) report "mode not supported: n should be greater than width" severity failure;
end architecture rtl;
| gpl-2.0 |
yuhailei1992/BearcodeOJ | bearcode/code_challenge/static/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-2.0 |
vargax/ejemplos | vhd/fundSistDigitales/practica4/comp_mux_sum.vhd | 1 | 1987 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:20:25 09/10/2011
-- Design Name:
-- Module Name: comp_mux_sum - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp_mux_sum is
Port ( nx1 : in STD_LOGIC_VECTOR (2 downto 0);
nx2 : in STD_LOGIC_VECTOR (2 downto 0);
nux1 : out STD_LOGIC_VECTOR (2 downto 0);
nux2 : out STD_LOGIC_VECTOR (2 downto 0));
end comp_mux_sum;
architecture Behavioral of comp_mux_sum is
component sumador
Port ( num : in STD_LOGIC_VECTOR (2 downto 0);
suma : out STD_LOGIC_VECTOR (2 downto 0));
end component;
component comparador
Port ( num1 : in STD_LOGIC_VECTOR (2 downto 0);
num2 : in STD_LOGIC_VECTOR (2 downto 0);
answer : out STD_LOGIC);
end component;
component mux
Port ( sel : in STD_LOGIC;
n : in STD_LOGIC_VECTOR (2 downto 0);
nsum : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (2 downto 0));
end component;
signal s1,s2,s3,s4 : std_logic_vector(2 downto 0);
signal r: bit;
begin
u1: component comparador port map(num1 <= nx1, num2 <= nx2, answer <= r);
u2: sumador port map(num <= nx2, suma <= s1);
u3: mux port map (sel <= r, n <= nx2, nsum <= s1, salida <= s2)
nux1 <= nx1;
end Behavioral;
| gpl-2.0 |
AngelLM/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/preesc_tb.vhd | 2 | 1659 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY preesc_tb IS
END preesc_tb;
ARCHITECTURE behavior OF preesc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(31 downto 0);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0):="0000000000000000";
signal salida_uds : std_logic_vector(1 downto 0):="00";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Stimulus process
stim_proc: process
begin
entrada_frec<="00000000000000000100000100010000";
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
klyone/wishbone-gen | lib/wbgen2_fifo_sync.vhd | 1 | 3131 |
library ieee;
use ieee.std_logic_1164.all;
use work.wbgen2_pkg.all;
entity wbgen2_fifo_sync is
generic (
g_width : integer;
g_size : integer;
g_usedw_size : integer);
port
(
clk_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_req_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
);
end wbgen2_fifo_sync;
architecture rtl of wbgen2_fifo_sync is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
signal empty_int : std_logic;
signal full_int : std_logic;
signal usedw_int : std_logic_vector(g_usedw_size-1 downto 0);
begin
wrapped_fifo: generic_sync_fifo
generic map (
g_data_width => g_width,
g_size => g_size,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => true)
port map (
rst_n_i => '1',
clk_i => clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
q_o => rd_data_o,
rd_i => rd_req_i,
empty_o => empty_int,
full_o => full_int,
almost_empty_o => open,
almost_full_o => open,
count_o => usedw_int);
rd_empty_o <= empty_int;
rd_full_o <= full_int;
rd_usedw_o <= usedw_int;
wr_empty_o <= empty_int;
wr_full_o <= full_int;
wr_usedw_o <= usedw_int;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/a_table.vhd | 3 | 36628 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; | gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/font_rom.vhd | 4 | 49333 | -- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_rom is
port(
clock: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end font_rom;
architecture arch of font_rom is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1)
of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition - 2^11-by-8
constant ROM: rom_type := (
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process(clock)
begin
if clock'event and clock = '1' then
addr_reg <= addr;
end if;
end process;
data <= ROM(to_integer(unsigned(addr_reg)));
end arch;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/cpu86pack.vhd | 3 | 17116 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
PACKAGE cpu86pack IS
constant RESET_CS_C : std_logic_vector(15 downto 0) := (others => '1'); -- FFFF:0000
constant RESET_IP_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_ES_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_SS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_DS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_VECTOR_C : std_logic_vector(19 downto 0) := (RESET_CS_C & X"0") + (X"0" & RESET_IP_C);
constant MUL_MCD_C : std_logic_vector(4 downto 0) := "00010"; -- mul MCP
-- Serial Divider delay
-- changed later to done signal
-- You can gain 1 clk cycle, done can be asserted 1 cycle earlier
constant DIV_MCD_C : std_logic_vector(4 downto 0) := "10011"; -- div waitstates 19!
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant ZEROVECTOR_C : std_logic_vector(31 downto 0) := X"00000000";
-- Minimum value for MAX_WS="000", this result in a 2 cycle rd/wr strobe
-- Total Read cycle is 1 cycle for address setup + 2 cycles for rd/wr strobe, thus
-- minimum bus cycle is 3 clk cycles.
constant WS_WIDTH : integer := 3; -- 2^WS_WIDTH=MAX Waitstates
constant MAX_WS : std_logic_vector(WS_WIDTH-1 downto 0) := "000"; -- 3 clk bus cycles
constant DONTCARE : std_logic_vector(31 downto 0):=X"FFFFFFFF";
-- Status record containing some data and flag register
type instruction_type is record
ireg : std_logic_vector(7 downto 0); -- Instruction register
xmod : std_logic_vector(1 downto 0); -- mod is a reserved word
reg : std_logic_vector(2 downto 0); -- between mode and rm
rm : std_logic_vector(2 downto 0);
data : std_logic_vector(15 downto 0);
disp : std_logic_vector(15 downto 0);
nb : std_logic_vector(2 downto 0); -- Number of bytes
end record;
-- Status record containing some data and flag register
type status_out_type is record
ax : std_logic_vector(15 downto 0);
cx_one : std_logic; -- '1' if CX=0001
cx_zero : std_logic; -- '1' if CX=0000
cl : std_logic_vector(7 downto 0); -- 5 bits shift/rotate counter
flag : std_logic_vector(15 downto 0);
div_err : std_logic; -- Divider overflow
end record;
--------------------------------------------------------------------------------------
-- Data Path Records
--------------------------------------------------------------------------------------
type path_in_type is record
datareg_input : std_logic_vector(6 downto 0); -- dimux(3) & w & seldreg(3)
alu_operation : std_logic_vector(14 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
dbus_output : std_logic_vector(1 downto 0); -- (Odd/Even) domux setting
segreg_input : std_logic_vector(3 downto 0); -- simux & selsreg
ea_output : std_logic_vector(9 downto 0); -- dispmux(3) & eamux(4) & [flag]&segop(2)
end record;
-- Write Strobe Record for Data Path
type write_in_type is record
wrd : std_logic; -- Write datareg
wralu : std_logic; -- Write ALU result
wrcc : std_logic; -- Write Flag register
wrs : std_logic; -- Write Segment register
wrip : std_logic; -- Write Instruction Pointer
wrop : std_logic; -- Write Segment Prefix register, Set Prefix Flag
wrtemp: std_logic; -- Write to ALU_TEMP register
end record;
constant SET_OPFLAG : std_logic:='1'; -- Override Prefix Flag
-- DIMUX
constant DATAIN_IN : std_logic_vector(2 downto 0) := "000";
constant EABUS_IN : std_logic_vector(2 downto 0) := "001";
constant ALUBUS_IN : std_logic_vector(2 downto 0) := "010";
constant MDBUS_IN : std_logic_vector(2 downto 0) := "011";
constant ES_IN : std_logic_vector(2 downto 0) := "100";
constant CS_IN : std_logic_vector(2 downto 0) := "101";
constant SS_IN : std_logic_vector(2 downto 0) := "110";
constant DS_IN : std_logic_vector(2 downto 0) := "111";
-- SIMUX Segment Register input Mux
constant SDATAIN_IN : std_logic_vector(1 downto 0) := "00";
constant SEABUS_IN : std_logic_vector(1 downto 0) := "01"; -- Effective Address
constant SALUBUS_IN : std_logic_vector(1 downto 0) := "10";
constant SMDBUS_IN : std_logic_vector(1 downto 0) := "11";
-- DOMUX (Note bit 2=odd/even)
constant ALUBUS_OUT : std_logic_vector(1 downto 0) := "00";
constant CCBUS_OUT : std_logic_vector(1 downto 0) := "01";
constant DIBUS_OUT : std_logic_vector(1 downto 0) := "10";
constant IPBUS_OUT : std_logic_vector(1 downto 0) := "11";
-- dispmux(3) & eamux(4) & poflag & segop[1:0]
-- note some bits may be dontcare!
constant NB_ES_IP : std_logic_vector(9 downto 0) := "0000000000"; -- IPREG+NB ADDR=ES:IP
constant NB_CS_IP : std_logic_vector(9 downto 0) := "0000000001";
constant NB_SS_IP : std_logic_vector(9 downto 0) := "0000000010";
constant NB_DS_IP : std_logic_vector(9 downto 0) := "0000000011";
constant NB_ES_EA : std_logic_vector(9 downto 0) := "0000001000"; -- IPREG+NB ADDR=EA
constant NB_CS_EA : std_logic_vector(9 downto 0) := "0000001001";
constant NB_SS_EA : std_logic_vector(9 downto 0) := "0000001010";
constant NB_DS_EA : std_logic_vector(9 downto 0) := "0000001011";
constant DISP_ES_EA : std_logic_vector(9 downto 0) := "0010001000"; -- IPREG+DISP ADDR=EA
constant DISP_CS_EA : std_logic_vector(9 downto 0) := "0010001001";
constant DISP_SS_EA : std_logic_vector(9 downto 0) := "0010001010";
constant DISP_DS_EA : std_logic_vector(9 downto 0) := "0010001011";
constant DISP_CS_IP : std_logic_vector(9 downto 0) := "0010000001"; -- Used for Jx instructions
constant PORT_00_DX : std_logic_vector(6 downto 0) := "0000010"; -- EAMUX IN/OUT instruction
constant PORT_00_EA : std_logic_vector(6 downto 0) := "0000001"; -- EAMUX Segm=00 00:IP or 00:DISP
constant NB_SS_SP : std_logic_vector(6 downto 0) := "0000100"; -- IP=IP+NBREQ, EAMUX=SS:SP , 100, 101, 110 unused
constant LD_SS_SP : std_logic_vector(6 downto 0) := "0100100"; -- Load new IP from MDBUS & out=SS:SP
constant LD_MD_IP : std_logic_vector(9 downto 0) := "0100000001"; -- Load new IP from MDBUS (e.g. RET instruction)
constant LD_CS_IP : std_logic_vector(9 downto 0) := "0110000001"; -- Load new IP (e.g. RET instruction)
constant EA_CS_IP : std_logic_vector(9 downto 0) := "1000001001"; -- Load new IP (e.g. RET instruction)
constant IPB_CS_IP : std_logic_vector(9 downto 0) := "1110000001"; -- Select IPBUS=IPREG
constant MD_EA2_DS : std_logic_vector(9 downto 0) := "0100011011"; -- IP<-MD, addr=DS:EA2
-- SELALUA/B or SELDREG(2 downto 0)
constant REG_AX : std_logic_vector(3 downto 0) := "0000"; -- W=1 Into ALUBUS A or B
constant REG_CX : std_logic_vector(3 downto 0) := "0001";
constant REG_DX : std_logic_vector(3 downto 0) := "0010";
constant REG_BX : std_logic_vector(3 downto 0) := "0011";
constant REG_SP : std_logic_vector(3 downto 0) := "0100";
constant REG_BP : std_logic_vector(3 downto 0) := "0101";
constant REG_SI : std_logic_vector(3 downto 0) := "0110";
constant REG_DI : std_logic_vector(3 downto 0) := "0111";
constant REG_DATAIN : std_logic_vector(3 downto 0) := "1000"; -- Pass data_in to ALU
constant REG_MDBUS : std_logic_vector(3 downto 0) := "1111"; -- Pass memory bus (mdbus) to ALU
-- Only for SELALUB
constant REG_CONST1 : std_logic_vector(3 downto 0) := "1001"; -- Used for INC/DEC function, W=0/1
constant REG_CONST2 : std_logic_vector(3 downto 0) := "1010"; -- Used for POP/PUSH function W=1
-- W+SELDREG
constant REG_AH : std_logic_vector(3 downto 0) := "0100"; -- W=1 SELDREG=AH
---------------------------------------------------------------
-- ALU Operations
-- Use ireg(5 downto 3) / modrm(5 downto 3) / ireg(3 downto 0)
-- Constants for
---------------------------------------------------------------
constant ALU_ADD : std_logic_vector(6 downto 0) := "0000000";
constant ALU_OR : std_logic_vector(6 downto 0) := "0000001";
constant ALU_ADC : std_logic_vector(6 downto 0) := "0000010";
constant ALU_SBB : std_logic_vector(6 downto 0) := "0000011";
constant ALU_AND : std_logic_vector(6 downto 0) := "0000100";
constant ALU_SUB : std_logic_vector(6 downto 0) := "0000101";
constant ALU_XOR : std_logic_vector(6 downto 0) := "0000110";
constant ALU_CMP : std_logic_vector(6 downto 0) := "0000111"; -- See also ALU_CMPS
constant ALU_TEST0 : std_logic_vector(6 downto 0) := "0001000";
constant ALU_TEST1 : std_logic_vector(6 downto 0) := "0001101";
-- Random assignment, these can be changed.
constant ALU_PUSH : std_logic_vector(6 downto 0) := "0001001"; -- Used for PUSH (SUB)
constant ALU_POP : std_logic_vector(6 downto 0) := "0001010"; -- Used for POP (ADD)
constant ALU_REGL : std_logic_vector(6 downto 0) := "0001011"; -- alureg(15..0) (latched alu_busb)
constant ALU_REGH : std_logic_vector(6 downto 0) := "0111011"; -- alureg(31..16) (latched alu_busa)
constant ALU_PASSA : std_logic_vector(6 downto 0) := "0001100"; -- abus_s only
constant ALU_TEMP : std_logic_vector(6 downto 0) := "1111001"; -- Used to select temp/scratchpad register (80186 only)
-- CONST & instr.irg(3 downto 0)
constant ALU_SAHF : std_logic_vector(6 downto 0) := "0001110"; -- AH -> Flags
-- CONST & instr.irg(3 downto 0)
constant ALU_LAHF : std_logic_vector(6 downto 0) := "0001111"; -- Flags->ALUBUS (->AH)
-- CONSTANT & instr.ireg(1) & modrm.reg(5 downto 3)
-- CONSTANT=001
constant ALU_ROL1 : std_logic_vector(6 downto 0) := "0010000"; -- count=1
constant ALU_ROR1 : std_logic_vector(6 downto 0) := "0010001";
constant ALU_RCL1 : std_logic_vector(6 downto 0) := "0010010";
constant ALU_RCR1 : std_logic_vector(6 downto 0) := "0010011";
constant ALU_SHL1 : std_logic_vector(6 downto 0) := "0010100";
constant ALU_SHR1 : std_logic_vector(6 downto 0) := "0010101";
constant ALU_SAR1 : std_logic_vector(6 downto 0) := "0010111";
constant ALU_ROL : std_logic_vector(6 downto 0) := "0011000"; -- Count in CL
constant ALU_ROR : std_logic_vector(6 downto 0) := "0011001";
constant ALU_RCL : std_logic_vector(6 downto 0) := "0011010";
constant ALU_RCR : std_logic_vector(6 downto 0) := "0011011";
constant ALU_SHL : std_logic_vector(6 downto 0) := "0011100";
constant ALU_SHR : std_logic_vector(6 downto 0) := "0011101";
constant ALU_SAR : std_logic_vector(6 downto 0) := "0011111";
-- CONST & modrm.reg(5 downto 3)/instr.ireg(5 downto 3)
constant ALU_INC : std_logic_vector(6 downto 0) := "0100000"; -- Increment
constant ALU_DEC : std_logic_vector(6 downto 0) := "0100001"; -- Decrement also used for LOOP/JCXZ
constant ALU_CLRTIF : std_logic_vector(6 downto 0) := "0100010"; -- Clear TF/IF flag, used for INT
constant ALU_CMPS : std_logic_vector(6 downto 0) := "0100111"; -- Compare String ALUREG-MDBUS
constant ALU_SCAS : std_logic_vector(6 downto 0) := "0101111"; -- AX/AL-MDBUS, no SEXT
-- CONST & instr.irg(3 downto 0)
constant ALU_CMC : std_logic_vector(6 downto 0) := "0100101"; -- Complement Carry
constant ALU_CLC : std_logic_vector(6 downto 0) := "0101000"; -- Clear Carry
constant ALU_STC : std_logic_vector(6 downto 0) := "0101001"; -- Set Carry
constant ALU_CLI : std_logic_vector(6 downto 0) := "0101010"; -- Clear interrupt
constant ALU_STI : std_logic_vector(6 downto 0) := "0101011"; -- Set Interrupt
constant ALU_CLD : std_logic_vector(6 downto 0) := "0101100"; -- Clear Direction
constant ALU_STD : std_logic_vector(6 downto 0) := "0101101"; -- Set Direction
-- CONST & modrm.reg(5 downto 3)
constant ALU_TEST2 : std_logic_vector(6 downto 0) := "0110000"; -- F6/F7
constant ALU_NOT : std_logic_vector(6 downto 0) := "0110010"; -- F6/F7
constant ALU_NEG : std_logic_vector(6 downto 0) := "0110011"; -- F6/F7
constant ALU_MUL : std_logic_vector(6 downto 0) := "0110100"; -- F6/F7
constant ALU_IMUL : std_logic_vector(6 downto 0) := "0110101"; -- F6/F7
constant ALU_DIV : std_logic_vector(6 downto 0) := "0110110"; -- F6/F7
constant ALU_IDIV : std_logic_vector(6 downto 0) := "0110111"; -- F6/F7
-- Second cycle write DX
constant ALU_MUL2 : std_logic_vector(6 downto 0) := "0111100"; -- F6/F7
constant ALU_IMUL2 : std_logic_vector(6 downto 0) := "0111101"; -- F6/F7
constant ALU_DIV2 : std_logic_vector(6 downto 0) := "0111110"; -- F6/F7
constant ALU_IDIV2 : std_logic_vector(6 downto 0) := "0111111"; -- F6/F7
-- CONST & instr.ireg(3 downto 0)
constant ALU_SEXT : std_logic_vector(6 downto 0) := "0111000"; -- Used for CBW
constant ALU_SEXTW : std_logic_vector(6 downto 0) := "0111001"; -- Used for CWD
-- CONSTANT & & instr.ireg(1) & instr.ireg(5 downto 3)
constant ALU_AAM : std_logic_vector(6 downto 0) := "1000010";
constant ALU_AAD : std_logic_vector(6 downto 0) := "1001010";
constant ALU_DAA : std_logic_vector(6 downto 0) := "1001100";
constant ALU_DAS : std_logic_vector(6 downto 0) := "1001101";
constant ALU_AAA : std_logic_vector(6 downto 0) := "1001110";
constant ALU_AAS : std_logic_vector(6 downto 0) := "1001111";
constant ALU_ADD_SE : std_logic_vector(6 downto 0) := "1100000";
constant ALU_OR_SE : std_logic_vector(6 downto 0) := "1100001";
constant ALU_ADC_SE : std_logic_vector(6 downto 0) := "1100010";
constant ALU_SBB_SE : std_logic_vector(6 downto 0) := "1100011";
constant ALU_AND_SE : std_logic_vector(6 downto 0) := "1100100";
constant ALU_SUB_SE : std_logic_vector(6 downto 0) := "1100101";
constant ALU_XOR_SE : std_logic_vector(6 downto 0) := "1100110";
constant ALU_CMP_SE : std_logic_vector(6 downto 0) := "1100111";
END cpu86pack;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/wingbutled.vhd | 1 | 1013 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:23:33 02/02/2011
-- Design Name:
-- Module Name: wingbutled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity wingbutled is
Port (
io : inout STD_LOGIC_VECTOR (7 downto 0);
buttons : out STD_LOGIC_VECTOR (3 downto 0);
leds : in STD_LOGIC_VECTOR (3 downto 0)
);
end wingbutled;
architecture Behavioral of wingbutled is
begin
io(0) <= leds(3);
io(2) <= leds(2);
io(4) <= leds(1);
io(6) <= leds(0);
io(1) <= 'Z';
io(3) <= 'Z';
io(5) <= 'Z';
io(7) <= 'Z';
buttons(3) <= io(1);
buttons(2) <= io(3);
buttons(1) <= io(5);
buttons(0) <= io(7);
end Behavioral;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/slib_mv_filter.vhd | 3 | 2656 | --
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/addr_gen.vhd | 30 | 4526 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
pmstrategygroup/mfi | sites/all/libraries/ace/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/lcdctl.vhd | 1 | 4704 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out STD_LOGIC;
vsync : out STD_LOGIC;
hsync : out STD_LOGIC;
ck : out STD_LOGIC;
r : out std_logic_vector(5 downto 0);
g : out std_logic_vector(5 downto 0);
b : out std_logic_vector(5 downto 0)
);
end lcdctl;
architecture Behavioral of lcdctl is
signal clk_fast : std_logic := '0';
signal ired : std_logic_vector(5 downto 0) := "000000";
signal igreen : std_logic_vector(5 downto 0) := "000000";
signal iblue : std_logic_vector(5 downto 0) := "000000";
signal fg_r : std_logic_vector(5 downto 0) := "000000";
signal fg_g : std_logic_vector(5 downto 0) := "000000";
signal fg_b : std_logic_vector(5 downto 0) := "000000";
signal bg_r : std_logic_vector(5 downto 0) := "000000";
signal bg_g : std_logic_vector(5 downto 0) := "000000";
signal bg_b : std_logic_vector(5 downto 0) := "000000";
signal lcdvsync : STD_LOGIC;
signal lcdhsync : STD_LOGIC;
signal char_addr: std_logic_vector(6 downto 0);
signal char_attr: std_logic_vector(7 downto 0) := x"42";
signal attr_not_char: std_logic := '1';
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal video_on: std_logic;
signal dout: std_logic_vector(7 downto 0) := "01100010";
signal addr_read: std_logic_vector(12 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal ipixel_x, ipixel_y: std_logic_vector(9 downto 0);
begin
ud <= '1';
rl <= '1';
enab <= '0';
ck <= clk_fast;
r <= ired;
g <= igreen;
b <= iblue;
hsync<=lcdhsync;
vsync<=lcdvsync;
sync0: entity work.vga_sync
port map(
clock=>clk_fast,
reset=>reset,
hsync=>lcdhsync, vsync=>lcdvsync,
video_on=>video_on,
pixel_tick=>open,
pixel_x=>pixel_x, pixel_y=>pixel_y
);
-- instantiate frame buffer
-- frame_buffer_unit: entity work.blk_mem_gen_v7_3
-- port map (
-- clka => clk,
-- wea => (others => '0'),
-- addra => (others => '0'),
-- dina => (others => '0'),
-- clkb => clk,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= "111" & addr_read;
dout <= vramdata;
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clk_fast,
addr => rom_addr,
data => font_word
);
-- tile RAM read
-- addr_read <= ((pixel_y(9 downto 4) & "000000") + ("00" & pixel_y(9 downto 4) & "0000") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
addr_read <= ((pixel_y(9 downto 4) * "000101") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
-- addr_read <= pixel_y(8 downto 4) & pixel_x(9 downto 3) & attr_not_char; -- ok but stride=256 instead of 80*2=160
process(clk,clk_fast,video_on)
begin
if rising_edge(clk) then
if video_on='0' then
attr_not_char <= '0';
clk_fast <= '0';
else
if clk_fast='0' then
char_attr <= dout(7 downto 0);
attr_not_char <= '1';
else
char_addr <= dout(6 downto 0);
attr_not_char <= '0';
end if;
end if;
clk_fast <= not clk_fast;
end if;
end process;
fg_r <= (others => '1') when char_attr(0)='1' else (others => '0');
fg_g <= (others => '1') when char_attr(1)='1' else (others => '0');
fg_b <= (others => '1') when char_attr(2)='1' else (others => '0');
bg_r <= (others => '1') when char_attr(3)='1' else (others => '0');
bg_g <= (others => '1') when char_attr(4)='1' else (others => '0');
bg_b <= (others => '1') when char_attr(5)='1' else (others => '0');
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
-- bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0))-2);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(font_bit,video_on,fg_r,fg_g,fg_b,bg_r,bg_g,bg_b)
begin
if video_on='0' then
ired <= (others => '0');
igreen <= (others => '0');
iblue <= (others => '0');
elsif font_bit = '1' then
ired <= fg_r;
igreen <= fg_g;
iblue <= fg_b;
-- ired <= (others => '1');
-- igreen <= (others => '1');
-- iblue <= (others => '1');
else
ired <= bg_r;
igreen <= bg_g;
iblue <= bg_b;
-- ired <= (others => '0');
-- igreen <= (others => '0');
-- iblue <= (others => '0');
end if;
end process;
end Behavioral;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/ipcore_dir/clk32to40.vhd | 4 | 6374 | -- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______700.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/clk32to40.vhd | 4 | 6374 | -- file: clk32to40.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______700.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/clk32to40/example_design/clk32to40_exdes.vhd | 2 | 5575 | -- file: clk32to40_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end clk32to40_exdes;
architecture xilinx of clk32to40_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk32to40
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/clk32to40/example_design/clk32to40_exdes.vhd | 2 | 5575 | -- file: clk32to40_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end clk32to40_exdes;
architecture xilinx of clk32to40_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk32to40
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/bmg_stim_gen.vhd | 2 | 7816 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(15 DOWNTO 0) <= WRITE_ADDR(15 DOWNTO 0);
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/dataregfile_rtl.vhd | 3 | 10670 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | papilio1/papilio1_tb.vhd | 1 | 10675 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:17:57 02/17/2015
-- Design Name:
-- Module Name: C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1/papilio1_tb.vhd
-- Project Name: papilio1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: papilio1_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
ENTITY papilio1_tb IS
END papilio1_tb;
ARCHITECTURE behavior OF papilio1_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT papilio1_top
PORT(
rx : IN std_logic;
tx : OUT std_logic;
W1A : INOUT std_logic_vector(15 downto 0);
W1B : INOUT std_logic_vector(15 downto 0);
W2C : INOUT std_logic_vector(15 downto 0);
clk : IN std_logic
);
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
--Inputs
signal rx : std_logic := '0';
signal clk : std_logic := '0';
--BiDirs
signal W1A : std_logic_vector(15 downto 0);
signal W1B : std_logic_vector(15 downto 0);
signal W2C : std_logic_vector(15 downto 0);
--Outputs
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
-- Instantiate the Unit Under Test (UUT)
uut: papilio1_top PORT MAP (
rx => rx,
tx => tx,
W1A => W1A,
W1B => W1B,
W2C => W2C,
clk => clk
);
w1b(1) <= resetn;
-- CTS => CTS,
TXD <= tx;
rx <= txcmd;
cpuerror <= w1b(0);
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable, -- default, working in simu but non-working in real-life ?
-- enable => rxenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
-- enable => txenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K/simulation/bmg_tb_pkg.vhd | 30 | 6206 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/bmg_tb_pkg.vhd | 30 | 6206 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/alu_rtl.vhd | 3 | 46054 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/checker.vhd | 26 | 5768 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K/simulation/checker.vhd | 26 | 5768 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/aaatop.vhd | 1 | 5481 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
W1A : inout STD_LOGIC_VECTOR (7 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
W2D : inout STD_LOGIC_VECTOR (15 downto 0);
Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal buttons : std_logic_vector(5 downto 0);
signal audio_left : STD_LOGIC;
signal audio_right : STD_LOGIC;
signal ud : STD_LOGIC;
signal rl : STD_LOGIC;
signal enab : STD_LOGIC;
signal vsync : STD_LOGIC;
signal hsync : STD_LOGIC;
signal ck : STD_LOGIC;
signal r : std_logic_vector(5 downto 0);
signal g : std_logic_vector(5 downto 0);
signal b : std_logic_vector(5 downto 0);
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT drigmorn1_top
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
winglcd0 : entity work.winglcdsndbut Port map(
W1A => w2c,
W1B => w2d,
buttons => buttons,
audio_left => audio_left,
audio_right => audio_right,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
w1a(0) <= vsync;
w1a(5) <= hsync;
w1a(7) <= r(0);
lcdctl0 : entity work.lcdctl Port map(
clk => CLOCK_40MHZ,
-- clk => clk,
reset=>reset,
vramaddr => vramaddr,
vramdata => vramdata,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
end Behavioral;
| gpl-2.0 |
nsauzede/cpu86 | papilio1/papilio1_top.vhd | 1 | 2630 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:43:24 02/17/2015
-- Design Name:
-- Module Name: papilio1_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY papilio1_top IS
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
END papilio1_top ;
ARCHITECTURE struct OF papilio1_top IS
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal RXD : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal TXD : std_logic;
COMPONENT drigmorn1_top
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
BEGIN
w1a(0) <= TXD;
tx <= TXD;
RXD <= rx;
CTS <= '1';
w1b(1) <= 'Z';
PIN3 <= not w1b(1); -- por
Inst_dcm32to40: entity work.dcm32to40 PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => CLOCK_40MHZ,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
drigmorn1_top0 : drigmorn1_top
PORT map(
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
END struct;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/uart_baudgen.vhd | 3 | 2301 | --
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
| gpl-2.0 |
VenturaSolutionsInc/VHDL | igmp/igmp_controller_tb.vhd | 1 | 4114 | -------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_wrapper"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_wrapper_tb.vhd
-- Author : Colin Shea <[email protected]>
-- Company :
-- Created : 2010-06-27
-- Last update: 2010-08-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-27 1.0 colinshea Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_wrapper_tb is
end igmp_wrapper_tb;
-------------------------------------------------------------------------------
architecture testbench of igmp_wrapper_tb is
-- component generics
constant gen_dataWidth : integer := 8;
signal srcMAC : std_logic_vector(47 downto 0):=X"010040506660";
signal destMAC : std_logic_vector(47 downto 0):=X"01005E1C1901";
signal vlanEn : std_logic := '1';
signal vlanId : std_logic_vector(11 downto 0):=X"06A";
signal srcIP : std_logic_vector(31 downto 0):=X"C0A80164";
signal destIP : std_logic_vector(31 downto 0):=X"EF9C1901";
signal tx_ready_n : std_logic;
signal tx_sof : std_logic;
signal tx_eof : std_logic;
signal tx_vld : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal igmp_vld : std_logic;
signal igmp_data : std_logic_vector(7 downto 0);
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal join : std_logic;
signal leave : std_logic;
signal respond : std_logic;
signal rspTime : std_logic_vector(7 downto 0);
-- signal destIP : std_logic_vector(31 downto 0);
-- signal destMAC : std_logic_vector(47 downto 0);
-- signal messageSent : std_logic;
-- signal out_join : std_logic;
-- signal out_leave : std_logic;
-- signal out_destMAC_o : std_logic_vector(47 downto 0);
-- signal out_destIP_o : std_logic_vector(31 downto 0);
signal out_enProc : std_logic;
signal out_enCommand : std_logic;
begin -- testbench
igmp_wrapper_1: entity work.igmp_wrapper
port map (
dataClk => dataClk,
reset => reset,
join => join,
leave => leave,
srcMAC => srcMAC,
srcIP => srcIP,
destMAC => destMAC,
destIP => destIP,
vlanEn => vlanEn,
vlanId => vlanId,
tx_ready_n => tx_ready_n,
tx_data => tx_data,
tx_vld => tx_vld,
tx_sof => tx_sof,
tx_eof => tx_eof,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
out_enProc => out_enProc,
out_enCommand => out_enCommand
);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
process
begin
reset <= '1';
rspTime <= (others => '0');
leave <= '0';
join <= '0';
respond <= '0';
tx_ready_n <= '1';
wait for 24 ns;
reset <= '0';
join <= '1';
tx_ready_n <= '0';
wait for 8 ns;
join <= '0';
wait for 1 ms;
respond <= '1';
rspTime <= X"0A";
wait for 8 ns;
respond <= '0';
wait for 1 sec;
wait for 750 ns;
leave <= '1';
wait for 8 ns;
leave <= '0';
wait;
end process;
end testbench;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/vga_sync.vhd | 2 | 2106 | --
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008
-- Chapters 12-13
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity vga_sync is
port(
clock: in std_logic;
reset: in std_logic;
hsync, vsync: out std_logic;
video_on: out std_logic;
pixel_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
signal h_sync_reg, v_sync_reg, video_on_reg: std_logic := '0';
signal v_count_reg: std_logic_vector(9 downto 0);
signal h_count_reg: std_logic_vector(9 downto 0);
-- VGA 640x480
constant thp : integer := 6; -- hsync 156
constant htotal : integer := 850; -- screen size, with back porch 900
constant tvp : integer := 34; -- vsync 1
constant vtotal : integer := 560; -- screen size, with back porch 560
begin
-- registers
process(clock)
begin
if rising_edge(clock) then
video_on_reg <= '1';
if h_count_reg < (thp) then
h_sync_reg <= '0';
video_on_reg <= '0';
else
h_sync_reg <= '1';
end if;
if v_count_reg < tvp then
v_sync_reg <= '0';
video_on_reg <= '0';
else
v_sync_reg <= '1';
end if;
if h_count_reg = htotal then
h_count_reg <= (others => '0');
if v_count_reg = vtotal then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
end if;
end process;
-- video on/off
-- video_on <= h_sync_reg and v_sync_reg;
video_on <= video_on_reg;
-- output signals
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg)-thp-104;
pixel_y <= std_logic_vector(v_count_reg)-tvp;
-- pixel_tick <= p_tick;
end arch;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/drigmorn1_top.vhd | 1 | 10820 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/aaatop.vhd | 1 | 5506 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
W1A : inout STD_LOGIC_VECTOR (7 downto 0);
W1B : inout STD_LOGIC_VECTOR (7 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
W2D : inout STD_LOGIC_VECTOR (15 downto 0);
Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal SD_MISO : std_logic;
signal SD_MOSI : std_logic;
signal SD_SCK : std_logic;
signal SD_nCS : std_logic;
signal buttons : std_logic_vector(5 downto 0);
signal audio_left : STD_LOGIC;
signal audio_right : STD_LOGIC;
signal ud : STD_LOGIC;
signal rl : STD_LOGIC;
signal enab : STD_LOGIC;
signal vsync : STD_LOGIC;
signal hsync : STD_LOGIC;
signal ck : STD_LOGIC;
signal r : std_logic_vector(5 downto 0);
signal g : std_logic_vector(5 downto 0);
signal b : std_logic_vector(5 downto 0);
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal spi_clk : std_logic := '1';
signal spi_csn : std_logic := '1';
signal spi_mosi : std_logic := '1';
signal spi_miso : std_logic := '1';
signal buttons2 : STD_LOGIC_VECTOR (3 downto 0);
signal leds : STD_LOGIC_VECTOR (3 downto 0);
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : entity work.drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
spi_cs => spi_csn,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
buttons => buttons2,
leds => leds,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
winglcd0 : entity work.winglcdsndbut Port map(
W1A => w2c,
W1B => w2d,
buttons => buttons,
audio_left => audio_left,
audio_right => audio_right,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
w1a(0) <= vsync;
w1a(5) <= hsync;
w1a(7) <= r(0);
lcdctl0 : entity work.lcdctl Port map(
clk => CLOCK_40MHZ,
-- clk => clk,
reset=>reset,
vramaddr => vramaddr,
vramdata => vramdata,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
--microSDwing
--0 not used in SPI
--1 MISO
--2 SCK
--3 MOSI
--4 CSN
spi_miso <= w1a(1);
w1a(2) <= spi_clk;
w1a(3) <= spi_mosi;
w1a(4) <= spi_csn;
butled1: entity work.wingbutled
Port map (
io => w1b,
buttons => buttons2,
leds => leds
);
-- leds <= buttons2;
end Behavioral;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/divider_rtl_ser.vhd | 3 | 10831 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY divider IS
GENERIC(
WIDTH_DIVID : integer := 32; -- Width Dividend
WIDTH_DIVIS : integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8 -- Check Overflow against short Byte/Word
);
PORT(
clk : IN std_logic; -- System Clock
reset : IN std_logic; -- Active high
dividend : IN std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : IN std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
remainder : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : IN std_logic;
w : IN std_logic; -- UNUSED!
overflow : OUT std_logic;
start : IN std_logic;
done : OUT std_logic
);
END divider ;
ARCHITECTURE rtl_ser OF divider IS
signal dividend_s : std_logic_vector(WIDTH_DIVID downto 0);
signal divisor_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal divis_rect_s : std_logic_vector(WIDTH_DIVIS-1 downto 0);
signal signquot_s : std_logic;
signal signremain_s : std_logic;
signal accumulator_s : std_logic_vector(WIDTH_DIVID downto 0);
signal aluout_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal newaccu_s : std_logic_vector(WIDTH_DIVID downto 0);
signal quot_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal remain_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
constant null_s : std_logic_vector(31 downto 0) := X"00000000";
signal count_s : std_logic_vector (3 downto 0); -- Number of iterations
signal overflow_s : std_logic; --_vector (WIDTH_DIVIS downto 0);
signal sremainder_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal squotient_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal signfailure_s : std_logic;
signal zeroq_s : std_logic;
signal zeror_s : std_logic;
signal zerod_s : std_logic;
signal pos_s : std_logic;
signal neg_s : std_logic;
type states is (s0,s1,s2);
signal state,nextstate: states;
function rectifyd (r : in std_logic_vector (WIDTH_DIVID downto 0); -- Rectifier for dividend + 1 bit
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVID downto 0);
begin
if ((r(WIDTH_DIVID) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVID) and twoc));
end;
function rectifys (r : in std_logic_vector (WIDTH_DIVIS-1 downto 0); -- Rectifier for divisor
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVIS-1 downto 0);
begin
if ((r(WIDTH_DIVIS-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVIS-1) and twoc));
end;
begin
-- Sign Quotient
signquot_s <= (dividend(WIDTH_DIVID-1) xor divisor(WIDTH_DIVIS-1)) and twocomp;
-- Sign Remainder
signremain_s <= dividend(WIDTH_DIVID-1) and twocomp;
dividend_s <= '0'÷nd when twocomp='0' else rectifyd(dividend(WIDTH_DIVID-1)÷nd, twocomp);
divisor_s <= ('1'&divisor) when (divisor(WIDTH_DIVIS-1) and twocomp)='1' else not('0'&divisor) + '1';
-- Subtractor (Adder, WIDTH_DIVIS+1)
aluout_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS) + divisor_s;
-- Append Quotient section to aluout_s
newaccu_s <= aluout_s & accumulator_s(WIDTH_DIVID-WIDTH_DIVIS-1 downto 0);
process (clk,reset)
begin
if (reset='1') then
accumulator_s <= (others => '0');
elsif (rising_edge(clk)) then
if start='1' then
accumulator_s <= dividend_s(WIDTH_DIVID-1 downto 0) & '0'; -- Load Dividend in remainder +shl
elsif pos_s='1' then -- Positive, remain=shl(remain,1)
accumulator_s <= newaccu_s(WIDTH_DIVID-1 downto 0) & '1'; -- Use sub result
elsif neg_s='1' then -- Negative, shl(remainder,0)
accumulator_s <= accumulator_s(WIDTH_DIVID-1 downto 0) & '0';-- Use original remainder
end if;
end if;
end process;
-- 2 Process Control FSM
process (clk,reset)
begin
if (reset = '1') then
state <= s0;
count_s <= (others => '0');
elsif (rising_edge(clk)) then
state <= nextstate;
if (state=s1) then
count_s <= count_s - '1';
elsif (state=s0) then
count_s <= CONV_STD_LOGIC_VECTOR(WIDTH_DIVIS-1, 4); -- extra step CAN REDUCE BY 1 since DONE is latched!!
end if;
end if;
end process;
process(state,start,aluout_s,count_s)
begin
case state is
when s0 =>
pos_s <= '0';
neg_s <= '0';
if start='1' then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
neg_s <= aluout_s(WIDTH_DIVIS);
pos_s <= not(aluout_s(WIDTH_DIVIS));
if (count_s=null_s(3 downto 0)) then nextstate <= s2; -- Done
else nextstate <= s1; -- Next sub&shift
end if;
when s2=>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
when others =>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
end case;
end process;
-- Correct remainder (SHR,1)
remain_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS+1);
-- Overflow if remainder>divisor or divide by 0 or sign error. Change all to positive.
divis_rect_s <= rectifys(divisor, twocomp);
overflow_s <= '1' when ((remain_s>=divis_rect_s) or (zerod_s='1')) else '0';
-- bottom part of remainder is quotient
quot_s <= accumulator_s(WIDTH_DIVIS-1 downto 0);
-- Remainder Result
sremainder_s <= ((not(remain_s)) + '1') when signremain_s='1' else remain_s;
remainder <= sremainder_s;
-- Qotient Result
squotient_s <= ((not(quot_s)) + '1') when signquot_s='1' else quot_s;
quotient <= squotient_s;
-- Detect zero vector
zeror_s <= '1' when (twocomp='1' and sremainder_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zeroq_s <= '1' when (twocomp='1' and squotient_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zerod_s <= '1' when (divisor=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
-- Detect Sign failure
signfailure_s <= '1' when (signquot_s='1' and squotient_s(WIDTH_DIVIS-1)='0' and zeroq_s='0') or
(signremain_s='1' and sremainder_s(WIDTH_DIVIS-1)='0' and zeror_s='0') else '0';
done <= '1' when state=s2 else '0';
overflow <= '1' when (overflow_s='1' or signfailure_s='1') else '0';
end architecture rtl_ser;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/divider_rtl_ser.vhd | 3 | 10831 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY divider IS
GENERIC(
WIDTH_DIVID : integer := 32; -- Width Dividend
WIDTH_DIVIS : integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8 -- Check Overflow against short Byte/Word
);
PORT(
clk : IN std_logic; -- System Clock
reset : IN std_logic; -- Active high
dividend : IN std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : IN std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
remainder : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : IN std_logic;
w : IN std_logic; -- UNUSED!
overflow : OUT std_logic;
start : IN std_logic;
done : OUT std_logic
);
END divider ;
ARCHITECTURE rtl_ser OF divider IS
signal dividend_s : std_logic_vector(WIDTH_DIVID downto 0);
signal divisor_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal divis_rect_s : std_logic_vector(WIDTH_DIVIS-1 downto 0);
signal signquot_s : std_logic;
signal signremain_s : std_logic;
signal accumulator_s : std_logic_vector(WIDTH_DIVID downto 0);
signal aluout_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal newaccu_s : std_logic_vector(WIDTH_DIVID downto 0);
signal quot_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal remain_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
constant null_s : std_logic_vector(31 downto 0) := X"00000000";
signal count_s : std_logic_vector (3 downto 0); -- Number of iterations
signal overflow_s : std_logic; --_vector (WIDTH_DIVIS downto 0);
signal sremainder_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal squotient_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal signfailure_s : std_logic;
signal zeroq_s : std_logic;
signal zeror_s : std_logic;
signal zerod_s : std_logic;
signal pos_s : std_logic;
signal neg_s : std_logic;
type states is (s0,s1,s2);
signal state,nextstate: states;
function rectifyd (r : in std_logic_vector (WIDTH_DIVID downto 0); -- Rectifier for dividend + 1 bit
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVID downto 0);
begin
if ((r(WIDTH_DIVID) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVID) and twoc));
end;
function rectifys (r : in std_logic_vector (WIDTH_DIVIS-1 downto 0); -- Rectifier for divisor
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVIS-1 downto 0);
begin
if ((r(WIDTH_DIVIS-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVIS-1) and twoc));
end;
begin
-- Sign Quotient
signquot_s <= (dividend(WIDTH_DIVID-1) xor divisor(WIDTH_DIVIS-1)) and twocomp;
-- Sign Remainder
signremain_s <= dividend(WIDTH_DIVID-1) and twocomp;
dividend_s <= '0'÷nd when twocomp='0' else rectifyd(dividend(WIDTH_DIVID-1)÷nd, twocomp);
divisor_s <= ('1'&divisor) when (divisor(WIDTH_DIVIS-1) and twocomp)='1' else not('0'&divisor) + '1';
-- Subtractor (Adder, WIDTH_DIVIS+1)
aluout_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS) + divisor_s;
-- Append Quotient section to aluout_s
newaccu_s <= aluout_s & accumulator_s(WIDTH_DIVID-WIDTH_DIVIS-1 downto 0);
process (clk,reset)
begin
if (reset='1') then
accumulator_s <= (others => '0');
elsif (rising_edge(clk)) then
if start='1' then
accumulator_s <= dividend_s(WIDTH_DIVID-1 downto 0) & '0'; -- Load Dividend in remainder +shl
elsif pos_s='1' then -- Positive, remain=shl(remain,1)
accumulator_s <= newaccu_s(WIDTH_DIVID-1 downto 0) & '1'; -- Use sub result
elsif neg_s='1' then -- Negative, shl(remainder,0)
accumulator_s <= accumulator_s(WIDTH_DIVID-1 downto 0) & '0';-- Use original remainder
end if;
end if;
end process;
-- 2 Process Control FSM
process (clk,reset)
begin
if (reset = '1') then
state <= s0;
count_s <= (others => '0');
elsif (rising_edge(clk)) then
state <= nextstate;
if (state=s1) then
count_s <= count_s - '1';
elsif (state=s0) then
count_s <= CONV_STD_LOGIC_VECTOR(WIDTH_DIVIS-1, 4); -- extra step CAN REDUCE BY 1 since DONE is latched!!
end if;
end if;
end process;
process(state,start,aluout_s,count_s)
begin
case state is
when s0 =>
pos_s <= '0';
neg_s <= '0';
if start='1' then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
neg_s <= aluout_s(WIDTH_DIVIS);
pos_s <= not(aluout_s(WIDTH_DIVIS));
if (count_s=null_s(3 downto 0)) then nextstate <= s2; -- Done
else nextstate <= s1; -- Next sub&shift
end if;
when s2=>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
when others =>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
end case;
end process;
-- Correct remainder (SHR,1)
remain_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS+1);
-- Overflow if remainder>divisor or divide by 0 or sign error. Change all to positive.
divis_rect_s <= rectifys(divisor, twocomp);
overflow_s <= '1' when ((remain_s>=divis_rect_s) or (zerod_s='1')) else '0';
-- bottom part of remainder is quotient
quot_s <= accumulator_s(WIDTH_DIVIS-1 downto 0);
-- Remainder Result
sremainder_s <= ((not(remain_s)) + '1') when signremain_s='1' else remain_s;
remainder <= sremainder_s;
-- Qotient Result
squotient_s <= ((not(quot_s)) + '1') when signquot_s='1' else quot_s;
quotient <= squotient_s;
-- Detect zero vector
zeror_s <= '1' when (twocomp='1' and sremainder_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zeroq_s <= '1' when (twocomp='1' and squotient_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zerod_s <= '1' when (divisor=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
-- Detect Sign failure
signfailure_s <= '1' when (signquot_s='1' and squotient_s(WIDTH_DIVIS-1)='0' and zeroq_s='0') or
(signremain_s='1' and sremainder_s(WIDTH_DIVIS-1)='0' and zeror_s='0') else '0';
done <= '1' when state=s2 else '0';
overflow <= '1' when (overflow_s='1' or signfailure_s='1') else '0';
end architecture rtl_ser;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/slib_input_sync.vhd | 3 | 1612 | --
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/d_table.vhd | 3 | 37240 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity d_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(3 downto 0));
end d_table;
architecture rtl of d_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "0000";
when "1110100100000000" => dout <= "0000";
when "1111111111100000" => dout <= "0000";
when "1111111100100110" => dout <= "0000";
when "1111111100100000" => dout <= "0000";
when "1111111101100000" => dout <= "0000";
when "1111111110100000" => dout <= "0000";
when "1110101000000000" => dout <= "0110";
when "1111111100101110" => dout <= "0000";
when "1111111100101000" => dout <= "0000";
when "1111111101101000" => dout <= "0000";
when "1111111110101000" => dout <= "0000";
when "1110100000000000" => dout <= "0000";
when "1111111111010000" => dout <= "0000";
when "1111111100010110" => dout <= "0000";
when "1111111100010000" => dout <= "0000";
when "1111111101010000" => dout <= "0000";
when "1111111110010000" => dout <= "0000";
when "1001101000000000" => dout <= "0110";
when "1111111100011110" => dout <= "0000";
when "1111111100011000" => dout <= "0000";
when "1111111101011000" => dout <= "0000";
when "1111111110011000" => dout <= "0000";
when "1100001100000000" => dout <= "0000";
when "1100001000000000" => dout <= "0010";
when "1100101100000000" => dout <= "0000";
when "1100101000000000" => dout <= "0010";
when "0111010000000000" => dout <= "0000";
when "0111110000000000" => dout <= "0000";
when "0111111000000000" => dout <= "0000";
when "0111001000000000" => dout <= "0000";
when "0111011000000000" => dout <= "0000";
when "0111101000000000" => dout <= "0000";
when "0111000000000000" => dout <= "0000";
when "0111100000000000" => dout <= "0000";
when "0111010100000000" => dout <= "0000";
when "0111110100000000" => dout <= "0000";
when "0111111100000000" => dout <= "0000";
when "0111001100000000" => dout <= "0000";
when "0111011100000000" => dout <= "0000";
when "0111101100000000" => dout <= "0000";
when "0111000100000000" => dout <= "0000";
when "0111100100000000" => dout <= "0000";
when "1110001100000000" => dout <= "0000";
when "1110001000000000" => dout <= "0000";
when "1110000100000000" => dout <= "0000";
when "1110000000000000" => dout <= "0000";
when "1100110100000000" => dout <= "0000";
when "1100110000000000" => dout <= "0000";
when "1100111000000000" => dout <= "0000";
when "1100111100000000" => dout <= "0000";
when "1111100000000000" => dout <= "0000";
when "1111010100000000" => dout <= "0000";
when "1111100100000000" => dout <= "0000";
when "1111110000000000" => dout <= "0000";
when "1111110100000000" => dout <= "0000";
when "1111101000000000" => dout <= "0000";
when "1111101100000000" => dout <= "0000";
when "1111010000000000" => dout <= "0000";
when "1001101100000000" => dout <= "0000";
when "1111000000000000" => dout <= "0000";
when "1001000000000000" => dout <= "0000";
when "0010011000000000" => dout <= "0000";
when "0010111000000000" => dout <= "0000";
when "0011011000000000" => dout <= "0000";
when "0011111000000000" => dout <= "0000";
when "1000100011000000" => dout <= "0000";
when "1000100000000000" => dout <= "0000";
when "1000100001000000" => dout <= "0000";
when "1000100010000000" => dout <= "0000";
when "1000100000000110" => dout <= "0000";
when "1000100111000000" => dout <= "0000";
when "1000100100000000" => dout <= "0000";
when "1000100101000000" => dout <= "0000";
when "1000100110000000" => dout <= "0000";
when "1000100100000110" => dout <= "0000";
when "1000101011000000" => dout <= "0000";
when "1000101000000000" => dout <= "0000";
when "1000101001000000" => dout <= "0000";
when "1000101010000000" => dout <= "0000";
when "1000101000000110" => dout <= "0000";
when "1000101111000000" => dout <= "0000";
when "1000101100000000" => dout <= "0000";
when "1000101101000000" => dout <= "0000";
when "1000101110000000" => dout <= "0000";
when "1000101100000110" => dout <= "0000";
when "1100011000000000" => dout <= "0011";
when "1100011001000000" => dout <= "0101";
when "1100011010000000" => dout <= "0111";
when "1100011000000110" => dout <= "0111";
when "1100011100000000" => dout <= "0100";
when "1100011101000000" => dout <= "0110";
when "1100011110000000" => dout <= "1000";
when "1100011100000110" => dout <= "1000";
when "1011000000000000" => dout <= "0001";
when "1011000100000000" => dout <= "0001";
when "1011001000000000" => dout <= "0001";
when "1011001100000000" => dout <= "0001";
when "1011010000000000" => dout <= "0001";
when "1011010100000000" => dout <= "0001";
when "1011011000000000" => dout <= "0001";
when "1011011100000000" => dout <= "0001";
when "1011100000000000" => dout <= "0010";
when "1011100100000000" => dout <= "0010";
when "1011101000000000" => dout <= "0010";
when "1011101100000000" => dout <= "0010";
when "1011110000000000" => dout <= "0010";
when "1011110100000000" => dout <= "0010";
when "1011111000000000" => dout <= "0010";
when "1011111100000000" => dout <= "0010";
when "1010000000000000" => dout <= "0000";
when "1010000100000000" => dout <= "0000";
when "1010001000000000" => dout <= "0000";
when "1010001100000000" => dout <= "0000";
when "1000111011000000" => dout <= "0000";
when "1000111000000000" => dout <= "0000";
when "1000111001000000" => dout <= "0000";
when "1000111010000000" => dout <= "0000";
when "1000111000000110" => dout <= "0000";
when "1000110011000000" => dout <= "0000";
when "1000110000000000" => dout <= "0000";
when "1000110001000000" => dout <= "0000";
when "1000110010000000" => dout <= "0000";
when "1000110000000110" => dout <= "0000";
when "1111111100110000" => dout <= "0000";
when "1111111101110000" => dout <= "0000";
when "1111111110110000" => dout <= "0000";
when "1111111100110110" => dout <= "0000";
when "0101000000000000" => dout <= "0000";
when "0101000100000000" => dout <= "0000";
when "0101001000000000" => dout <= "0000";
when "0101001100000000" => dout <= "0000";
when "0101010000000000" => dout <= "0000";
when "0101010100000000" => dout <= "0000";
when "0101011000000000" => dout <= "0000";
when "0101011100000000" => dout <= "0000";
when "0000011000000000" => dout <= "0000";
when "0000111000000000" => dout <= "0000";
when "0001011000000000" => dout <= "0000";
when "0001111000000000" => dout <= "0000";
when "1000111100000000" => dout <= "0000";
when "1000111101000000" => dout <= "0000";
when "1000111110000000" => dout <= "0000";
when "1000111100000110" => dout <= "0000";
when "1000111111000000" => dout <= "0000";
when "0101100000000000" => dout <= "0000";
when "0101100100000000" => dout <= "0000";
when "0101101000000000" => dout <= "0000";
when "0101101100000000" => dout <= "0000";
when "0101110000000000" => dout <= "0000";
when "0101110100000000" => dout <= "0000";
when "0101111000000000" => dout <= "0000";
when "0101111100000000" => dout <= "0000";
when "0000011100000000" => dout <= "0000";
when "0001011100000000" => dout <= "0000";
when "0001111100000000" => dout <= "0000";
when "1000011011000000" => dout <= "0000";
when "1000011000000000" => dout <= "0000";
when "1000011001000000" => dout <= "0000";
when "1000011010000000" => dout <= "0000";
when "1000011000000110" => dout <= "0000";
when "1000011111000000" => dout <= "0000";
when "1000011100000000" => dout <= "0000";
when "1000011101000000" => dout <= "0000";
when "1000011110000000" => dout <= "0000";
when "1000011100000110" => dout <= "0000";
when "1001000100000000" => dout <= "0000";
when "1001001000000000" => dout <= "0000";
when "1001001100000000" => dout <= "0000";
when "1001010000000000" => dout <= "0000";
when "1001010100000000" => dout <= "0000";
when "1001011000000000" => dout <= "0000";
when "1001011100000000" => dout <= "0000";
when "1110010000000000" => dout <= "0000";
when "1110010100000000" => dout <= "0000";
when "1110110000000000" => dout <= "0000";
when "1110110100000000" => dout <= "0000";
when "1110011000000000" => dout <= "0000";
when "1110011100000000" => dout <= "0000";
when "1110111100000000" => dout <= "0000";
when "1110111000000000" => dout <= "0000";
when "1101011100000000" => dout <= "0000";
when "1001111100000000" => dout <= "0000";
when "1001111000000000" => dout <= "0000";
when "1001110000000000" => dout <= "0000";
when "1001110100000000" => dout <= "0000";
when "1000110100000110" => dout <= "0000";
when "1000110111000000" => dout <= "0000";
when "1000110100000000" => dout <= "0000";
when "1000110101000000" => dout <= "0000";
when "1000110110000000" => dout <= "0000";
when "1100010100000110" => dout <= "0000";
when "1100010100000000" => dout <= "0000";
when "1100010101000000" => dout <= "0000";
when "1100010110000000" => dout <= "0000";
when "1100010000000110" => dout <= "0000";
when "1100010000000000" => dout <= "0000";
when "1100010001000000" => dout <= "0000";
when "1100010010000000" => dout <= "0000";
when "0000000011000000" => dout <= "0000";
when "0000000000000110" => dout <= "0000";
when "0000000000000000" => dout <= "0000";
when "0000000001000000" => dout <= "0000";
when "0000000010000000" => dout <= "0000";
when "0000000111000000" => dout <= "0000";
when "0000000100000110" => dout <= "0000";
when "0000000100000000" => dout <= "0000";
when "0000000101000000" => dout <= "0000";
when "0000000110000000" => dout <= "0000";
when "0000001011000000" => dout <= "0000";
when "0000001000000110" => dout <= "0000";
when "0000001000000000" => dout <= "0000";
when "0000001001000000" => dout <= "0000";
when "0000001010000000" => dout <= "0000";
when "0000001111000000" => dout <= "0000";
when "0000001100000110" => dout <= "0000";
when "0000001100000000" => dout <= "0000";
when "0000001101000000" => dout <= "0000";
when "0000001110000000" => dout <= "0000";
when "1000000011000000" => dout <= "0011";
when "1000000000000110" => dout <= "0111";
when "1000000000000000" => dout <= "0011";
when "1000000001000000" => dout <= "0101";
when "1000000010000000" => dout <= "0111";
when "1000000111000000" => dout <= "0100";
when "1000000100000110" => dout <= "1000";
when "1000000100000000" => dout <= "0100";
when "1000000101000000" => dout <= "0110";
when "1000000110000000" => dout <= "1000";
when "1000001111000000" => dout <= "0011";
when "1000001100000110" => dout <= "0111";
when "1000001100000000" => dout <= "0011";
when "1000001101000000" => dout <= "0101";
when "1000001110000000" => dout <= "0111";
when "0000010000000000" => dout <= "0001";
when "0000010100000000" => dout <= "0010";
when "0001000011000000" => dout <= "0000";
when "0001000000000110" => dout <= "0000";
when "0001000000000000" => dout <= "0000";
when "0001000001000000" => dout <= "0000";
when "0001000010000000" => dout <= "0000";
when "0001000111000000" => dout <= "0000";
when "0001000100000110" => dout <= "0000";
when "0001000100000000" => dout <= "0000";
when "0001000101000000" => dout <= "0000";
when "0001000110000000" => dout <= "0000";
when "0001001011000000" => dout <= "0000";
when "0001001000000110" => dout <= "0000";
when "0001001000000000" => dout <= "0000";
when "0001001001000000" => dout <= "0000";
when "0001001010000000" => dout <= "0000";
when "0001001111000000" => dout <= "0000";
when "0001001100000110" => dout <= "0000";
when "0001001100000000" => dout <= "0000";
when "0001001101000000" => dout <= "0000";
when "0001001110000000" => dout <= "0000";
when "1000000011010000" => dout <= "0011";
when "1000000000010110" => dout <= "0111";
when "1000000000010000" => dout <= "0011";
when "1000000001010000" => dout <= "0101";
when "1000000010010000" => dout <= "0111";
when "1000000111010000" => dout <= "0100";
when "1000000100010110" => dout <= "1000";
when "1000000100010000" => dout <= "0100";
when "1000000101010000" => dout <= "0110";
when "1000000110010000" => dout <= "1000";
when "1000001111010000" => dout <= "0011";
when "1000001100010110" => dout <= "0111";
when "1000001100010000" => dout <= "0011";
when "1000001101010000" => dout <= "0101";
when "1000001110010000" => dout <= "0111";
when "0001010000000000" => dout <= "0001";
when "0001010100000000" => dout <= "0010";
when "0010100011000000" => dout <= "0000";
when "0010100000000110" => dout <= "0000";
when "0010100000000000" => dout <= "0000";
when "0010100001000000" => dout <= "0000";
when "0010100010000000" => dout <= "0000";
when "0010100111000000" => dout <= "0000";
when "0010100100000110" => dout <= "0000";
when "0010100100000000" => dout <= "0000";
when "0010100101000000" => dout <= "0000";
when "0010100110000000" => dout <= "0000";
when "0010101011000000" => dout <= "0000";
when "0010101000000110" => dout <= "0000";
when "0010101000000000" => dout <= "0000";
when "0010101001000000" => dout <= "0000";
when "0010101010000000" => dout <= "0000";
when "0010101111000000" => dout <= "0000";
when "0010101100000110" => dout <= "0000";
when "0010101100000000" => dout <= "0000";
when "0010101101000000" => dout <= "0000";
when "0010101110000000" => dout <= "0000";
when "1000000011101000" => dout <= "0011";
when "1000000000101110" => dout <= "0111";
when "1000000000101000" => dout <= "0011";
when "1000000001101000" => dout <= "0101";
when "1000000010101000" => dout <= "0111";
when "1000000111101000" => dout <= "0100";
when "1000000100101110" => dout <= "1000";
when "1000000100101000" => dout <= "0100";
when "1000000101101000" => dout <= "0110";
when "1000000110101000" => dout <= "1000";
when "1000001111101000" => dout <= "0011";
when "1000001100101110" => dout <= "0111";
when "1000001100101000" => dout <= "0011";
when "1000001101101000" => dout <= "0101";
when "1000001110101000" => dout <= "0111";
when "0010110000000000" => dout <= "0001";
when "0010110100000000" => dout <= "0010";
when "0001100011000000" => dout <= "0000";
when "0001100000000110" => dout <= "0000";
when "0001100000000000" => dout <= "0000";
when "0001100001000000" => dout <= "0000";
when "0001100010000000" => dout <= "0000";
when "0001100111000000" => dout <= "0000";
when "0001100100000110" => dout <= "0000";
when "0001100100000000" => dout <= "0000";
when "0001100101000000" => dout <= "0000";
when "0001100110000000" => dout <= "0000";
when "0001101011000000" => dout <= "0000";
when "0001101000000110" => dout <= "0000";
when "0001101000000000" => dout <= "0000";
when "0001101001000000" => dout <= "0000";
when "0001101010000000" => dout <= "0000";
when "0001101111000000" => dout <= "0000";
when "0001101100000110" => dout <= "0000";
when "0001101100000000" => dout <= "0000";
when "0001101101000000" => dout <= "0000";
when "0001101110000000" => dout <= "0000";
when "1000000011011000" => dout <= "0011";
when "1000000000011110" => dout <= "0111";
when "1000000000011000" => dout <= "0011";
when "1000000001011000" => dout <= "0101";
when "1000000010011000" => dout <= "0111";
when "1000000111011000" => dout <= "0100";
when "1000000100011110" => dout <= "1000";
when "1000000100011000" => dout <= "0100";
when "1000000101011000" => dout <= "0110";
when "1000000110011000" => dout <= "1000";
when "1000001111011000" => dout <= "0011";
when "1000001100011110" => dout <= "0111";
when "1000001100011000" => dout <= "0011";
when "1000001101011000" => dout <= "0101";
when "1000001110011000" => dout <= "0111";
when "0001110000000000" => dout <= "0001";
when "0001110100000000" => dout <= "0010";
when "1111111011000000" => dout <= "0000";
when "1111111000000110" => dout <= "0000";
when "1111111000000000" => dout <= "0000";
when "1111111001000000" => dout <= "0000";
when "1111111010000000" => dout <= "0000";
when "1111111100000110" => dout <= "0000";
when "1111111100000000" => dout <= "0000";
when "1111111101000000" => dout <= "0000";
when "1111111110000000" => dout <= "0000";
when "0100000000000000" => dout <= "0000";
when "0100000100000000" => dout <= "0000";
when "0100001000000000" => dout <= "0000";
when "0100001100000000" => dout <= "0000";
when "0100010000000000" => dout <= "0000";
when "0100010100000000" => dout <= "0000";
when "0100011000000000" => dout <= "0000";
when "0100011100000000" => dout <= "0000";
when "1111111011001000" => dout <= "0000";
when "1111111000001110" => dout <= "0000";
when "1111111000001000" => dout <= "0000";
when "1111111001001000" => dout <= "0000";
when "1111111010001000" => dout <= "0000";
when "1111111100001110" => dout <= "0000";
when "1111111100001000" => dout <= "0000";
when "1111111101001000" => dout <= "0000";
when "1111111110001000" => dout <= "0000";
when "0100100000000000" => dout <= "0000";
when "0100100100000000" => dout <= "0000";
when "0100101000000000" => dout <= "0000";
when "0100101100000000" => dout <= "0000";
when "0100110000000000" => dout <= "0000";
when "0100110100000000" => dout <= "0000";
when "0100111000000000" => dout <= "0000";
when "0100111100000000" => dout <= "0000";
when "0011101011000000" => dout <= "0000";
when "0011101000000110" => dout <= "0000";
when "0011101000000000" => dout <= "0000";
when "0011101001000000" => dout <= "0000";
when "0011101010000000" => dout <= "0000";
when "0011101111000000" => dout <= "0000";
when "0011101100000110" => dout <= "0000";
when "0011101100000000" => dout <= "0000";
when "0011101101000000" => dout <= "0000";
when "0011101110000000" => dout <= "0000";
when "0011100000000110" => dout <= "0000";
when "0011100000000000" => dout <= "0000";
when "0011100001000000" => dout <= "0000";
when "0011100010000000" => dout <= "0000";
when "0011100011000000" => dout <= "0000";
when "0011100100000110" => dout <= "0000";
when "0011100100000000" => dout <= "0000";
when "0011100101000000" => dout <= "0000";
when "0011100110000000" => dout <= "0000";
when "0011100111000000" => dout <= "0000";
when "1000000011111000" => dout <= "0011";
when "1000000000111110" => dout <= "0111";
when "1000000000111000" => dout <= "0011";
when "1000000001111000" => dout <= "0101";
when "1000000010111000" => dout <= "0111";
when "1000000111111000" => dout <= "0100";
when "1000000100111110" => dout <= "1000";
when "1000000100111000" => dout <= "0100";
when "1000000101111000" => dout <= "0110";
when "1000000110111000" => dout <= "1000";
when "1000001111111000" => dout <= "0011";
when "1000001100111110" => dout <= "0111";
when "1000001100111000" => dout <= "0011";
when "1000001101111000" => dout <= "0101";
when "1000001110111000" => dout <= "0111";
when "0011110000000000" => dout <= "0001";
when "0011110100000000" => dout <= "0010";
when "1111011011011000" => dout <= "0000";
when "1111011000011110" => dout <= "0000";
when "1111011000011000" => dout <= "0000";
when "1111011001011000" => dout <= "0000";
when "1111011010011000" => dout <= "0000";
when "1111011111011000" => dout <= "0000";
when "1111011100011110" => dout <= "0000";
when "1111011100011000" => dout <= "0000";
when "1111011101011000" => dout <= "0000";
when "1111011110011000" => dout <= "0000";
when "0011011100000000" => dout <= "0000";
when "0010011100000000" => dout <= "0000";
when "0011111100000000" => dout <= "0000";
when "0010111100000000" => dout <= "0000";
when "1111011011100000" => dout <= "0000";
when "1111011000100110" => dout <= "0000";
when "1111011000100000" => dout <= "0000";
when "1111011001100000" => dout <= "0000";
when "1111011010100000" => dout <= "0000";
when "1111011111100000" => dout <= "0000";
when "1111011100100110" => dout <= "0000";
when "1111011100100000" => dout <= "0000";
when "1111011101100000" => dout <= "0000";
when "1111011110100000" => dout <= "0000";
when "1111011011101000" => dout <= "0000";
when "1111011000101110" => dout <= "0000";
when "1111011000101000" => dout <= "0000";
when "1111011001101000" => dout <= "0000";
when "1111011010101000" => dout <= "0000";
when "1111011111101000" => dout <= "0000";
when "1111011100101110" => dout <= "0000";
when "1111011100101000" => dout <= "0000";
when "1111011101101000" => dout <= "0000";
when "1111011110101000" => dout <= "0000";
when "1111011011110000" => dout <= "0000";
when "1111011000110110" => dout <= "0000";
when "1111011000110000" => dout <= "0000";
when "1111011001110000" => dout <= "0000";
when "1111011010110000" => dout <= "0000";
when "1111011111110000" => dout <= "0000";
when "1111011100110110" => dout <= "0000";
when "1111011100110000" => dout <= "0000";
when "1111011101110000" => dout <= "0000";
when "1111011110110000" => dout <= "0000";
when "1111011011111000" => dout <= "0000";
when "1111011000111110" => dout <= "0000";
when "1111011000111000" => dout <= "0000";
when "1111011001111000" => dout <= "0000";
when "1111011010111000" => dout <= "0000";
when "1111011111111000" => dout <= "0000";
when "1111011100111110" => dout <= "0000";
when "1111011100111000" => dout <= "0000";
when "1111011101111000" => dout <= "0000";
when "1111011110111000" => dout <= "0000";
when "1101010000000000" => dout <= "0000";
when "1101010100000000" => dout <= "0000";
when "1001100000000000" => dout <= "0000";
when "1001100100000000" => dout <= "0000";
when "1101000011000000" => dout <= "0000";
when "1101000000000110" => dout <= "0000";
when "1101000000000000" => dout <= "0000";
when "1101000001000000" => dout <= "0000";
when "1101000010000000" => dout <= "0000";
when "1101000111000000" => dout <= "0000";
when "1101000100000110" => dout <= "0000";
when "1101000100000000" => dout <= "0000";
when "1101000101000000" => dout <= "0000";
when "1101000110000000" => dout <= "0000";
when "1101001011000000" => dout <= "0000";
when "1101001000000110" => dout <= "0000";
when "1101001000000000" => dout <= "0000";
when "1101001001000000" => dout <= "0000";
when "1101001010000000" => dout <= "0000";
when "1101001111000000" => dout <= "0000";
when "1101001100000110" => dout <= "0000";
when "1101001100000000" => dout <= "0000";
when "1101001101000000" => dout <= "0000";
when "1101001110000000" => dout <= "0000";
when "0010000011000000" => dout <= "0000";
when "0010000000000110" => dout <= "0000";
when "0010000000000000" => dout <= "0000";
when "0010000001000000" => dout <= "0000";
when "0010000010000000" => dout <= "0000";
when "0010000111000000" => dout <= "0000";
when "0010000100000110" => dout <= "0000";
when "0010000100000000" => dout <= "0000";
when "0010000101000000" => dout <= "0000";
when "0010000110000000" => dout <= "0000";
when "0010001011000000" => dout <= "0000";
when "0010001000000110" => dout <= "0000";
when "0010001000000000" => dout <= "0000";
when "0010001001000000" => dout <= "0000";
when "0010001010000000" => dout <= "0000";
when "0010001111000000" => dout <= "0000";
when "0010001100000110" => dout <= "0000";
when "0010001100000000" => dout <= "0000";
when "0010001101000000" => dout <= "0000";
when "0010001110000000" => dout <= "0000";
when "1000000011100000" => dout <= "0011";
when "1000000000100110" => dout <= "0111";
when "1000000000100000" => dout <= "0011";
when "1000000001100000" => dout <= "0101";
when "1000000010100000" => dout <= "0111";
when "1000000111100000" => dout <= "0100";
when "1000000100100110" => dout <= "1000";
when "1000000100100000" => dout <= "0100";
when "1000000101100000" => dout <= "0110";
when "1000000110100000" => dout <= "1000";
when "1000001111100000" => dout <= "0011";
when "1000001100100110" => dout <= "0111";
when "1000001100100000" => dout <= "0011";
when "1000001101100000" => dout <= "0101";
when "1000001110100000" => dout <= "0111";
when "0010010000000000" => dout <= "0001";
when "0010010100000000" => dout <= "0010";
when "0000100000000110" => dout <= "0000";
when "0000100000000000" => dout <= "0000";
when "0000100001000000" => dout <= "0000";
when "0000100010000000" => dout <= "0000";
when "0000100011000000" => dout <= "0000";
when "0000100100000110" => dout <= "0000";
when "0000100100000000" => dout <= "0000";
when "0000100101000000" => dout <= "0000";
when "0000100110000000" => dout <= "0000";
when "0000100111000000" => dout <= "0000";
when "0000101011000000" => dout <= "0000";
when "0000101000000110" => dout <= "0000";
when "0000101000000000" => dout <= "0000";
when "0000101001000000" => dout <= "0000";
when "0000101010000000" => dout <= "0000";
when "0000101111000000" => dout <= "0000";
when "0000101100000110" => dout <= "0000";
when "0000101100000000" => dout <= "0000";
when "0000101101000000" => dout <= "0000";
when "0000101110000000" => dout <= "0000";
when "1000000011001000" => dout <= "0011";
when "1000000000001110" => dout <= "0111";
when "1000000000001000" => dout <= "0011";
when "1000000001001000" => dout <= "0101";
when "1000000010001000" => dout <= "0111";
when "1000000111001000" => dout <= "0100";
when "1000000100001110" => dout <= "1000";
when "1000000100001000" => dout <= "0100";
when "1000000101001000" => dout <= "0110";
when "1000000110001000" => dout <= "1000";
when "1000001111001000" => dout <= "0011";
when "1000001100001110" => dout <= "0111";
when "1000001100001000" => dout <= "0011";
when "1000001101001000" => dout <= "0101";
when "1000001110001000" => dout <= "0111";
when "0000110000000000" => dout <= "0001";
when "0000110100000000" => dout <= "0010";
when "1000010000000110" => dout <= "0000";
when "1000010000000000" => dout <= "0000";
when "1000010001000000" => dout <= "0000";
when "1000010010000000" => dout <= "0000";
when "1000010100000110" => dout <= "0000";
when "1000010100000000" => dout <= "0000";
when "1000010101000000" => dout <= "0000";
when "1000010110000000" => dout <= "0000";
when "1000010011000000" => dout <= "0000";
when "1000010111000000" => dout <= "0000";
when "1111011011000000" => dout <= "0011";
when "1111011000000110" => dout <= "0111";
when "1111011000000000" => dout <= "0011";
when "1111011001000000" => dout <= "0101";
when "1111011010000000" => dout <= "0111";
when "1111011111000000" => dout <= "0100";
when "1111011100000110" => dout <= "1000";
when "1111011100000000" => dout <= "0100";
when "1111011101000000" => dout <= "0110";
when "1111011110000000" => dout <= "1000";
when "1010100000000000" => dout <= "0001";
when "1010100100000000" => dout <= "0010";
when "0011000000000110" => dout <= "0000";
when "0011000000000000" => dout <= "0000";
when "0011000001000000" => dout <= "0000";
when "0011000010000000" => dout <= "0000";
when "0011000011000000" => dout <= "0000";
when "0011000100000110" => dout <= "0000";
when "0011000100000000" => dout <= "0000";
when "0011000101000000" => dout <= "0000";
when "0011000110000000" => dout <= "0000";
when "0011000111000000" => dout <= "0000";
when "0011001011000000" => dout <= "0000";
when "0011001000000110" => dout <= "0000";
when "0011001000000000" => dout <= "0000";
when "0011001001000000" => dout <= "0000";
when "0011001010000000" => dout <= "0000";
when "0011001111000000" => dout <= "0000";
when "0011001100000110" => dout <= "0000";
when "0011001100000000" => dout <= "0000";
when "0011001101000000" => dout <= "0000";
when "0011001110000000" => dout <= "0000";
when "1000000011110000" => dout <= "0011";
when "1000000000110110" => dout <= "0111";
when "1000000000110000" => dout <= "0011";
when "1000000001110000" => dout <= "0101";
when "1000000010110000" => dout <= "0111";
when "1000000111110000" => dout <= "0100";
when "1000000100110110" => dout <= "1000";
when "1000000100110000" => dout <= "0100";
when "1000000101110000" => dout <= "0110";
when "1000000110110000" => dout <= "1000";
when "1000001111110000" => dout <= "0011";
when "1000001100110110" => dout <= "0111";
when "1000001100110000" => dout <= "0011";
when "1000001101110000" => dout <= "0101";
when "1000001110110000" => dout <= "0111";
when "0011010000000000" => dout <= "0001";
when "0011010100000000" => dout <= "0010";
when "1111011011010000" => dout <= "0000";
when "1111011000010110" => dout <= "0000";
when "1111011000010000" => dout <= "0000";
when "1111011001010000" => dout <= "0000";
when "1111011010010000" => dout <= "0000";
when "1111011111010000" => dout <= "0000";
when "1111011100010110" => dout <= "0000";
when "1111011100010000" => dout <= "0000";
when "1111011101010000" => dout <= "0000";
when "1111011110010000" => dout <= "0000";
when "1010010000000000" => dout <= "0000";
when "1010010100000000" => dout <= "0000";
when "1010011000000000" => dout <= "0000";
when "1010011100000000" => dout <= "0000";
when "1010111000000000" => dout <= "0000";
when "1010111100000000" => dout <= "0000";
when "1010110000000000" => dout <= "0000";
when "1010110100000000" => dout <= "0000";
when "1010101000000000" => dout <= "0000";
when "1010101100000000" => dout <= "0000";
when "1111001000000000" => dout <= "0000";
when "1111001100000000" => dout <= "0000";
when "0110000000000000" => dout <= "0000";
when "0110000100000000" => dout <= "0000";
when "1100100000000000" => dout <= "0000";
when "1100100100000000" => dout <= "0000";
when "0110001000000000" => dout <= "0000";
when "0110110000000000" => dout <= "0000";
when "0110110100000000" => dout <= "0000";
when "0110111000000000" => dout <= "0000";
when "0110111100000000" => dout <= "0000";
when "0000111100000000" => dout <= "0000";
when "0110001100000000" => dout <= "0000";
when "0110010000000000" => dout <= "0000";
when "0110010100000000" => dout <= "0000";
when "0110011000000000" => dout <= "0000";
when "0110011100000000" => dout <= "0000";
when "1000001000000000" => dout <= "0000";
when "1101011000000000" => dout <= "0000";
when "1111000100000000" => dout <= "0000";
when "1100000000000000" => dout <= "0000";
when "1100000100000000" => dout <= "0000";
when others => dout <= "----";
end case;
end process;
end rtl; | gpl-2.0 |
davewebb8211/ghdl | libraries/vital2000/prmtvs_p.vhdl | 7 | 68530 | -- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
| gpl-2.0 |
loetlab-jena/das-atv | hdl/syn/ip/pll2.vhd | 1 | 15117 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 50,
clk0_duty_cycle => 50,
clk0_multiply_by => 27,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "108"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 |
davewebb8211/ghdl | libraries/vital2000/memory_p.vhdl | 7 | 78216 | -- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
-- : Jose De Castro, Consultant
-- : Prakash Bare, GDA Technologies
-- : William Yam, LSI Logic Corporation
-- : Dennis Brophy, Model Technology
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC memory models.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Ver:|Auth:| Date:| Changes Made:
-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal
-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme
-- 0.3 | jdc |090297| Extensive updates for TAG review (functional)
-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable
-- | | | Added interface of VitalMemoryCrossPorts() &
-- | | | VitalMemoryViolation().
-- 0.5 | jdc |092997| Completed naming changes thoughout package body.
-- | | | Testing with simgle port test model looks ok.
-- 0.6 | jdc |121797| Major updates to the packages:
-- | | | - Implement VitalMemoryCrossPorts()
-- | | | - Use new VitalAddressValueType
-- | | | - Use new VitalCrossPortModeType enum
-- | | | - Overloading without SamePort args
-- | | | - Honor erroneous address values
-- | | | - Honor ports disabled with 'Z'
-- | | | - Implement implicit read 'M' table symbol
-- | | | - Cleanup buses to use (H DOWNTO L)
-- | | | - Message control via MsgOn,HeaderMsg,PortName
-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases
-- 0.7 | jdc |052698| Bug fixes to the packages:
-- | | | - Fix failure with negative Address values
-- | | | - Added debug messages for VMT table search
-- | | | - Remove 'S' for action column (only 's')
-- | | | - Remove 's' for response column (only 'S')
-- | | | - Remove 'X' for action and response columns
-- 0.8 | jdc |061298| Implemented VitalMemoryViolation()
-- | | | - Minimal functionality violation tables
-- | | | - Missing:
-- | | | - Cannot handle wide violation variables
-- | | | - Cannot handle sub-word cases
-- | | | Fixed IIC version of MemoryMatch
-- | | | Fixed 'M' vs 'm' switched on debug output
-- | | | TO BE DONE:
-- | | | - Implement 'd' corrupting a single bit
-- | | | - Implement 'D' corrupting a single bit
-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType
-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType
-- 0.11|eb/sc|081798| Added overloaded function interface for
-- | | | VitalDeclareMemory
-- 0.14| jdc |113198| Merging of memory functionality and version
-- | | | 1.4 9/17/98 of timing package from Prakash
-- 0.15| jdc |120198| Major development of VMV functionality
-- 0.16| jdc |120298| Complete VMV functionlality for initial testing
-- | | | - New ViolationTableCorruptMask() procedure
-- | | | - New MemoryTableCorruptMask() procedure
-- | | | - HandleMemoryAction():
-- | | | - Removed DataOutBus bogus output
-- | | | - Replaced DataOutTmp with DataInTmp
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'c','l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit
-- | | | - HandleDataAction():
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'L','D','E' to use HighBit, LowBit
-- | | | - MemoryTableLookUp():
-- | | | - Added MsgOn table debug output
-- | | | - Uses new MemoryTableCorruptMask()
-- | | | - ViolationTableLookUp():
-- | | | - Uses new ViolationTableCorruptMask()
-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType,
-- | | | VitalMemoryViolationTableType data
-- | | | types but not used yet (need to discuss)
-- | | | - Added overload for VitalMemoryViolation()
-- | | | which does not have array flags
-- | | | - Bug fixes for VMV functionality:
-- | | | - ViolationTableLookUp() not handling '-' in
-- | | | scalar violation matching
-- | | | - VitalMemoryViolation() now normalizes
-- | | | VFlagArrayTmp'LEFT as LSB before calling
-- | | | ViolationTableLookUp() for proper scanning
-- | | | - ViolationTableCorruptMask() had to remove
-- | | | normalization of CorruptMaskTmp and
-- | | | ViolMaskTmp for proper MSB:LSB corruption
-- | | | - HandleMemoryAction(), HandleDataAction()
-- | | | - Removed 'D','E' since not being used
-- | | | - Use XOR instead of OR for corrupt masks
-- | | | - Now 'd' is sensitive to HighBit, LowBit
-- | | | - Fixed LowBit overflow in bit writeable case
-- | | | - MemoryTableCorruptMask()
-- | | | - ViolationTableCorruptMask()
-- | | | - VitalMemoryTable()
-- | | | - VitalMemoryCrossPorts()
-- | | | - Fixed VitalMemoryViolation() failing on
-- | | | error AddressValue from earlier VMT()
-- | | | - Minor cleanup of code formatting
-- 0.18| jdc |032599| - In VitalDeclareMemory()
-- | | | - Added BinaryLoadFile formal arg and
-- | | | modified LoadMemory() to handle bin
-- | | | - Added NOCHANGE to VitalPortFlagType
-- | | | - For VitalCrossPortModeType
-- | | | - Added CpContention enum
-- | | | - In HandleDataAction()
-- | | | - Set PortFlag := NOCHANGE for 'S'
-- | | | - In HandleMemoryAction()
-- | | | - Set PortFlag := NOCHANGE for 's'
-- | | | - In VitalMemoryTable() and
-- | | | VitalMemoryViolation()
-- | | | - Honor PortFlag = NOCHANGE returned
-- | | | from HandleMemoryAction()
-- | | | - In VitalMemoryCrossPorts()
-- | | | - Fixed Address = AddressJ for all
-- | | | conditions of DoWrCont & DoCpRead
-- | | | - Handle CpContention like WrContOnly
-- | | | under CpReadOnly conditions, with
-- | | | associated memory message changes
-- | | | - Handle PortFlag = NOCHANGE like
-- | | | PortFlag = READ for actions
-- | | | - Modeling change:
-- | | | - Need to init PortFlag every delta
-- | | | PortFlag_A := (OTHES => UNDEF);
-- | | | - Updated InternalTimingCheck code
-- 0.19| jdc |042599| - Fixes for bit-writeable cases
-- | | | - Check PortFlag after HandleDataAction
-- | | | in VitalMemoryViolation()
-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash
-- | | | and Willian:
-- | | | VitalMemorySchedulePathDelay()
-- | | | VitalMemoryExpandPortFlag()
-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums,
-- | | | added new CpReadAndReadContention.
-- | | | - Fixed VitalMemoryCrossPorts() parameter
-- | | | SamePortFlag to INOUT so that it can
-- | | | set CORRUPT or READ value.
-- | | | - Fixed VitalMemoryTable() where PortFlag
-- | | | setting by HandleDataAction() is being
-- | | | ignored when HandleMemoryAction() sets
-- | | | PortFlagTmp to NOCHANGE.
-- | | | - Fixed VitalMemoryViolation() to set
-- | | | all bits of PortFlag when violating.
-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData
-- | | | checks whether the previous state is HIGHZ.
-- | | | If yes then portFlag should be NOCHANGE
-- | | | for VMPD to ignore IORetain corruption.
-- | | | The idea is that the first Z should be
-- | | | propagated but later ones should be ignored.
-- | | |
-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99
-- | | | - Changed VitalPortFlagType to record of
-- | | | new VitalPortStateType to hold current,
-- | | | previous values and separate disable.
-- | | | Also created VitalDefaultPortFlag const.
-- | | | Removed usage of PortFlag NOCHANGE
-- | | | - VitalMemoryTable() changes:
-- | | | Optimized return when all curr = prev
-- | | | AddressValue is now INOUT to optimize
-- | | | Transfer PF.MemoryCurrent to MemoryPrevious
-- | | | Transfer PF.DataCurrent to DataPrevious
-- | | | Reset PF.OutputDisable to FALSE
-- | | | Expects PortFlag init in declaration
-- | | | No need to init PortFlag every delta
-- | | | - VitalMemorySchedulePathDelay() changes:
-- | | | Initialize with VitalDefaultPortFlag
-- | | | Check PortFlag.OutputDisable
-- | | | - HandleMemoryAction() changes:
-- | | | Set value of PortFlag.MemoryCurrent
-- | | | Never set PortFlag.OutputDisable
-- | | | - HandleDataAction() changes:
-- | | | Set value of PortFlag.DataCurrent
-- | | | Set PortFlag.DataCurrent for HIGHZ
-- | | | - VitalMemoryCrossPorts() changes:
-- | | | Check/set value of PF.MemoryCurrent
-- | | | Check value of PF.OutputDisable
-- | | | - VitalMemoryViolation() changes:
-- | | | Fixed bug - not reading inout PF value
-- | | | Clean up setting of PortFlag
-- 0.24| jdc |100899| - Modified update of PF.OutputDisable
-- | | | to correctly accomodate 2P1W1R case:
-- | | | the read port should not exhibit
-- | | | IO retain corrupt when reading
-- | | | addr unrelated to addr being written.
-- 0.25| jdc |100999| - VitalMemoryViolation() change:
-- | | | Fixed bug with RDNWR mode incorrectly
-- | | | updating the PF.OutputDisable
-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change:
-- | | | Fixed bugs with update of PF
-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change:
-- | | | Added DoRdWrCont message (ErrMcpRdWrCo,
-- | | | Memory cross port read/write data only
-- | | | contention)
-- | | | - VitalMemoryTable() change:
-- | | | Set PF.OutputDisable := TRUE for the
-- | | | optimized cases.
-- 0.28| pb |112399| - Added 8 VMPD procedures for vector
-- | | | PathCondition support. Now the total
-- | | | number of overloadings for VMPD is 24.
-- | | | - Number of overloadings for SetupHold
-- | | | procedures increased to 5. Scalar violations
-- | | | are not supported anymore. Vector checkEnabled
-- | | | support is provided through the new overloading
-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction()
-- | | | Reinstated 'D' and 'E' actions but
-- | | | with new PortFlagType
-- | | | - Updated file handling syntax, must compile
-- | | | with -93 syntax now.
-- 0.30| jdc |022300| - Formated for 80 column max width
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.Vital_Timing.ALL;
USE IEEE.Vital_Primitives.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE Vital_Memory IS
-- ----------------------------------------------------------------------------
-- Timing Section
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Types and constants for Memory timing procedures
-- ----------------------------------------------------------------------------
TYPE VitalMemoryArcType IS (ParallelArc, CrossArc, SubwordArc);
TYPE OutputRetainBehaviorType IS (BitCorrupt, WordCorrupt);
TYPE VitalMemoryMsgFormatType IS (Vector, Scalar, VectorEnum);
TYPE X01ArrayT IS ARRAY (NATURAL RANGE <> ) OF X01;
TYPE X01ArrayPT IS ACCESS X01ArrayT;
TYPE VitalMemoryViolationType IS ACCESS X01ArrayT;
CONSTANT DefaultNumBitsPerSubword : INTEGER := -1;
-- Data type storing path delay and schedule information for output bits
TYPE VitalMemoryScheduleDataType IS RECORD
OutputData : std_ulogic;
NumBitsPerSubWord : INTEGER;
ScheduleTime : TIME;
ScheduleValue : std_ulogic;
LastOutputValue : std_ulogic;
PropDelay : TIME;
OutputRetainDelay : TIME;
InputAge : TIME;
END RECORD;
TYPE VitalMemoryTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
RefLastA : X01ArrayPT;
RefTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
TYPE VitalPeriodDataArrayType IS ARRAY (NATURAL RANGE <>) OF
VitalPeriodDataType;
-- Data type storing path delay and schedule information for output
-- vectors
TYPE VitalMemoryScheduleDataVectorType IS ARRAY (NATURAL RANGE <> ) OF
VitalMemoryScheduleDataType;
-- VitalPortFlagType records runtime mode of port sub-word slices
-- TYPE VitalPortFlagType IS (
-- UNDEF,
-- READ,
-- WRITE,
-- CORRUPT,
-- HIGHZ,
-- NOCHANGE
-- );
-- VitalPortFlagType records runtime mode of port sub-word slices
TYPE VitalPortStateType IS (
UNDEF,
READ,
WRITE,
CORRUPT,
HIGHZ
);
TYPE VitalPortFlagType IS RECORD
MemoryCurrent : VitalPortStateType;
MemoryPrevious : VitalPortStateType;
DataCurrent : VitalPortStateType;
DataPrevious : VitalPortStateType;
OutputDisable : BOOLEAN;
END RECORD;
CONSTANT VitalDefaultPortFlag : VitalPortFlagType := (
MemoryCurrent => READ,
MemoryPrevious => UNDEF,
DataCurrent => READ,
DataPrevious => UNDEF,
OutputDisable => FALSE
);
-- VitalPortFlagVectorType to be same width i as enables of a port
-- or j multiples thereof, where j is the number of cross ports
TYPE VitalPortFlagVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalPortFlagType;
-- ----------------------------------------------------------------------------
-- Functions : VitalMemory path delay procedures
-- - VitalMemoryInitPathDelay
-- - VitalMemoryAddPathDelay
-- - VitalMemorySchedulePathDelay
--
-- Description: VitalMemoryInitPathDelay, VitalMemoryAddPathDelay and
-- VitalMemorySchedulePathDelay are Level 1 routines used
-- for selecting the propagation delay paths based on
-- path condition, transition type and delay values and
-- schedule a new output value.
--
-- Following features are implemented in these procedures:
-- o condition dependent path selection
-- o Transition dependent delay selection
-- o shortest delay path selection from multiple
-- candidate paths
-- o Scheduling of the computed values on the specified
-- signal.
-- o output retain behavior if outputRetain flag is set
-- o output mapping to alternate strengths to model
-- pull-up, pull-down etc.
--
-- <More details to be added here>
--
-- Following is information on overloading of the procedures.
--
-- VitalMemoryInitPathDelay is overloaded for ScheduleDataArray and
-- OutputDataArray
--
-- ----------------------------------------------------------------------------
-- ScheduleDataArray OutputDataArray
-- ----------------------------------------------------------------------------
-- Scalar Scalar
-- Vector Vector
-- ----------------------------------------------------------------------------
--
--
-- VitalMemoryAddPathDelay is overloaded for ScheduleDataArray,
-- PathDelayArray, InputSignal and delaytype.
--
-- ----------------------------------------------------------------------------
-- DelayType InputSignal ScheduleData PathDelay
-- Array Array
-- ----------------------------------------------------------------------------
-- VitalDelayType Scalar Scalar Scalar
-- VitalDelayType Scalar Vector Vector
-- VitalDelayType Vector Scalar Vector
-- VitalDelayType Vector Vector Vector
-- VitalDelayType01 Scalar Scalar Scalar
-- VitalDelayType01 Scalar Vector Vector
-- VitalDelayType01 Vector Scalar Vector
-- VitalDelayType01 Vector Vector Vector
-- VitalDelayType01Z Scalar Scalar Scalar
-- VitalDelayType01Z Scalar Vector Vector
-- VitalDelayType01Z Vector Scalar Vector
-- VitalDelayType01Z Vector Vector Vector
-- VitalDelayType01XZ Scalar Scalar Scalar
-- VitalDelayType01XZ Scalar Vector Vector
-- VitalDelayType01XZ Vector Scalar Vector
-- VitalDelayType01XZ Vector Vector Vector
-- ----------------------------------------------------------------------------
--
--
-- VitalMemorySchedulePathDelay is overloaded for ScheduleDataArray,
-- and OutSignal
--
-- ----------------------------------------------------------------------------
-- OutSignal ScheduleDataArray
-- ----------------------------------------------------------------------------
-- Scalar Scalar
-- Vector Vector
-- ----------------------------------------------------------------------------
--
-- Procedure Declarations:
--
--
-- Function : VitalMemoryInitPathDelay
--
-- Arguments:
--
-- INOUT Type Description
--
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each output bit
--
--
-- IN
--
-- OutputDataArray/ STD_LOGIC_VECTOR/Array containing current output
-- OutputData STD_ULOGIC value
--
--
-- NumBitsPerSubWord INTEGER Number of bits per subword.
-- Default value of this argument
-- is DefaultNumBitsPerSubword
-- which is interpreted as no
-- subwords
--
-- ----------------------------------------------------------------------------
--
--
-- ScheduleDataArray - Vector
-- OutputDataArray - Vector
--
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR;
CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword
);
--
-- ScheduleDataArray - Scalar
-- OutputDataArray - Scalar
--
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
VARIABLE OutputData : IN STD_ULOGIC
);
-- ----------------------------------------------------------------------------
--
-- Function : VitalMemoryAddPathDelay
--
-- Arguments
--
-- INOUT Type Description
--
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each output bit
--
-- InputChangeTimeArray/ VitaltimeArrayT/Time
-- InputChangeTime Holds the time since the last
-- input change
--
-- IN
--
-- InputSignal STD_LOGIC_VECTOR
-- STD_ULOGIC/ Array holding the input value
--
-- OutputSignalName STRING The output signal name
--
-- PathDelayArray/ VitalDelayArrayType01ZX,
-- PathDelay VitalDelayArrayType01Z,
-- VitalDelayArrayType01,
-- VitalDelayArrayType/
-- VitalDelayType01ZX,
-- VitalDelayType01Z,
-- VitalDelayType01,
-- VitalDelayType Array of delay values
--
-- ArcType VitalMemoryArcType
-- Indicates the Path type. This
-- can be SubwordArc, CrossArc or
-- ParallelArc
--
-- PathCondition BOOLEAN If True, the transition in
-- the corresponding input signal
-- is considered while
-- caluculating the prop. delay
-- else the transition is ignored.
--
-- OutputRetainFlag BOOLEAN If specified TRUE,output retain
-- (hold) behavior is implemented.
--
-- ----------------------------------------------------------------------------
--
-- #1
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #2
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #3
-- DelayType - VitalDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
);
-- #4
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #5
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #6
-- DelayType - VitalDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
);
-- #7
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #8
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #9
-- DelayType - VitalDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
);
-- #10
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #11
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
);
-- #12
-- DelayType - VitalDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
);
-- #13
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #14
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #15
-- DelayType - VitalDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #16
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #17
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #18
-- DelayType - VitalDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #19
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelay : IN VitalDelayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #20
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #21
-- DelayType - VitalDelayType01ZX
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTime : INOUT Time;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
);
-- #22
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #23
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- #24
-- DelayType - VitalDelayType01ZX
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING := "";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
);
-- ----------------------------------------------------------------------------
--
-- Function : VitalMemorySchedulePathDelay
--
-- Arguments:
--
-- OUT Type Description
-- OutSignal STD_LOGIC_VECTOR/ The output signal for
-- STD_ULOGIC scheduling
--
-- IN
-- OutputSignalName STRING The name of the output signal
--
-- IN
-- PortFlag VitalPortFlagType Port flag variable from
-- functional procedures
--
-- IN
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the
-- output can be mapped to
-- alternate strengths to model
-- tri-state devices, pull-ups
-- and pull-downs.
--
-- INOUT
-- ScheduleDataArray/ VitalMemoryScheduleDataVectorType/
-- ScheduleData VitalMemoryScheduleDataType
-- Internal data variable for
-- storing delay and schedule
-- information for each
-- output bit
--
-- ----------------------------------------------------------------------------
--
-- ScheduleDataArray - Vector
-- OutputSignal - Vector
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
);
--
-- ScheduleDataArray - Vector
-- OutputSignal - Vector
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
);
--
-- ScheduleDataArray - Scalar
-- OutputSignal - Scalar
--
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT std_ulogic;
CONSTANT OutputSignalName : IN STRING := "";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType
);
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryTimingDataInit RETURN VitalMemoryTimingDataType;
-- ----------------------------------------------------------------------------
--
-- Function Name: VitalMemorySetupHoldCheck
--
-- Description: The VitalMemorySetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal and reference signals. Parallel, Subword and
-- Cross Arc relationships between test and reference
-- signals are supported.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_logic_vector Value of test signal
-- TestSignalName STRING Name of test signal
-- TestDelay VitalDelayArrayType Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- std_logic_vector
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- VitalDelayArrayType with RefSignal
-- SetupHigh VitalDelayArrayType Absolute minimum time duration
-- before the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to proceed
-- to the "1" state without causing
-- a setup violation.
-- SetupLow VitalDelayArrayType Absolute minimum time duration
-- before the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to proceed
-- to the "0" state without causing
-- a setup violation.
-- HoldHigh VitalDelayArrayType Absolute minimum time duration
-- after the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to
-- proceed to the "1" state without
-- causing a hold violation.
-- HoldLow VitalDelayArrayType Absolute minimum time duration
-- after the transition of RefSignal
-- for which transitions of
-- TestSignal are allowed to
-- proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events
-- on the RefSignal which match the
-- edge spec. are used as reference
-- edges.
-- ArcType VitalMemoryArcType
-- NumBitsPerSubWord INTEGER
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output
-- parameter is set to "X".
-- Otherwise, Violation is always
-- set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are
-- generated, even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- MsgFormat VitalMemoryMsgFormatType
-- Format of the Test/Reference
-- signals in violation messages.
--
-- INOUT
-- TimingData VitalMemoryTimingDataType
-- VitalMemorySetupHoldCheck information
-- storage area. This is used
-- internally to detect reference
-- edges and record the time of the
-- last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
-- X01ArrayT Overloaded for array type.
--
--
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayType;
CONSTANT SetupLow : IN VitalDelayType;
CONSTANT HoldHigh : IN VitalDelayType;
CONSTANT HoldLow : IN VitalDelayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
--------------- following are not needed --------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArrayType;
CONSTANT SetupHigh : IN VitalDelayArrayType;
CONSTANT SetupLow : IN VitalDelayArrayType;
CONSTANT HoldHigh : IN VitalDelayArrayType;
CONSTANT HoldLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
);
-- ----------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_logic_vector Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay VitalDelayArrayType
-- Model's internal delay associated
-- with TestSignal
-- Period VitalDelayArrayType
-- Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh VitalDelayArrayType
-- Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow VitalDelayArrayType
-- Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- MsgFormat VitalMemoryMsgFormatType
-- Format of the Test/Reference signals
-- in violation messages.
--
-- INOUT
-- PeriodData VitalPeriodDataArrayType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
-- X01ArrayT Overloaded for array type.
--
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
CONSTANT Period : IN VitalDelayArrayType;
CONSTANT PulseWidthHigh : IN VitalDelayArrayType;
CONSTANT PulseWidthLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
);
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArrayType;
CONSTANT Period : IN VitalDelayArrayType;
CONSTANT PulseWidthHigh : IN VitalDelayArrayType;
CONSTANT PulseWidthLow : IN VitalDelayArrayType;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
);
-- ----------------------------------------------------------------------------
-- Functionality Section
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- All Memory Types and Record definitions.
-- ----------------------------------------------------------------------------
TYPE MemoryWordType IS ARRAY (NATURAL RANGE <>) OF UX01;
TYPE MemoryWordPtr IS ACCESS MemoryWordType;
TYPE MemoryArrayType IS ARRAY (NATURAL RANGE <>) OF MemoryWordPtr;
TYPE MemoryArrayPtrType IS ACCESS MemoryArrayType;
TYPE VitalMemoryArrayRecType IS
RECORD
NoOfWords : POSITIVE;
NoOfBitsPerWord : POSITIVE;
NoOfBitsPerSubWord : POSITIVE;
NoOfBitsPerEnable : POSITIVE;
MemoryArrayPtr : MemoryArrayPtrType;
END RECORD;
TYPE VitalMemoryDataType IS ACCESS VitalMemoryArrayRecType;
TYPE VitalTimingDataVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalTimingDataType;
TYPE VitalMemoryViolFlagSizeType IS ARRAY (NATURAL RANGE <>) OF INTEGER;
-- ----------------------------------------------------------------------------
-- Symbol Literals used for Memory Table Modeling
-- ----------------------------------------------------------------------------
-- Symbol literals from '/' to 'S' are closely related to MemoryTableMatch
-- lookup matching and the order cannot be arbitrarily changed.
-- The remaining symbol literals are interpreted directly and matchting is
-- handled in the MemoryMatch procedure itself.
TYPE VitalMemorySymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S', -- steady value
'g', -- Good address (no transition)
'u', -- Unknown address (no transition)
'i', -- Invalid address (no transition)
'G', -- Good address (with transition)
'U', -- Unknown address (with transition)
'I', -- Invalid address (with transition)
'w', -- Write data to memory
's', -- Retain previous memory contents
'c', -- Corrupt entire memory with 'X'
'l', -- Corrupt a word in memory with 'X'
'd', -- Corrupt a single bit in memory with 'X'
'e', -- Corrupt a word with 'X' based on data in
'C', -- Corrupt a sub-word entire memory with 'X'
'L', -- Corrupt a sub-word in memory with 'X'
-- The following entries are commented since their
-- interpretation overlap with existing definitions.
-- 'D', -- Corrupt a single bit of a sub-word with 'X'
-- 'E', -- Corrupt a sub-word with 'X' based on datain
'M', -- Implicit read data from memory
'm', -- Read data from memory
't' -- Immediate assign/transfer data in
);
TYPE VitalMemoryTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalMemorySymbolType;
TYPE VitalMemoryViolationSymbolType IS (
'X', -- Unknown level
'0', -- low level
'-' -- don't care
);
TYPE VitalMemoryViolationTableType IS
ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalMemoryViolationSymbolType;
TYPE VitalPortType IS (
UNDEF,
READ,
WRITE,
RDNWR
);
TYPE VitalCrossPortModeType IS (
CpRead, -- CpReadOnly,
WriteContention, -- WrContOnly,
ReadWriteContention, -- CpContention
CpReadAndWriteContention, -- WrContAndCpRead,
CpReadAndReadContention
);
SUBTYPE VitalAddressValueType IS INTEGER;
TYPE VitalAddressValueVectorType IS
ARRAY (NATURAL RANGE <>) OF VitalAddressValueType;
-- ----------------------------------------------------------------------------
-- Procedure: VitalDeclareMemory
-- Parameters: NoOfWords - Number of words in the memory
-- NoOfBitsPerWord - Number of bits per word in memory
-- NoOfBitsPerSubWord - Number of bits per sub word
-- MemoryLoadFile - Name of data file to load
-- Description: This function is intended to be used to initialize
-- memory data declarations, i.e. to be executed duing
-- simulation elaboration time. Handles the allocation
-- and initialization of memory for the memory data.
-- Default NoOfBitsPerSubWord is NoOfBits.
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT NoOfBitsPerSubWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType;
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryTable
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- PrevDataInBus - Previous data bus for edge detection
-- PrevAddressBus - Previous address bus for edge detection
-- PortFlag - Indicates port operating mode
-- PortFlagArray - Vector form of PortFlag for sub-word
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- MemoryTable - Input memory action table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure implements the majority of the memory
-- modeling functionality via lookup of the memory action
-- tables and performing the specified actions if matches
-- are found, or the default actions otherwise. The
-- overloadings are provided for the word and sub-word
-- (using the EnableBus and PortFlagArray arguments) addressing
-- cases.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevEnableBus : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryCrossPorts
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- SamePortFlag - Operating mode for same port
-- SamePortAddressValue - Decoded AddressBus for same port
-- CrossPortFlagArray - Operating modes for cross ports
-- CrossPortAddressArray - Decoded AddressBus for cross ports
-- CrossPortMode - Write contention and crossport read control
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
--
-- Description: These procedures control the effect of memory operations
-- on a given port due to operations on other ports in a
-- multi-port memory.
-- This includes data write through when reading and writing
-- to the same address, as well as write contention when
-- there are multiple write to the same address.
-- If addresses do not match then data bus is unchanged.
-- The DataOutBus can be diabled with 'Z' value.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType;
CONSTANT SamePortAddressValue : IN VitalAddressValueType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT CrossPortMode : IN VitalCrossPortModeType
:= CpReadAndWriteContention;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) ;
PROCEDURE VitalMemoryCrossPorts (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) ;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryViolation
-- Parameters: DataOutBus - Output zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PortFlag - Indicates port operating mode
-- DataInBus - Input value of data bus in
-- AddressValue - Decoded value of the AddressBus
-- ViolationFlags - Aggregate of scalar violation vars
-- ViolationFlagsArray - Concatenation of vector violation vars
-- ViolationTable - Input memory violation table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure is intended to implement all actions on the
-- memory contents and data out bus as a result of timing viols.
-- It uses the memory action table to perform various corruption
-- policies specified by the user.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN X01ArrayT;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) ;
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) ;
END Vital_Memory;
| gpl-2.0 |
loetlab-jena/das-atv | hdl/src/timing_gen.vhd | 1 | 1739 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timing_gen is
port
(
clk : in std_logic;
de : in std_logic;
vs : in std_logic;
hs : in std_logic;
sync : out std_logic;
burst : out std_logic
);
end entity;
architecture rtl of timing_gen is
signal de_d : std_logic;
signal vs_d : std_logic;
signal hs_d : std_logic;
signal hcnt : unsigned(10 downto 0);
signal vcnt : integer range 0 to 1023;
signal ss : std_logic; -- short sync
signal ns : std_logic; -- normal sync
signal bs : std_logic; -- burst sync
signal ls : std_logic; -- long sync
begin
counter : process
begin
wait until rising_edge(clk);
vs_d <= vs;
hs_d <= hs;
hcnt <= hcnt + 1;
if hs_d = '1' and hs = '0' then
hcnt <= (others => '0');
vcnt <= vcnt + 1;
end if;
if vs_d = '1' and vs = '0' and hs_d = '1' and hs = '0' then
vcnt <= 0;
end if;
end process;
sync_generator : process
begin
wait until rising_edge(clk);
if hcnt = 0 then
case vcnt is
when 0|1|2|313|314 =>
ls <= '1';
bs <= '0';
when 3|4|310|311|312|315|316|622|623|624 =>
ss <= '1';
bs <= '0';
when others =>
ns <= '1';
bs <= '1';
end case;
end if;
if hcnt = 863 then
case vcnt is
when 0|1|312|313|314 =>
ls <= '1';
when 2|3|4|310|311|315|316|622|623|624 =>
ss <= '1';
when others =>
end case;
end if;
if hcnt = 54 or hcnt = 918 then
ss <= '0';
end if;
if hcnt = 127 then
ns <= '0';
end if;
if hcnt = 810 or hcnt = 1674 then
ls <= '0';
end if;
if hcnt = 151 and bs = '1' then
burst <= '1';
end if;
if hcnt = 212 and bs = '1' then
burst <= '0';
end if;
end process;
sync <= ss or ns or ls;
end rtl;
| gpl-2.0 |
davewebb8211/ghdl | libraries/ieee/std_logic_1164.vhdl | 6 | 9546 | -- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/92 |
-- --------------------------------------------------------------------
PACKAGE std_logic_1164 IS
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;
-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; --V93
FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector; --V93
FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;--V93
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT;
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01 ( b : BIT ) RETURN X01;
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
END std_logic_1164;
| gpl-2.0 |
davewebb8211/ghdl | libraries/synopsys/std_logic_textio.vhdl | 9 | 17971 | ----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
| gpl-2.0 |
davewebb8211/ghdl | libraries/synopsys/std_logic_arith.vhdl | 5 | 70211 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in integer range 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in integer range 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-2.0 |
louis-bonicel/VHDL | Porte_AND/componant_1_tb.vhd | 2 | 1440 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:55:04 01/15/2015
-- Design Name:
-- Module Name: componant_1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_1_tb is
end componant_1_tb;
architecture Behavioral of componant_1_tb is
signal entree1, entree2, sortie1, sortie2 : std_logic;
component componant_1
port (e1,e2 : in std_logic;
s1,s2 : out std_logic);
end component;
begin
uut: componant_1 port map (e1 => entree1, e2 => entree2, s1 => sortie1, s2 => sortie2);
stimuli:process
begin
entree1<='0';
entree2<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end Behavioral;
| gpl-2.0 |
louis-bonicel/VHDL | Porte_AND/porteAND_tb.vhd | 2 | 1025 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:21 01/15/2015
-- Design Name:
-- Module Name: porteAND_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--Testbench
library ieee;
use ieee.std_logic_1164.all;
entity tb_porteAND is
end tb_porteAND;
architecture archi of tb_porteAND is
signal entree1, entree2, sortie : std_logic;
component porteAND
port (a,b: in std_logic;
s: out std_logic);
end component;
begin
uut: porteAND port map (a => entree1, b => entree2, s => sortie);
stimuli:process
begin
entree1<='0';
entree2<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end archi;
----------------------------------
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2251.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2251.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02251ent IS
END c07s02b06x00p01n01i02251ent;
ARCHITECTURE c07s02b06x00p01n01i02251arch OF c07s02b06x00p01n01i02251ent IS
BEGIN
TESTING: PROCESS
-- array types.
type WORD is array(0 to 31) of BIT;
-- access types.
type WORDPTR is access WORD;
variable WORDPTRV,
WORDPTR2V: WORDPTR;
variable k : integer;
BEGIN
k := WORDPTRV rem WORDPTR2V;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02251 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02251arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc243.vhd | 4 | 1722 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc243.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00243ent IS
END c03s01b02x00p04n01i00243ent;
ARCHITECTURE c03s01b02x00p04n01i00243arch OF c03s01b02x00p04n01i00243ent IS
type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
constant x: CLSI := Jim;
constant y: CLSI := Paul;
type People is range x to y;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00243 - Type mis-match in integer range constraint for type 'People'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00243arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd | 4 | 2292 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc921.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s03b00x00p16n01i00921ent_a is
generic ( x : integer; y : real );
end c10s03b00x00p16n01i00921ent_a;
architecture c10s03b00x00p16n01i00921arch_a of c10s03b00x00p16n01i00921ent_a is
begin
TESTING : PROCESS
BEGIN
assert NOT( real(x)=y )
report "***PASSED TEST: c10s03b00x00p16n01i00921"
severity NOTE;
assert ( real(x)=y )
report "***FAILED TEST: c10s03b00x00p16n01i00921 - Named associated formal generic can be made visible by selection."
severity ERROR;
wait;
END PROCESS TESTING;
end c10s03b00x00p16n01i00921arch_a;
ENTITY c10s03b00x00p16n01i00921ent IS
END c10s03b00x00p16n01i00921ent;
ARCHITECTURE c10s03b00x00p16n01i00921arch OF c10s03b00x00p16n01i00921ent IS
component d
end component;
BEGIN
instance : d;
END c10s03b00x00p16n01i00921arch;
configuration c10s03b00x00p16n01i00921cfg of c10s03b00x00p16n01i00921ent is
for c10s03b00x00p16n01i00921arch
for instance : d
use entity work.c10s03b00x00p16n01i00921ent_a(c10s03b00x00p16n01i00921arch_a) generic map ( x => 10, y => 10.0 );
end for;
end for;
end c10s03b00x00p16n01i00921cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1264.vhd | 4 | 1593 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1264.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n01i01264ent IS
END c08s02b00x00p06n01i01264ent;
ARCHITECTURE c08s02b00x00p06n01i01264arch OF c08s02b00x00p06n01i01264ent IS
BEGIN
TESTING: PROCESS
variable B : BIT;
BEGIN
assert B;
assert FALSE
report "***FAILED TEST: c08s02b00x00p06n01i01264 - Condition must be of Boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n01i01264arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd | 4 | 1766 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2739.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n01i02739ent IS
END c13s06b00x00p03n01i02739ent;
ARCHITECTURE c13s06b00x00p03n01i02739arch OF c13s06b00x00p03n01i02739ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(('A'/='a')and("ABCDE"/=string'("abcde")))
report "***PASSED TEST: c13s06b00x00p03n01i02739"
severity NOTE;
assert (('A'/='a')and("ABCDE"/=string'("abcde")))
report "***FAILED TEST: c13s06b00x00p03n01i02739 - Uppercase and lowercase letters should distinct within a string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n01i02739arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc383.vhd | 4 | 1892 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc383.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n01i00383ent IS
END c03s02b01x01p04n01i00383ent;
ARCHITECTURE c03s02b01x01p04n01i00383arch OF c03s02b01x01p04n01i00383ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_vector is array (positive range <>) of MVL;
function tristate (X:MVL_vector) return MVL;
subtype tribit is tristate MVL;
type tribit_vector is array (positive range <>) of tribit;
subtype byte is tribit_vector (7 downto 0); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p04n01i00383 - The index constraint values are not compatible with the corresponding subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n01i00383arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd | 4 | 5227 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1552.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n03i01552ent IS
END c08s09b00x00p10n03i01552ent;
ARCHITECTURE c08s09b00x00p10n03i01552arch OF c08s09b00x00p10n03i01552ent IS
BEGIN
TESTING: PROCESS
-- enumerated type.
type COLORS is (RED, GREEN, BLUE, ORANGE, PINK, GRAY, YELLOW);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable LAST_INT : INTEGER;
variable LAST_COLOR : COLORS;
variable k : integer := 0;
BEGIN
-- 1. Test ascending and descending integer discrete ranges.
EXECUTED_ONCE := FALSE;
LAST_INT := INTEGER'LOW + 1;
for I in (INTEGER'LOW+1) to (INTEGER'LOW + 10) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= (integer'low + 1)) then
k := 1;
end if;
assert (I = (INTEGER'LOW+1))
report "First value is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (integer'succ(last_int) /= I) then
k := 1;
end if;
assert (INTEGER'SUCC( LAST_INT ) = I)
report "Subsequent values are bad.";
LAST_INT := I;
end if;
end loop;
EXECUTED_ONCE := FALSE;
LAST_INT := INTEGER'HIGH - 1;
for I in (INTEGER'HIGH-1) downto (INTEGER'HIGH - 10) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= integer'high-1) then
k := 1;
end if;
assert (I = (INTEGER'HIGH-1))
report "First value, second loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (integer'pred(last_int) /= I) then
k := 1;
end if;
assert (INTEGER'PRED( LAST_INT ) = I)
report "Subsequent values, second loop, are bad.";
LAST_INT := I;
end if;
end loop;
-- 2. Test ascending and descending enumerated type ranges.
EXECUTED_ONCE := FALSE;
LAST_COLOR := COLORS'SUCC( COLORS'LOW );
for I in (COLORS'SUCC( COLORS'LOW )) to (COLORS'HIGH) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= colors'succ(colors'low)) then
k := 1;
end if;
assert (I = (COLORS'SUCC( COLORS'LOW )))
report "First value, third loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (colors'succ(last_color) /= I) then
k := 1;
end if;
assert (COLORS'SUCC( LAST_COLOR ) = I)
report "Subsequent values, third loop, are bad.";
LAST_COLOR := I;
end if;
end loop;
EXECUTED_ONCE := FALSE;
LAST_COLOR := COLORS'PRED( COLORS'HIGH );
for I in (COLORS'PRED( COLORS'HIGH )) downto (COLORS'LOW) loop
-- Verify that the first value is correct.
if (not(EXECUTED_ONCE)) then
if (I /= colors'pred(colors'high)) then
k := 1;
end if;
assert (I = (COLORS'PRED( COLORS'HIGH )))
report "First value, fourth loop, is bad.";
EXECUTED_ONCE := TRUE;
-- Otherwise, test that this value is to the right of the previous one.
else
if (colors'pred(last_color) /= I) then
k := 1;
end if;
assert (COLORS'PRED( LAST_COLOR ) = I)
report "Subsequent values, fourth loop, are bad.";
LAST_COLOR := I;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n03i01552"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n03i01552 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n03i01552arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd | 4 | 2146 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1080.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01080ent IS
END c06s05b00x00p01n02i01080ent;
ARCHITECTURE c06s05b00x00p01n02i01080arch OF c06s05b00x00p01n02i01080ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL result : boolean;
CONSTANT v_slice : bit_vector_8 := B"1010_1100";
procedure subprogram ( constant v : in bit_vector_4; signal resultt : out boolean ) is
begin
if (v = "1010") then
resultt <= true;
else
resultt <= false;
end if;
end ;
BEGIN
TESTING: PROCESS
BEGIN
subprogram ( v_slice ( 0 to 3 ), result );
wait for 11 ns;
assert NOT(result = true)
report "***PASSED TEST: c06s05b00x00p01n02i01080"
severity NOTE;
assert (result = true)
report "***FAILED TEST: c06s05b00x00p01n02i01080 - A slice of a constant should still be a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01080arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1312.vhd | 4 | 1843 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1312.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n03i01312ent IS
END c08s04b00x00p07n03i01312ent;
ARCHITECTURE c08s04b00x00p07n03i01312arch OF c08s04b00x00p07n03i01312ent IS
type BIT_VECTOR is array (natural range <>) of bit;
type INDEX is range 3 downto 0;
subtype BVI is BIT_VECTOR(INDEX);
signal S : BVI;
BEGIN
TESTING: PROCESS
variable k : Index;
BEGIN
(S(3), S(k), S(1), S(0)) <= BVI'('1', others => '0');
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n03i01312 - The expression in the element association is not locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n03i01312arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2822.vhd | 4 | 1608 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2822.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity OTHERS is
end OTHERS;
ENTITY c13s09b00x00p99n01i02822ent IS
END c13s09b00x00p99n01i02822ent;
ARCHITECTURE c13s09b00x00p99n01i02822arch OF c13s09b00x00p99n01i02822ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02822 - Reserved word OTHERS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02822arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd | 4 | 2495 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc183.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s04b00x00p04n02i00183pkg is
attribute a1 : integer;
attribute a2 : integer;
attribute a1 of c04s04b00x00p04n02i00183pkg : package is 3;
constant c1 : integer := c04s04b00x00p04n02i00183pkg'a1;
attribute a2 of c04s04b00x00p04n02i00183pkg : package is c1 * 2;
function fn1 return integer;
function fn2 return integer;
end c04s04b00x00p04n02i00183pkg;
package body c04s04b00x00p04n02i00183pkg is
constant t1 : integer := 3; --testgen'a1;
constant t2 : integer := 6; --testgen'a2;
function fn1 return integer is
begin
return t1;
end;
function fn2 return integer is
begin
return t2;
end;
end c04s04b00x00p04n02i00183pkg;
use work.c04s04b00x00p04n02i00183pkg.all;
ENTITY c04s04b00x00p04n02i00183ent IS
END c04s04b00x00p04n02i00183ent;
ARCHITECTURE c04s04b00x00p04n02i00183arch OF c04s04b00x00p04n02i00183ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )
report "***PASSED TEST: c04s04b00x00p04n02i00183"
severity NOTE;
assert ( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )
report "***FAILED TEST: c04s04b00x00p04n02i00183 - Package attribute test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p04n02i00183arch;
| gpl-2.0 |
peteut/ghdl | libraries/ieee2008/std_logic_textio.vhdl | 4 | 1988 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_TEXTIO package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages is provided as a replacement for non-standard
-- : implementations of the package provided by implementers of
-- : previous versions of this standard. The declarations that
-- : appeared in those non-standard implementations appear in the
-- : package STD_LOGIC_1164 in this standard.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
PACKAGE std_logic_textio IS
-- This package is empty - see notes above.
END PACKAGE std_logic_textio;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd | 4 | 1898 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n02i01216ent IS
END c08s01b00x00p26n02i01216ent;
ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
BEGIN
-- First, wait for 1fs;
wait for 1 fs;
assert FALSE
report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
severity NOTE;
-- Then, wait until the end of time.
wait;
assert (FALSE)
report "Should never have executed this statement."
severity FAILURE;
END PROCESS TESTING;
END c08s01b00x00p26n02i01216arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd | 4 | 2542 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc634.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00634ent IS
END c03s04b01x00p01n01i00634ent;
ARCHITECTURE c03s04b01x00p01n01i00634arch OF c03s04b01x00p01n01i00634ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type primary_memory_module_file is file of primary_memory_module;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
BEGIN
TESTING: PROCESS
file filein : primary_memory_module_file open write_mode is "iofile.43";
BEGIN
for i in 1 to 100 loop
write(filein, C45);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00634 - The output file will be verified by test s010288.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00634arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd | 4 | 3430 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc707.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:44 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:46 1996 --
-- **************************** --
package c03s04b01x00p23n01i00707pkg is
type Waveform_element is record
Value: Bit;
At: Time;
end record;
type Signal_history is file of Waveform_element;
end c03s04b01x00p23n01i00707pkg;
use work.c03s04b01x00p23n01i00707pkg.all;
ENTITY c03s04b01x00p23n01i00707ent IS
END c03s04b01x00p23n01i00707ent;
ARCHITECTURE c03s04b01x00p23n01i00707arch OF c03s04b01x00p23n01i00707ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to read.
file FILEV : Signal_history open read_mode is "iofile.58";
-- Declare a variable into which we will read.
constant con : Waveform_element := ('1',10 ns);
variable VAR : Waveform_element;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00707"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00707 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00707arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2651.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2651.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02651ent IS
END c13s03b01x00p02n01i02651ent;
ARCHITECTURE c13s03b01x00p02n01i02651arch OF c13s03b01x00p02n01i02651ent IS
BEGIN
TESTING: PROCESS
variable +k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02651 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02651arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd | 4 | 1816 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1982.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n03i01982ent IS
END c07s02b02x00p01n03i01982ent;
ARCHITECTURE c07s02b02x00p01n03i01982arch OF c07s02b02x00p01n03i01982ent IS
BEGIN
TESTING: PROCESS
variable i, j, k, l, m, n, o, p : integer := 1;
BEGIN
if (m=n) then -- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p01n03i01982"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p01n03i01982 - The result type of each relational operator is the predefined type BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n03i01982arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd | 4 | 1925 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1485.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01485ent IS
END c08s08b00x00p04n03i01485ent;
ARCHITECTURE c08s08b00x00p04n03i01485arch OF c08s08b00x00p04n03i01485ent IS
BEGIN
TESTING: PROCESS
variable m : severity_level := NOTE;
variable k : integer := 0;
BEGIN
case m is
when severity_level'low | severity_level'high => k := 5;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01485"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01485 - Each choice in a case statement alternative must be of the same type as the expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01485arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd | 4 | 2036 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system is
port ( terminal vp, vm : electrical;
terminal px : electrical_vector(1 to 3) );
end entity motor_system;
----------------------------------------------------------------
architecture state_space of motor_system is
quantity v_in across vp to vm;
quantity x across i_x through px to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
type real_matrix is array (1 to 3, 1 to 3) of real;
constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ),
( -Ke/Te, -1.0/Te, 0.0 ),
( 0.0, Km/Tm, -1.0/Tm ) );
begin
state_eqn : procedural is
variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0);
begin
for i in 1 to 3 loop
for j in 1 to 3 loop
sum(i) := sum(i) + c(i, j) * x(j);
end loop;
end loop;
x(1)'dot := sum(1);
x(2)'dot := sum(2) + (Ke/Te)*v_in;
x(3)'dot := sum(3);
end procedural state_eqn;
end architecture state_space;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd | 4 | 1793 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07a is
end entity inline_07a;
----------------------------------------------------------------
architecture test of inline_07a is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : real_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd | 4 | 2240 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity analog_output_interface is
port ( signal wr : in std_ulogic;
signal data : std_ulogic_vector(7 downto 0);
terminal analog_out : electrical );
end entity analog_output_interface;
----------------
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity analog_interface_dac is
port ( signal d_in : std_ulogic_vector(7 downto 0);
terminal output : electrical;
terminal plus_supply, minus_supply : electrical );
end entity analog_interface_dac;
architecture macroblock of analog_interface_dac is
begin
end architecture macroblock;
-- end not in book
architecture structural of analog_output_interface is
-- This architecture implements the interface as a register connected to a DAC.
-- NOTE: it uses the analog power supply terminals from clock_power_pkg
-- to supply the DAC.
signal register_out : -- . . .;
-- not in book
std_ulogic_vector(7 downto 0);
-- end not in book
begin
-- ...
dac : entity work.analog_interface_dac(macroblock)
port map ( d_in => register_out, output => analog_out,
plus_supply => work.clock_power_pkg.analog_plus_supply,
minus_supply => work.clock_power_pkg.analog_ground );
end architecture structural;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd | 4 | 2104 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_19a is
end entity inline_19a;
architecture test of inline_19a is
signal reset, trigger_n : std_ulogic;
terminal rc_ext : electrical;
quantity v_rc_ext across rc_ext;
constant half_vdd : voltage := 2.5;
begin
block_1 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
-- ...
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
break;
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
break;
end if;
-- ...
-- end code from book
wait;
end process;
end block block_1;
block_2 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1' after 20 ns;
break;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1';
break;
-- end code from book
wait;
end process;
end block block_3;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd | 4 | 6566 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1366.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01366ent IS
END c08s05b00x00p03n01i01366ent;
ARCHITECTURE c08s05b00x00p03n01i01366arch OF c08s05b00x00p03n01i01366ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01366"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01366 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01366arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd | 4 | 916 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.int_types.all;
entity small_adder is
port ( a, b : in small_int; s : out small_int );
end entity small_adder;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd | 4 | 1954 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc534.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p04n02i00534ent IS
END c03s03b00x00p04n02i00534ent;
ARCHITECTURE c03s03b00x00p04n02i00534arch OF c03s03b00x00p04n02i00534ent IS
BEGIN
TESTING: PROCESS
-- The access type we will use.
type ACT is access BIT;
-- Declare a variable of this type. Initialize it.
variable VAR : ACT := NEW BIT'( '0' );
BEGIN
-- Attempt to assign a value to it.
VAR.all := '1';
assert NOT( VAR.all = '1' )
report "***PASSED TEST: c03s03b00x00p04n02i00534"
severity NOTE;
assert ( VAR.all = '1' )
report "***FAILED TEST: c03s03b00x00p04n02i00534 - Object designated by an access value is always an object of class variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p04n02i00534arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd | 4 | 2346 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1091.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s05b00x00p02n01i01091pkg is
type FIVE is range 1 to 5;
type ABASE is array (FIVE range <>) of BOOLEAN;
subtype A1 is ABASE(FIVE);
attribute AT1 : A1;
function fat1(i:integer) return a1;
end c06s05b00x00p02n01i01091pkg;
package body c06s05b00x00p02n01i01091pkg is
function fat1(i:integer) return a1 is
variable va1 : a1;
begin
return Va1;
end fat1;
end c06s05b00x00p02n01i01091pkg;
use work.c06s05b00x00p02n01i01091pkg.all;
ENTITY c06s05b00x00p02n01i01091ent IS
port (PT: BOOLEAN) ;
attribute AT1 of PT : signal is fat1(8);
END c06s05b00x00p02n01i01091ent;
ARCHITECTURE c06s05b00x00p02n01i01091arch OF c06s05b00x00p02n01i01091ent IS
BEGIN
TESTING: PROCESS
variable V1 : A1;
BEGIN
V1(2 to 4) := PT'AT1(2 to 4);
assert NOT(V1(2 to 4)=(false,false,false))
report "***PASSED TEST: c06s05b00x00p02n01i01091"
severity NOTE;
assert (V1(2 to 4)=(false,false,false))
report "***FAILED TEST: c06s05b00x00p02n01i01091 - Slice name consists of a single discrete range enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p02n01i01091arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd | 4 | 2087 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2105.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02105ent IS
END c07s02b04x00p20n01i02105ent;
ARCHITECTURE c07s02b04x00p20n01i02105arch OF c07s02b04x00p20n01i02105ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_4 is positive_v (1 to 4);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING : PROCESS
variable result : positive_4;
variable l_operand : positive_null;
variable r_operand : positive_4 := ( 1 , 89 , 1 , 89 );
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT(result = ( 1 , 89 , 1 , 89 ))
report "***PASSED TEST: c07s02b04x00p20n01i02105"
severity NOTE;
assert (result = ( 1 , 89 , 1 , 89 ))
report "***FAILED TEST: c07s02b04x00p20n01i02105 - Concatenation of null and POSITIVE arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02105arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2811.vhd | 4 | 1758 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2811.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity LOOP is
end LOOP;
ENTITY c13s09b00x00p99n01i02811ent IS
END c13s09b00x00p99n01i02811ent;
ARCHITECTURE c13s09b00x00p99n01i02811arch OF c13s09b00x00p99n01i02811ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02811 - Reserved word LOOP can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02811arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd | 4 | 1617 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity limiter is
generic ( limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8 ); -- lower limit
port ( quantity input : in real;
quantity output : out real);
end entity limiter;
----------------------------------------------------------------
architecture simple of limiter is
constant slope : real := 1.0e-4;
begin
if input > limit_high use -- upper limit exceeded, so limit input signal
output == limit_high + slope*(input - limit_high);
elsif input < limit_low use -- lower limit exceeded, so limit input signal
output == limit_low + slope*(input - limit_low);
else -- no limit exceeded, so pass input signal as is
output == input;
end use;
break on input'above(limit_high), input'above(limit_low);
end architecture simple;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd | 4 | 5491 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture verifier of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a_behav : dlx_address;
signal d_behav : dlx_word;
signal halt_behav : std_logic;
signal width_behav : dlx_mem_width;
signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
signal a_rtl : dlx_address;
signal d_rtl : dlx_word;
signal halt_rtl : std_logic;
signal width_rtl : dlx_mem_width;
signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
signal ready_mem : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
burst => open,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_behav : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
ifetch => ifetch_behav,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_rtl : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
a => a_rtl, d => d_rtl,
width => width_rtl, write_enable => write_enable_rtl,
ifetch => ifetch_rtl,
mem_enable => mem_enable_rtl, ready => ready_mem );
verification_section : block is
begin
fwd_data_from_mem_to_rtl :
d_rtl <= d_behav when mem_enable_rtl = '1'
and write_enable_rtl = '0' else
disabled_dlx_word;
monitor : process
variable write_command_behav : boolean;
variable write_command_rtl : boolean;
begin
monitor_loop : loop
-- wait for a command, valid on leading edge of phi2
wait until rising_edge(phi2)
and mem_enable_behav = '1' and mem_enable_rtl = '1';
--
-- capture the command information
write_command_behav := write_enable_behav = '1';
write_command_rtl := write_enable_rtl = '1';
assert a_behav = a_rtl
report "addresses differ";
assert write_enable_behav = write_enable_rtl
report "write enable states differ";
assert ifetch_behav = ifetch_rtl
report "instruction fetch states differ";
assert width_behav = width_rtl
report "widths differ";
if write_command_behav and write_command_rtl then
assert d_behav = d_rtl
report "write data differs";
end if;
--
-- wait for the response from memory
ready_loop : loop
wait until falling_edge(phi2);
exit monitor_loop when reset = '1';
exit ready_loop when ready_mem = '1';
end loop ready_loop;
end loop monitor_loop;
--
-- get here when reset is asserted
wait until reset = '0';
--
-- process monitor now starts again from beginning
end process monitor;
end block verification_section;
end architecture verifier;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug22868/fails1.vhdl | 3 | 436 | library ieee;
use ieee.std_logic_1164.all;
entity fails1 is
generic (
w : integer := 8
);
port(
x : in std_logic;
y : out std_logic_vector(7 downto 0);
z : out std_logic
);
end entity;
architecture a of fails1 is
component subcomponent is
port(
x : in std_logic;
y : out std_logic_vector(8 downto 0)
);
end component;
begin
s : subcomponent
port map(
x => x,
y(w downto 1) => y,
y(0) => z
);
end a;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd | 4 | 3254 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd | 4 | 2796 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_07 is
end entity ch_05_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_05_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_05_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_05_3_c;
----------------
process_05_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_05_3_d;
----------------
process_05_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_05_3_e;
----------------
stimulus_05_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_05_3_c_d;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd | 4 | 1556 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer;
----------------------------------------------------------------
architecture weighted of mixer is
quantity v_in across inputs;
quantity v_out across i_out through output;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
apply_weights : procedural is
variable sum : real := 0.0;
begin
for index in v_in'range loop
sum := sum + v_in(index) * gains(index);
end loop;
v_out := sum;
end procedural apply_weights;
end architecture weighted;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd | 4 | 1842 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type integer_file is file of integer;
file lookup_table_file : integer_file is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
type file_open_kind is (read_mode, write_mode, append_mode);
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure read ( file f : file_type; value : out element_type );
function endfile ( file f : file_type ) return boolean;
-- end of code from book
procedure read ( file f : file_type; value : out element_type ) is
begin
end;
function endfile ( file f : file_type ) return boolean is
begin
end;
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd | 4 | 1257 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd | 4 | 2023 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc628.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00628ent IS
END c03s04b01x00p01n01i00628ent;
ARCHITECTURE c03s04b01x00p01n01i00628arch OF c03s04b01x00p01n01i00628ent IS
type byte is array(0 to 7) of bit;
type byte_file is file of byte;
constant C38 : byte := (others => '1');
BEGIN
TESTING: PROCESS
file filein : byte_file open write_mode is "iofile.40";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00628 - The output file will be verified by test s010282.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00628arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd | 4 | 1800 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc877.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b02x00p02n01i00877ent IS
END c01s03b02x00p02n01i00877ent;
ARCHITECTURE c01s03b02x00p02n01i00877arch OF c01s03b02x00p02n01i00877ent IS
BEGIN
BB : block
component LOCAL
end component;
begin
CIS : LOCAL;
assert FALSE
report "***PASSED TEST: c01s03b02x00p02n01i00877"
severity NOTE;
end block BB;
END c01s03b02x00p02n01i00877arch;
configuration c01s03b02x00p02n01i00877cfg of c01s03b02x00p02n01i00877ent is
for c01s03b02x00p02n01i00877arch
for BB
for CIS : LOCAL -- Success_here
end for;
end for;
end for ;
end c01s03b02x00p02n01i00877cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/perf02/ilb_table.vhd | 3 | 2190 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity ilb_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end ilb_table;
architecture augh of ilb_table is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000100000000000", "00000000000000000000100000101101", "00000000000000000000100001011011", "00000000000000000000100010001010", "00000000000000000000100010111001", "00000000000000000000100011101010", "00000000000000000000100100011100", "00000000000000000000100101001111", "00000000000000000000100110000011", "00000000000000000000100110111001", "00000000000000000000100111101111", "00000000000000000000101000100111", "00000000000000000000101001100000", "00000000000000000000101010011010", "00000000000000000000101011010110", "00000000000000000000101100010010", "00000000000000000000101101010000", "00000000000000000000101110010000", "00000000000000000000101111010001", "00000000000000000000110000010011", "00000000000000000000110001010110", "00000000000000000000110010011100", "00000000000000000000110011100010", "00000000000000000000110100101011", "00000000000000000000110101110100", "00000000000000000000110111000000", "00000000000000000000111000001101", "00000000000000000000111001011100", "00000000000000000000111010101100", "00000000000000000000111011111110", "00000000000000000000111101010010", "00000000000000000000111110101000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
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