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cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_phy_alt_mem_phy_seq.vhd | 1 | 648425 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ram_controller_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ram_controller_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ram_controller_phy_alt_mem_phy_record_pkg;
--
package body ram_controller_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ram_controller_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ram_controller_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ram_controller_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ram_controller_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ram_controller_phy_alt_mem_phy_iram_addr_pkg;
--
package body ram_controller_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ram_controller_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
package ram_controller_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ram_controller_phy_alt_mem_phy_regs_pkg;
--
package body ram_controller_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ram_controller_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ram_controller_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ram_controller_phy_alt_mem_phy_iram_ram;
--
entity ram_controller_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ram_controller_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ram_controller_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ram_controller_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ram_controller_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ram_controller_phy_alt_mem_phy_admin;
--
use work.ram_controller_phy_alt_mem_phy_mmi;
--
use work.ram_controller_phy_alt_mem_phy_iram;
--
use work.ram_controller_phy_alt_mem_phy_dgrb;
--
use work.ram_controller_phy_alt_mem_phy_dgwb;
--
use work.ram_controller_phy_alt_mem_phy_ctrl;
--
architecture struct of ram_controller_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ram_controller_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ram_controller_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ram_controller_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ram_controller_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ram_controller_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ram_controller_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-2.0 |
samvartaka/simon_vhdl | MIXED_ROUND_PIPELINING/tb_neg_reg_32.vhd | 3 | 1825 | -- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal data_in : std_logic_vector(31 downto 0) := (others => '0'); -- input
--Outputs
signal data_out : std_logic_vector(31 downto 0); -- output
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: neg_reg_32 PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
data_out => data_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
rst <= '1';
wait for clk_period;
assert data_out = X"00000000"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
rst <= '0';
data_in <= X"CAFECAFE";
wait for clk_period;
assert data_out = X"CAFECAFE"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
| gpl-2.0 |
twasiluk/hdmilight | fpga/ws2811Driver.vhd | 2 | 3565 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ws2811Driver is
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (23 downto 0);
busy : out STD_LOGIC := '0';
dataout : out STD_LOGIC);
end ws2811Driver;
architecture Behavioral of ws2811Driver is
signal bitcount : std_logic_vector(4 downto 0);
signal subbitcount : std_logic_vector(4 downto 0);
--signal count : std_logic_vector(9 downto 0) := "1011111000";
signal countEnable : std_logic;
signal shiftData : std_logic_vector(23 downto 0);
signal shiftEnable : std_logic;
signal shiftOutput : std_logic;
signal nextOutput : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
bitcount <= (others => '0');
subbitcount <= (others => '0');
elsif(countEnable = '1') then
subbitcount <= std_logic_vector(unsigned(subbitcount) + 1);
if(subbitcount = "10011") then
bitcount <= std_logic_vector(unsigned(bitcount) + 1);
subbitcount <= (others => '0');
end if;
end if;
end if;
end process;
--process(clk)
--begin
-- if(rising_edge(clk)) then
-- if(load = '1') then
-- count <= (others => '0');
-- elsif(countEnable = '1') then
-- count <= std_logic_vector(unsigned(count) + 1);
-- end if;
-- end if;
--end process;
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
shiftData <= datain;
elsif(shiftEnable = '1') then
shiftData <= shiftData(22 downto 0) & "0";
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
dataout <= nextOutput;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
busy <= '1';
elsif (bitcount = "10111" and subbitcount = "10001") then
busy <= '0';
end if;
end if;
end process;
-- freeze counter when it reaches 24 bytes (24*4 clocks)
countEnable <= '0' when bitcount = "10111" and subbitcount = "10011" else '1';
-- enable shift every 4 clocks
shiftEnable <= '1' when subbitcount = "10011" else '0';
shiftOutput <= shiftData(23);
-- over a 4 clock period:
-- for a 1 output 1 1 1 0
-- for a 0 output 1 0 0 0
nextOutput <= '1' when subbitcount(4 downto 2) = "000" else
'0' when subbitcount(4 downto 2) = "100" else
shiftOutput;
end Behavioral;
| gpl-2.0 |
sksavant/geda-gaf | gnetlist/tests/gnetlistrc.vhdl | 8 | 205 | ;
; This file is really a gnetlistrc file.
; It is renamed to gnetlistrc before any vhdl backend test is run.
;
; The path is hardcoded for now.
;
(component-library "${HOME}/geda/share/gEDA/sym/vhdl")
| gpl-2.0 |
quartushaters/project | M1/Part 1/LCD_Display.vhd | 1 | 9000 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 8);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use X"20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location X"0" & 4-bit field from Hex_Display_Data
-- state machine sees X"0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of X"FE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is X"41"
-- *see LCD Controller's Datasheet for other graphics characters available
--
PORT(reset, clk_48Mhz : IN STD_LOGIC;
Hex_Display_Data : IN STD_LOGIC_VECTOR((Num_Hex_Digits*4)-1 DOWNTO 0);
Display_Data : IN STD_LOGIC_VECTOR(((Num_Hex_Digits*4)*4)-1 DOWNTO 0);
LCD_RS, LCD_EN : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY LCD_Display;
ARCHITECTURE a OF LCD_Display IS
TYPE character_string IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, Print_String,
LINE2, RETURN_HOME, DROP_LCD_EN, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL LCD_display_string : character_string;
-- Enter new ASCII hex data above for LCD Display
SIGNAL DATA_BUS_VALUE, Next_Char: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CHAR_COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK_400HZ_Enable,LCD_RW_INT : STD_LOGIC;
SIGNAL Line1_chars, Line2_chars: STD_LOGIC_VECTOR(127 DOWNTO 0);
BEGIN
LCD_display_string <= (
-- ASCII hex values for LCD Display
-- Enter Live Hex Data Values from hardware here
-- LCD DISPLAYS THE FOLLOWING:
------------------------------
--| Count=XX |
--| Data =XXXXXXXX |
------------------------------
-- Line 1
X"43",X"6F",X"75",X"6E",X"74",X"3D",
X"0" & Hex_Display_Data(7 DOWNTO 4),X"0" & Hex_Display_Data(3 DOWNTO 0),
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 2
X"44",X"41",X"54",X"41",X"20",X"3D",
X"0" & Display_Data(31 DOWNTO 28),
X"0" & Display_Data(27 DOWNTO 24),
X"0" & Display_Data(23 DOWNTO 20),
X"0" & Display_Data(19 DOWNTO 16),
X"0" & Display_Data(15 DOWNTO 12),
X"0" & Display_Data(11 DOWNTO 8),
X"0" & Display_Data(7 DOWNTO 4),
X"0" & Display_Data(3 DOWNTO 0),
X"20",X"20");
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW_INT = '0' ELSE "ZZZZZZZZ";
-- get next character in display string
Next_Char <= LCD_display_string(CONV_INTEGER(CHAR_COUNT));
LCD_RW <= LCD_RW_INT;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0EA60" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
CLK_400HZ_Enable <= '0';
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (CLK_48MHZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '1';
ELSIF CLK_48MHZ'EVENT AND CLK_48MHZ = '1' THEN
-- State Machine to send commands and data to LCD DISPLAY
IF CLK_400HZ_Enable = '1' THEN
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET2;
CHAR_COUNT <= "00000";
WHEN RESET2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET3;
WHEN RESET3 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"08";
state <= DROP_LCD_EN;
next_command <= DISPLAY_CLEAR;
-- Clear Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"01";
state <= DROP_LCD_EN;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"0C";
state <= DROP_LCD_EN;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"06";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Write ASCII hex character in first LCD character location
WHEN Print_String =>
state <= DROP_LCD_EN;
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW_INT <= '0';
-- ASCII character to output
IF Next_Char(7 DOWNTO 4) /= X"0" THEN
DATA_BUS_VALUE <= Next_Char;
ELSE
-- Convert 4-bit value to an ASCII hex digit
IF Next_Char(3 DOWNTO 0) >9 THEN
-- ASCII A...F
DATA_BUS_VALUE <= X"4" & (Next_Char(3 DOWNTO 0)-9);
ELSE
-- ASCII 0...9
DATA_BUS_VALUE <= X"3" & Next_Char(3 DOWNTO 0);
END IF;
END IF;
state <= DROP_LCD_EN;
-- Loop to send out 32 characters to LCD Display (16 by 2 lines)
IF (CHAR_COUNT < 31) AND (Next_Char /= X"FE") THEN
CHAR_COUNT <= CHAR_COUNT +1;
ELSE
CHAR_COUNT <= "00000";
END IF;
-- Jump to second line?
IF CHAR_COUNT = 15 THEN next_command <= line2;
-- Return to first line?
ELSIF (CHAR_COUNT = 31) OR (Next_Char = X"FE") THEN
next_command <= return_home;
ELSE next_command <= Print_String; END IF;
-- Set write address to line 2 character 1
WHEN LINE2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"C0";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Return write address to first character postion on line 1
WHEN RETURN_HOME =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"80";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- The next three states occur at the end of each command or data transfer to the LCD
-- Drop LCD E line - falling edge loads inst/data to LCD controller
WHEN DROP_LCD_EN =>
LCD_EN <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
| gpl-2.0 |
samvartaka/simon_vhdl | ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/round_f.vhd | 4 | 1054 |
-- SIMON 64/128
-- feistel round function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end round_f;
architecture Behavioral of round_f is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
-- shifts over left half
op_1_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 8));
-- xors/ands over subkey and right half
v_out <= ((op_1_s and op_8_s) xor op_2_s xor v_in(31 downto 0) xor v_k) & v_in(63 downto 32);
end Behavioral; | gpl-2.0 |
samvartaka/simon_vhdl | ITERATIVE/ITERATIVE_INTEGRATED_RAMROUTE/round_f.vhd | 4 | 1054 |
-- SIMON 64/128
-- feistel round function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end round_f;
architecture Behavioral of round_f is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
-- shifts over left half
op_1_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(v_in(63 downto 32)), 8));
-- xors/ands over subkey and right half
v_out <= ((op_1_s and op_8_s) xor op_2_s xor v_in(31 downto 0) xor v_k) & v_in(63 downto 32);
end Behavioral; | gpl-2.0 |
datalogics-kam/ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_rx/simulation/fifo_rx_pkg.vhd | 2 | 11257 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fifo_rx_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fifo_rx_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_rx_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_rx_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fifo_rx_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_rx_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_rx_exdes IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(9-1 DOWNTO 0);
DOUT : OUT std_logic_vector(9-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fifo_rx_pkg;
PACKAGE BODY fifo_rx_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fifo_rx_pkg;
| gpl-2.0 |
pf3gnuchains/urjtag | extra/fjmem/fjmem_pack-p.vhd | 1 | 3039 | -------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
--
-- Written by Arnim Laeuger <[email protected]>, 2008.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.fjmem_config_pack.all;
package fjmem_pack is
-----------------------------------------------------------------------------
-- Constants that build the shift register
--
constant shift_instr_pos_c : natural := 0;
constant shift_instr_width_c : natural := 3;
constant shift_ack_pos_c : natural := shift_instr_pos_c + shift_instr_width_c;
constant shift_ack_width_c : natural := 1;
constant shift_block_pos_c : natural := shift_ack_pos_c + shift_ack_width_c;
constant shift_block_width_c : natural := num_block_field_c;
constant shift_addr_pos_c : natural := shift_block_pos_c + shift_block_width_c;
constant shift_addr_width_c : natural := max_addr_width_c;
constant shift_data_pos_c : natural := shift_addr_pos_c + shift_addr_width_c;
constant shift_data_width_c : natural := max_data_width_c;
constant shift_width_c : natural := shift_data_pos_c + shift_data_width_c;
--
subtype instr_range_t is natural range shift_instr_width_c-1 downto 0;
subtype block_range_t is natural range shift_block_pos_c+shift_block_width_c-1 downto shift_block_pos_c;
subtype addr_range_t is natural range shift_addr_pos_c+shift_addr_width_c-1 downto shift_addr_pos_c;
subtype data_range_t is natural range shift_data_pos_c+shift_data_width_c-1 downto shift_data_pos_c;
subtype shift_range_t is natural range shift_width_c-1 downto 0;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Instruction constants
--
constant instr_idle_c : std_logic_vector(instr_range_t) := "000";
constant instr_detect_c : std_logic_vector(instr_range_t) := "111";
constant instr_query_c : std_logic_vector(instr_range_t) := "110";
constant instr_read_c : std_logic_vector(instr_range_t) := "001";
constant instr_write_c : std_logic_vector(instr_range_t) := "010";
--
-----------------------------------------------------------------------------
end;
| gpl-2.0 |
xerpi/3ds-arm9-linux | toolchain/ndstool/source/passme.vhd | 3 | 3058 | -- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO : inout std_logic_vector(7 downto 0);
DSCART_CLK : out std_logic;
DSCART_ROMCS : out std_logic;
DSCART_RESET : out std_logic;
DSCART_EEPCS : out std_logic;
DSCART_IRQ : in std_logic;
DSCART_IO : inout std_logic_vector(7 downto 0);
LED0 : out std_logic
);
end entity;
architecture rtl of passme is
-- removes Xilinx mapping errors
attribute CLOCK_BUFFER : string;
attribute CLOCK_BUFFER of DSSLOT_CLK: signal is "ibuf";
attribute CLOCK_BUFFER of DSCART_CLK: signal is "obuf";
signal is_command : boolean;
signal cmddata_cnt : natural range 0 to 511; -- 8 + 504
signal patched_data : std_logic_vector(7 downto 0);
signal patch_en : boolean;
begin
-- direct passthrough
DSCART_CLK <= DSSLOT_CLK;
DSCART_ROMCS <= DSSLOT_ROMCS;
DSCART_RESET <= DSSLOT_RESET;
DSSLOT_IRQ <= DSCART_IRQ;
DSCART_EEPCS <= DSSLOT_EEPCS;
-- activity LED
LED0 <= not DSSLOT_ROMCS;
-- patch
process (cmddata_cnt)
begin
case (cmddata_cnt - 8) is
--! ALL PATCHES ARE TO BE GENERATED HERE
when others => patched_data <= DSCART_IO;
end case;
end process;
-- dataswitcher
process (DSSLOT_RESET, DSSLOT_ROMCS, DSSLOT_EEPCS, DSSLOT_IO, DSCART_IO, patched_data)
begin
DSSLOT_IO <= (others => 'Z'); -- default is high impedance
DSCART_IO <= (others => 'Z'); -- default is high impedance
if (DSSLOT_RESET='1') then -- if not reset
if (DSSLOT_ROMCS='0') then -- ROM is selected
if (is_command) then -- is command byte
DSCART_IO <= DSSLOT_IO; -- from DS to cartridge
else -- is data byte
if (patch_en) then -- patch enabled
DSSLOT_IO <= patched_data;
else
DSSLOT_IO <= DSCART_IO;
end if;
end if;
elsif (DSSLOT_EEPCS='0') then -- EEPROM is selected
DSCART_IO(7) <= DSSLOT_IO(7); -- pass serial data
DSSLOT_IO(6) <= DSCART_IO(6); -- pass serial data in opposite direction
end if;
end if;
end process;
-- patch_en
process (DSSLOT_RESET, DSSLOT_CLK)
begin
if (DSSLOT_RESET='0') then
patch_en <= true; -- patch header
elsif (rising_edge(DSSLOT_CLK)) then
if (is_command) then
if (DSCART_IO(5) = '1') then -- detect 3C command, assume other command bytes are 00
patch_en <= false; -- do not patch other data
end if;
end if;
end if;
end process;
-- cmddata_cnt, is_command
process (DSSLOT_ROMCS, DSSLOT_CLK)
begin
if (DSSLOT_ROMCS='1') then
cmddata_cnt <= 0; -- new transfer
is_command <= true; -- start with command
elsif (rising_edge(DSSLOT_CLK)) then
if (cmddata_cnt mod 8 = 7) then
is_command <= false; -- next byte is data
end if;
cmddata_cnt <= cmddata_cnt + 1; -- next byte
end if;
end process;
end architecture;
| gpl-2.0 |
gigglesninja/digital-system-design | lab9_uart_rx/ipcore_dir/fifo_rx/simulation/fifo_rx_dgen.vhd | 1 | 4520 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
ENTITY fifo_rx_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_rx_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_rx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
pragmaware/ctags | Units/parser-vhdl.r/vhdl-type.d/input.vhd | 7 | 9685 | --
-- Taken from rtl/misclib/types_misc.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! @brief Declaration of components visible on SoC top level.
package types_misc is
--! @defgroup irq_id_group AXI4 interrupt generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Unique indentificator of the interrupt pin also used
--! as an index in the interrupts bus.
--! @{
--! Zero interrupt index must be unused.
constant CFG_IRQ_UNUSED : integer := 0;
--! UART_A interrupt pin.
constant CFG_IRQ_UART1 : integer := 1;
--! Ethernet MAC interrupt pin.
constant CFG_IRQ_ETHMAC : integer := 2;
--! GP Timers interrupt pin
constant CFG_IRQ_GPTIMERS : integer := 3;
--! GNSS Engine IRQ pin that generates 1 msec pulses.
constant CFG_IRQ_GNSSENGINE : integer := 4;
--! Total number of used interrupts in a system
constant CFG_IRQ_TOTAL : integer := 5;
--! @}
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component axi4_sram is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024
type spi_in_type is record
SDI : std_logic;
end record;
type spi_out_type is record
SDO : std_logic;
SCK : std_logic;
nCS : std_logic;
nWP : std_logic;
nHOLD : std_logic;
RESET : std_logic;
end record;
constant spi_out_none : spi_out_type := (
'0', '0', '1', '1', '1', '0'
);
component axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end component;
--! @brief AXI4 GPIO controller
component axi4_gpio is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
width : integer := 12
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
i_gpio : in std_logic_vector(width-1 downto 0);
o_gpio : out std_logic_vector(width-1 downto 0);
o_gpio_dir : out std_logic_vector(width-1 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component axi4_uart is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic);
end component;
--! Test Access Point via UART (debug access)
component uart_tap is
port (
nrst : in std_logic;
clk : in std_logic;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
-- JTAG TAP
component tap_jtag is
generic (
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic; -- in:
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component axi4_pnp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0;
hw_id : std_logic_vector(31 downto 0) := X"20170101"
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in bus0_xmst_cfg_vector;
slvcfg : in bus0_xslv_cfg_vector;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
-- OTP Timing control
i_otp_busy : in std_logic;
o_otp_cfg_rsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wactive : out std_logic_vector(31 downto 0);
o_otp_cfg_whold : out std_logic_vector(3 downto 0)
);
end component;
component axi4_otp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#ffffe#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_otp_we : out std_ulogic;
o_otp_re : out std_ulogic;
o_otp_addr : out std_logic_vector(11 downto 0);
o_otp_wdata : out std_logic_vector(15 downto 0);
i_otp_rdata : in std_logic_vector(15 downto 0);
i_cfg_rsetup : in std_logic_vector(3 downto 0);
i_cfg_wadrsetup : in std_logic_vector(3 downto 0);
i_cfg_wactive : in std_logic_vector(31 downto 0);
i_cfg_whold : in std_logic_vector(3 downto 0);
o_busy : out std_logic
);
end component;
end; -- package declaration
| gpl-2.0 |
gigglesninja/digital-system-design | lab9_uart_rx/ipcore_dir/fifo_rx/simulation/fifo_rx_rng.vhd | 2 | 3884 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo_rx_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo_rx_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
gigglesninja/digital-system-design | lab8_uart_tx/ipcore_dir/fifo/example_design/fifo_exdes.vhd | 1 | 4767 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_exdes;
architecture xilinx of fifo_exdes is
signal clk_i : std_logic;
component fifo is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : fifo
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_tx/simulation/fifo_tx_tb.vhd | 1 | 5704 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tx_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_tx_pkg.ALL;
ENTITY fifo_tx_tb IS
END ENTITY;
ARCHITECTURE fifo_tx_arch OF fifo_tx_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo_tx_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo_tx_synth
fifo_tx_synth_inst:fifo_tx_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 27
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
pf3gnuchains/urjtag | extra/fjmem/fjmem_config_pack_spartan3-p.vhd | 1 | 3042 | -------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
--
-- Written by Arnim Laeuger <[email protected]>, 2008.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package fjmem_config_pack is
-----------------------------------------------------------------------------
-- Specify the active levels of trst_i, shift_i and res_i
--
constant trst_act_level_c : std_logic := '1';
constant shift_act_level_c : std_logic := '1';
constant res_act_level_c : std_logic := '1';
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Adapt the number of used blocks and the number of bits that are
-- required for the block field (2 ** num_block_field_c >= num_blocks_c)
--
-- number of used blocks
constant num_blocks_c : natural := 4;
-- number of bits for block field
constant num_block_field_c : natural := 2;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Don't change the array type
--
type block_desc_t is
record
addr_width : natural;
data_width : natural;
end record;
type block_array_t is array (natural range 0 to num_blocks_c-1) of block_desc_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fill in the array for all your used blocks
--
constant blocks_c : block_array_t :=
((addr_width => 24, -- block #0, FLASH
data_width => 16),
(addr_width => 18, -- block #1, RAM0
data_width => 16),
(addr_width => 18, -- block #2, RAM1
data_width => 16),
(addr_width => 8, -- block #3, embedded RAM
data_width => 8)
);
--
-- And specify the maximum address and data width
--
constant max_addr_width_c : natural := 24;
constant max_data_width_c : natural := 16;
--
-----------------------------------------------------------------------------
end;
| gpl-2.0 |
simlrh/ctags | Units/review-needed.r/test.vhd.t/input.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_register_16bit.vhd | 4 | 2290 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd | 4 | 2290 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:12:05 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_register_16bit.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_16bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register_16bit IS
END tb_register_16bit;
ARCHITECTURE behavior OF tb_register_16bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_16bit PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_trafo.vhd | 4 | 3581 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:21:42 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_trafo.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trafo
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_trafo IS
END tb_trafo;
ARCHITECTURE behavior OF tb_trafo IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trafo
PORT(
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X1 : std_logic_vector(15 downto 0) := (others => '0');
signal X2 : std_logic_vector(15 downto 0) := (others => '0');
signal X3 : std_logic_vector(15 downto 0) := (others => '0');
signal X4 : std_logic_vector(15 downto 0) := (others => '0');
signal Z1 : std_logic_vector(15 downto 0) := (others => '0');
signal Z2 : std_logic_vector(15 downto 0) := (others => '0');
signal Z3 : std_logic_vector(15 downto 0) := (others => '0');
signal Z4 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Y1 : std_logic_vector(15 downto 0);
signal Y2 : std_logic_vector(15 downto 0);
signal Y3 : std_logic_vector(15 downto 0);
signal Y4 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trafo PORT MAP (
X1 => X1,
X2 => X2,
X3 => X3,
X4 => X4,
Z1 => Z1,
Z2 => Z2,
Z3 => Z3,
Z4 => Z4,
Y1 => Y1,
Y2 => Y2,
Y3 => Y3,
Y4 => Y4
);
X1 <= std_logic_vector(to_unsigned(2596, 16));
X2 <= std_logic_vector(to_unsigned(152, 16));
X3 <= std_logic_vector(to_unsigned(60523, 16));
X4 <= std_logic_vector(to_unsigned(18725, 16));
Z1 <= std_logic_vector(to_unsigned(128, 16));
Z2 <= std_logic_vector(to_unsigned(192, 16));
Z3 <= std_logic_vector(to_unsigned(256, 16));
Z4 <= std_logic_vector(to_unsigned(320, 16));
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_multiplexer_4_to_1.vhd | 2 | 2887 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:42 12/23/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs2/tb_multiplexer_4_to_1.vhd
-- Project Name: idea_rcs2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplexer_4_to_1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_multiplexer_4_to_1 IS
END tb_multiplexer_4_to_1;
ARCHITECTURE behavior OF tb_multiplexer_4_to_1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplexer_4_to_1
PORT(
in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
s : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal in1 : std_logic_vector(15 downto 0) := (others => '0');
signal in2 : std_logic_vector(15 downto 0) := (others => '0');
signal in3 : std_logic_vector(15 downto 0) := (others => '0');
signal in4 : std_logic_vector(15 downto 0) := (others => '0');
signal s : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplexer_4_to_1 PORT MAP (
in1 => in1,
in2 => in2,
in3 => in3,
in4 => in4,
s => s,
O => O
);
in1 <= "0000000000000000", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in2 <= "0000000000000001", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in3 <= "0000000000000010", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
in4 <= "0000000000000100", "0000000000000001" after 20 ns, "0000000000000011" after 40 ns;
s <= "00", "01" after 5 ns, "11" after 15 ns, "10" after 25 ns, "00" after 35 ns, "01" after 40 ns, "10" after 50 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/idea_com_inner.vhd | 1 | 11113 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 20:59:47 06/19/2008
-- Design Name:
-- Module Name: idea_com_inner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 2.00 (nnc) - Key can be programmed
-- Revision 2.01 (nnc) - Add loopback mode for cable testing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_com_inner is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com_inner;
architecture Behavioral of idea_com_inner is
-- The UART for the communication with the PC:
component uart
port ( mclkx16 : in STD_LOGIC;
reset : in STD_LOGIC;
read : in STD_LOGIC;
write : in STD_LOGIC;
--data : inout STD_LOGIC_VECTOR (7 downto 0);
rxdata : out STD_LOGIC_VECTOR (7 downto 0);
txdata : in STD_LOGIC_VECTOR (7 downto 0);
sin : in STD_LOGIC;
sout : out STD_LOGIC;
rxrdy : out STD_LOGIC;
txrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC );
end component;
--component idea_hw
-- Port ( CLK : in STD_LOGIC;
-- START : in STD_LOGIC;
-- READY : out STD_LOGIC;
-- KEY : in STD_LOGIC_VECTOR (127 downto 0);
-- X1 : in STD_LOGIC_VECTOR (15 downto 0);
-- X2 : in STD_LOGIC_VECTOR (15 downto 0);
-- X3 : in STD_LOGIC_VECTOR (15 downto 0);
-- X4 : in STD_LOGIC_VECTOR (15 downto 0);
-- Y1 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y2 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y3 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y4 : out STD_LOGIC_VECTOR (15 downto 0));
--end component;
COMPONENT idea_single
PORT(
KEY : IN std_logic_vector(127 downto 0);
clk_in : IN std_logic;
ready_out : OUT std_logic;
start_in : IN std_logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
-- All used signals for the top level are defined here:
signal read : STD_LOGIC := '1';
signal write : STD_LOGIC := '1';
signal rxrdy, txrdy : STD_LOGIC := '1';
signal parity_error, framing_error, overrun : STD_LOGIC := '0';
signal data : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal txdata : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal start_idea, ready_idea : STD_LOGIC := '0';
signal x1, x2, x3, x4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal y1, y2, y3, y4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal key : STD_logic_vector (127 downto 0) := x"00000000000000000000000000000000";
type STATE_TYPE is ( IDLE, WAIT_FOR_DATA, RECEIVED_BYTE, READ_BYTE,
WAIT_FOR_RXRDY_0, WAIT_FOR_IDEA_TO_DEACTIVATE_READY,
WAIT_FOR_IDEA_TO_COMPLETE,
WRITE_BYTE, WRITE_BYTE_NOW, WRITE_BYTE_ACK,
WAIT_FOR_TXRDY_1, LOOPBACK_MODE );
signal state : STATE_TYPE := IDLE;
signal byte_cntr : std_logic_vector(4 downto 0) := "00000";
signal loopback_select : std_logic := '0';
signal z1, z2, z3, z4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal led_count_sig : std_logic_vector(7 downto 0) := "00000000";
signal counter_sig : std_logic_vector(18 downto 0) := (others => '0');
begin
-- The UART module
uart1: uart port map( Clk, Reset,
read, write, data, txdata,
RxD, TxD,
rxrdy, txrdy,
parity_error, framing_error, overrun );
-- The encryption algorithm
-- idea1: idea_hw port map( clk, start_idea, ready_idea, key, x1, x2, x3, x4, y1, y2, y3, y4);
uut: idea_single PORT MAP (
KEY => key,
clk_in => Clk,
ready_out => ready_idea,
start_in => start_idea,
X1 => x1,
X2 => x2,
X3 => x3,
X4 => x4,
Y1 => y1,
Y2 => y2,
Y3 => y3,
Y4 => y4
);
-- mux for loopback mode
mux1 : multiplexer port map(
A => y1,
B => x1,
S => loopback_select,
O => z1);
mux2 : multiplexer port map(
A => y2,
B => x2,
S => loopback_select,
O => z2);
mux3 : multiplexer port map(
A => y3,
B => X3,
S => loopback_select,
O => z3);
mux4 : multiplexer port map(
A => y4,
B => X4,
S => loopback_select,
O => z4);
-- The state machine for the communication:
process ( Clk )
begin
if ( Clk'event and Clk='1' ) then
if ( Reset = '1' ) then
state <= IDLE;
byte_cntr <= "00000";
read <= '1';
write <= '1';
--LEDs <= "00000000";
else
if ( state = IDLE ) then
-- Initial state
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
elsif ( state = WAIT_FOR_DATA ) then
write <= '1';
-- Waiting for incoming data.
if ( rxrdy = '1' ) then
-- There is a byte at the receiver!
state <= RECEIVED_BYTE;
end if;
elsif ( state = RECEIVED_BYTE ) then
-- The UART signalizes, that there
-- is a new byte to be read!
read <= '0';
--LEDs(3) <= '0';
state <= READ_BYTE;
elsif ( state = READ_BYTE ) then
-- Read the byte and set the
-- right input registers of the
-- IDEA block.
--LEDs(0) <= framing_error;
--LEDs(1) <= parity_error;
--LEDs(2) <= overrun;
byte_cntr <= byte_cntr+"00001";
if ( byte_cntr = "00000" ) then
x1(7 downto 0) <= data;
elsif ( byte_cntr = "00001" ) then
x1(15 downto 8) <= data;
elsif ( byte_cntr = "00010" ) then
x2(7 downto 0) <= data;
elsif ( byte_cntr = "00011" ) then
x2(15 downto 8) <= data;
elsif ( byte_cntr = "00100" ) then
x3(7 downto 0) <= data;
elsif ( byte_cntr = "00101" ) then
x3(15 downto 8) <= data;
elsif ( byte_cntr = "00110" ) then
x4(7 downto 0) <= data;
elsif ( byte_cntr = "00111" ) then
x4(15 downto 8) <= data;
elsif ( byte_cntr = "01000" ) then
key(7 downto 0) <= data;
elsif ( byte_cntr = "01001" ) then
key(15 downto 8) <= data;
elsif ( byte_cntr = "01010" ) then
key(23 downto 16) <= data;
elsif ( byte_cntr = "01011" ) then
key(31 downto 24) <= data;
elsif ( byte_cntr = "01100" ) then
key(39 downto 32) <= data;
elsif ( byte_cntr = "01101" ) then
key(47 downto 40) <= data;
elsif ( byte_cntr = "01110" ) then
key(55 downto 48) <= data;
elsif ( byte_cntr = "01111" ) then
key(63 downto 56) <= data;
elsif ( byte_cntr = "10000" ) then
key(71 downto 64) <= data;
elsif ( byte_cntr = "10001" ) then
key(79 downto 72) <= data;
elsif ( byte_cntr = "10010" ) then
key(87 downto 80) <= data;
elsif ( byte_cntr = "10011" ) then
key(95 downto 88) <= data;
elsif ( byte_cntr = "10100" ) then
key(103 downto 96) <= data;
elsif ( byte_cntr = "10101" ) then
key(111 downto 104) <= data;
elsif ( byte_cntr = "10110" ) then
key(119 downto 112) <= data;
elsif ( byte_cntr = "10111" ) then
key(127 downto 120) <= data;
end if;
read <= '1';
state <= WAIT_FOR_RXRDY_0;
elsif ( state = WAIT_FOR_RXRDY_0 ) then
-- Wait until the UART has acknowledged
-- that the data has been read.
if ( rxrdy = '0' ) then
if ( byte_cntr = "11000" ) then
-- add loopback mode
if (key = X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF") then
state <= LOOPBACK_MODE;
loopback_select <= '1';
else
start_idea <= '1';
state <= WAIT_FOR_IDEA_TO_DEACTIVATE_READY;
loopback_select <= '0';
end if;
-- added newly: 20130405
-- read <= '1';
else
state <= WAIT_FOR_DATA;
end if;
end if;
elsif(state=LOOPBACK_MODE) then
byte_cntr <= "00000";
state <= WRITE_BYTE;
elsif ( state = WAIT_FOR_IDEA_TO_DEACTIVATE_READY ) then
if ( ready_idea = '0' ) then
state <= WAIT_FOR_IDEA_TO_COMPLETE;
end if;
elsif ( state = WAIT_FOR_IDEA_TO_COMPLETE ) then
-- The IDEA algorithm has computed its results now.
byte_cntr <= "00000";
start_idea <= '0';
if ( ready_idea = '1' ) then
state <= WRITE_BYTE;
end if;
elsif ( state = WRITE_BYTE ) then
-- Write back the computed data set
byte_cntr <= byte_cntr + "00001";
if ( byte_cntr = "00000" ) then
txdata <= z1(7 downto 0);
elsif ( byte_cntr = 1 ) then
txdata <= z1(15 downto 8);
elsif ( byte_cntr = 2 ) then
txdata <= z2(7 downto 0);
elsif ( byte_cntr = 3 ) then
txdata <= z2(15 downto 8);
elsif ( byte_cntr = 4 ) then
txdata <= z3(7 downto 0);
elsif ( byte_cntr = 5 ) then
txdata <= z3(15 downto 8);
elsif ( byte_cntr = 6 ) then
txdata <= z4(7 downto 0);
elsif ( byte_cntr = 7 ) then
txdata <= z4(15 downto 8);
end if;
state <= WRITE_BYTE_NOW;
elsif ( state = WRITE_BYTE_NOW ) then
write <= '0';
state <= WRITE_BYTE_ACK;
elsif ( state = WRITE_BYTE_ACK ) then
write <= '1';
if ( txrdy = '0' ) then
state <= WAIT_FOR_TXRDY_1;
end if;
elsif ( state = WAIT_FOR_TXRDY_1 ) then
if ( txrdy = '1' ) then
txdata <= "00000000";
if ( byte_cntr = "01000" ) then
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
else
state <= WRITE_BYTE;
end if;
end if;
end if;
end if;
end if;
end process;
LEDs_proc : process ( Clk )
begin
if ( Clk'event and Clk='1' ) then
if(counter_sig = "1001011000000000000") then
counter_sig <= "0000000000000000000";
if(led_count_sig = "11111111") then
led_count_sig <= "00000000";
else
LEDs <= led_count_sig;
led_count_sig <= led_count_sig +1;
end if;
else
counter_sig <= counter_sig +1;
end if;
end if;
end process LEDs_proc;
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/Exercise1/direct_implementation/tb_mulop.vhd | 4 | 2226 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/datapath.vhd | 2 | 6774 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:11:48 12/23/2015
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datapath is
Port ( Clock : in STD_LOGIC;
S : IN std_logic_vector(1 downto 0);
S_t : IN std_logic_vector(1 downto 0);
EN125 : in STD_LOGIC;
EN346 : in STD_LOGIC;
EN78 : in STD_LOGIC;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0));
end datapath;
architecture Behavioral of datapath is
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
COMPONENT multiplexer_4_to_1
PORT(
in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
S : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL MUL1_OUT : std_logic_vector(15 downto 0);
SIGNAL ADD1_OUT : std_logic_vector(15 downto 0);
SIGNAL XOR1_OUT : std_logic_vector(15 downto 0);
SIGNAL R1_OUT : std_logic_vector(15 downto 0);
SIGNAL R2_OUT : std_logic_vector(15 downto 0);
SIGNAL R3_OUT : std_logic_vector(15 downto 0);
SIGNAL R4_OUT : std_logic_vector(15 downto 0);
SIGNAL R5_OUT : std_logic_vector(15 downto 0);
SIGNAL R6_OUT : std_logic_vector(15 downto 0);
SIGNAL R7_OUT : std_logic_vector(15 downto 0);
SIGNAL R8_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX1_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX2_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX3_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX4_OUT : std_logic_vector(15 downto 0);
begin
Y3_trafo <= R3_OUT;
Y2_trafo <= R2_OUT;
Y4_trafo <= R4_OUT;
Y1_trafo <= R1_OUT;
REG_1: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R1_OUT,
en => EN125,
clk => Clock
);
REG_2: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R2_OUT,
en => EN125,
clk => Clock
);
REG_3: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R3_OUT,
en => EN346,
clk => Clock
);
REG_4: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R4_OUT,
en => EN346,
clk => Clock
);
REG_5: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R5_OUT,
en => EN125,
clk => Clock
);
REG_6: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R6_OUT,
en => EN346,
clk => Clock
);
REG_7: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R7_OUT,
en => EN78,
clk => Clock
);
REG_8: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R8_OUT,
en => EN78,
clk => Clock
);
XOR_1: xorop PORT MAP (
A => MUL1_OUT,
B => ADD1_OUT,
O => XOR1_OUT
);
XOR_2: xorop PORT MAP (
A => R3_OUT,
B => ADD1_OUT,
O => Y3
);
XOR_3: xorop PORT MAP (
A => R2_OUT,
B => MUL1_OUT,
O => Y2
);
XOR_4: xorop PORT MAP (
A => R4_OUT,
B => ADD1_OUT,
O => Y4
);
XOR_5: xorop PORT MAP (
A => R1_OUT,
B => MUL1_OUT,
O => Y1
);
ADDER1: addop PORT MAP (
A => MUX3_OUT,
B => MUX4_OUT,
O => ADD1_OUT
);
MUL1: mulop PORT MAP (
X => MUX1_OUT,
Y => MUX2_OUT,
O => MUL1_OUT
);
MUX1_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X1,
in2 => X4,
in3 => Z5,
in4 => Z6,
S => S,
O => MUX1_OUT
);
MUX2_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z1,
in2 => Z4,
in3 => R5_OUT,
in4 => R8_OUT,
S => S,
O => MUX2_OUT
);
MUX3_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X3,
in2 => X2,
in3 => R6_OUT,
in4 => R7_OUT,
S => S,
O => MUX3_OUT
);
MUX4_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z3,
in2 => Z2,
in3 => MUL1_OUT,
in4 => MUL1_OUT,
S => S_t,
O => MUX4_OUT
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/idea_single.vhd | 4 | 8352 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:05:10 11/16/2015
-- Design Name:
-- Module Name: idea_single - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_single is
Port ( KEY : in std_logic_vector(127 downto 0);
clk_in : in std_logic;
ready_out : out std_logic;
start_in : in std_logic;
X1 : in std_logic_vector(15 downto 0);
X2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
X4 : in std_logic_vector(15 downto 0);
Y1 : out std_logic_vector(15 downto 0);
Y2 : out std_logic_vector(15 downto 0);
Y3 : out std_logic_vector(15 downto 0);
Y4 : out std_logic_vector(15 downto 0));
end idea_single;
architecture Behavioral of idea_single is
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0) ;
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
COMPONENT trafo
PORT(
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT round
PORT(
x1 : IN std_logic_vector(15 downto 0);
x2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
x4 : IN std_logic_vector(15 downto 0);
z1 : IN std_logic_vector(15 downto 0);
z2 : IN std_logic_vector(15 downto 0);
z3 : IN std_logic_vector(15 downto 0);
z4 : IN std_logic_vector(15 downto 0);
z5 : IN std_logic_vector(15 downto 0);
z6 : IN std_logic_vector(15 downto 0);
y1 : OUT std_logic_vector(15 downto 0);
y2 : OUT std_logic_vector(15 downto 0);
y3 : OUT std_logic_vector(15 downto 0);
y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
round : OUT std_logic_vector(3 downto 0);
ready : OUT std_logic;
en : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
signal round_out_y1 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y2 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y3 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y4 : std_logic_vector(15 downto 0) := (others => '0');
signal round_number : std_logic_vector(3 downto 0) := (others => '0');
signal enable_sig : std_logic := '0';
signal s_sig : std_logic := '0';
signal key_1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_4_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_5_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_6_sig : std_logic_vector(15 downto 0) := (others => '0');
signal reg_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal y1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y4_sig : std_logic_vector(15 downto 0) := (others => '0');
begin
Y1 <= y1_sig;
Y2 <= y2_sig;
Y3 <= y3_sig;
Y4 <= y4_sig;
register_1: register_16bit PORT MAP (
D => round_out_y1,
Q => reg_1_out,
en => enable_sig,
clk => clk_in
);
register_2: register_16bit PORT MAP (
D => round_out_y2,
Q => reg_2_out,
en => enable_sig,
clk => clk_in
);
register_3: register_16bit PORT MAP (
D => round_out_y3,
Q => reg_3_out,
en => enable_sig,
clk => clk_in
);
register_4: register_16bit PORT MAP (
D => round_out_y4,
Q => reg_4_out,
en => enable_sig,
clk => clk_in
);
control_1: control PORT MAP (
clk => clk_in,
start => start_in,
round => round_number,
ready => ready_out,
en => enable_sig,
s => s_sig
);
trafo_1: trafo PORT MAP (
X1 => reg_1_out,
X2 => reg_2_out,
X3 => reg_3_out,
X4 => reg_4_out,
Z1 => key_1_sig,
Z2 => key_2_sig,
Z3 => key_3_sig,
Z4 => key_4_sig,
Y1 => y1_sig,
Y2 => y2_sig,
Y3 => y3_sig,
Y4 => y4_sig
);
round_module: round PORT MAP (
x1 => mux_1_out,
x2 => mux_2_out,
X3 => mux_3_out,
x4 => mux_4_out,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig,
y1 => round_out_y1,
y2 => round_out_y2,
y3 => round_out_y3,
y4 => round_out_y4
);
mux_1: multiplexer PORT MAP (
A => X1,
B => reg_1_out,
O => mux_1_out,
s => s_sig
);
mux_2: multiplexer PORT MAP (
A => X2,
B => reg_2_out,
O => mux_2_out,
s => s_sig
);
mux_3: multiplexer PORT MAP (
A => X3,
B => reg_3_out,
O => mux_3_out,
s => s_sig
);
mux_4: multiplexer PORT MAP (
A => X4,
B => reg_4_out,
O => mux_4_out,
s => s_sig
);
keygen_module: keygen PORT MAP (
rc => round_number,
key_in => KEY,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/idea_single.vhd | 4 | 8352 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:05:10 11/16/2015
-- Design Name:
-- Module Name: idea_single - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_single is
Port ( KEY : in std_logic_vector(127 downto 0);
clk_in : in std_logic;
ready_out : out std_logic;
start_in : in std_logic;
X1 : in std_logic_vector(15 downto 0);
X2 : in std_logic_vector(15 downto 0);
X3 : in std_logic_vector(15 downto 0);
X4 : in std_logic_vector(15 downto 0);
Y1 : out std_logic_vector(15 downto 0);
Y2 : out std_logic_vector(15 downto 0);
Y3 : out std_logic_vector(15 downto 0);
Y4 : out std_logic_vector(15 downto 0));
end idea_single;
architecture Behavioral of idea_single is
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0) ;
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
COMPONENT trafo
PORT(
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT round
PORT(
x1 : IN std_logic_vector(15 downto 0);
x2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
x4 : IN std_logic_vector(15 downto 0);
z1 : IN std_logic_vector(15 downto 0);
z2 : IN std_logic_vector(15 downto 0);
z3 : IN std_logic_vector(15 downto 0);
z4 : IN std_logic_vector(15 downto 0);
z5 : IN std_logic_vector(15 downto 0);
z6 : IN std_logic_vector(15 downto 0);
y1 : OUT std_logic_vector(15 downto 0);
y2 : OUT std_logic_vector(15 downto 0);
y3 : OUT std_logic_vector(15 downto 0);
y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
round : OUT std_logic_vector(3 downto 0);
ready : OUT std_logic;
en : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
signal round_out_y1 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y2 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y3 : std_logic_vector(15 downto 0) := (others => '0');
signal round_out_y4 : std_logic_vector(15 downto 0) := (others => '0');
signal round_number : std_logic_vector(3 downto 0) := (others => '0');
signal enable_sig : std_logic := '0';
signal s_sig : std_logic := '0';
signal key_1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_4_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_5_sig : std_logic_vector(15 downto 0) := (others => '0');
signal key_6_sig : std_logic_vector(15 downto 0) := (others => '0');
signal reg_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal reg_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_1_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_2_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_3_out : std_logic_vector(15 downto 0) := (others => '0');
signal mux_4_out : std_logic_vector(15 downto 0) := (others => '0');
signal y1_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y2_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y3_sig : std_logic_vector(15 downto 0) := (others => '0');
signal y4_sig : std_logic_vector(15 downto 0) := (others => '0');
begin
Y1 <= y1_sig;
Y2 <= y2_sig;
Y3 <= y3_sig;
Y4 <= y4_sig;
register_1: register_16bit PORT MAP (
D => round_out_y1,
Q => reg_1_out,
en => enable_sig,
clk => clk_in
);
register_2: register_16bit PORT MAP (
D => round_out_y2,
Q => reg_2_out,
en => enable_sig,
clk => clk_in
);
register_3: register_16bit PORT MAP (
D => round_out_y3,
Q => reg_3_out,
en => enable_sig,
clk => clk_in
);
register_4: register_16bit PORT MAP (
D => round_out_y4,
Q => reg_4_out,
en => enable_sig,
clk => clk_in
);
control_1: control PORT MAP (
clk => clk_in,
start => start_in,
round => round_number,
ready => ready_out,
en => enable_sig,
s => s_sig
);
trafo_1: trafo PORT MAP (
X1 => reg_1_out,
X2 => reg_2_out,
X3 => reg_3_out,
X4 => reg_4_out,
Z1 => key_1_sig,
Z2 => key_2_sig,
Z3 => key_3_sig,
Z4 => key_4_sig,
Y1 => y1_sig,
Y2 => y2_sig,
Y3 => y3_sig,
Y4 => y4_sig
);
round_module: round PORT MAP (
x1 => mux_1_out,
x2 => mux_2_out,
X3 => mux_3_out,
x4 => mux_4_out,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig,
y1 => round_out_y1,
y2 => round_out_y2,
y3 => round_out_y3,
y4 => round_out_y4
);
mux_1: multiplexer PORT MAP (
A => X1,
B => reg_1_out,
O => mux_1_out,
s => s_sig
);
mux_2: multiplexer PORT MAP (
A => X2,
B => reg_2_out,
O => mux_2_out,
s => s_sig
);
mux_3: multiplexer PORT MAP (
A => X3,
B => reg_3_out,
O => mux_3_out,
s => s_sig
);
mux_4: multiplexer PORT MAP (
A => X4,
B => reg_4_out,
O => mux_4_out,
s => s_sig
);
keygen_module: keygen PORT MAP (
rc => round_number,
key_in => KEY,
z1 => key_1_sig,
z2 => key_2_sig,
z3 => key_3_sig,
z4 => key_4_sig,
z5 => key_5_sig,
z6 => key_6_sig
);
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/tb_idea_com.vhd | 4 | 2368 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:16:27 11/18/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_idea_com.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: idea_com
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_idea_com IS
END tb_idea_com;
ARCHITECTURE behavior OF tb_idea_com IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT idea_com
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
RxD : IN std_logic;
TxD : OUT std_logic;
LEDs : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal RxD : std_logic := '0';
--Outputs
signal TxD : std_logic;
signal LEDs : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: idea_com PORT MAP (
Clk => Clk,
Reset => Reset,
RxD => RxD,
TxD => TxD,
LEDs => LEDs
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd | 4 | 3237 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_keygen.vhd | 4 | 3237 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:01 11/15/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_keygen.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keygen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_keygen IS
END tb_keygen;
ARCHITECTURE behavior OF tb_keygen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT keygen
PORT(
rc : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
z1 : OUT std_logic_vector(15 downto 0);
z2 : OUT std_logic_vector(15 downto 0);
z3 : OUT std_logic_vector(15 downto 0);
z4 : OUT std_logic_vector(15 downto 0);
z5 : OUT std_logic_vector(15 downto 0);
z6 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal rc : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal z1 : std_logic_vector(15 downto 0);
signal z2 : std_logic_vector(15 downto 0);
signal z3 : std_logic_vector(15 downto 0);
signal z4 : std_logic_vector(15 downto 0);
signal z5 : std_logic_vector(15 downto 0);
signal z6 : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: keygen PORT MAP (
rc => rc,
key_in => key_in,
z1 => z1,
z2 => z2,
z3 => z3,
z4 => z4,
z5 => z5,
z6 => z6
);
key_in <= std_logic_vector(to_unsigned(1,16))&std_logic_vector(to_unsigned(2,16))&std_logic_vector(to_unsigned(3,16))&std_logic_vector(to_unsigned(4,16))&std_logic_vector(to_unsigned(5,16))&std_logic_vector(to_unsigned(6,16))&std_logic_vector(to_unsigned(7,16))&std_logic_vector(to_unsigned(8,16));
rc <= std_logic_vector(to_unsigned(0,4)), std_logic_vector(to_unsigned(1,4))after 10 ns, std_logic_vector(to_unsigned(2,4)) after 20 ns,std_logic_vector(to_unsigned(3,4)) after 30 ns,std_logic_vector(to_unsigned(4,4)) after 40 ns,std_logic_vector(to_unsigned(5,4)) after 50 ns,std_logic_vector(to_unsigned(6,4)) after 60 ns,std_logic_vector(to_unsigned(7,4)) after 70 ns,std_logic_vector(to_unsigned(8,4)) after 80 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | uni_rech/rcs1/tb_control.vhd | 2 | 2308 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:23:07 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_control.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_control IS
END tb_control;
ARCHITECTURE behavior OF tb_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
round : OUT std_logic_vector(3 downto 0);
ready : OUT std_logic;
en : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal start : std_logic := '0';
--Outputs
signal round : std_logic_vector(3 downto 0);
signal ready : std_logic;
signal en : std_logic;
signal s : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control PORT MAP (
clk => clk,
start => start,
round => round,
ready => ready,
en => en,
s => s
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
start <= '0', '1' after 5 ns, '0' after 15 ns, '1' after 505 ns, '0' after 515 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs1/idea_rcs1/tb_control.vhd | 2 | 2308 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:23:07 11/16/2015
-- Design Name:
-- Module Name: /home/superus/vhdl_system_design/workspace/idea_rcs1/idea_rcs1/tb_control.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_control IS
END tb_control;
ARCHITECTURE behavior OF tb_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control
PORT(
clk : IN std_logic;
start : IN std_logic;
round : OUT std_logic_vector(3 downto 0);
ready : OUT std_logic;
en : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal start : std_logic := '0';
--Outputs
signal round : std_logic_vector(3 downto 0);
signal ready : std_logic;
signal en : std_logic;
signal s : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control PORT MAP (
clk => clk,
start => start,
round => round,
ready => ready,
en => en,
s => s
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
start <= '0', '1' after 5 ns, '0' after 15 ns, '1' after 505 ns, '0' after 515 ns;
END;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/tb_reg_sync.vhd | 4 | 2269 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
| gpl-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/ipcore_dir/ROM_4K_ste/example_design/bmg_wrapper.vhd | 1 | 10171 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : ROM_4K.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT ROM_4K_top IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ROM_4K_top
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2plus/idea_com.vhd | 4 | 1828 | ----------------------------------------------------------------------------------
-- TUM
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 16:34:40 06/16/2008
-- Design Name:
-- Module Name: idea_com - Behavioral
-- Project Name: idea lab
-- Target Devices: Spartan 3E
-- Tool versions: > 9.2
-- Description: This file is intended to be the top
-- level module. It brings the clock generator
-- and the clocked idea module together.
--
-- Revision 1.00 - File created and tested
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Make this the top module:
entity idea_com is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com;
architecture Behavioral of idea_com is
-- Mapping the inner idea part.
-- The outer part is only to syntesize
-- the clock generator properly.
component idea_com_inner
port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- The clock generator for the UART.
-- This block generates a clock of approx. 16*9600 Hz
-- from the 50 MHz system clock.
component clk_div
port ( CLK : in STD_LOGIC;
CLK_OUT : out STD_LOGIC );
end component;
signal clk_out : STD_LOGIC;
begin
clk_div_1 : clk_div port map( clk, clk_out );
idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs ); --here original: idea_1 : idea_com_inner port map( clk_out, Reset, RxD, TxD, LEDs );
end Behavioral;
| gpl-2.0 |
tolgasel/vhdl_system_design | workspace/idea_rcs2/trafo.vhd | 4 | 2281 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trafo is
Port ( X1 : in STD_LOGIC_VECTOR(15 downto 0);
X2 : in STD_LOGIC_VECTOR(15 downto 0);
X3 : in STD_LOGIC_VECTOR(15 downto 0);
X4 : in STD_LOGIC_VECTOR(15 downto 0);
Z1 : in STD_LOGIC_VECTOR(15 downto 0);
Z2 : in STD_LOGIC_VECTOR(15 downto 0);
Z3 : in STD_LOGIC_VECTOR(15 downto 0);
Z4 : in STD_LOGIC_VECTOR(15 downto 0);
Y1 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y2 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y3 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y4 : OUT STD_LOGIC_VECTOR(15 downto 0));
end trafo;
architecture Behavioral of trafo is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
begin
mulop_1: mulop PORT MAP (
X => X1,
Y => Z1,
O => Y1
);
mulop_2: mulop PORT MAP (
X => X4,
Y => Z4,
O => Y4
);
addop_1: addop PORT MAP (
A => X3,
B => Z2,
O => Y2
);
addop_2: addop PORT MAP (
A => X2,
B => Z3,
O => Y3
);
end Behavioral;
| gpl-2.0 |
ashtonchase/logic_analyzer | target_hardware/Zybo/zybo_top.vhd | 1 | 4355 | -------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top.vhd
-- Created : 2016-02-22
-- Last update: 2016-02-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
ENTITY zybo_top IS
PORT (
clk : IN STD_LOGIC; -- 125 MHz clock
je : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- PMOD JE inputs
led : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --LED outputs
sw : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Switches
btn : IN STD_LOGIC_VECTOR(3 DOWNTO 0) --Buttons
);
END ENTITY zybo_top;
ARCHITECTURE top OF zybo_top IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
COMPONENT clock_gen
PORT
( -- Clock in ports
clk_in1 : IN STD_LOGIC;
-- Clock out ports
clk_25mhz : OUT STD_LOGIC;
-- Status and control signals
reset : IN STD_LOGIC;
locked : OUT STD_LOGIC
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
SIGNAL reset : STD_LOGIC := '1'; -- reset (async high, sync low)
SIGNAL run_clk : STD_LOGIC := '0'; -- clock output of the clocking wizard
SIGNAL clk_locked : STD_LOGIC := '0'; -- indicator if the clocking wizard has locked
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
ALIAS reset_btn : STD_LOGIC IS btn(0);
BEGIN -- ARCHITECTURE top
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : clock_gen
PORT MAP (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_btn,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
reset_proc : PROCESS (reset_btn, clk) IS
BEGIN -- PROCESS reset_proc
IF reset_btn = '1' THEN
reset <= '1';
ELSIF rising_edge(clk) THEN
reset <= '0';
END IF;
END PROCESS reset_proc;
END ARCHITECTURE top;
| gpl-2.0 |
terfect/Geany-plus | data/filetypes.vhdl | 1 | 3198 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# foreground;background;bold;italic
default=0x000000;0xffffff;false;false
comment=0xd00000;0xffffff;false;false
comment_line_bang=0x3f5fbf;0xffffff;false;false;
number=0x007f00;0xffffff;false;false
string=0xff901e;0xffffff;false;false
operator=0x301010;0xffffff;false;false
identifier=0x000000;0xffffff;false;false
stringeol=0x000000;0xe0c0e0;false;false
keyword=0x001a7f;0xffffff;true;false
stdoperator=0x007f7f;0xffffff;false;false
attribute=0x804020;0xffffff;false;false
stdfunction=0x808020;0xffffff;true;false
stdpackage=0x208020;0xffffff;false;false
stdtype=0x208080;0xffffff;false;false
userword=0x804020;0xffffff;true;false
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
| gpl-2.0 |
alyoshin/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/voltage_source.vhdl | 15 | 415 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY VOLTAGE_SOURCE;
| gpl-2.0 |
alyoshin/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/resistor.vhdl | 15 | 289 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 60.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
| gpl-2.0 |
ashtonchase/logic_analyzer | src/msg_processor.vhd | 1 | 7195 | -------------------------------------------------------------------------------
-- Title : Message Processor
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : msg_processor.vhd
-- Created : 2016-03-17
-- Last update: 2016-04-09
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: The message processor waits for the UART module to provide
-- commands and data from the SUMP software. When the command is ready, it is
-- read, the ready flag is driven low, and the command is decoded. After the
-- command is decoded, appropiate lines are set to control the sample rate,
-- trigger mask, and sample counts.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-17 0.0 David Created
-- 2016-03-31 0.1 David Entity done
-- 2016-04-04 0.2 David State machine in progress
-- 2016-04-05 1.0 David Complete
-- 2016-04-07 1.1 David Handles unrecognized commands
-- 2016-04-08 1.2 Ashton Changed READ_CMD check of cmd_in from
-- invalid if statement to case statement.
-- Beautified..
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity msg_processor is
port(
-- Global Signals
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous reset
-- UART Interface
byte_in : in std_logic_vector(7 downto 0); -- Byte of command/data from UART
byte_new : in std_logic; -- Strobe to indicate new byte
-- Sample Rate Control Interface
sample_f : out std_logic_vector(23 downto 0); -- Sampling frequency to Sample Rate Control
-- Capture Control Interface
reset : out std_logic; -- Reset capture control
armed : out std_logic; -- Arm capture control
send_ID : out std_logic; -- Send device ID
send_debug : out std_logic; -- Send debug status
read_cnt : out std_logic_vector(15 downto 0); -- Number of samples (divided by 4) to send to memory
delay_cnt : out std_logic_vector(15 downto 0); -- Number of samples (divided by 4) to capture after trigger
trig_msk : out std_logic_vector(31 downto 0); -- Define which trigger values must match
trig_vals : out std_logic_vector(31 downto 0) -- Set the trigger's individual bit values
); -- port
end entity msg_processor;
architecture behave of msg_processor is
signal cmd_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in : std_logic_vector(31 downto 0) := (others => '0');
type state_t is (INIT, READ_CMD, DO_CMD, BYTE1, BYTE2, BYTE3, BYTE4);
signal state : state_t;
begin
process(clk)
begin
if rising_edge(clk) then
reset <= '0';
armed <= '0';
send_ID <= '0';
send_debug <= '0';
if rst = '1' then
read_cnt <= x"0000";
delay_cnt <= x"0000";
sample_f <= x"000000";
trig_msk <= x"00000000";
trig_vals <= x"00000000";
state <= INIT;
else
case state is
when INIT =>
if byte_new = '1' then
cmd_in <= byte_in;
state <= READ_CMD;
end if;
when READ_CMD =>
case cmd_in is
when x"C0" | x"C4" | x"C8" | x"CC" | -- Trig Mask
x"C1" | x"C5" | x"C9" | x"CD" | -- Trig Vals
x"C2" | x"C6" | x"CA" | x"CE" | -- Trig Config
x"80" | x"81" | x"82" =>
state <= BYTE1; -- Recognized long command
when others =>
state <= DO_CMD; -- Unrecognized command or short command
end case;
when BYTE1 =>
if byte_new = '1' then
data_in(7 downto 0) <= byte_in;
state <= BYTE2;
end if;
when BYTE2 =>
if byte_new = '1' then
data_in(15 downto 8) <= byte_in;
state <= BYTE3;
end if;
when BYTE3 =>
if byte_new = '1' then
data_in(23 downto 16) <= byte_in;
state <= BYTE4;
end if;
when BYTE4 =>
if byte_new = '1' then
data_in(31 downto 24) <= byte_in;
state <= DO_CMD;
end if;
when DO_CMD =>
case cmd_in is
when x"00" => -- Reset
reset <= '1';
when x"01" => -- Run
armed <= '1';
when x"02" => -- Send ID
send_ID <= '1';
when x"11" => -- XON (unimplemented)
when x"13" => -- XOFF (unimplemented)
-- when x"C0" | x"C4" | x"C8" | x"CC" => -- Set Trigger Mask
when x"C0" => -- Set Trigger Mask
trig_msk <= data_in;
--when x"C1" | x"C5" | x"C9" | x"CD" => -- Set Trigger Values
when x"C1" => -- Set Trigger Values
trig_vals <= data_in;
when x"C2" | x"C6" | x"CA" | x"CE" => -- Set Trigger Configuration (unimplemented)
when x"80" => -- Set Divider
sample_f <= data_in(23 downto 0);
when x"81" => -- Set Read & Delay Count
read_cnt <= data_in(15 downto 0);
delay_cnt <= data_in(31 downto 16);
when x"82" => -- Set Flags (unimplemented)
when x"FF" => -- Debug
send_debug <= '1';
when others =>
end case;
state <= INIT;
end case;
end if;
end if;
end process;
end architecture; | gpl-2.0 |
ashtonchase/logic_analyzer | test/capture_ctrl_tb.vhd | 1 | 6755 | -------------------------------------------------------------------------------
-- Title : Testbench for design "capture_ctrl"
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : capture_ctrl_tb.vhd
-- Created : 2016-02-27
-- Last update: 2016-02-27
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-----------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-27 1.0 ashton Created
-------------------------------------------------------------------------------
USE std.textio.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
---------------------------------------------
ENTITY capture_ctrl_tb IS
END ENTITY capture_ctrl_tb;
-------------------------------------------------------------------------------
ARCHITECTURE acj_func_test OF capture_ctrl_tb IS
-- component generics
CONSTANT DATA_WIDTH : POSITIVE RANGE 1 TO 32 := 8;
-- component ports
SIGNAL rst : STD_LOGIC := '1';
SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL armed : STD_LOGIC;
SIGNAL triggered : STD_LOGIC;
SIGNAL rst_cmd : STD_LOGIC := '0';
SIGNAL arm_cmd : STD_LOGIC := '0';
SIGNAL id_cmd : STD_LOGIC := '0';
SIGNAL debug_cmd : STD_LOGIC := '0';
SIGNAL sample_enable : STD_LOGIC := '1';
SIGNAL sample_cnt_rst : STD_LOGIC;
SIGNAL read_cnt_4x : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1000,16));
SIGNAL par_trig_msk : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := X"FE_6B_28_40";
SIGNAL par_trig_val : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL capture_rdy : STD_LOGIC;
SIGNAL fifo_tdata : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL fifo_tvalid : STD_LOGIC;
SIGNAL fifo_tlast : STD_LOGIC;
SIGNAL fifo_tready : STD_LOGIC := '0';
SIGNAL fifo_tfull : STD_LOGIC := '0';
SIGNAL placeholder : STD_LOGIC := '0';
-- clock
SIGNAL Clk : STD_LOGIC := '1';
BEGIN -- ARCHITECTURE acj_func_test
-- component instantiation
DUT : ENTITY work.capture_ctrl
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH)
PORT MAP (
clk => clk,
rst => rst,
din => din,
armed => armed,
triggered => triggered,
rst_cmd => rst_cmd,
arm_cmd => arm_cmd,
id_cmd => id_cmd,
debug_cmd => debug_cmd,
sample_enable => sample_enable,
sample_cnt_rst => sample_cnt_rst,
delay_cnt_4x => read_cnt_4x,
read_cnt_4x => read_cnt_4x,
par_trig_msk => par_trig_msk,
par_trig_val => par_trig_val,
capture_rdy => capture_rdy,
fifo_tdata => fifo_tdata,
fifo_tvalid => fifo_tvalid,
fifo_tlast => fifo_tlast,
fifo_tready => fifo_tready,
fifo_tfull => fifo_tfull,
placeholder => placeholder);
rst <= '0' AFTER 5 US;
-- clock generation
Clk <= NOT Clk AFTER 2 NS;
sample_rate_sim : process
begin
wait UNTIL falling_edge(sample_cnt_rst);
loop
sample_enable<='0';
wait for 30ns;
WAIT UNTIL rising_edge(clk);
sample_enable<='1';
WAIT UNTIL rising_edge(clk);
end loop;
end process;
-- waveform generation
WaveGen_Proc : PROCESS
BEGIN
-- insert signal assignments here
WAIT UNTIL rst = '0';
FOR cycle IN 0 TO 20 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP; -- cycle
WAIT UNTIL rising_edge(capture_rdy);
WAIT UNTIL rising_edge(clk);
arm_cmd <= '1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '0';
rst_cmd<='1';
WAIT UNTIL rising_edge(clk);
rst_cmd<='0';
wait for 10 us;
WAIT UNTIL rising_edge(clk);
id_cmd<='1';
WAIT UNTIL rising_edge(clk);
id_cmd<='0';
wait for 10 us;
WAIT UNTIL rising_edge(clk);
debug_cmd<='1';
WAIT UNTIL rising_edge(clk);
debug_cmd<='0';
wait for 10 us;
FOR cycle IN 0 TO 20 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP; -- cycle
WAIT UNTIL rising_edge(clk);
arm_cmd <= '1';
WAIT UNTIL rising_edge(clk);
arm_cmd <= '0';
WAIT;
END PROCESS WaveGen_Proc;
din_gen : PROCESS (clk) IS
BEGIN -- PROCESS din_gen
IF rising_edge(clk) THEN -- rising clock edge
IF rst = '1' THEN -- synchronous reset (active high)
din <= (OTHERS => '0');
ELSE
din <= STD_LOGIC_VECTOR(UNSIGNED(din)+1);
END IF;
END IF;
END PROCESS din_gen;
PROCESS (armed) IS
BEGIN -- PROCESS
IF rising_edge(armed) THEN
REPORT "system has armed" SEVERITY NOTE;
END IF;
END PROCESS;
PROCESS (triggered) IS
BEGIN -- PROCESS
IF rising_edge(triggered) THEN
REPORT "system has triggered" SEVERITY NOTE;
ASSERT din = X"40" REPORT "system triggered on incorrect value" SEVERITY ERROR;
END IF;
END PROCESS;
PROCESS IS
BEGIN -- PROCESS
WAIT UNTIL falling_edge(rst);
WAIT FOR 1 US;
fifo_tready <= '1';
WAIT;
END PROCESS;
END ARCHITECTURE acj_func_test;
-------------------------------------------------------------------------------
------------------------------------------------
| gpl-2.0 |
ashtonchase/logic_analyzer | target_hardware/ZedBoard/zed_top_uart_test.vhd | 1 | 10973 | -------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-25
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zed_uart_top is
port (
--Clock Source
GCLK : in std_logic; -- 100 MHz clock
--LED Outputs
LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 : out std_logic;
--Buttons
BTNC, BTND, BTNL, BTNR, BTNU : in std_logic;
--Temporary Data Ouput (JA10-JA7, JA4-JA1)
JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1 : out std_logic;
--UART SIGNALS
JB4 : in std_logic := 'H'; --RX
JB1 : out std_logic; --TX
--Switches
SW7, SW6, SW5, SW4, SW3, SW2, SW1, SW0 : in std_logic
--Fixed Zync Signals
--DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
--DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
--DDR_cas_n : INOUT STD_LOGIC;
--DDR_ck_n : INOUT STD_LOGIC;
--DDR_ck_p : INOUT STD_LOGIC;
--DDR_cke : INOUT STD_LOGIC;
--DDR_cs_n : INOUT STD_LOGIC;
--DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
--DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_odt : INOUT STD_LOGIC;
--DDR_ras_n : INOUT STD_LOGIC;
--DDR_reset_n : INOUT STD_LOGIC;
--DDR_we_n : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
--FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
--FIXED_IO_ps_clk : INOUT STD_LOGIC;
--FIXED_IO_ps_porb : INOUT STD_LOGIC;
--FIXED_IO_ps_srstb : INOUT STD_LOGIC;
);
end entity zed_uart_top;
architecture top of zed_uart_top is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
component Zynq_BD_wrapper is
port (
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
UART_rxd : in std_logic;
UART_txd : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant DATA_WIDTH : positive := 32;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal reset, reset_clk_gen : std_logic := '1'; -- reset (async high, sync low)
signal run_clk : std_logic := '0'; -- clock output of the clocking wizard
signal clk_locked : std_logic := '0'; -- indicator if the clocking wizard has locked
signal din : std_logic_vector(DATA_WIDTH-1 downto 0);
signal armed : std_logic;
signal triggered : std_logic;
signal rst_cmd : std_logic := '0';
signal arm_cmd : std_logic;
signal sample_enable : std_logic := '1';
signal sample_cnt_rst : std_logic;
signal delay_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '0');
signal read_cnt_4x : std_logic_vector(16-1 downto 0) := std_logic_vector(to_unsigned(1000, 16));
signal par_trig_msk : std_logic_vector(32-1 downto 0) := X"00_00_00_03";
signal par_trig_val : std_logic_vector(32-1 downto 0) := (others => '1');
signal capture_rdy : std_logic;
signal in_fifo_tdata : std_logic_vector(31 downto 0);
signal in_fifo_tvalid : std_logic;
signal in_fifo_tlast : std_logic;
signal in_fifo_tready : std_logic;
signal in_fifo_tfull : std_logic;
signal in_fifo_tempty : std_logic;
signal in_fifo_tflush : std_logic;
--
signal out_fifo_tdata : std_logic_vector(7 downto 0);
signal out_fifo_tvalid : std_logic;
signal out_fifo_tlast : std_logic;
signal out_fifo_tready : std_logic;
--
signal rx_get_more_data : std_logic;
signal rx_data_ready : std_logic;
signal rx : std_logic;
signal tx_data_sent : std_logic;
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
alias reset_btn : std_logic is BTND;
alias CLK : std_logic is GCLK;
alias UART_RX : std_logic is JB4;
alias UART_TX : std_logic is JB1;
begin -- ARCHITECTURE top
LD7 <= out_fifo_tdata(7);
LD6<= out_fifo_tdata(6);
LD5<= out_fifo_tdata(5);
LD4<= out_fifo_tdata(4);
LD3<= out_fifo_tdata(3);
LD2<= out_fifo_tdata(2);
LD1<= out_fifo_tdata(1);
LD0<= out_fifo_tdata(0);
--LED to indicate that the clock is locked
uart_comms_test_blk : entity work.uart_comms
generic map (
baud_rate => 115_200,
clock_freq => 10_000_000)
port map (
clk => run_clk,
rst => reset_clk_gen,
rx_get_more_data => '1',
rx => UART_RX,
tx_data_ready => BTNU,
tx => UART_TX,
data_in => SW7& SW6& SW5& SW4& SW3& SW2& SW1& SW0,
data_out =>out_fifo_tdata);
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : entity work.clock_gen
port map (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_clk_gen,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
run_clk_reset_proc : process (reset_btn, run_clk) is
variable reset_dly_v : std_logic;
begin -- PROCESS reset_proc
if reset_btn = '1' then
reset <= '1';
reset_dly_v := '1';
elsif rising_edge(run_clk) then
if clk_locked = '1' then
reset <= reset_dly_v;
reset_dly_v := '0';
else
reset <= '1';
reset_dly_v := '1';
end if;
end if;
end process run_clk_reset_proc;
reset_proc : process (reset_btn, clk) is
variable reset_dly_v : std_logic;
begin -- PROCESS reset_proc
if reset_btn = '1' then
reset_clk_gen <= '1';
elsif rising_edge(clk) then
reset_clk_gen <= reset_dly_v;
reset_dly_v := '0';
end if;
end process reset_proc;
--zynq : ENTITY work.Zynq_BD_wrapper
-- PORT MAP (
-- DDR_addr => DDR_addr,
-- DDR_ba => DDR_ba,
-- DDR_cas_n => DDR_cas_n,
-- DDR_ck_n => DDR_ck_n,
-- DDR_ck_p => DDR_ck_p,
-- DDR_cke => DDR_cke,
-- DDR_cs_n => DDR_cs_n,
-- DDR_dm => DDR_dm,
-- DDR_dq => DDR_dq,
-- DDR_dqs_n => DDR_dqs_n,
-- DDR_dqs_p => DDR_dqs_p,
-- DDR_odt => DDR_odt,
-- DDR_ras_n => DDR_ras_n,
-- DDR_reset_n => DDR_reset_n,
-- DDR_we_n => DDR_we_n,
-- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
-- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
-- FIXED_IO_mio => FIXED_IO_mio,
-- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
-- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
-- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
-- UART_rxd => UART_rxd,
-- UART_txd => UART_txd);
end architecture top;
| gpl-2.0 |
oridb/ctags | Units/review-needed.r/bug2374109.vhd.t/input.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_user_logic_adder.vhd | 1 | 5765 | -- File: dyplo_user_logic_stub.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic�s maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
entity dyplo_user_logic_adder is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 DOWNTO 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end dyplo_user_logic_adder;
architecture rtl of dyplo_user_logic_adder is
type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0);
signal value_to_add : signed_matrix_4x32;
signal cout_tdata_i : signed_matrix_4x32 := (others => (others => '0'));
signal cout_tvalid_i : std_logic_vector(OUTPUT_STREAMS - 1 downto 0) := (others => '0');
signal cin_tready_i : std_logic_vector(INPUT_STREAMS - 1 downto 0) := (others => '0');
begin
config_reg : process (dab_clk)
variable index : integer;
begin
if rising_edge(dab_clk) then
if (dab_rst = '1') then
value_to_add <= (others => (others => '0'));
else
index := to_integer(unsigned(dab_addr(3 downto 2)));
if (dab_sel = '1') and (dab_wvalid = '1') then
value_to_add(index) <= signed(dab_wdata);
end if;
dab_rdata <= std_logic_vector(value_to_add(index));
end if;
end if;
end process config_reg;
adders : for i in 0 to 3 generate
type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH);
signal sm_calc : sm_calc_states := S_FETCH;
signal tdata : signed(31 downto 0) := (others => '0');
begin
calc_data : process (dab_clk)
begin
if rising_edge(dab_clk) then
if (dab_rst = '1') then
cin_tready_i(i) <= '0';
tdata <= (others => '0');
sm_calc <= S_FETCH;
cout_tvalid_i(i) <= '0';
else
case sm_calc is
when S_FETCH =>
if (cin_tvalid(i) = '1') then
cin_tready_i(i) <= '1';
tdata <= signed(cin_tdata(i));
sm_calc <= S_CALC;
end if;
when S_CALC =>
cin_tready_i(i) <= '0';
cout_tdata_i(i) <= tdata + value_to_add(i);
cout_tvalid_i(i) <= '1';
sm_calc <= S_SEND;
when S_SEND =>
if (cout_tready(i) = '1') then
cout_tvalid_i(i) <= '0';
sm_calc <= S_FINISH;
end if;
when S_FINISH =>
sm_calc <= S_FETCH;
end case;
end if;
end if;
end process calc_data;
end generate adders;
cout_tvalid <= cout_tvalid_i;
cin_tready <= cin_tready_i;
cout_tdata(0) <= std_logic_vector(cout_tdata_i(0));
cout_tdata(1) <= std_logic_vector(cout_tdata_i(1));
cout_tdata(2) <= std_logic_vector(cout_tdata_i(2));
cout_tdata(3) <= std_logic_vector(cout_tdata_i(3));
end rtl;
| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sources_1/dyplo_fifo.vhd | 3 | 11516 | `protect begin_protected
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| gpl-2.0 |
kennethlyn/fpga-image-example | hdl_nodes/adder/adder.srcs/sim_1/backplane_simulator.vhd | 3 | 30931 | -- File: backplane_simulator.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic's maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library tb_lib;
use tb_lib.tb_env_pkg.all;
library std;
use std.env.all;
use std.textio.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
library dyplo;
use dyplo.all;
entity backplane_simulator is
end backplane_simulator;
architecture rtl of backplane_simulator is
-- clock and reset for testbench
signal dab_clk : std_logic := '0';
signal dab_rst : std_logic := '1';
--Internal signals for HDL node
signal dab_clk_i : std_logic;
signal dab_rst_i : std_logic;
signal dab_addr_i : std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
signal dab_sel_i : std_logic;
signal dab_wvalid_i : std_logic;
signal dab_rvalid_i : std_logic;
signal dab_wdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
signal dab_rdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
signal b2f_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
signal b2f_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
signal b2f_tvalid_i : std_logic;
signal b2f_tready_i : std_logic;
-- Send data from FIFO to backplane
signal f2b_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
signal f2b_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
signal f2b_tvalid_i : std_logic;
signal f2b_tready_i : std_logic;
-- Clock signals
signal dest_fifo_status_i : std_logic_vector(3 downto 0) := (others => '1');
-- Clock signals
signal user_clocks_i : std_logic_vector(3 downto 0);
--internal signals for stim_reader
signal cmd_i : cmd_record;
signal cmd_accept_i : std_logic;
signal eof_i : std_logic;
--stream signals for datain stream processes
type streams_in_tdata_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
type streams_in_tstream_id_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
signal streams_in_tdata : streams_in_tdata_type;
signal streams_in_tstream_id : streams_in_tstream_id_type;
signal streams_in_tvalid : std_logic_vector(c_input_streams - 1 downto 0);
signal streams_in_tready : std_logic_vector(c_input_streams - 1 downto 0);
--tready signals for dataout stream processes
signal streams_out_tready : std_logic_vector(c_output_streams - 1 downto 0);
--tready signals for dataout combinatoric combined with tstream_id
signal streams_out_tready_c : std_logic_vector(c_output_streams - 1 downto 0);
--data signal for storing stream parameters for each stream
type data_in_streams_type is array (0 to c_input_streams - 1) of data_stream;
signal data_in_streams : data_in_streams_type;
type data_out_streams_type is array (0 to c_output_streams - 1) of data_stream;
signal data_out_streams : data_out_streams_type;
--type definition of type for state machine
type sm_control_type is (IDLE, PARSE_CMD, DAB_DELAY_WRITE, DAB_DELAY_READ);
signal sm_control : sm_control_type := IDLE;
signal schedule_in_streams : integer := 0;
signal dab_delay_cnt : unsigned(1 downto 0); --delay for dab r/w
signal out_streams_enabled : std_logic_vector(c_output_streams - 1 downto 0);
signal out_streams_finished : std_logic_vector(c_output_streams - 1 downto 0);
signal in_streams_enabled : std_logic_vector(c_input_streams - 1 downto 0);
signal in_streams_finished : std_logic_vector(c_input_streams - 1 downto 0);
--component declaration stim_reader
component tb_stim_reader is
generic(
STIM_FILE_NAME : string := ""
);
port (
cmd_out : out cmd_record;
cmd_accept_in : in std_logic;
eof : out std_logic
);
end component;
--component declaration HDL_node
component dyplo_hdl_node is
port(
-- Miscellaneous
node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0);
-- DAB interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Receive data from backplane to FIFO
b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
b2f_tvalid : in std_logic;
b2f_tready : out std_logic;
-- Send data from FIFO to backplane
f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0);
f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0);
f2b_tvalid : out std_logic;
f2b_tready : in std_logic;
-- Serial fifo status info
fifo_status_sync : in std_logic;
fifo_status_flag : out std_logic;
-- fifo statuses of destination fifo's
dest_fifo_status : in std_logic_vector(3 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end component;
begin
hdl_node : dyplo_hdl_node
port map(
-- Miscellaneous
node_id => "00010", -- don't change, because of address range in simulation
-- DAB interface
dab_clk => dab_clk_i,
dab_rst => dab_rst_i,
dab_addr => dab_addr_i,
dab_sel => dab_sel_i,
dab_wvalid => dab_wvalid_i,
dab_rvalid => dab_rvalid_i,
dab_wdata => dab_wdata_i,
dab_rdata => dab_rdata_i,
-- Receive data from backplane to FIFO
b2f_tdata => b2f_tdata_i,
b2f_tstream_id => b2f_tstream_id_i,
b2f_tvalid => b2f_tvalid_i,
b2f_tready => b2f_tready_i,
-- Send data from FIFO to backplane
f2b_tdata => f2b_tdata_i,
f2b_tstream_id => f2b_tstream_id_i,
f2b_tvalid => f2b_tvalid_i,
f2b_tready => f2b_tready_i,
-- Serial fifo status info
fifo_status_sync => '0',
fifo_status_flag => open,
-- fifo statuses of destination fifo's
dest_fifo_status => dest_fifo_status_i,
-- Clock signals
user_clocks => user_clocks_i
);
stim_reader : tb_stim_reader
generic map(
STIM_FILE_NAME => "../../stimuli/control_stimuli.txt"
)
port map(
cmd_out => cmd_i,
cmd_accept_in => cmd_accept_i,
eof => eof_i
);
dab_clk <= not dab_clk after 5 ns; -- 100MHz clock
dab_rst <= '0' after 50 ns; -- Synchronous, active high reset
dab_clk_i <= dab_clk;
dab_rst_i <= dab_rst;
control : process(dab_clk)
variable stream_no : integer := 0;
variable v_value_int : integer;
variable v_value_slv : std_logic_vector(31 downto 0);
variable v_result : boolean;
variable v_result_len : integer;
variable v_string : string(1 to CMD_WORD_SIZE);
begin
if(rising_edge(dab_clk)) then
if(dab_rst = '1') then
dab_addr_i <= (others => '0');
dab_sel_i <= '0';
dab_wvalid_i <= '0';
dab_rvalid_i <= '0';
dab_wdata_i <= (others => '0');
dab_delay_cnt <= "11";
sm_control <= IDLE;
data_in_streams <= (others => ((others => NUL), 0, '0'));
data_out_streams <= (others => ((others => NUL), 0, '0'));
else
case(sm_control) is
when IDLE =>
dab_sel_i <= '0';
dab_wvalid_i <= '0';
dab_rvalid_i <= '0';
if(cmd_i.valid = true) then
sm_control <= PARSE_CMD;
else
cmd_accept_i <= '0'; --release command
end if;
when PARSE_CMD =>
if (cmd_i.word(0)(1 to 12) = "write_config") then -- dab write_control (hdl_node) command
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
proc_get_value (
str => v_string(1 to cmd_i.size(i)),
slv => v_value_slv,
result => v_result,
len => v_result_len
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
if (i=1) then --address
dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0));
elsif (i=2) then --data
dab_wdata_i <= v_value_slv(31 downto 0);
end if;
end loop;
dab_sel_i <= '1';
dab_delay_cnt <= "11";
sm_control <= DAB_DELAY_WRITE;
elsif (cmd_i.word(0)(1 to 10) = "write_data") then -- dab write_data (user_logic) command
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
proc_get_value (
str => v_string(1 to cmd_i.size(i)),
slv => v_value_slv,
result => v_result,
len => v_result_len
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
if (i=1) then --address
dab_addr_i <= "00010" & v_value_slv(15 downto 0);
elsif (i=2) then --data
dab_wdata_i <= v_value_slv(31 downto 0);
end if;
end loop;
dab_sel_i <= '1';
dab_delay_cnt <= "11";
sm_control <= DAB_DELAY_WRITE;
elsif (cmd_i.word(0)(1 to 11) = "read_config") then -- dab read_control (hdl_node) command
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
proc_get_value (
str => v_string(1 to cmd_i.size(i)),
slv => v_value_slv,
result => v_result,
len => v_result_len
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
if (i=1) then --address
dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0));
end if;
end loop;
dab_sel_i <= '1';
dab_delay_cnt <= "11";
sm_control <= DAB_DELAY_READ;
elsif (cmd_i.word(0)(1 to 9) = "read_data") then -- dab read_data (user_logic) command
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
proc_get_value (
str => v_string(1 to cmd_i.size(i)),
slv => v_value_slv,
result => v_result,
len => v_result_len
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
if (i=1) then --address
dab_addr_i <= "00010" & v_value_slv(15 downto 0);
end if;
end loop;
dab_sel_i <= '1';
dab_delay_cnt <= "11";
sm_control <= DAB_DELAY_READ;
elsif (cmd_i.word(0)(1 to 9) = "stream_in") then -- stream settings
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string := (others => NUL);
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
if(i /= 3) then
proc_str_to_int (
str => v_string(1 to cmd_i.size(i)),
int => v_value_int,
result => v_result
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
end if;
if (i=1) then --stream_no
stream_no := v_value_int;
if(stream_no >= c_input_streams) then
report "ERROR: stream_in command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_input_streams - 1)
severity failure;
else
data_in_streams(stream_no).enable <= '1';
end if;
elsif (i=2) then --length
data_in_streams(stream_no).length <= v_value_int;
elsif (i=3) then --filename
if(v_string(1) /= NUL) then
data_in_streams(stream_no).filename <= v_string;
else
report "ERROR: stream_in command: Filename cannot be empty"
severity failure;
end if;
end if;
end loop;
sm_control <= IDLE;
elsif (cmd_i.word(0)(1 to 10) = "stream_out") then -- stream settings
--read arguments
for i in 1 to (cmd_i.cnt-1) loop
v_string := (others => NUL);
v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i));
if(i /= 3) then
proc_str_to_int (
str => v_string(1 to cmd_i.size(i)),
int => v_value_int,
result => v_result
);
if not(v_result) then
report "ERROR: Unknown value!";
report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i));
report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100"
severity failure;
end if;
end if;
if (i=1) then --stream_no
stream_no := v_value_int;
if(stream_no >= c_output_streams) then
report "ERROR: stream_out command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_output_streams - 1)
severity failure;
else
data_out_streams(stream_no).enable <= '1';
end if;
elsif (i=2) then --length
data_out_streams(stream_no).length <= v_value_int;
elsif (i=3) then --filename
data_out_streams(stream_no).filename <= v_string;
end if;
end loop;
sm_control <= IDLE;
else
report "ERROR: Unknown command!";
report "Found: " & cmd_i.word(0)
severity failure;
end if;
cmd_accept_i <= '1'; -- do accept command
when DAB_DELAY_WRITE =>
if (dab_delay_cnt /= 0) then
dab_delay_cnt <= dab_delay_cnt - 1;
else
dab_wvalid_i <= '1';
sm_control <= IDLE;
end if;
when DAB_DELAY_READ =>
if (dab_delay_cnt /= 0) then
dab_delay_cnt <= dab_delay_cnt - 1;
else
dab_rvalid_i <= '1';
sm_control <= IDLE;
end if;
end case;
end if;
end if;
end process;
-- Data in streams
data_streams_in : for i in 0 to c_input_streams - 1 generate
signal words_send : integer := 0;
type sm_stream_type is (START_BURST, INTERRUPT_BURST, BURST);
signal sm_stream : sm_stream_type := START_BURST;
signal burst_cnt : integer := 0;
begin
stream_x : process(dab_clk)
file datafile : text;
variable v_file_opened : boolean := false;
variable v_data_file_status : file_open_status;
variable v_data_line : line;
variable v_data_word : string(1 to 10);
begin
if(rising_edge(dab_clk)) then
if(dab_rst = '1') then
streams_in_tdata(i) <= (others => '0');
streams_in_tstream_id(i) <= (others => '0');
streams_in_tvalid(i) <= '0';
in_streams_finished(i) <= '0';
sm_stream <= START_BURST;
else
streams_in_tstream_id(i) <= std_logic_vector(to_unsigned(i,c_hdl_stream_id_width));
if(data_in_streams(i).enable = '1' and words_send < data_in_streams(i).length) then
case(sm_stream) is
when START_BURST =>
if(v_file_opened = false) then
file_open(v_data_file_status, datafile, (string'("../../data/") & data_in_streams(i).filename), read_mode);
if not(v_data_file_status = OPEN_OK) then
report "ERROR: Unable to open data file: " & string'(data_in_streams(i).filename)
severity failure;
else
v_file_opened := true;
end if;
end if;
--read line from data file
if(not endfile(datafile)) then
str_read(datafile, v_data_word);
streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10));
streams_in_tvalid(i) <= '1';
else
report "ERROR: End of file!"
severity failure;
end if;
burst_cnt <= 0;
sm_stream <= BURST;
when BURST =>
if(streams_in_tready(i) = '1' and streams_in_tvalid(i) = '1') then
words_send <= words_send + 1;
burst_cnt <= burst_cnt + 1;
if( (words_send + 1) < data_in_streams(i).length) then
--read line from data file
if(not endfile(datafile)) then
str_read(datafile, v_data_word);
streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10));
if(burst_cnt = 63) then
streams_in_tvalid(i) <= '0';
burst_cnt <= 0;
sm_stream <= INTERRUPT_BURST;
else
streams_in_tvalid(i) <= '1';
end if;
else
file_close(datafile);
report "ERROR: End of file!"
severity failure;
end if;
else
streams_in_tvalid(i) <= '0';
in_streams_finished(i) <= '1';
file_close(datafile);
end if;
end if;
when INTERRUPT_BURST =>
streams_in_tvalid(i) <= '1';
sm_stream <= BURST;
end case;
end if;
end if;
end if;
end process;
end generate;
b2f_tdata_i <= streams_in_tdata(schedule_in_streams);
b2f_tstream_id_i <= streams_in_tstream_id(schedule_in_streams);
b2f_tvalid_i <= streams_in_tvalid(schedule_in_streams);
streams_in_tready <= (schedule_in_streams => b2f_tready_i, others => '0');
-- Data in streams
data_streams_out : for i in 0 to c_output_streams - 1 generate
signal words_received : integer := 0;
type sm_stream_type is (WAITING, BURST, END_BURST);
signal sm_stream : sm_stream_type := WAITING;
begin
stream_x : process(dab_clk)
file datafile : text;
variable v_file_opened : boolean := false;
variable v_data_file_status : file_open_status;
variable v_data_line : line;
variable v_data_word : string(1 to 10);
variable v_expected_data : std_logic_vector(31 downto 0);
begin
if(rising_edge(dab_clk)) then
if(dab_rst = '1') then
streams_out_tready(i) <= '0';
out_streams_finished(i) <= '0';
else
if(data_out_streams(i).enable = '1' and words_received < data_out_streams(i).length) then
streams_out_tready(i) <= '1';
if(data_out_streams(i).filename(1) /= NUL) then
if(v_file_opened = false) then
file_open(v_data_file_status, datafile, (string'("../../data/") & data_out_streams(i).filename), read_mode);
if not(v_data_file_status = OPEN_OK) then
report "ERROR: Unable to open data file: " & string'(data_out_streams(i).filename)
severity failure;
else
v_file_opened := true;
end if;
end if;
end if;
if(f2b_tvalid_i = '1' and streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) then
words_received <= words_received + 1;
if(data_out_streams(i).filename(1) /= NUL) then
--read line from data file
if(not endfile(datafile)) then
str_read(datafile, v_data_word);
v_expected_data := hstr_to_slv(v_data_word(3 to 10));
else
report "ERROR: End of file!"
severity failure;
end if;
assert f2b_tdata_i = v_expected_data
report "ERROR: Received data does not match expected data"
severity failure;
end if;
--read from file and data bus and check (assert)
if( (words_received + 1) = data_out_streams(i).length) then
streams_out_tready(i) <= '0';
out_streams_finished(i) <= '1';
if(data_out_streams(i).filename(1) /= NUL) then
file_close(datafile);
end if;
end if;
end if;
end if;
end if;
end if;
end process;
streams_out_tready_c(i) <= '1' when (streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) else '0';
end generate;
f2b_tready_i <= '1' when (streams_out_tready_c /= std_logic_vector(to_unsigned(0,4))) else '0';
schedule : process(dab_clk)
variable schedule_in_next : integer := 0;
begin
if(rising_edge(dab_clk)) then
if(dab_rst_i = '1') then
schedule_in_streams <= 0;
else
if(streams_in_tvalid(schedule_in_streams) = '0') then
--Schedule, next lane
schedule_in_next := schedule_in_streams;
for s in 0 to c_input_streams - 1 loop
if(schedule_in_next = c_input_streams - 1) then
schedule_in_next := 0;
else
schedule_in_next := schedule_in_next + 1;
end if;
if(streams_in_tvalid(schedule_in_next) = '1') then
exit;
end if;
end loop;
schedule_in_streams <= schedule_in_next;
--Schedule, next lane
end if;
end if;
end if;
end process;
user_clock_0 : process
begin
user_clocks_i(0) <= '0';
wait for 20 ns;
user_clocks_i(0) <= '1';
wait for 20 ns;
end process;
user_clock_1 : process
begin
user_clocks_i(1) <= '0';
wait for 15 ns;
user_clocks_i(1) <= '1';
wait for 15 ns;
end process;
user_clock_2 : process
begin
user_clocks_i(2) <= '0';
wait for 10 ns;
user_clocks_i(2) <= '1';
wait for 10 ns;
end process;
user_clock_3 : process
begin
user_clocks_i(3) <= '0';
wait for 5 ns;
user_clocks_i(3) <= '1';
wait for 5 ns;
end process;
enabled_in: for i in 0 to c_input_streams - 1 generate
begin
in_streams_enabled(i) <= data_in_streams(i).enable;
end generate enabled_in;
enabled_out: for i in 0 to c_output_streams - 1 generate
begin
out_streams_enabled(i) <= data_out_streams(i).enable;
end generate enabled_out;
p_finished: process(dab_clk)
begin
if (rising_edge(dab_clk)) then
if dab_rst_i = '0' then
if(eof_i = '1' and (out_streams_finished = out_streams_enabled and in_streams_finished = in_streams_enabled) ) then
report "*** End of simulation ***";
finish(0);
end if;
end if;
end if;
end process p_finished;
end rtl;
| gpl-2.0 |
scriptum/geany | tests/ctags/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
mbgh/aes128-hdl | src/vhdl/keyExpansion.vhd | 1 | 12251 | -------------------------------------------------------------------------------
--! @file keyExpansion.vhd
--! @brief AES-128 key expansion
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-10-30
--! @platform Simulation: ModelSim; Synthesis: Synopsys
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: keyExpansion.vhd 43 2014-10-30 12:22:52Z u59323933 $
-- Revision : $Revision: 43 $
-- Local Date : $Date: 2014-10-30 13:22:52 +0100 (Thu, 30 Oct 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-- 2014-06-10 1.1 michmueh Removed controlling FSM an replaced the
-- roundkey enables with a simple shift
-- register.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES-128 key expansion
--!
--! The present design implements the key expansion for the 128-bit version of
--! the Advanced Encryption Standard (AES). Since the design targets a
--! high-throughput implementation, the key expansion is implemented using
--! pipeline register between each roundkey calculation.
-------------------------------------------------------------------------------
entity keyExpansion is
port (
--! @brief System clock.
Clk_CI : in std_logic;
--! @brief Asynchronous, active-high reset.
Reset_RBI : in std_logic;
--! @brief Determines whether a new cipherkey has been applied or not.
--! <TABLE BORDER="0">
--! <TR><TD>0</TD><TD>...</TD><TD>No new cipherkey has been applied.</TD></TR>
--! <TR><TD>1</TD><TD>...</TD><TD>New cipherkey has been applied.</TD></TR>
--! </TABLE>
Start_SI : in std_logic;
--! @brief The cipher key (master key) for the encryption/decryption.
Cipherkey_DI : in std_logic_vector(127 downto 0);
--! @brief The generated round keys.
Roundkeys_DO : out roundkeyArrayType);
end entity keyExpansion;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture description of AES-128 key expansion.
-------------------------------------------------------------------------------
architecture Behavioral of keyExpansion is
-----------------------------------------------------------------------------
-- Type definitions
-----------------------------------------------------------------------------
type byteArrayType is array (0 to 9) of std_logic_vector(7 downto 0);
type subWordArrayType is array (0 to 9) of Word;
type expkeyArrayType is array (0 to 43) of Word;
type rconArrayType is array (0 to 9) of Word;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant RCON : byteArrayType := (
x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- purpose: Provides an exclusive-or (XOR) operation for words.
function "xor" (
left : Word;
right : Word) return Word is
variable Result : Word;
begin
Result(0) := left(0) xor right(0);
Result(1) := left(1) xor right(1);
Result(2) := left(2) xor right(2);
Result(3) := left(3) xor right(3);
return Result;
end "xor";
-- purpose: Converts a word to a std_logic_vector. The 0-th byte of the word
-- becomes the most significant byte of the std_logic_vector.
function conv_std_logic_vector (
input : Word)
return std_logic_vector is
begin -- function conv_std_logic_vector
return input(0) & input(1) & input(2) & input(3);
end function conv_std_logic_vector;
-- purpose: Converts four words (i.e., a matrix) to a std_logic_vector.
function conv_std_logic_vector (
column0 : Word;
column1 : Word;
column2 : Word;
column3 : Word)
return std_logic_vector is
begin -- function conv_std_logic_vector
return
column0(0) & column0(1) & column0(2) & column0(3) &
column1(0) & column1(1) & column1(2) & column1(3) &
column2(0) & column2(1) & column2(2) & column2(3) &
column3(0) & column3(1) & column3(2) & column3(3);
end function conv_std_logic_vector;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component subWord is
port (
In_DI : in Word;
Out_DO : out Word);
end component subWord;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- ExpKey_D: Array of 32-bit words (each made up of four bytes) holding the
-- expanded key.
signal ExpKey_DN, ExpKey_DP : expkeyArrayType;
-- SubWordIn_D: Array holding the ten inputs, each of them one 32-word wide,
-- connected to the input of the AES S-box.
signal SubWordIn_D : subWordArrayType;
-- SubWordOut_D: Array holding the ten outputs, each of them one 32-word wide,
-- connected to the output of the AES S-box.
signal SubWordOut_D : subWordArrayType;
-- Rcon_D: Array holding the ten signals after the XOR operation with the
-- round constants.
signal Rcon_D : rconArrayType;
-- Roundkeys_D: Array holding all the roundkeys produced by the key epansion.
signal Roundkeys_D : roundkeyArrayType;
-- Shift register holding the enables for the roundkey registers.
signal EnRndKeys_SN, EnRndKeys_SP : std_logic_vector(0 to 9);
-- Indicates that all roundkey registers currently hold their correct value
-- and must not be enabled (e.g., no new cipherkey is provided to the design
-- and the corresponding roundkeys have already been derived).
signal AllRndKeysDisabled_S : std_logic;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Generate the ten SubWord instances.
gen_subWords : for i in 0 to 9 generate
subWords : subWord
port map (
In_DI => SubWordIn_D(i),
Out_DO => SubWordOut_D(i));
end generate gen_subWords;
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
-- Connect the columns of the expanded key to the round key outputs.
gen_outputKeys : for i in 0 to 10 generate
Roundkeys_DO(i) <= conv_std_logic_vector(
ExpKey_DP(4*i), ExpKey_DP(4*i+1), ExpKey_DP(4*i+2), ExpKey_DP(4*i+3));
end generate gen_outputKeys;
-----------------------------------------------------------------------------
-- Connect the cipherkey to the first four columns (i.e., words) of the
-- expanded key.
-----------------------------------------------------------------------------
-- Use the first roundkey (i.e., the actual cipherkey) as the first four
-- 32-bit words of the expanded key.
ExpKey_DN(0) <= conv_word(Cipherkey_DI(127 downto 96)) when Start_SI = '1' else ExpKey_DP(0);
ExpKey_DN(1) <= conv_word(Cipherkey_DI(95 downto 64)) when Start_SI = '1' else ExpKey_DP(1);
ExpKey_DN(2) <= conv_word(Cipherkey_DI(63 downto 32)) when Start_SI = '1' else ExpKey_DP(2);
ExpKey_DN(3) <= conv_word(Cipherkey_DI(31 downto 0)) when Start_SI = '1' else ExpKey_DP(3);
-----------------------------------------------------------------------------
-- Calculation of further round key words.
-----------------------------------------------------------------------------
-- Since the "RotWord" function only performs a byte-wise rotation of a word,
-- we can perform it either before or after the "SubWord" substitution.
gen_roundKeys : for i in 0 to 9 generate
SubWordIn_D(i) <= ExpKey_DP(4*i+3);
Rcon_D(i)(0) <= SubWordOut_D(i)(1) xor RCON(i);
Rcon_D(i)(1) <= SubWordOut_D(i)(2);
Rcon_D(i)(2) <= SubWordOut_D(i)(3);
Rcon_D(i)(3) <= SubWordOut_D(i)(0);
-- Calculate the next expanded key only when the respective enable signal
-- is set.
ExpKey_DN(4*(i+1)+0) <= Rcon_D(i) xor ExpKey_DP(4*i) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+0);
ExpKey_DN(4*(i+1)+1) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+1);
ExpKey_DN(4*(i+1)+2) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) xor ExpKey_DP(4*i+2) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+2);
ExpKey_DN(4*(i+1)+3) <= Rcon_D(i) xor ExpKey_DP(4*i) xor ExpKey_DP(4*i+1) xor ExpKey_DP(4*i+2) xor ExpKey_DP(4*i+3) when EnRndKeys_SP(i) = '1' else ExpKey_DP(4*(i+1)+3);
end generate gen_roundKeys;
-----------------------------------------------------------------------------
-- Compute the next state logic for the shift register holding the enables for
-- the roundkeys.
-----------------------------------------------------------------------------
-- The enables for the roundkeys are generated by a one-hot encoded shift
-- register, which gets the start signal as an input.
EnRndKeys_SN <=
-- Start signal is set, so shift in a '1'.
'1' & EnRndKeys_SP(0 to 8) when Start_SI = '1' else
-- Since none of the roundkeys currently holds a substantial value, we do
-- not even have to shift in the zeros, but just hold the current state
-- (this might be the case when, the encryption pipeline has been emptied
-- and no encryption is going on anymore, i.e., no other plaintext blocks
-- have been provided).
EnRndKeys_SP when AllRndKeysDisabled_S = '1' else
-- Otherwise shift the enables such that they are proceeded correctly
-- together with their current pipeline stage (this enables-holding shift
-- register serves as kind of a shimming register).
'0' & EnRndKeys_SP(0 to 8);
-----------------------------------------------------------------------------
-- Compute the signal indicating that none of the roundkey registers has to
-- be updated, i.e., no new cipherkey has to be propagated through the key
-- expansion pipeline registers.
-----------------------------------------------------------------------------
pComb_CalcAllRndKeysDisabled : process (EnRndKeys_SP) is
variable tmp : std_logic;
begin -- process pComb_CalcAllRndKeysDisabled
tmp := EnRndKeys_SP(0);
for i in 1 to 9 loop
tmp := tmp or EnRndKeys_SP(i);
end loop; -- i
AllRndKeysDisabled_S <= not tmp;
end process pComb_CalcAllRndKeysDisabled;
-----------------------------------------------------------------------------
-- Flip Flops
-----------------------------------------------------------------------------
pSequ_FlipFlops : process (Clk_CI, Reset_RBI) is
begin -- process p_FlipFlops
if Reset_RBI = '0' then -- asynchronous reset (active low)
ExpKey_DP <= (others => ZERO_WORD);
EnRndKeys_SP <= (others => '0');
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
ExpKey_DP <= ExpKey_DN;
EnRndKeys_SP <= EnRndKeys_SN;
end if;
end process pSequ_FlipFlops;
end architecture Behavioral;
| gpl-2.0 |
bluecmd/hackrf | firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_ecb_tbl_testbench_192bits.vhd | 1 | 10562 | -- Twofish_ecb_tbl_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tbl_testbench192 is
end tbl_testbench192;
architecture tbl_encryption192_testbench_arch of tbl_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round192
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_tbl_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_tbl_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 50) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_encryption_circuit: twofish_encryption_round192
port map (
in1_ter192 => to_round(127 downto 96),
in2_ter192 => to_round(95 downto 64),
in3_ter192 => to_round(63 downto 32),
in4_ter192 => to_round(31 downto 0),
in_Sfirst_ter192 => Sfirst,
in_Ssecond_ter192 => Ssecond,
in_Sthird_ter192 => Sthird,
in_key_up_ter192 => key_up,
in_key_down_ter192 => key_down,
out1_ter192 => to_encr_reg128(127 downto 96),
out2_ter192 => to_encr_reg128(95 downto 64),
out3_ter192 => to_encr_reg128(63 downto 32),
out4_ter192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
tbl_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable counter : integer range 1 to 50 := 1;
variable round : integer range 0 to 16 := 0;
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(pt_f,input_data);
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Tables Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process tbl_proc;
end tbl_encryption192_testbench_arch;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_cbc_decryption_monte_carlo_testbench_256bits.vhd | 1 | 11593 | -- Twofish_cbc_decryption_monte_carlo_testbench_256bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 256 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench256 is
end cbc_decryption_monte_carlo_testbench256;
architecture cbc_decryption256_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench256 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched256
port (
odd_in_tk256,
even_in_tk256 : in std_logic_vector(7 downto 0);
in_key_tk256 : in std_logic_vector(255 downto 0);
out_key_up_tk256,
out_key_down_tk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched256
port (
in_key_twk256 : in std_logic_vector(255 downto 0);
out_K0_twk256,
out_K1_twk256,
out_K2_twk256,
out_K3_twk256,
out_K4_twk256,
out_K5_twk256,
out_K6_twk256,
out_K7_twk256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round256
port (
in1_tdr256,
in2_tdr256,
in3_tdr256,
in4_tdr256,
in_Sfirst_tdr256,
in_Ssecond_tdr256,
in_Sthird_tdr256,
in_Sfourth_tdr256,
in_key_up_tdr256,
in_key_down_tdr256 : in std_logic_vector(31 downto 0);
out1_tdr256,
out2_tdr256,
out3_tdr256,
out4_tdr256 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S256
port (
in_key_ts256 : in std_logic_vector(255 downto 0);
out_Sfirst_ts256,
out_Ssecond_ts256,
out_Sthird_ts256,
out_Sfourth_ts256 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_256bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_256bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(255 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
Sfourth,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched256
port map (
in_key_twk256 => twofish_key,
out_K0_twk256 => K0,
out_K1_twk256 => K1,
out_K2_twk256 => K2,
out_K3_twk256 => K3,
out_K4_twk256 => K4,
out_K5_twk256 => K5,
out_K6_twk256 => K6,
out_K7_twk256 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched256
port map (
odd_in_tk256 => odd_number,
even_in_tk256 => even_number,
in_key_tk256 => twofish_key,
out_key_up_tk256 => key_up,
out_key_down_tk256 => key_down
);
producing_the_Skeys: twofish_S256
port map (
in_key_ts256 => twofish_key,
out_Sfirst_ts256 => Sfirst,
out_Ssecond_ts256 => Ssecond,
out_Sthird_ts256 => Sthird,
out_Sfourth_ts256 => Sfourth
);
the_decryption_circuit: twofish_decryption_round256
port map (
in1_tdr256 => to_round(127 downto 96),
in2_tdr256 => to_round(95 downto 64),
in3_tdr256 => to_round(63 downto 32),
in4_tdr256 => to_round(31 downto 0),
in_Sfirst_tdr256 => Sfirst,
in_Ssecond_tdr256 => Ssecond,
in_Sthird_tdr256 => Sthird,
in_Sfourth_tdr256 => Sfourth,
in_key_up_tdr256 => key_up,
in_key_down_tdr256 => key_down,
out1_tdr256 => to_encr_reg128(127 downto 96),
out2_tdr256 => to_encr_reg128(95 downto 64),
out3_tdr256 => to_encr_reg128(63 downto 32),
out4_tdr256 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(255 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 256 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption256_monte_carlo_testbench_arch;
| gpl-2.0 |
zefie/hackrf | firmware/cpld/sgpio_if_passthrough/top.vhd | 14 | 1910 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
SGPIO : inout std_logic_vector(15 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : in std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
type transfer_direction is (to_sgpio, from_sgpio);
signal transfer_direction_i : transfer_direction;
begin
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
else from_sgpio;
DD <= (DD'high => '1', others => '0');
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
else (others => 'Z');
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
else (others => 'Z');
end Behavioral;
| gpl-2.0 |
bluecmd/hackrf | firmware/cpld/sgpio_if/top.vhd | 12 | 5535 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mbgh/aes128-hdl | src/vhdl/cipherRound.vhd | 1 | 3670 | -------------------------------------------------------------------------------
--! @file cipherRound.vhd
--! @brief AES-128 single cipher round
--! @project VLSI Book - AES-128 Example
--! @author Michael Muehlberghuber ([email protected])
--! @company Integrated Systems Laboratory, ETH Zurich
--! @copyright Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
--! @date 2014-06-05
--! @updated 2014-06-05
--! @platform Simulation: ModelSim; Synthesis: Synopsys, Xilinx XST/Vivado
--! @standard VHDL'93/02
-------------------------------------------------------------------------------
-- Revision Control System Information:
-- File ID : $Id: cipherRound.vhd 6 2014-06-12 12:49:55Z u59323933 $
-- Revision : $Revision: 6 $
-- Local Date : $Date: 2014-06-12 14:49:55 +0200 (Thu, 12 Jun 2014) $
-- Modified By : $Author: u59323933 $
-------------------------------------------------------------------------------
-- Major Revisions:
-- Date Version Author Description
-- 2014-06-05 1.0 michmueh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.aes128Pkg.all;
-------------------------------------------------------------------------------
--! @brief AES-128 single cipher round
--!
--! Implements a single cipher round of the AES-128 encryption algorithm, which
--! can then be instantiated multiple times in order to create a high-throughput
--! architecture.
-------------------------------------------------------------------------------
entity cipherRound is
port (
--! @brief The internal state of AES being applied to this round.
StateIn_DI : in Matrix;
--! @brief The roundkey to be used for the current AES round.
Roundkey_DI : in std_logic_vector(127 downto 0);
--! @brief The resulting state of AES after applying this round.
StateOut_DO : out Matrix);
end entity cipherRound;
-------------------------------------------------------------------------------
--! @brief Behavioral architecture description of a single AES round.
-------------------------------------------------------------------------------
architecture Behavioral of cipherRound is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component subMatrix is
port (
In_DI : in Matrix;
Out_DO : out Matrix);
end component subMatrix;
component mixMatrix is
port (
In_DI : in Matrix;
Out_DO : out Matrix);
end component mixMatrix;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal SubMatrixOut_D : Matrix; -- State after "SubMatrix".
signal ShiftRowsOut_D : Matrix; -- State after "ShiftRows".
signal MixMatrixOut_D : Matrix; -- State after "MixColumns".
begin -- architecture Behavioral
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
subMatrix_1 : subMatrix
port map (
In_DI => StateIn_DI,
Out_DO => SubMatrixOut_D);
mixMatrix_1 : entity work.mixMatrix
port map (
In_DI => ShiftRowsOut_D,
Out_DO => MixMatrixOut_D);
ShiftRowsOut_D <= shift_rows(SubMatrixOut_D);
StateOut_DO <= MixMatrixOut_D xor Roundkey_DI;
end architecture Behavioral;
| gpl-2.0 |
freecores/twofish | vhdl/twofish_testbenches_secondary_circuits.vhd | 1 | 3119 | -- Twofish_testbenches_secondary_circuits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file contains all the secondary circuits that are needed for running the testbenches
--
--
-- reg128
--
library ieee;
use ieee.std_logic_1164.all;
entity reg128 is
port ( in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128,clk_reg128 : in std_logic
);
end reg128;
architecture reg128_arch of reg128 is
begin
clk_proc: process(clk_reg128, reset_reg128,enable_reg128)
variable internal_state : std_logic_vector(127 downto 0);
begin
if reset_reg128 = '1' then
internal_state := ( others => '0' );
elsif (clk_reg128'event and clk_reg128 = '1') then
if enable_reg128='1' then
internal_state := in_reg128;
else
internal_state := internal_state;
end if;
end if;
out_reg128 <= internal_state;
end process clk_proc;
end reg128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- mux128
--
library ieee;
use ieee.std_logic_1164.all;
entity mux128 is
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end mux128;
architecture mux128_arch of mux128 is
begin
with selection_mux128 select
out_mux128 <= in1_mux128 when '0',
in2_mux128 when others;
end mux128_arch;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
-- --
-- new component --
-- --
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--
-- demux128
--
library ieee;
use ieee.std_logic_1164.all;
entity demux128 is
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end demux128;
architecture demux128_arch of demux128 is
begin
demux_proc: process(in_demux128, selection_demux128)
begin
if selection_demux128 = '0' then
out1_demux128 <= in_demux128;
else
out2_demux128 <= in_demux128;
end if;
end process demux_proc;
end demux128_arch;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/uart/uart2.in.vhd | 6 | 128 | -- UART 2
constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmulru.vhd | 1 | 6015 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulru
-- File: mmulru.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulru is
generic (
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end mmulru;
architecture rtl of mmulru is
constant entries_log : integer := log2(entries);
component mmulrue
generic (
position : integer;
entries : integer := 8
);
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type
);
end component;
type lru_rtype is record
bar : std_logic_vector(1 downto 0);
clear : std_logic_vector(M_ENT_MAX-1 downto 0);
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
signal c,r : lru_rtype;
signal lruei : mmulruei_a (entries-1 downto 0);
signal lrueo : mmulrueo_a (entries-1 downto 0);
begin
p0: process (rst, r, lrui, lrueo)
variable v : lru_rtype;
variable reinit : std_logic;
variable pos : std_logic_vector(entries_log-1 downto 0);
variable touch : std_logic;
begin
v := r;
-- #init
reinit := '0';
--# eather element in luri or element 0 to top
pos := lrui.pos(entries_log-1 downto 0);
touch := lrui.touch;
if (lrui.touchmin) = '1' then
pos := lrueo(0).pos(entries_log-1 downto 0);
touch := '1';
end if;
for i in entries-1 downto 0 loop
lruei(i).pos <= (others => '0'); -- this is really ugly ...
lruei(i).left <= (others => '0');
lruei(i).right <= (others => '0');
lruei(i).pos(entries_log-1 downto 0) <= pos;
lruei(i).touch <= touch;
lruei(i).clear <= r.clear((entries-1)-i); -- reverse order
lruei(i).flush <= lrui.flush;
end loop;
lruei(entries-1).fromleft <= '0';
lruei(entries-1).fromright <= lrueo(entries-2).movetop;
lruei(entries-1).right(entries_log-1 downto 0) <= lrueo(entries-2).pos(entries_log-1 downto 0);
for i in entries-2 downto 1 loop
lruei(i).left(entries_log-1 downto 0) <= lrueo(i+1).pos(entries_log-1 downto 0);
lruei(i).right(entries_log-1 downto 0) <= lrueo(i-1).pos(entries_log-1 downto 0);
lruei(i).fromleft <= lrueo(i+1).movetop;
lruei(i).fromright <= lrueo(i-1).movetop;
end loop;
lruei(0).fromleft <= lrueo(1).movetop;
lruei(0).fromright <= '0';
lruei(0).left(entries_log-1 downto 0) <= lrueo(1).pos(entries_log-1 downto 0);
if not (r.bar = lrui.mmctrl1.bar) then
reinit := '1';
end if;
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (reinit = '1') then
v.bar := lrui.mmctrl1.bar;
v.clear := (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
v.clear(1 downto 0) := "11"; -- reverse order
when "10" =>
v.clear(2 downto 0) := "111"; -- reverse order
when "11" =>
v.clear(4 downto 0) := "11111"; -- reverse order
when others =>
v.clear(0) := '1';
end case;
end if;
--# drive signals
lruo.pos <= lrueo(0).pos;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.bar <= lrui.mmctrl1.bar;
r.clear <= (others => '0');
case lrui.mmctrl1.bar is
when "01" =>
r.clear(1 downto 0) <= "11"; -- reverse order
when "10" =>
r.clear(2 downto 0) <= "111"; -- reverse order
when "11" =>
r.clear(4 downto 0) <= "11111"; -- reverse order
when others =>
r.clear(0) <= '1';
end case;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r.bar <= mmctrl_type1_none.bar;
r.clear <= (others => '0');
r.clear(0) <= '1';
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
--# lru entries
lrue0: for i in entries-1 downto 0 generate
l1 : mmulrue
generic map ( position => i,
entries => entries )
port map (rst, clk, lruei(i), lrueo(i));
end generate lrue0;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/esa/pci/pci_arb.vhd | 4 | 18127 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
--============================================================================--
-- Design unit : pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - nested round-robbing in two different priority levels
-- - priority assignment hard-coded or APB-programmable
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : Numbering for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
-- The arbiter considers strong signal levels ('1' and '0')
-- only. Weak levels ('H', 'L') are not considered. The
-- appropriate translation function (to_X01) must be applied
-- to the inputs. This is usually done by the pads,
-- and therefore not contained in this model.
--
-- Configuration: The arbiter can be configured to NB_AGENTS = 4, 8, 16 or 32.
-- A priority level (0 = high, 1 = low) is assigned to each device.
-- Exception is agent NB_AGENTS-1, which has always lowest priority.
--
-- a) The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- The constant ARB_LVL_C must then be set to appropriate values.
--
-- b) When APB_PRIOS = true, the levels are programmable via the
-- APB-address 0x80 (allows to be ored with the PCI interface):
-- Bit 31 (leftmost) = master 31 . . bit 0 (rightmost) = master 0.
-- Bit NB_AGENTS-1 is dont care at write and reads 1.
-- Bits NB_AGENTS to 31, if existing, are dont care and read 0.
-- The constant ARB_LVL_C is then the reset value.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by two nested round-robbing loops.
-- An agent number and a priority level is assigned to each agent.
-- The agent number determines, the pair of req_n/gnt_n lines.
-- Agents are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level 1 as a group have access
-- equal to each agent of level 0.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : LEON config package
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
-- Copyright (C): European Space Agency (ESA) 2002.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.5e on Linux RedHat 7.2
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R. W. 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
-- 0.3 R. Weigand 2002/03/19 Default assignment to owneri in find_next
-- 1.0 RW. 2002/04/08 Implementation of TMR registers
-- Removed recursive function call
-- Fixed ARB_LEVELS = 2
-- 3.0 R. Weigand 2002/04/16 Released for leon2
-- 4.0 M. Isomaki 2004/10/19 Minor changes for GRLIB integration
-- 4.1 J.Gaisler 2004/11/17 Minor changes for GRLIB integration
--$Log$
-- Revision 3.1 2002/07/31 13:22:09 weigand
-- Bugfix for cases where no valid request in level 0 (level 1 was not rearbitrated)
--
-- Revision 3.0 2002/07/24 12:19:38 weigand
-- Installed RCS with version 3.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library esa;
use esa.pci_arb_pkg.all;
entity pci_arb is
generic(NB_AGENTS : integer := 4;
ARB_SIZE : integer := 2;
APB_EN : integer := 1
);
port (clk : in clk_type; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in EAPB_Slv_In_Type; -- APB inputs
pbo : out EAPB_Slv_Out_Type -- APB outputs
);
end pci_arb;
architecture rtl of pci_arb is
subtype agent_t is std_logic_vector(ARB_SIZE-1 downto 0);
subtype arb_lvl_t is std_logic_vector(NB_AGENTS-1 downto 0);
subtype agentno_t is integer range 0 to NB_AGENTS-1;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in level 1
-- Example: x010 = prio 0 for agent 2 and 0, prio 1 for agent 3 and 1.
-- Default: start with all devices equal priority at level 1.
constant ARB_LVL_C : arb_lvl_t := (others => '1');
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
--Necessary definitions from amba.vhd and iface.vhd
--added to pci_arb package with modified names to avoid
--name clashes in GRLIB
constant APB_PRIOS : boolean := APB_EN = 1;
signal owner0, owneri0 : agent_t; -- current owner in level 0
signal owner1, owneri1 : agent_t; -- current owner in level 1
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : std_logic_vector(3 downto 0); -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t; -- := ARB_LVL_C; -- level registers
type nmstarr is array (0 to 3) of agentno_t;
type nvalarr is array (0 to 3) of boolean;
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner0, owner1, req_n, rearb, tout, turn, frame_n,
arb_lvl, rst_n)
variable owner0v, owner1v : agentno_t; -- integer variables for current owner
variable new_request : agentno_t; -- detected request
variable nmst : nmstarr;
variable nvalid : nvalarr;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri0 <= owner0;
owneri1 <= owner1;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
owner0v := conv_integer(owner0);
owner1v := conv_integer(owner1);
new_request := conv_integer(cown);
nvalid(0 to 3) := (others => false);
nmst(0 to 3) := (others => 0);
-- Determine next request in both priority levels
rob : for i in NB_AGENTS-1 downto 0 loop
-- consider all masters with valid request
if req_n(i) = '0' then
-- next in prio level 0
if arb_lvl(i) = '0' then
if i > owner0v then
nmst(0) := i; nvalid(0) := true;
elsif i < owner0v then
nmst(1) := i; nvalid(1) := true;
end if;
-- next in prio level 1
elsif arb_lvl(i) = '1' then
if i > owner1v then
nmst(2) := i; nvalid(2) := true;
elsif i < owner1v then
nmst(3) := i; nvalid(3) := true;
end if;
end if; -- arb_lvl
end if; -- req_n
end loop rob;
-- select new master
if nvalid(0) then -- consider level 0 before wrap
new_request := nmst(0);
owner0v := nmst(0);
-- consider level 1 only once, except when no request in level 0
elsif owner0v /= NB_AGENTS-1 or not nvalid(1) then
if nvalid(2) then -- level 1 before wrap
new_request := nmst(2);
owner0v := NB_AGENTS-1;
owner1v := nmst(2);
elsif nvalid(3) then -- level 1 after wrap
new_request := nmst(3);
owner0v := NB_AGENTS-1;
owner1v := nmst(3);
end if;
elsif nvalid(1) then -- level 0 after wrap
new_request := nmst(1);
owner0v := nmst(1);
end if;
owneri0 <= conv_std_logic_vector(owner0v, ARB_SIZE);
owneri1 <= conv_std_logic_vector(owner1v, ARB_SIZE);
-- rearbitration if any request asserted & different from current owner
if conv_integer(cown) /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= conv_std_logic_vector(new_request, ARB_SIZE);
touti <= "0000"; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= "1111";
elsif frame_n = '1' then -- request, but no transaction
if tout = "1111" then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= "0000"; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = conv_integer(cown) and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
-- synchronous reset
if rst_n = '0' then
touti <= "0000";
cowni <= (others => '0');
owneri0 <= (others => '0');
owneri1 <= (others => '0');
rearbi <= '0';
turni <= '0';
new_request := 0;
end if;
end process arbiter;
arb_lvl(NB_AGENTS-1) <= '1'; -- always prio 1.
fixed_prios : if not APB_PRIOS generate -- assign constant value
arb_lvl(NB_AGENTS-2 downto 0) <= ARB_LVL_C(NB_AGENTS-2 downto 0);
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl, prst_n
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl, prst_n)
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80
if pbi.PADDR(7 downto 0) = "10000000" and pbi.PSEL = '1' then -- address select
if (pbi.PWRITE and pbi.PENABLE) = '1' then -- APB write
arb_lvli <= pbi.PWDATA(NB_AGENTS-1 downto 0);
end if;
pbo.PRDATA(NB_AGENTS-1 downto 0) <= arb_lvl;
end if;
-- synchronous reset
if prst_n = '0' then
arb_lvli <= ARB_LVL_C; -- assign default value
end if;
end process config;
-- APB registers
apb_regs : process (pclk)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if pclk'event and pclk = '1' then -- '
arb_lvl(NB_AGENTS-2 downto 0) <= arb_lvli(NB_AGENTS-2 downto 0);
end if;
end process apb_regs;
end generate apbgen;
-- PCI registers
regs0 : process (clk)
begin -- process regs
if clk'event and clk = '1' then -- '
tout <= touti;
owner0 <= owneri0;
owner1 <= owneri1;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/misc/ahbstat.in.vhd | 6 | 144 | -- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de0-nano/config.vhd | 1 | 6412 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/adqsin.vhd | 6 | 1455 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsin is
port(
dqs_pad : in std_logic; -- DQS pad
dqsn_pad : in std_logic; -- DQSN pad
dqs : out std_logic
);
end;
architecture rtl of adqsin is
component stratixiii_io_ibuf IS
generic (
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "z";
lpm_type : string := "stratixiii_io_ibuf"
);
port (
i : in std_logic := '0';
ibar : in std_logic := '0';
o : out std_logic
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_buf : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- In buffer (DQS, DQSN) ------------------------------------------------------------
dqs_buf0 : stratixiii_io_ibuf
generic map(
differential_mode => "true",
bus_hold => "false",
simulate_z_as => "z",
lpm_type => "stratixiii_io_ibuf"
)
port map(
i => dqs_pad,
ibar => dqsn_pad,
o => dqs_buf
);
dqs <= dqs_buf;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/libiu.vhd | 1 | 8958 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
constant cctrl_none : cctrltype := (
burst => '0', dfrz => '0', ifrz => '0', dsnoop => '0',
dcs => (others => '0'), ics => (others => '0')
);
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
fline : std_logic_vector(31 downto 3); -- flush line offset
nobpmiss : std_ulogic; -- Predicted instruction, block hold
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
cstat : l3_cstat_type;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
hit : std_ulogic;
cstat : l3_cstat_type;
wbhold : std_ulogic;
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15 := 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
tbo_2p : in tracebuf_2p_out_type;
tbi_2p : out tracebuf_2p_in_type;
sclk : in std_ulogic
);
end component;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/mig.in.vhd | 4 | 374 | -- Xilinx MIG
constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-nuhorizons-3s1500/testbench.vhd | 1 | 13672 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8+8*CFG_MCTRL_RAM16BIT; -- rom data width (8/16)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal flash_d : std_logic_vector(15 downto 0);
signal romsn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal ereset : std_logic;
signal led : std_logic_vector(8 downto 1);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal ba : std_logic_vector(3 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal pb_sw : std_logic_vector(4 downto 1);
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_en : std_ulogic;
signal lcd_backl: std_ulogic;
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal smsc_addr : std_logic_vector(21 downto 0);
signal smsc_data : std_logic_vector(31 downto 0);
signal smsc_nbe : std_logic_vector(3 downto 0);
signal smsc_resetn : std_ulogic;
signal smsc_ardy : std_ulogic;
signal smsc_intr : std_ulogic;
signal smsc_nldev : std_ulogic;
signal smsc_nrd : std_ulogic;
signal smsc_nwr : std_ulogic;
signal smsc_ncs : std_ulogic;
signal smsc_aen : std_ulogic;
signal smsc_lclk : std_ulogic;
signal smsc_wnr : std_ulogic;
signal smsc_rdyrtn : std_ulogic;
signal smsc_cycle : std_ulogic;
signal smsc_nads : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1'; error <= led(8); sa(14 downto 12) <= "000";
pb_sw <= rst & "00" & dsubre;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (pb_sw, clk, led, address(21 downto 1), flash_d,
sa(11 downto 0), sd, ba, sddqm, sdclk, sdcke, sdcsn, sdwen, sdrasn,
sdcasn, txd1, rxd1, open, gnd, dsutx, dsurx, open, gnd,
oen, writen, romsn, open, vcc, open, open,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, emdc, gnd, ereset, gpio,
-- lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_backl,
can_txd, can_rxd,
smsc_addr(14 downto 0), smsc_data, smsc_nbe, smsc_resetn, smsc_ardy,-- smsc_intr,
smsc_nldev, smsc_nrd, smsc_nwr, smsc_ncs, smsc_aen, smsc_lclk,
smsc_wnr, smsc_rdyrtn, smsc_cycle, smsc_nads);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => ba(1 downto 0), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => ba(3 downto 2), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
rom8 : if romwidth /= 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= flash_d(15);
end generate;
rom16 : if romwidth = 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= '0';
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
flash_d <= buskeep(flash_d) after 5 ns;
sd <= buskeep(sd) after 5 ns;
smsc_data <= buskeep(smsc_data) after 5 ns;
smsc_addr(21 downto 15) <= (others => '0');
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), smsc_data,
smsc_ncs, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/grlib/util/debug.in.vhd | 6 | 76 | -- GRLIB debugging
constant CFG_DUART : integer := CONFIG_DEBUG_UART;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/sim/phy.vhd | 1 | 24640 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 10 ns when rmii = 1 else
not int_clk after 4 ns when r.ctrl.speedsel = "01" else
not int_clk after 20 ns when r.ctrl.speedsel = "10" else
not int_clk after 200 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 20 ns when r.ctrl.speedsel = "10" else
not clkslow after 200 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '1'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
if rmii = 0 then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_dv <= '1'; rx_er <= '1'; --unused should not affect anything
rx_col <= '0'; rx_crs <= tx_en;
if tx_en = '0' then
rxd(1 downto 0) <= "00";
else
rxd(1 downto 0) <= txd(1 downto 0);
end if;
if rgmii = 1 then
if (gtx_clk = '1' and tx_en = '0') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
rx_clk <= '0'; tx_clk <= '0';
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0'; rx_er <= '0';
rxd <= (others => '0');
if rgmii = 1 then
if (gtx_clk = '1') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
if rmii = 0 then
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
end if;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml501/svga2ch7301c.vhd | 3 | 10231 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/odpad.vhd | 1 | 5741 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: odpad
-- File: odpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity odpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of odpad is
signal gnd, oen, padx : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= gnd
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
igl2 : if (tech = igloo2) generate
x0 : igloo2_toutpad port map (pad, gnd, oen);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
um : if (tech = umc) generate
x0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_toutpad generic map(level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (level, slew, voltage, strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (strength)
port map (padx, gnd, oen, open);
pad <= padx;
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen,cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10),
cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity odpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of odpadv is
begin
v : for j in width-1 downto 0 generate
x0 : odpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/cachemem.vhd | 1 | 22317 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic;
testin: in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of cachemem is
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant DSNOOPFAST : boolean := (dsnoop = 2) or (dsnoop = 6);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+---+--------+-----+-------+
-- | LRR | LOCK_BIT |PAR| MMUCTX | TAG | VALID |
-- +-----+----------+---+--------+-----+-------+
-- [opt] [ opt ] [ ] [ opt ] [ ]
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + ICLOCK_BIT + MMUCTX_BITS
;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + DCLOCK_BIT + MMUCTX_BITS
;
constant IDWIDTH : natural := 32
;
constant DDWIDTH : natural := 32
;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant DTLRR_BIT_POS : natural := DTWIDTH-DLRR_BIT; -- if DTLRR_BIT=0 discard (pos DTWIDTH)
constant DTLOCK_BIT_POS : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT); -- if DTCLOCK_BIT=0 but DTLRR_BIT=1 lrr will overwrite
constant DTMMU_VEC_U : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT
)-1;
constant DTMMU_VEC_D : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT+
MMUCTX_BITS);
constant ITLRR_BIT_POS : natural := ITWIDTH-ILRR_BIT; -- if DLRR_BIT=0 discard (pos DTWIDTH)
constant ITLOCK_BIT_POS : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT); -- if DCLOCK_BIT=0 but DLRR_BIT=1 lrr will overwrite
constant ITMMU_VEC_U : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT
)-1;
constant ITMMU_VEC_D : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT+
MMUCTX_BITS);
constant DPTAG_RAM_BITS : integer := DPTAG_BITS
;
constant DTAG_RAM_BITS : integer := DTAG_BITS
;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype dddatain_vector is std_logic_vector(DDWIDTH-1 downto 0);
type dddatain_type is array (0 to MAXSETS-1) of dddatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdatainx : itdatain_type;
signal itdatain_cmp : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatainx : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatain_cmp : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr3 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatainx : dtdatain_type;
signal dtdatain_cmp : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : dddatain_type;
signal dddatainx : dddatain_type;
signal dddatain_cmp : dddatain_type;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(clk, crami, dtdataout2, dtdataout3
)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : dddatain_type;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)(DTMMU_VEC_U downto DTMMU_VEC_D) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTLOCK_BIT_POS) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
if drepl = lrr then
vdtdatain(i)(DTLRR_BIT_POS) := crami.dcramin.tag(i)(CTAG_LRRPOS);
end if;
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (crami.dcramin.flush(i) = '1') then
vdtdatain(i) := (others => '0');
vdtdatain(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to DSETS-1 loop
vdtdatain2(i) := (others => '0');
vdddatain(i)(31 downto 0) := crami.dcramin.data(i);
vdtdatain2(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain2(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain2(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end loop;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
if DSNOOPSEP and (crami.dcramin.flush(i) = '1') then
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"F3";
vdtdatain3(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain3(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)(ITMMU_VEC_U downto ITMMU_VEC_D) := crami.icramin.ctx;
end if;
vitdatain(i)(ITLOCK_BIT_POS) := crami.icramin.tag(i)(CTAG_LOCKPOS);
if irepl = lrr then
vitdatain(i)(ITLRR_BIT_POS) := crami.icramin.tag(i)(CTAG_LRRPOS);
end if;
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW)
& crami.icramin.tag(i)(ilinesize-1 downto 0);
if (crami.icramin.flush = '1') then
vitdatain(i) := (others => '0');
vitdatain(i)(ITAG_BITS-1 downto ITAG_BITS-8) := X"FF";
vitdatain(i)(ITAG_BITS-9 downto ITAG_BITS-10) := conv_std_logic_vector(i,2);
vitdatain(i)(ITAG_BITS-11 downto ITAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
-- pragma translate_off
itdatainx <= vitdatain; iddatainx <= viddatain;
dtdatainx <= vdtdatain; dddatainx <= vdddatain;
-- pragma translate_on
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dddatain <= vdddatain;
dtdatain3 <= vdtdatain3;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
dtaddr3 <= crami.dcramin.faddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH, testen, memtest_vlen)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i), testin
);
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH, testen, memtest_vlen)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i), testin
);
itdataout(i)(ITWIDTH) <= '0';
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32, testen, memtest_vlen)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write, testin
);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH, testen, memtest_vlen)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i), testin
);
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if not DSNOOPSEP generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i), testin
);
end generate;
end generate;
-- virtual address snoop case
mdt1 : if DSNOOPSEP generate
slow : if not DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout(i)(DTWIDTH-1 downto dlinesize-1), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout2(i)(DTWIDTH-1 downto dlinesize-1), dtenable2(i), dtwrite2(i), testin
);
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, testen, memtest_vlen) port map (
clk, dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i),
testin
);
end generate;
end generate;
fast : if DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_2p
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, 0, 1, testen, 0, memtest_vlen) port map (
clk, dtenable(i), dtaddr, dtdataout(i)(DTWIDTH-1 downto dlinesize-1),
sclk, dtwrite2(i), dtaddr3, dtdatain(i)(DTWIDTH-1 downto dlinesize-1), testin
);
dtags1 : syncram_2p
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, 0, 1, testen, 0, memtest_vlen) port map (
sclk, dtenable2(i), dtaddr2, dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
clk, dtwrite3(i), dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
testin
);
end generate;
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH, testen, memtest_vlen)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i), testin
);
dtdataout(i)(DTWIDTH) <= '0';
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0)(31 downto 0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1)(31 downto 0);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32, testen, memtest_vlen)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write, testin
);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITLRR_BIT_POS);
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITLOCK_BIT_POS);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)(ITMMU_VEC_U downto ITMMU_VEC_D);
end generate;
noictx : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
cramo.icramo.ctx(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
-- cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= (others => dtdataout(i)(dlinesize-1));
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTLRR_BIT_POS);
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTLOCK_BIT_POS);
dctx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)(DTMMU_VEC_U downto DTMMU_VEC_D);
end generate;
nodctx : if mmuen = 0 generate
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
stagv : if DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
stagp : if not DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
noilr: if ilram=0 generate
ildataout <= (others => '0');
end generate;
nodlr: if dlram=0 generate
ldataout <= (others => '0');
end generate;
end ;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep3sl150/config.vhd | 1 | 6714 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-ep1c20/leon3mp.vhd | 1 | 21191 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 25 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
iosn : out std_ulogic;
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal lclk, lclkout : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal dsubre : std_ulogic;
component clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic;
clkn : out std_logic;
sdclk : out std_logic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; --cgi.pllref <= lclk; --pllref; -- clk; --'0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkout_pad : outpad generic map (tech => padtech, slew => 1) port map (clkout, lclkout);
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clkgen0 : clkgen_ep1c20board
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, CFG_CLK_NOFB)
port map (lclk, lclkout, clkm, open, sdclkl, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo2.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo2.sdcsn(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
----
----
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP1C20 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/toutpad.vhd | 1 | 7228 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_toutpad port map (pad, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
saed : if (tech = saed32) generate
u0 : saed32_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhs : if (tech = rhs65) generate
u0 : rhs65_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
u0 : dare_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
u0 : ut90nhbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), cfgi);
end generate;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-terasic-de4/grlib_config.vhd | 2 | 2900 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 32;
-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
-- The value of CFG_AHB_ACDM is assigned to the constant CORE_ACDM in the
-- grlib.amba package. Note that this setting is separate from the ACDM setting
-- of the AHBCTRL core (which is set directly via a AHBCTRL VHDL generic).
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
grlib_techmap_testin_extra => 0,
grlib_sync_reset_enable_all => 0,
grlib_async_reset_enable => 0,
others => 0);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd | 1 | 9285 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
ddr0: ddrram
generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml501/ahbrom.vhd | 15 | 5978 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 272;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800006";
when 16#00030# => romdata <= X"033FFC00";
when 16#00031# => romdata <= X"82106100";
when 16#00032# => romdata <= X"0539A81B";
when 16#00033# => romdata <= X"8410A260";
when 16#00034# => romdata <= X"C4204000";
when 16#00035# => romdata <= X"3D1003FF";
when 16#00036# => romdata <= X"BC17A3E0";
when 16#00037# => romdata <= X"9C27A060";
when 16#00038# => romdata <= X"03100000";
when 16#00039# => romdata <= X"81C04000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000000";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000000";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-digilent-nexys4ddr/dprc_fir_demo/fir_v2.vhd | 4 | 4971 | ------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v2.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 2) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, fill_sh, running, step);
type sh_type is array (0 to 9) of unsigned(7 downto 0);
type regs is record
state : fsm_state;
sh : sh_type;
cdata : unsigned(8 downto 0);
acc : unsigned(31 downto 0);
citer : unsigned(4 downto 0);
start : std_logic;
end record;
signal reg, reg_in : regs;
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
out_data <= std_logic_vector(reg.acc);
comb_proc: process(reg, start, in_data)
variable vreg : regs;
begin
vreg := reg;
in_data_read <= '0';
out_data_write <= '0';
case vreg.state is
when idle =>
if vreg.start='1' then
vreg.state := fill_sh;
in_data_read <= '1';
end if;
vreg.cdata := (others=>'0');
vreg.acc := (others=>'0');
vreg.citer := (others=>'0');
when fill_sh =>
if vreg.citer=9 then
vreg.state := running;
vreg.citer := (others=>'0');
else
in_data_read <= '1';
vreg.citer := vreg.citer + 1;
end if;
for i in 9 downto 1 loop --shift
vreg.sh(i) := vreg.sh(i-1);
end loop;
vreg.sh(0) := unsigned(in_data(7 downto 0));
when running =>
if vreg.citer=9 then
vreg.state := step;
in_data_read <= '1';
end if;
vreg.acc := vreg.acc + (vreg.sh(to_integer(vreg.citer))*coeff(to_integer(vreg.citer)));
vreg.citer := vreg.citer + 1;
when step =>
if vreg.cdata=90 then
vreg.state := idle;
else
vreg.state := running;
vreg.cdata := vreg.cdata + 1;
vreg.citer := (others=>'0');
vreg.acc := (others=>'0');
for i in 9 downto 1 loop --shift
vreg.sh(i) := vreg.sh(i-1);
end loop;
vreg.sh(0) := unsigned(in_data(7 downto 0));
end if;
out_data_write <= '1';
end case;
vreg.start := start;
reg_in <= vreg;
end process;
reg_proc: process(clk,rst)
begin
if (rst='1') then
reg.state <= idle;
for i in 0 to 9 loop
reg.sh(i) <= (others=>'0');
end loop;
reg.cdata <= (others=>'0');
reg.acc <= (others=>'0');
reg.citer <= (others=>'0');
reg.start <= '0';
elsif rising_edge(clk) then
reg <= reg_in;
end if;
end process;
end fir_rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ahb2avl_async_be.vhd | 1 | 10973 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async_be
-- File: ahb2avl_async_be.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Avalon clock domain part of ahb2avl_async
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end;
architecture rtl of ahb2avl_async_be is
constant avlbl: integer := (burstlen*32) / avldbits;
constant onev: std_logic_vector(15 downto 0) := (others => '1');
type be_state is (idle,acc1,acc2,rdwait);
type be_regs is record
req1,req2 : ddr_request_type;
start1,start2: std_ulogic;
resp: ddr_response_type;
s: be_state;
ramaddr: std_logic_vector(log2(avlbl)-1 downto 0);
beginburst: std_ulogic;
wr: std_ulogic;
rd: std_ulogic;
reading: std_ulogic;
rdata_valid_prev: std_ulogic;
wmaskmode: std_ulogic;
rstarted: std_ulogic;
end record;
signal r,nr: be_regs;
begin
comb: process(r,rst,request,start_tog,avlso,wbrdata)
variable v: be_regs;
variable vstart: std_logic;
variable vreq: ddr_request_type;
variable startmask,endmask,mask,mask16,mask8: std_logic_vector(avldbits/8-1 downto 0);
variable ad32: std_logic_vector(3 downto 2);
variable nwmaskmode: std_ulogic;
variable rbw: std_ulogic;
variable slvi: ddravl_slv_in_type;
variable rddone: std_ulogic;
variable inc_ramaddr: std_ulogic;
variable aendaddr: std_logic_vector(9 downto 0);
begin
v := r;
slvi := ddravl_slv_in_none;
slvi.burstbegin := r.beginburst;
slvi.addr(avlabits-1 downto log2(avlbl)) :=
vreq.startaddr(avlabits-1-log2(avlbl)+log2(burstlen*4) downto log2(burstlen*4));
slvi.addr(log2(avlbl)-1 downto 0) := r.ramaddr;
slvi.wdata(avldbits-1 downto 0) := wbrdata;
slvi.write_req := r.wr;
slvi.size := std_logic_vector(to_unsigned(avlbl, slvi.size'length));
-- fix for accesses wider than 32-b word
aendaddr := request.endaddr; --(log2(4*burstlen)-1 downto 2);
if request.hsize(1 downto 0)="11" and request.hio='0' then
aendaddr(2):='1';
end if;
if ahbbits > 64 and request.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbbits > 128 and request.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
v.req1 := request;
v.req1.endaddr := aendaddr;
v.req2 := r.req1;
v.start1 := start_tog;
v.start2 := r.start1;
vstart:=r.start2; vreq:=r.req2;
if nosync /= 0 then vstart:=start_tog; vreq:=r.req1; end if;
startmask := (others => '1'); endmask := (others => '1');
mask16 := (others => '1'); mask8 := (others => '1');
case avldbits is
when 32 =>
if vreq.startaddr(1)='0' then mask16:="1100"; else mask16:="0011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010"; else mask8:="0101"; end if;
when 64 =>
if vreq.startaddr(2)='0' then startmask:="11111111";
else startmask:="00001111";
end if;
if vreq.endaddr(2)='0' then endmask:="11110000";
else endmask:="11111111";
end if;
if vreq.startaddr(1)='0' then mask16:="11001100"; else mask16:="00110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010"; else mask8:="01010101"; end if;
when 128 =>
ad32 := vreq.startaddr(3 downto 2);
case ad32 is
when "00" => startmask:="1111111111111111";
when "01" => startmask:="0000111111111111";
when "10" => startmask:="0000000011111111";
when others => startmask:="0000000000001111";
end case;
ad32 := vreq.endaddr(3 downto 2);
case ad32 is
when "00" => endmask:="1111000000000000";
when "01" => endmask:="1111111100000000";
when "10" => endmask:="1111111111110000";
when others => endmask:="1111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="1100110011001100"; else mask16:="0011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010101010101010"; else mask8:="0101010101010101"; end if;
when 256 =>
case vreq.startaddr(4 downto 2) is
when "000" => startmask:="11111111111111111111111111111111";
when "001" => startmask:="00001111111111111111111111111111";
when "010" => startmask:="00000000111111111111111111111111";
when "011" => startmask:="00000000000011111111111111111111";
when "100" => startmask:="00000000000000001111111111111111";
when "101" => startmask:="00000000000000000000111111111111";
when "110" => startmask:="00000000000000000000000011111111";
when others => startmask:="00000000000000000000000000001111";
end case;
case vreq.endaddr(4 downto 2) is
when "000" => endmask:="11110000000000000000000000000000";
when "001" => endmask:="11111111000000000000000000000000";
when "010" => endmask:="11111111111100000000000000000000";
when "011" => endmask:="11111111111111110000000000000000";
when "100" => endmask:="11111111111111111111000000000000";
when "101" => endmask:="11111111111111111111111100000000";
when "110" => endmask:="11111111111111111111111111110000";
when others => endmask:="11111111111111111111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="11001100110011001100110011001100"; else mask16:="00110011001100110011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010101010101010101010101010"; else mask8:="01010101010101010101010101010101"; end if;
when others =>
--pragma translate_off
assert false report "Unsupported data bus width" severity failure;
--pragma translate_on
end case;
mask := (others => r.wmaskmode);
nwmaskmode := r.wmaskmode;
if r.wmaskmode='0' then
if r.ramaddr=vreq.startaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := startmask;
nwmaskmode:='1';
if r.reading='1' then v.rstarted := '1'; end if;
end if;
end if;
if r.ramaddr=vreq.endaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := mask and endmask;
nwmaskmode:='0';
end if;
if vreq.hsize(2 downto 1)="00" then
mask := mask and mask16;
if vreq.hsize(0)='0' then
mask := mask and mask8;
end if;
end if;
rddone := '0';
inc_ramaddr := '0';
rbw := '0';
if r.reading /= '0' then
if avlso.rdata_valid='1' then
rbw := '1';
inc_ramaddr := '1';
if v.rstarted='1' then
v.resp.rctr_gray(log2(avlbl)-1 downto 0) := nextgray(r.resp.rctr_gray(log2(avlbl)-1 downto 0));
end if;
if r.ramaddr=(r.ramaddr'range => '1') then
rddone:='1';
end if;
end if;
else
v.resp.rctr_gray := (others => '0');
end if;
v.beginburst := '0';
case r.s is
when idle =>
if vstart /= r.resp.done_tog then
v.s := acc1;
v.beginburst := '1';
end if;
v.reading := '0';
v.rstarted := '0';
v.wmaskmode := '0';
v.rd := '0';
v.wr := '0';
when acc1 =>
v.wr := vreq.hwrite;
v.rd := not vreq.hwrite;
v.reading := not vreq.hwrite;
if vreq.hwrite='1' then
slvi.write_req := '1';
end if;
if vreq.hwrite/='0' then
v.s := acc2;
end if;
if vreq.hwrite='0' and avlso.ready='1' then
v.s := rdwait;
end if;
if vreq.hwrite = '0' then
mask := (others => '1');
end if;
if avlso.ready='1' and vreq.hwrite/='0' then
inc_ramaddr := '1';
end if;
when acc2 =>
if avlso.ready='1' then
inc_ramaddr := '1';
if r.ramaddr=onev(r.ramaddr'length-1 downto 0) then
v.wr := '0';
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end if;
when rdwait =>
v.rd := '0';
if rddone='1' then
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end case;
if inc_ramaddr/='0' then
v.ramaddr := std_logic_vector(unsigned(r.ramaddr)+1);
v.wmaskmode := nwmaskmode;
end if;
if v.s=idle then
v.ramaddr := (others => '0');
end if;
slvi.read_req := v.rd;
slvi.be(avldbits/8-1 downto 0) := mask;
if rst='0' then
v.s := idle;
v.resp := ddr_response_none;
end if;
nr <= v;
response <= r.resp;
wbraddr <= r.resp.done_tog & v.ramaddr;
rbwaddr <= r.ramaddr;
rbwdata <= avlso.rdata(avldbits-1 downto 0);
rbwrite <= rbw;
avlsi <= slvi;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-gr-xc3s-1500/config.vhd | 1 | 8992 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/leon3v3/leon3sh.vhd | 1 | 6728 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3sh
-- File: leon3sh.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3sh is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of leon3sh is
signal gnd, vcc : std_logic;
begin
gnd <= '0'; vcc <= '1';
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => fpui,
fpuo => fpuo,
clken => vcc
);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spi2ahb.vhd | 1 | 2979 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/eth/core/greth_rx.vhd | 1 | 11677 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
-- attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/srmmu/mmutlb.vhd | 1 | 21804 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits: integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 :=
conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s2_tlbstate : states;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
s2_ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
tlbmiss : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlb_rtype := (
s2_tlbstate => idle,
s2_entry => (others => '0'),
s2_hm => '0',
s2_needsync => '0',
s2_data => (others => '0'),
s2_isid => id_icache,
s2_su => '0',
s2_read => '0',
s2_flush => '0',
s2_ctx => (others => '0'),
walk_use => '0',
walk_transdata => mmuidco_zero,
walk_fault => mmutlbfault_out_zero,
nrep => (others => '0'),
tpos => (others => '0'),
touch => '0',
sync_isw => '0',
tlbmiss => '0');
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (entries-1 downto 0);
signal tlbcamo : mmutlbcamo_a (entries-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (rst, r, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(entries_log-1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to entries-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to entries-1;
variable i_reppos : integer range 0 to entries-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r; v.tlbmiss := '0';
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, r.s2_ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk; v.tlbmiss := '1';
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( mmupgsz, tlbi.mmctrl1, LVL, PTE, r.s2_data, transdata.data );
--# reset
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
v.s2_ctx := tlbi.mmctrl1.ctx;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
twi.tlbmiss <= r.tlbmiss;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).mmctrl <= tlbi.mmctrl1;
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type, mmupgsz )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log, testen => scantest, custombits => ramcbits)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write,
testin
);
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/pci/ptf/pt_pci_arb.vhd | 1 | 4042 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-altera-c5ekit/config.vhd | 1 | 5254 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 1;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/i2c/i2cslv.vhd | 1 | 20281 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- [email protected]
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- [filter]
-- Length of filters used on SCL and SDA
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if r.transmit and v.scl = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= r.reg.ctrl.en;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/spw/comp/spwcomp.vhd | 1 | 31498 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickin_busy : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
credcnt : out std_logic_vector(5 downto 0);
ocredcnt : out std_logic_vector(5 downto 0);
--misc
powerdown : out std_ulogic;
powerdownrx : out std_ulogic;
-- input timing testing
testdi : in std_logic_vector(1 downto 0) := "00";
testsi : in std_logic_vector(1 downto 0) := "00";
testinput : in std_ulogic := '0'
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/spi/spimctrl.in.vhd | 2 | 665 | -- SPI memory controller
constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
constant CFG_SPIMCTRL_OFFSET : integer := 16#CONFIG_SPIMCTRL_OFFSET#;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/maps/ddr_oreg.vhd | 1 | 3202 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_oreg
-- File: ddr_oreg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR output reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_oreg is generic (tech : integer; arch : integer := 0; scantest: integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic;
testen: in std_ulogic;
testrst: in std_ulogic);
end;
architecture rtl of ddr_oreg is
begin
inf : if not ((tech = lattice) or (is_unisim(tech) = 1) or
(tech = axcel) or (tech = axdsp) or (tech = apa3) or
(tech = apa3e) or (tech = apa3l) or (tech = igloo2)) generate
inf0 : gen_oddr_reg generic map (scantest,0) port map (Q, C1, C2, CE, D1, D2, R, S, testen, testrst);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
ax0 : axcel_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
lat : if tech = lattice generate
lat0 : ec_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
igl2 : if tech = igloo2 generate
igl20 : igloo2_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_oddr_reg generic map (tech, arch)
port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_oreg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml50x/grlib_config.vhd | 1 | 2828 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
-- CFG_GRETH_SGMII_MODE: set to 0 to connect to the Ethernet PHY via GMII signals.
-- Set to 1 to connect to the Ethernet PHY in SGMII mode through high-speed serial
-- signals.
constant CFG_GRETH_SGMII_MODE : integer := 0;
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/ddr/ddr2spax_ddr.vhd | 1 | 52372 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr2spax_ddr;
architecture rtl of ddr2spax_ddr is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
function tosl(x: integer) return std_logic is
begin
if x /= 0 then return '1'; else return '0'; end if;
end tosl;
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(3 downto 0);
trcd : std_logic_vector(2 downto 0); -- tRCD : 2-9 clock cycles
trfc : std_logic_vector(7 downto 0);
trp : std_logic_vector(2 downto 0); -- precharge to activate: 2-9 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
cal_pll : std_logic_vector(1 downto 0); -- *** ??? pll_reconf
cal_rst : std_logic;
readdly : std_logic_vector(3 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
dqsctrl : std_logic_vector(7 downto 0);
eightbanks : std_ulogic;
caslat : std_logic_vector(1 downto 0); -- CAS latency 3-6
odten : std_logic_vector(1 downto 0);
tras : std_logic_vector(4 downto 0); -- RAS-to-Precharge minimum
trtp : std_ulogic;
regmem : std_ulogic; -- Registered memory (1 cycle extra latency)
strength : std_ulogic; -- Drive strength 1=reduced, 0=normal
end record;
constant ddr_burstlen: integer := (burstlen*32)/(2*ddrbits);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
type ddrstate is (dsidle,dsrascas,dscaslat,dsreaddly,dsdata,dsdone,dsagain,dsreg,dsrefresh,dspreall);
type ddrcmdstate is (dcrstdel,dcoff,dcinit1,dcinit2,dcinit3,dcinit4,dcinit5,dcinit6,dcinit7,dcinit8,dcon);
type ddr_reg_type is record
s : ddrstate;
cmds : ddrcmdstate;
response : ddr_response_type;
response1 : ddr_response_type;
response2 : ddr_response_type;
response_prev : ddr_response_type;
cfg : sdram_cfg_type;
rowsel : std_logic_vector(2 downto 0);
endaddr : std_logic_vector(l2blen-4 downto 2);
addrlo : std_logic_vector(l2ddrw-4 downto 0);
col : std_logic_vector(13 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(2 downto 0);
ctr : std_logic_vector(7 downto 0);
casctr : std_logic_vector(l2ddr_burstlen-1 downto 0);
datacas : std_logic;
prectr : std_logic_vector(5 downto 0);
rastimer : std_logic_vector(4 downto 0);
tras_met : std_logic;
pchpend : std_logic;
refctr : std_logic_vector(16 downto 0);
refpend : std_logic;
pastlast : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_wen : std_ulogic;
wen_prev : std_ulogic;
sdo_rasn : std_ulogic;
rasn_pre : std_ulogic;
sdo_casn : std_ulogic;
sdo_dqm : std_logic_vector(15 downto 0);
dqm_prev : std_logic_vector(15 downto 0);
twr_plus_cl : std_logic_vector(5 downto 0);
request_row : std_logic_vector(14 downto 0);
request_bank : std_logic_vector(2 downto 0);
request_cs : std_logic_vector(0 downto 0);
row : std_logic_vector(14 downto 0);
setrow : std_logic;
samerow : std_logic;
start_tog_prev: std_logic;
sdo_bdrive : std_ulogic;
sdo_qdrive : std_ulogic;
sdo_nbdrive : std_ulogic;
sdo_address : std_logic_vector(14 downto 0);
sdo_address_prev: std_logic_vector(14 downto 0);
sdo_ba : std_logic_vector(2 downto 0);
sdo_data : std_logic_vector(sdo.data'length-1 downto 0);
sdo_cb : std_logic_vector(sdo.cb'length-1 downto 0);
sdo_odt : std_logic;
sdo_oct : std_logic;
rbwrite : std_logic;
rbwdata : std_logic_vector(rbuf_wdbits-1 downto 0);
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
ramaddr_prev : std_logic_vector(rbuf_wabits-1 downto 0);
mr_twr : std_logic_vector(2 downto 0);
mr_tcl : std_logic_vector(2 downto 0);
read_pend : std_logic_vector(15 downto 0);
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
hwidth1 : std_logic;
hwidth : std_logic;
hwcas : std_logic;
hwctr : std_logic;
end record;
signal dr,ndr : ddr_reg_type;
signal muxsel2,muxsel1,muxsel0: std_ulogic;
signal muxin4: std_logic_vector(31 downto 0);
signal muxout4: std_logic_vector(3 downto 0);
signal start_tog_delta1,start_tog_delta2: std_logic;
signal arst: std_ulogic;
attribute syn_keep: boolean;
attribute syn_keep of muxsel2:signal is true;
attribute syn_keep of muxsel1:signal is true;
attribute syn_keep of muxsel0:signal is true;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
start_tog_delta1 <= start_tog;
start_tog_delta2 <= start_tog_delta1;
muxsel2 <= dr.rowsel(2);
muxsel1 <= dr.rowsel(1);
muxsel0 <= dr.rowsel(0);
muxproc : process(muxin4,muxsel2,muxsel1,muxsel0)
begin
muxout4(3) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(31 downto 24));
muxout4(2) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(23 downto 16));
muxout4(1) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(15 downto 8));
muxout4(0) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(7 downto 0));
end process;
ddrcomb : process(ddr_rst,sdi,request,frequest,start_tog_delta2,dr,wbrdata,muxout4,hwidth,reqsel,testen,testoen)
constant plmemwrite: boolean := false;
constant plmemread: boolean := false;
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable bdrive,qdrive: std_logic;
variable vreq,vreqf: ddr_request_type;
variable resp,resp2: ddr_response_type;
variable vstart: std_logic;
variable acsn: std_logic_vector(1 downto 0);
variable arow: std_logic_vector(14 downto 0);
variable acol: std_logic_vector(13 downto 0);
variable abank: std_logic_vector(2 downto 0);
variable aendaddr: std_logic_vector(l2blen-4 downto 2);
variable aloa: std_logic_vector(l2ddrw-4 downto 0);
variable rbw: std_logic;
variable rbwd: std_logic_vector(rbuf_wdbits-1 downto 0);
variable rbwa: std_logic_vector(rbuf_wabits-1 downto 0);
variable wbra: std_logic_vector(wbuf_rabits-1 downto 0);
variable regdata: std_logic_vector(31 downto 0);
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
variable regsd4 : std_logic_vector(31 downto 0); -- data from registers
variable regsd5 : std_logic_vector(31 downto 0); -- data from registers
variable mr : std_logic_vector(14 downto 0); -- DDR2 Mode register
variable mask: std_logic_vector(15 downto 0);
variable hio1: std_logic;
variable w5: std_logic;
variable precharge_next: std_logic;
variable precharge_notras: std_logic;
variable goto_caslat: std_logic;
variable block_precharge: std_logic;
variable regt0,regt1: std_logic_vector(ddrbits-1 downto 0);
variable addrtemp3,addrtemp2,addrtemp1,addrtemp0: std_logic_vector(7 downto 0);
variable expcsize: std_logic_vector(2 downto 0);
variable caslat_reg: std_logic_vector(2 downto 0);
variable addrlo32, endaddr32: std_logic_vector(3 downto 2);
variable endaddr43: std_logic_vector(4 downto 3);
variable endaddr42: std_logic_vector(4 downto 2);
variable inc_rctr: std_logic;
begin
dv := dr;
o := ddrctrl_out_none;
o.sdcke := (others => dr.cfg.cke);
o.sdcsn := dr.sdo_csn;
o.sdwen := dr.wen_prev;
o.rasn := dr.sdo_rasn and dr.rasn_pre;
o.casn := dr.sdo_casn and dr.datacas;
o.dqm := dr.dqm_prev;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
o.nbdrive := dr.sdo_nbdrive;
o.address := dr.sdo_address;
o.data := dr.sdo_data;
o.ba := dr.sdo_ba;
o.cal_en := dr.cfg.cal_en;
o.cal_inc := dr.cfg.cal_inc;
o.cal_pll := dr.cfg.cal_pll;
o.cal_rst := dr.cfg.cal_rst;
o.odt := (others => dr.sdo_odt);
o.oct := dr.sdo_oct;
o.cb := dr.sdo_cb;
o.cbcal_en := dr.cfg.cbcal_en;
o.cbcal_inc := dr.cfg.cbcal_inc;
resp := ddr_response_none;
resp2 := ddr_response_none;
rbw := dr.rbwrite;
rbwd := dr.rbwdata;
rbwa := (others => '0');
w5 := '0';
wbra := dr.response.done_tog & dr.ramaddr;
dv.ramaddr_prev := dr.ramaddr;
dv.dqm_prev := dr.sdo_dqm;
dv.wen_prev := dr.sdo_wen;
dv.response_prev := dr.response;
dv.sdo_address_prev := dr.sdo_address;
dv.cfg.cal_en := (others => '0');
dv.cfg.cal_inc := (others => '0');
dv.cfg.cal_pll := (others => '0');
dv.cfg.cal_rst := '0';
dv.cfg.cbcal_en := (others => '0');
dv.cfg.cbcal_inc := (others => '0');
dv.sdo_data := (others => '0');
dv.sdo_data(2*ddrbits-1 downto ddrbits) := wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_cb := (others => '0');
if chkbits > 0 then
dv.sdo_cb(2*chkbits-1 downto chkbits) := wbrdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits);
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
end if;
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.sdo_data(ddrbits-1 downto 0) := dr.sdo_data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto chkbits);
end if;
end if;
if not (hwidthen/=0 and hasdqvalid/=0 and sdi.datavalid='0') then
dv.rbwdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := sdi.data(2*ddrbits-1 downto ddrbits);
dv.rbwdata(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits) := sdi.cb(2*chkbits-1 downto chkbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
end if;
-- Half-width input data muxing
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.rbwdata(2*ddrbits+chkbits-1 downto 2*ddrbits+chkbits-ddrbits/2) :=
dr.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits);
dv.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits) :=
dr.rbwdata(ddrbits/2-1 downto 0);
dv.rbwdata(ddrbits-1 downto ddrbits/2) :=
sdi.data(ddrbits+ddrbits/2-1 downto ddrbits);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+2*chkbits-chkbits/2) :=
dr.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits);
dv.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits) :=
dr.rbwdata(ddrbits+chkbits/2-1 downto ddrbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits+chkbits/2) :=
sdi.cb(chkbits+chkbits/2-1 downto chkbits);
end if;
end if;
end if;
-- hwidth input should be constant but sample it for robustness
-- then sample in one more stage to allow replication if necessary
dv.hwidth1 := hwidth;
dv.hwidth := dr.hwidth1;
if hwidthen=0 then dv.hwidth:='0'; end if;
-- Synchronize 1/2 stages
dv.req1 := request; dv.req2 := dr.req1;
dv.start1 := start_tog_delta2; dv.start2 := dr.start1;
vstart := dr.start2;
vreq := dr.req2;
vreqf := dr.req1;
if nosync /= 0 then vstart:=start_tog_delta2; vreq:=request; vreqf:=request; end if;
if nosync > 1 then vreqf:=frequest; end if;
dv.start_tog_prev := vstart;
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.ocd & dr.cfg.emr & dr.cfg.bsize(3) & dr.cfg.trcd(0) &
dr.cfg.bsize(2 downto 0) & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(25 downto 18) := std_logic_vector(to_unsigned(phytech,8));
if bigmem /= 0 then regsd2(17):='1'; end if;
if chkbits > 0 then regsd2(16):='1'; end if;
regsd2(15 downto 0) := "1" &
std_logic_vector(to_unsigned(log2(ddrbits/8),3)) &
std_logic_vector(to_unsigned(MHz,12));
if dr.hwidth='1' then
regsd2(14 downto 12) := std_logic_vector(to_unsigned(log2((ddrbits/2)/8),3));
end if;
regsd3 := (others => '0');
regsd3(17 downto 16) := dr.cfg.readdly(1 downto 0);
regsd3(22 downto 18) := dr.cfg.trfc(4 downto 0);
regsd3(27 downto 23) := dr.cfg.twr;
regsd3(28) := dr.cfg.trp(0);
regsd4 := (others => '0');
regsd4(23 downto 22) := dr.cfg.readdly(3 downto 2);
regsd4(21) := dr.cfg.regmem;
regsd4(13 downto 0) := dr.cfg.trtp & "00" & dr.cfg.caslat &
dr.cfg.eightbanks & dr.cfg.dqsctrl;
regsd5 := (others => '0');
regsd5(30 downto 28) := dr.cfg.trp;
regsd5(25 downto 18) := dr.cfg.trfc;
regsd5(17 downto 16) := dr.cfg.odten;
regsd5(15) := dr.cfg.strength;
regsd5(10 downto 8) := dr.cfg.trcd;
regsd5(4 downto 0) := dr.cfg.tras;
case ddrbits is
when 16 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(31 downto 0);
when 32 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when 64 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when others => o.regwdata := dr.sdo_data(2*ddrbits-7*32-1 downto 2*ddrbits-8*32) &
dr.sdo_data(2*ddrbits-6*32-1 downto 2*ddrbits-7*32);
end case;
if dr.cfg.regmem='1' then
caslat_reg := std_logic_vector(unsigned('0' & dr.cfg.caslat)+1);
else
caslat_reg := '0' & dr.cfg.caslat;
end if;
-- Mode register
dv.mr_twr := std_logic_vector(unsigned(dr.cfg.twr(2 downto 0))-3);
if dv.mr_twr="110" or dv.mr_twr="111" or dv.mr_twr="000" then
dv.mr_twr := "101";
end if;
dv.mr_tcl := std_logic_vector(unsigned('0' & dr.cfg.caslat)+3);
mr := (others => '0');
mr(12) := '0'; -- Power down exit time
mr(11 downto 9) := dr.mr_twr; -- WR-1
mr(8) := dr.cfg.dllrst; -- DLL Reset
mr(7) := '0'; -- Test mode
mr(6 downto 4) := dr.mr_tcl; -- CL
mr(3) := '0'; -- Burst type, 0=seq 1=interl
mr(2 downto 0) := "010"; -- Burst len 010=4, 011=8
-- Calculate address parts from a2ds.haddr and a2ds.startword
expcsize := dr.hwidth & dr.cfg.csize;
case expcsize is
when "011" => arow := vreqf.startaddr(l2ddrw+22 downto l2ddrw+8);
when "111" | "010" => arow := vreqf.startaddr(l2ddrw+21 downto l2ddrw+7);
when "110" | "001" => arow := vreqf.startaddr(l2ddrw+20 downto l2ddrw+6);
when "101" | "000" => arow := vreqf.startaddr(l2ddrw+19 downto l2ddrw+5);
when others => arow := vreqf.startaddr(l2ddrw+18 downto l2ddrw+4);
end case;
dv.rowsel := dr.cfg.bsize(2 downto 0);
if bigmem /= 0 and dr.cfg.bsize(3 downto 1)="000" then
dv.rowsel := "010";
end if;
if bigmem = 0 and dr.cfg.bsize(3)='1' then
dv.rowsel := "111";
end if;
addrtemp3 := vreqf.startaddr(30 downto 23); --CS
addrtemp2 := vreqf.startaddr(29 downto 22); --BA2/1
addrtemp1 := vreqf.startaddr(28 downto 21); --BA1/0
addrtemp0 := vreqf.startaddr(27 downto 20); --BA0/-
if bigmem=1 then
addrtemp3(1 downto 0) := "0" & vreqf.startaddr(31);
addrtemp2(1 downto 0) := vreqf.startaddr(31 downto 30);
addrtemp1(1 downto 0) := vreqf.startaddr(30 downto 29);
addrtemp0(1 downto 0) := vreqf.startaddr(29 downto 28);
end if;
muxin4 <= addrtemp3 & addrtemp2 & addrtemp1 & addrtemp0;
abank := muxout4(2 downto 0);
if dr.cfg.eightbanks='0' then
abank := '0' & abank(2) & abank(1);
end if;
acol := vreqf.startaddr(log2(ddrbits/8)+13 downto log2(ddrbits/8));
if ddrbits=16 then acol(0):='0'; end if; -- Always align to at least 32 bits
acsn(0) := muxout4(3);
acsn(1) := not acsn(0);
dv.setrow := '0';
if dr.setrow='1' then
dv.row := dr.sdo_address_prev;
end if;
dv.samerow := '0';
if abank=dr.sdo_ba and acsn=dr.sdo_csn and arow=dr.row then
dv.samerow := '1';
end if;
dv.request_row := arow;
dv.request_cs := acsn(0 downto 0);
dv.request_bank := abank;
hio1 := vreqf.hio;
if raspipe /= 0 then
vstart := dr.start_tog_prev;
arow := dr.request_row;
acsn := (not dr.request_cs) & dr.request_cs;
abank := dr.request_bank;
hio1 := vreq.hio;
end if;
aendaddr := vreq.endaddr(log2(4*burstlen)-1 downto 2);
if vreq.hsize(1 downto 0)="11" and vreq.hio='0' then
aendaddr(2):='1';
end if;
if ahbdw > 64 and vreqf.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbdw > 128 and vreqf.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
aloa(l2ddrw-4 downto 0) := vreq.startaddr(l2ddrw-4 downto 0);
if ddrbits > 32 then addrlo32 := dr.addrlo(3 downto 2);
elsif ddrbits > 16 then addrlo32 := '0' & dr.addrlo(2);
else addrlo32 := "00";
end if;
endaddr32 := dr.endaddr(3 downto 2);
endaddr43 := dr.endaddr(4 downto 3);
endaddr42 := dr.endaddr(4 downto 2);
-- Calculate data mask
mask := (others => dr.pastlast);
-- Set mask bits for <word access
if dr.hsize="000" then
if dr.addrlo(0)='1' then
mask := mask or "1010101010101010";
else
mask := mask or "0101010101010101";
end if;
end if;
if dr.hsize(2 downto 1)="00" then
if dr.addrlo(1)='1' then
mask := mask or "1100110011001100";
else
mask := mask or "0011001100110011";
end if;
end if;
-- First access
-- (this could be written in generic code instead)
if dr.ctr=zerov(dr.ctr'length) then
case ddrbits is
when 16 =>
null;
when 32 =>
if dr.addrlo(2)='1' then
mask(7 downto 0) := mask(7 downto 0) or x"F0";
end if;
when 64 =>
case addrlo32 is
when "00" => null;
when "01" => mask := mask or x"F000";
when "10" => mask := mask or x"FF00";
when others => mask := mask or x"FFF0";
end case;
when others => null;
end case;
end if;
-- Last access
if dr.ramaddr = dr.endaddr(log2(4*burstlen)-1 downto log2(2*ddrbits/8)) then
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
dv.pastlast := '1';
end if;
case ddrbits is
when 16 => null;
when 32 =>
if dr.endaddr(2)='0' then
mask(7 downto 0) := mask(7 downto 0) or x"0F";
end if;
when 64 =>
case endaddr32 is
when "00" => mask := mask or x"0FFF";
when "01" => mask := mask or x"00FF";
when "10" => mask := mask or x"000F";
when others => null;
end case;
when others => null;
end case;
end if;
-- Before first
if dr.col(1)='1' and dr.ctr(0)='1' and dr.ctr(dr.ctr'high downto 1)=zerov(dr.ctr'length-1) then
mask := mask or x"FFFF";
end if;
dv.sdo_rasn := '1'; dv.sdo_casn := '1'; dv.sdo_wen := '1';
dv.sdo_odt := '0'; dv.sdo_oct := '0';
dv.rbwrite := '0';
dv.ctr := std_logic_vector(unsigned(dr.ctr)+1);
if hwidthen/=0 and dr.hwidth='1' and dr.s=dsdata then
dv.hwctr := not dr.hwctr;
if dr.hwctr='0' then dv.ctr := dr.ctr; end if;
end if;
dv.rastimer := std_logic_vector(unsigned(dr.rastimer)+1);
if dr.rastimer=dr.cfg.tras then dv.tras_met := '1'; end if;
-- Calculate whether we would precharge the next cycle if Tras=0
precharge_notras := '0';
if dr.casctr=zerov(dr.casctr'length) and dr.prectr="000000" and dr.pchpend='1' then
precharge_notras := '1';
end if;
-- Calculate whether we should precharge the next cycle
precharge_next := precharge_notras and dr.tras_met;
block_precharge := '0';
inc_rctr := '0';
goto_caslat := '0';
case dr.s is
when dsidle =>
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_nbdrive := not oepols;
dv.col := acol;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.response.rctr_gray := "0000";
if dr.refpend='1' and dr.cfg.refon='1' then
-- Periodic refresh
dv.sdo_csn := (others => '0');
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.refpend := '0';
dv.s := dsrefresh;
elsif vstart /= dr.response.done_tog and (dr.cmds=dcon or (dr.cmds=dcoff and dr.cfg.renable='0')) then
-- R/W data
dv.sdo_rasn := '0' or hio1;
dv.sdo_csn := acsn;
dv.sdo_address := arow;
dv.sdo_ba := abank;
dv.s := dsrascas;
elsif dr.cfg.command /= "000" then
-- Command
dv.sdo_csn := (others => '0');
if dr.cfg.command(2 downto 1)="11" then
dv.sdo_wen:='0'; dv.sdo_casn:='0'; dv.sdo_rasn:='0';
dv.sdo_ba := "00" & dr.cfg.command(0);
if dr.cfg.command(0)='0' or dr.cfg.emr="00" then
dv.sdo_ba := "000";
dv.sdo_address := mr;
else
dv.sdo_ba := "0" & dr.cfg.emr;
if dr.cfg.emr="01" then
dv.sdo_address := "0000"&conv_std_logic(dqsse=1)&dr.cfg.ocd&dr.cfg.ocd&dr.cfg.ocd
& dr.cfg.odten(1)&"000"& dr.cfg.odten(0) & dr.cfg.strength & "0";
else
dv.sdo_address := (others => '0');
end if;
end if;
else
dv.sdo_wen := dr.cfg.command(2);
dv.sdo_casn := dr.cfg.command(1);
dv.sdo_rasn := dr.cfg.command(0);
dv.sdo_address(10) := '1';
-- print("X Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
dv.cfg.command := "000";
if dr.cfg.command=CMD_REF then
dv.s := dsrefresh;
end if;
if dr.cfg.command=CMD_PRE then
dv.s := dspreall;
end if;
end if;
when dsrascas =>
if dr.ctr(2 downto 0)="000" then
-- pragma translate_off
assert dr.ctr="00000000" severity failure;
-- pragma translate_on
-- dv.row := dr.sdo_address;
dv.setrow := '1';
end if;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
if dr.hwidth='1' then
dv.sdo_address := dr.col(12 downto 9) & '0' & dr.col(8 downto 1) & "00";
end if;
if vreq.hio='1' and dr.ctr(0)='1' then
dv.s := dsreg;
dv.ctr := (others => '0');
dv.hwctr := '0';
elsif vreq.hio='0' and dr.ctr(2 downto 0)=dr.cfg.trcd then
goto_caslat := '1';
end if;
when dscaslat =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(2 downto 0)=caslat_reg then
if dr.hwrite='1' then
dv.s := dsdata;
else
dv.s := dsreaddly;
end if;
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
end if;
when dsreaddly =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(3 downto 0)=dr.cfg.readdly then
dv.s := dsdata;
dv.ctr := (others => '0');
dv.hwctr := '0';
end if;
when dsdata =>
inc_rctr := '0';
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.rbwrite := '1';
dv.sdo_dqm := mask;
dv.sdo_bdrive := not (dr.hwrite xor oepols);
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
-- If-case to handle pausing for half-width mode
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
inc_rctr := '1';
-- The first request may be on a 2-odd column to get the first data first
-- Make sure following requests are on even mult of 4xcolumns
if dr.ctr(0)='1' then
dv.col(1) := '0';
end if;
-- Make sure we don't advance read counter for the unwanted 3:rd/4:th
-- word in the burst in this case
if dr.ctr(0)='1' and dr.col(1)='1' then
inc_rctr := '0';
end if;
-- Toggle done and change state after completed burst
if dr.ctr(log2(ddr_burstlen)-1 downto 0)=(not zerov(l2ddr_burstlen)) then
dv.sdo_nbdrive := not oepols;
dv.s := dsdone;
dv.response.done_tog := not dr.response.done_tog;
end if;
end if;
-- Stall if not ready yet
if hasdqvalid/=0 and sdi.datavalid='0' and dr.hwrite='0' then
dv.ctr := dr.ctr;
dv.hwctr := dr.hwctr;
dv.response := dr.response;
dv.s := dsdata;
dv.col(1) := dr.col(1);
dv.rbwrite := '0';
inc_rctr := '0';
end if;
if inc_rctr='1' and dr.hwrite='0' then
dv.response.rctr_gray(l2ddr_burstlen-1 downto 0) :=
nextgray(dr.response.rctr_gray(l2ddr_burstlen-1 downto 0));
end if;
when dsdone =>
dv.response.rctr_gray := "0000";
dv.sdo_bdrive := not oepols;
if dr.ctr(0)='1' then
dv.sdo_qdrive := not oepols;
end if;
if dr.pchpend='0' and dr.prectr=zerov(dr.prectr'length) then
dv.s := dsidle;
end if;
-- Short circuit if request on same row and waiting for Tras to expire
if precharge_notras='1' and precharge_next='0' and
dr.start_tog_prev /= dr.response.done_tog and dr.samerow='1' and vreq.hio='0' then
dv.col := acol;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.s := dsagain;
dv.sdo_qdrive := not oepols;
end if;
when dsagain =>
block_precharge := '1';
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
goto_caslat := '1';
when dsreg =>
-- This code assumes ddrbits>=16, needs to be changed slightly to support
-- smaller widths
dv.rbwrite := '1';
-- DDR2CFG1-5,PHYCFG read
regt0 := (others => '0'); regt1 := (others => '0');
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regt0 := regsd1(31 downto 16); regt1 := regsd1(15 downto 0);
when "001" => regt0 := regsd2(31 downto 16); regt1 := regsd2(15 downto 0);
when "010" => regt0 := regsd3(31 downto 16); regt1 := regsd3(15 downto 0);
when "011" => regt0 := regsd4(31 downto 16); regt1 := regsd4(15 downto 0);
when "100" | "101" => regt0 := regsd5(31 downto 16); regt1 := regsd5(15 downto 0);
when "110" => regt0 := sdi.regrdata(31 downto 16); regt1 := sdi.regrdata(15 downto 0);
when others => regt0 := sdi.regrdata(63 downto 48); regt1 := sdi.regrdata(47 downto 32);
end case;
when 32 =>
case endaddr43 is
when "00" => regt0 := regsd1; regt1 := regsd2;
when "01" => regt0 := regsd3; regt1 := regsd4;
when "10" => regt0 := regsd5; regt1 := regsd2;
when others => regt0 := sdi.regrdata(31 downto 0); regt1 := sdi.regrdata(63 downto 32);
end case;
when 64 =>
case dr.endaddr(4) is
when '0' => regt0 := regsd1 & regsd2; regt1 := regsd3 & regsd4;
when others => regt0 := regsd5 & regsd2; regt1 := sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
when 128 =>
regt0 := regsd1 & regsd2 & regsd3 & regsd4;
regt1 := regsd5 & regsd2 & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
when others =>
regt0(ddrbits-1 downto ddrbits-255) := regsd1 & regsd2 & regsd3 & regsd4 &
regsd5 & x"00000000" & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
dv.rbwdata(ddrbits*2+chkbits-1 downto ddrbits+chkbits) := regt0;
dv.rbwdata(ddrbits-1 downto 0) := regt1;
-- Note write data is two cycles behind
regt0 := dr.sdo_data(ddrbits*2-1 downto ddrbits);
regt1 := dr.sdo_data(ddrbits-1 downto 0);
if dr.hwrite='1' and dr.ctr(2 downto 0)="010" then
w5 := '0';
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regsd1 := regt0 & regt1;
when "001" => regsd2 := regt0 & regt1;
when "010" => regsd3 := regt0 & regt1;
when "011" => regsd4 := regt0 & regt1;
when "100" => regsd5 := regt0 & regt1;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 32 =>
case endaddr42 is
when "000" => regsd1 := regt0;
when "001" => regsd2 := regt1;
when "010" => regsd3 := regt0;
when "011" => regsd4 := regt1;
when "100" => regsd5 := regt0;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 64 =>
case endaddr42 is
when "000" => regsd1 := regt0(63 downto 32);
when "001" => regsd2 := regt0(31 downto 0);
when "010" => regsd3 := regt1(63 downto 32);
when "011" => regsd4 := regt1(31 downto 0);
when "100" => regsd5 := regt0(63 downto 32);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 128 =>
case endaddr42 is
when "000" => regsd1 := regt0(127 downto 96);
when "001" => regsd2 := regt0(95 downto 64);
when "010" => regsd3 := regt0(63 downto 32);
when "011" => regsd4 := regt0(31 downto 0);
when "100" => regsd5 := regt1(127 downto 96);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when others =>
case endaddr42 is
when "000" => regsd1 := regt0(ddrbits-1 downto ddrbits-32);
when "001" => regsd2 := regt0(ddrbits-33 downto ddrbits-64);
when "010" => regsd3 := regt0(ddrbits-65 downto ddrbits-96);
when "011" => regsd4 := regt0(ddrbits-97 downto ddrbits-128);
when "100" => regsd5 := regt0(ddrbits-129 downto ddrbits-160);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
end case;
-- Update lsb aliases for expanded fields in ddr2cfg5
if w5='1' then
regsd3(28) := regsd5(28); -- TRP
regsd3(22 downto 18) := regsd5(22 downto 18); -- TRFC
regsd1(26) := regsd5(8); -- TRCD
end if;
end if;
if (dr.hwrite='1' and dr.ctr(2 downto 1)="11") or dr.hwrite='0' then
dv.s := dsidle;
dv.response.done_tog := not dr.response.done_tog;
end if;
dv.cfg := (refon => regsd1(31), ocd => regsd1(30), emr => regsd1(29 downto 28),
trcd => regsd5(10 downto 9) & regsd1(26),
bsize => regsd1(27) & regsd1(25 downto 23), csize => regsd1(22 downto 21),
command => regsd1(20 downto 18), dllrst => regsd1(17), renable => regsd1(16),
cke => regsd1(15), refresh => regsd1(11 downto 0),
cal_pll => regsd3(30 downto 29), cal_rst => regsd3(31),
trp => regsd5(30 downto 29) & regsd3(28),
twr => regsd3(27 downto 23),
trfc => regsd5(25 downto 23) & regsd3(22 downto 18),
readdly => regsd4(23 downto 22) & regsd3(17 downto 16), cal_inc => regsd3(15 downto 8),
cal_en => regsd3(7 downto 0),
eightbanks => regsd4(8), dqsctrl => regsd4(7 downto 0),
caslat => regsd4(10 downto 9),
odten => regsd5(17 downto 16), tras => regsd5(4 downto 0), strength => regsd5(15),
trtp => regsd4(13), cbcal_inc => regsd4(31 downto 28), cbcal_en => regsd4(27 downto 24),
regmem => regsd4(21)
);
when dsrefresh =>
if dr.ctr(7 downto 0)=dr.cfg.trfc then
dv.s := dsidle;
end if;
when dspreall =>
-- Wait for tRP (eightbanks=0) or tRP+1 (eightbanks=1)
if dr.ctr(3 downto 0)=std_logic_vector(("0" & unsigned(dr.cfg.trp)) + (2+eightbanks)) then
dv.s := dsidle;
end if;
end case;
if goto_caslat='1' then
dv.s := dscaslat;
-- Set counter to -4 for read and -1 for write to compensate
-- write-read diff and pipelining.
-- Only need lowest three bits so set highest 3 to '0' as usual
dv.ctr(5 downto 3) := "000";
dv.ctr(2 downto 0) := "100";
if vreq.hwrite='1' then
dv.ctr(2 downto 0) := "111";
end if;
dv.casctr := std_logic_vector(to_unsigned(ddr_burstlen/2, dv.casctr'length));
dv.hwcas := '0';
dv.pchpend := '1';
end if;
-- CAS and precharge handling
-- FSM above sets up casctr and pchpend
dv.twr_plus_cl := std_logic_vector(("0" & unsigned(dr.cfg.twr)) + ("0000" & unsigned(dr.cfg.caslat)));
if dr.prectr /= zerov(dr.prectr'length) then
dv.prectr := std_logic_vector(unsigned(dr.prectr)-1);
end if;
dv.read_pend := '0' & dr.read_pend(dr.read_pend'high downto 1);
dv.datacas := '1';
if dr.casctr /= zerov(dr.casctr'length) then
if dr.datacas='1' then
dv.datacas := '0';
-- dv.sdo_casn := '0';
dv.sdo_wen := not dr.hwrite;
if dr.hwrite='0' then
case dr.cfg.caslat is
when "00" => dv.read_pend(4 downto 3) := "11";
when "01" => dv.read_pend(5 downto 4) := "11";
when "10" => dv.read_pend(6 downto 5) := "11";
when others => dv.read_pend(7 downto 6) := "11";
end case;
end if;
elsif dr.hwidth='1' then
dv.hwcas := not dr.hwcas;
if dr.hwcas='1' then
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw+1 downto 3) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw+1 downto 3)+1));
end if;
dv.sdo_address(2) := '0';
else
dv.sdo_address(2) := not dr.sdo_address(2);
end if;
else
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw downto 2) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 2)+1));
end if;
dv.sdo_address(1) := '0';
end if;
-- Set up precharge counter (will not run until casctr=0)
if dr.hwrite='0' then
dv.prectr := "00000" & dr.cfg.trtp;
else
dv.prectr := dr.twr_plus_cl;
end if;
end if;
o.read_pend := dv.read_pend(7 downto 0);
dv.rasn_pre := '1';
if precharge_next='1' and block_precharge='0' then
dv.pchpend := '0';
dv.sdo_wen := '0';
-- dv.sdo_rasn := '0';
dv.rasn_pre := '0';
dv.prectr := "000" & dr.cfg.trp;
end if;
-- Refresh and init handling
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
case dr.cmds is
when dcrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel, dr.refctr'length)) then
dv.cmds := dcoff;
end if;
-- Bypass reset delay by writing anything to regsd2
if dr.start_tog_prev='1' and
vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001" then
dv.cmds := dcoff;
end if;
when dcoff =>
-- Wait for renable to be set high and phy to be locked
dv.refctr := (others => '0');
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
dv.cfg.dllrst := '1';
dv.cfg.ocd := '0';
dv.cmds := dcinit1;
end if;
when dcinit1 =>
-- Wait >=400 ns
if dr.refctr=std_logic_vector(to_unsigned((MHz*4+9)/10, dr.refctr'length)) then
dv.cmds := dcinit2;
dv.cfg.command := CMD_PRE;
dv.cfg.emr := "00";
end if;
when dcinit2 =>
-- MR order 2,3,1,0
-- 2xcycles per command
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := (not dr.cfg.emr(0)) & dr.cfg.emr(1); -- 00->10->11->01->00
if dr.cfg.emr="01" then
dv.cmds := dcinit3;
dv.refctr := (others => '0');
end if;
end if;
when dcinit3 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_PRE;
dv.cmds := dcinit4;
end if;
when dcinit4 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit5;
end if;
when dcinit5 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit6;
end if;
when dcinit6 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "00";
dv.cfg.dllrst := '0';
dv.cmds := dcinit7;
dv.refctr := (others => '0');
end if;
when dcinit7 =>
if dr.refctr(7 downto 0)=std_logic_vector(to_unsigned(200,8)) then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "01";
dv.cfg.ocd := '1';
dv.cmds := dcinit8;
end if;
when dcinit8 =>
if dr.cfg.command="000" then
if dr.cfg.ocd='1' then
dv.cfg.ocd := '0';
dv.cfg.command := CMD_EMR;
else
dv.cmds := dcon;
dv.cfg.renable := '0';
end if;
end if;
dv.refctr := (others => '0');
when dcon =>
if dr.cfg.cke='0' then
dv.cmds := dcoff;
elsif dr.cfg.renable='1' then
dv.cmds := dcinit2;
dv.refctr := (others => '0');
elsif dr.refctr(11 downto 0)=dr.cfg.refresh then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
end case;
-- Calculate next address
dv.ramaddr(0) := dv.ctr(0) xor dv.col(1);
if rbuf_wabits > 1 then
dv.ramaddr(rbuf_wabits-1 downto 1) :=
std_logic_vector(unsigned(dr.col(rbuf_wabits downto 2)) +
unsigned(dv.ctr(rbuf_wabits-1 downto 1)));
end if;
-- print("col: " & tost(dr.col) & ", dv.ctr: " & tost(dv.ctr) & ", res: " & tost(dv.ramaddr));
if eightbanks=0 then dv.cfg.eightbanks:='0'; end if;
rbwd := dv.rbwdata;
rbwa := dr.ramaddr;
rbw := dv.rbwrite;
if plmemwrite then
rbwd := dr.rbwdata;
rbwa := dr.ramaddr_prev;
rbw := dr.rbwrite;
end if;
if not plmemread then
o.dqm := dr.sdo_dqm;
o.sdwen := dr.sdo_wen;
o.data := dv.sdo_data;
o.cb := dv.sdo_cb;
end if;
-- half-width output data muxing, placed after (potential) pipeline regs.
if hwidthen/=0 and dr.hwidth='1' then
if dr.hwctr='1' then
o.data(ddrbits/2-1 downto 0) := o.data(2*ddrbits-ddrbits/2-1 downto ddrbits);
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(2*ddrbits-1 downto 2*ddrbits-ddrbits/2);
if chkbits > 0 then
o.cb(chkbits/2-1 downto 0) := o.cb(2*chkbits-chkbits/2-1 downto chkbits);
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(2*chkbits-1 downto 2*chkbits-chkbits/2);
end if;
o.dqm(ddrbits/16-1 downto 0) := o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8);
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/4-1 downto ddrbits/4-ddrbits/16);
else
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(ddrbits-1 downto ddrbits/2);
if chkbits > 0 then
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(chkbits-1 downto chkbits/2);
end if;
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/8-1 downto ddrbits/16);
end if;
end if;
if ddr_rst='0' then
dv.s := dsidle;
dv.cmds := dcrstdel;
dv.response := ddr_response_none;
dv.casctr := (others => '0');
dv.refctr := (others => '0');
dv.pchpend := '0';
dv.refpend := '0';
dv.rbwrite := '0';
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_nbdrive := not oepols;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.cfg.command := "000";
dv.cfg.emr := "00";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 4);
dv.cfg.refon := '0';
dv.cfg.trfc := conv_std_logic_vector(TRFC*MHz/1000-2, 8);
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
dv.sdo_dqm := (others => '1');
dv.cfg.dllrst := '0';
dv.cfg.cke := '0';
dv.cfg.ocd := '0';
dv.cfg.readdly := conv_std_logic_vector(readdly, 4);
dv.cfg.eightbanks := conv_std_logic_vector(eightbanks, 1)(0);
dv.cfg.odten := std_logic_vector(to_unsigned(odten,2));
dv.cfg.dqsctrl := (others => '0');
dv.cfg.strength := '0';
if pwron = 1 then dv.cfg.renable := '1'; else dv.cfg.renable:='0'; end if;
-- Default to min 15 ns tRCD, 15 ns tRP, min(7.5 ns,2*tCK) tRTP
-- Use CL=3 for DDR2-400/533, 4 for DDR2-667, 5 for DDR2-800
dv.cfg.trcd := "000";
dv.cfg.trp := "000";
dv.cfg.trtp := '0';
dv.cfg.caslat := "00";
dv.cfg.regmem := '0';
if MHz > 130 then
dv.cfg.trcd := "001";
dv.cfg.trp := "001";
end if;
if MHz > 200 then
-- Will work up to 600 MHz, then trcd/trp needs to be expanded
dv.cfg.trcd := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
dv.cfg.trp := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
end if;
if MHz > 267 then
-- Works up to 400 MHz, then trtp will need to be expanded
dv.cfg.trtp := '1';
dv.cfg.caslat := "01";
end if;
if MHz > 334 then
dv.cfg.caslat := "10";
end if;
dv.cfg.cal_rst := '1'; -- Reset input delays
dv.sdo_ba := (others => '0');
dv.sdo_address := (others => '0');
-- Default to min 45 ns tRAS
dv.cfg.tras := std_logic_vector(to_unsigned((45*MHz+999)/1000 - 2, 5));
dv.read_pend := (others => '0');
if ddr_syncrst /= 0 then
dv.cfg.cke := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_odt := '0';
if phyptctrl /= 0 then
o.sdcke := "00";
o.bdrive := not oepols;
o.qdrive := not oepols;
o.odt := (others => '0');
end if;
end if;
end if;
if dr.cfg.odten="00" then
dv.sdo_odt := '0';
end if;
if octen=0 then
dv.sdo_oct := '0';
end if;
for x in 0 to chkbits/4-1 loop
o.cbdqm(x) := o.dqm(x*ddrbits/chkbits);
end loop;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if dr.cfg.command /= "000" then
-- print("Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
-- Dynamic nosync handling (nosync=2)
if plmemwrite then
dv.response1 := dr.response;
dv.response2 := dr.response;
else
dv.response1 := dv.response;
dv.response2 := dv.response;
end if;
if reqsel='1' then dv.response1 := ddr_response_none; end if;
if reqsel='0' then dv.response2 := ddr_response_none; end if;
if nosync > 1 then
resp := dr.response1;
elsif plmemwrite then
resp := dr.response_prev;
else
resp := dr.response;
end if;
resp2 := dr.response2;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
rbwdata <= rbwd;
rbwaddr <= rbwa;
rbwrite <= rbw;
wbraddr <= wbra;
sdo <= o;
response <= resp;
response2 <= resp2;
ndr <= dv;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.cfg.cke <= '0';
dr.sdo_bdrive <= not oepols;
dr.sdo_qdrive <= not oepols;
dr.sdo_odt <= '0';
end if;
end process;
end;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/docs/README.vhdl | 7 | 598 |
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/gaisler/pci/pcipads.vhd | 1 | 10989 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v; -- input/output voltage
nolock : integer := 0
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
dolock : if nolock = 0 generate
pad_pci_lock : iopad
generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
end generate;
donolock : if nolock = 1 generate
pcii.lock <= pci_lock;
end generate;
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/inferred/mul_inferred.vhd | 1 | 4283 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-ml605/leon3mp.vhd | 1 | 35626 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.ml605.all;
use work.pcie.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF"
);
port (
reset : in std_ulogic;
errorn : out std_ulogic;
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
alatch : out std_ulogic;
-- DDR3 memory
ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_odt : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
gmiiclk_p : in std_ulogic;
gmiiclk_n : in std_ulogic;
egtx_clk : out std_ulogic;
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
erstn : out std_ulogic;
iic_scl_main : inout std_ulogic;
iic_sda_main : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
clk_33 : in std_ulogic; -- SYSACE clock
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0);
pci_exp_txp : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_txn : out std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxp : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
pci_exp_rxn : in std_logic_vector(CFG_NO_OF_LANES-1 downto 0);
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- Output signals to LEDs
led : out std_logic_vector(6 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal lclk, clk_ddr, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
signal tb_rst : std_logic;
signal tb_clk : std_logic;
signal phy_init_done : std_logic;
signal lerrorn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- VGA
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal clk100 : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
-- IIC
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
-- SYSACE
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
-- Used for connecting input/output signals to the DDR3 controller
signal migi : mig_app_in_type;
signal migo : mig_app_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clk_ddr : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_preserve of clk_ddr : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
attribute keep of clk_ddr : signal is true;
constant VCO_FREQ : integer := 1200000; -- MMCM VCO frequency in KHz
constant CPU_FREQ : integer := VCO_FREQ / CFG_MIG_CLK4; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
alatch <= '0';
erstn <= rstn;
-- Glitch free reset that can be used for the Eth Phy and flash memory
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+CFG_PCIEXP,
nahbs => 9)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
lerrorn <= dbgo(0).error and rstn;
error_pad : odpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (errorn, lerrorn);
dsugen : if CFG_DSU = 1 generate
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (level => cmos, voltage => x15v, tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, iomask => 0, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 24)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (writen, memo.writen);
end generate;
bdr : iopadvv generic map (level => cmos, voltage => x25v, tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
-- mig_gen : if (CFG_MIG_DDR2 = 1) generate
ahb2mig0 : ahb2mig_ml605
generic map ( hindex => 0, haddr => 16#400#, hmask => 16#E00#,
MHz => 400, Mbyte => 512, nosync => boolean'pos(CFG_MIG_CLK4=12)) --CFG_CLKDIV/12)
port map (
rst => rstn, clk_ahb => clkm, clk_ddr => clk_ddr,
ahbsi => ahbsi, ahbso => ahbso(0), migi => migi, migo => migo);
ddr3ctrl : entity work.mig_37
generic map (SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,CLKOUT_DIVIDE4 => work.config.CFG_MIG_CLK4)
port map(
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
ddr3_dq => ddr3_dq,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
app_wdf_wren => migi.app_wdf_wren,
app_wdf_data => migi.app_wdf_data,
app_wdf_mask => migi.app_wdf_mask,
app_wdf_end => migi.app_wdf_end,
app_addr => migi.app_addr,
app_cmd => migi.app_cmd,
app_en => migi.app_en,
app_rdy => migo.app_rdy,
app_wdf_rdy => migo.app_wdf_rdy,
app_rd_data => migo.app_rd_data,
app_rd_data_valid => migo.app_rd_data_valid,
tb_rst => open,
tb_clk => clk_ddr,
clk_ahb => clkm,
clk100 => clk100,
phy_init_done => phy_init_done,
sys_rst_13 => reset,
sys_rst_14 => rstraw
);
led(3) <= phy_init_done;
led(4) <= rstn;
led(5) <= reset;
led(6) <= '0';
lock <= phy_init_done; -- and cgo.clklock;
-- end generate;
-- noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= cgo.clklock; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 7, hirq => 10, mode => 2,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(7), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
clk_33_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (clk_33, clkace);
sysace_mpa_pads : outpadv generic map (level => cmos, voltage => x25v, width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (sysace_d(7 downto 0), aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (sysace_mpirq, acei.irq);
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP: pcie_master_target_virtex
generic map (
fabtech => fabtech,
hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
hslvndx => 8,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
pcie_bar_mask => 16#FFE#,
nsync => 2, -- 1 or 2 sync regs between clocks
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#,
Master => CFG_PCIE_SIM_MAS,
lane_width => CFG_NO_OF_LANES
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)
);
end generate;
------------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (fabtech => fabtech, memtech => memtech, dmstndx =>(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE),
dapbndx => 8, dapbaddr => 8,dapbirq => 8, blength => 12, abits => 21,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID, pcie_bar_mask => 16#FFE#,
slvndx => 8, apbndx => 5, apbaddr => 5, haddr => 16#A00#,hmask=> 16#FFF#,
nsync => 2,lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(8),
dahbmo => ahbmo((CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE)),
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(8)
);
end generate;
----------------------------------------------------------------------
pcie_mf_no_dma: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_virtex
generic map (fabtech => fabtech, memtech => memtech,
hslvndx => 8, abits => 21, device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
pcie_bar_mask => 16#FFE#, pindex => 5, paddr => 5,
haddr => 16#A00#, hmask => 16#FFF#, nsync => 2, lane_width => CFG_NO_OF_LANES)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(8),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- VGA + IIC --------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 24000, clk2 => 20000, clk3 => 16000, burstlen => 4,
ahbaccsz => CFG_AHBDW)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (clk100, ethi.gtx_clk, lock, clk_sel, vgao, clkvga, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 7, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
tft_lcd_data_pad : outpadv generic map (level => cmos, voltage => x25v, width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
-- greth1g: if CFG_GRETH1G = 1 generate
gtxclk0 : entity work.gtxclk port map (
clk_p => gmiiclk_p, clk_n => gmiiclk_n, clkint => ethi.gtx_clk,
clkout => egtx_clk);
-- end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (level => cmos, voltage => x25v, tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (level => cmos, voltage => x25v, tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1+CFG_PCIEXP) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Virtex6 ML605 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/eth/comp/ethcomp.vhd | 1 | 20848 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ethcomp is
component grethc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbitc is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0;
mdiochain : integer range 0 to 1 := 0;
iotest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(8 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(8 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(8 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(8 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--edcl buf
erenable : out std_ulogic;
eraddress : out std_logic_vector(15 downto 0);
ewritem : out std_ulogic;
ewritel : out std_ulogic;
ewaddressm : out std_logic_vector(15 downto 0);
ewaddressl : out std_logic_vector(15 downto 0);
ewdata : out std_logic_vector(31 downto 0);
erdata : in std_logic_vector(31 downto 0);
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
gbit : out std_ulogic;
speed : out std_ulogic;
-- mdio sharing
mdiochain_first : in std_ulogic := '0'; -- First in chain (ignore ticki/sampi)
mdiochain_ticki : in std_ulogic := '0'; -- From above in chain
mdiochain_datai : in std_ulogic := '0';
mdiochain_locko : out std_ulogic; -- To above in chain
mdiochain_ticko : out std_ulogic; -- To below in chain
mdiochain_i : out std_ulogic; -- To below in chain
mdiochain_locki : in std_ulogic := '0'; -- From below in chain
mdiochain_o : in std_ulogic := '0';
mdiochain_oe : in std_ulogic := '0'
);
end component;
component greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end component;
component greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end component;
end package;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/techmap/stratixiii/alt/apll.vhd | 4 | 9287 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY apll IS
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC;
phasedone : OUT STD_LOGIC
);
END apll;
ARCHITECTURE SYN OF apll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL scanclk_clk5 : STD_LOGIC ;
signal phasecounter_reg : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
attribute syn_keep of phasecounter_reg : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of phasecounter_reg : signal is true;
constant period : integer := 1000000/freq;
function set_phase(freq : in integer) return string is
variable s : string(1 to 4) := "0000";
variable f,r : integer;
begin
f := freq;
while f /= 0 loop
r := f mod 10;
case r is
when 0 => s := "0" & s(1 to 3);
when 1 => s := "1" & s(1 to 3);
when 2 => s := "2" & s(1 to 3);
when 3 => s := "3" & s(1 to 3);
when 4 => s := "4" & s(1 to 3);
when 5 => s := "5" & s(1 to 3);
when 6 => s := "6" & s(1 to 3);
when 7 => s := "7" & s(1 to 3);
when 8 => s := "8" & s(1 to 3);
when 9 => s := "9" & s(1 to 3);
when others =>
end case;
f := f / 10;
end loop;
return s;
end function;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 21) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769"), -- 120 & 130 MHz
("1786", "3571", "5357"), ("1667", "3333", "5000"), -- 140 & 150 MHz
("1563", "3125", "4688"), ("1471", "2941", "4412"), -- 160 & 170 MHz
("1389", "2778", "4167"), ("1316", "2632", "3947"), -- 180 & 190 MHz
("1250", "2500", "3750"), ("1190", "2381", "3571")); -- 200 & 210 MHz
--constant pshift_90 : string := phasearr((freq*mult)/(10*div))(1);
constant pshift_90 : string := set_phase(100000/((4*freq*mult)/(10*div)));
--constant pshift_180 : string := phasearr((freq*mult)/(10*div))(2);
constant pshift_180 : string := set_phase(100000/((2*freq*mult)/(10*div)));
--constant pshift_270 : string := phasearr((freq*mult)/(10*div))(3);
constant pshift_270 : string := set_phase(300000/((4*freq*mult)/(10*div)));
constant pshift_rclk : string := set_phase(rskew);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
scanclk_clk5 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
-- quartus bug, cant be constant
--process(scanclk)
process(scanclk_clk5)
begin
--if rising_edge(scanclk) then
if rising_edge(scanclk_clk5) then -- use ddr clock/2 to not violate 100MHz max freq
phasecounter_reg <= "0110"; --phasecounter;
end if;
end process;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => div,--5,
clk0_duty_cycle => 50,
clk0_multiply_by => mult,--8,
clk0_phase_shift => "0",
clk1_divide_by => div,--5,
clk1_duty_cycle => 50,
clk1_multiply_by => mult,--8,
clk1_phase_shift => pshift_90,--"1250",
clk2_divide_by => div,--5,
clk2_duty_cycle => 50,
clk2_multiply_by => mult,--8,
clk2_phase_shift => pshift_180,--"2500",
clk3_divide_by => div,--5,
clk3_duty_cycle => 50,
clk3_multiply_by => mult,--8,
clk3_phase_shift => pshift_270,--"3750",
clk4_divide_by => div,
clk4_duty_cycle => 50,
clk4_multiply_by => mult,
clk4_phase_shift => pshift_rclk,--"0",
clk5_divide_by => div*2,
clk5_duty_cycle => 50,
clk5_multiply_by => mult,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => period,--8000,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=apll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_USED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
phasestep => phasestep,
phaseupdown => phaseupdown,
inclk => sub_wire8,
phasecounterselect => phasecounter_reg,
areset => areset,
--scanclk => scanclk,
scanclk => scanclk_clk5,
clk => sub_wire0,
locked => sub_wire6,
phasedone => phasedone
);
END SYN;
| gpl-2.0 |
gareth8118/lepton-eda | gnetlist/examples/vams/vhdl/basic-vhdl/spice_cs_arc.vhdl | 15 | 244 | ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/ahbrom.vhd | 3 | 8224 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 496;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800018";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E148";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"10800004";
when 16#00051# => romdata <= X"FD18C000";
when 16#00052# => romdata <= X"00000000";
when 16#00053# => romdata <= X"00000000";
when 16#00054# => romdata <= X"87444000";
when 16#00055# => romdata <= X"8730E01C";
when 16#00056# => romdata <= X"8688E00F";
when 16#00057# => romdata <= X"1280000B";
when 16#00058# => romdata <= X"03200000";
when 16#00059# => romdata <= X"82106300";
when 16#0005A# => romdata <= X"84102052";
when 16#0005B# => romdata <= X"C4206004";
when 16#0005C# => romdata <= X"C4206000";
when 16#0005D# => romdata <= X"C0206008";
when 16#0005E# => romdata <= X"84103FFF";
when 16#0005F# => romdata <= X"C4206014";
when 16#00060# => romdata <= X"84102007";
when 16#00061# => romdata <= X"C4206008";
when 16#00062# => romdata <= X"05000080";
when 16#00063# => romdata <= X"82100000";
when 16#00064# => romdata <= X"80A0E000";
when 16#00065# => romdata <= X"02800005";
when 16#00066# => romdata <= X"01000000";
when 16#00067# => romdata <= X"82004002";
when 16#00068# => romdata <= X"10BFFFFC";
when 16#00069# => romdata <= X"8620E001";
when 16#0006A# => romdata <= X"3D1003FF";
when 16#0006B# => romdata <= X"BC17A3E0";
when 16#0006C# => romdata <= X"BC278001";
when 16#0006D# => romdata <= X"9C27A060";
when 16#0006E# => romdata <= X"03100000";
when 16#0006F# => romdata <= X"81C04000";
when 16#00070# => romdata <= X"01000000";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"01000000";
when 16#00073# => romdata <= X"01000000";
when 16#00074# => romdata <= X"01000000";
when 16#00075# => romdata <= X"01000000";
when 16#00076# => romdata <= X"01000000";
when 16#00077# => romdata <= X"01000000";
when 16#00078# => romdata <= X"00000000";
when 16#00079# => romdata <= X"00000000";
when 16#0007A# => romdata <= X"00000000";
when 16#0007B# => romdata <= X"00000000";
when 16#0007C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd | 1 | 21946 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-2.0 |
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