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lennartbublies/ecdsa | tests/tb_ecdsa.vhd | 1 | 6,197 | ----------------------------------------------------------------------------------------------------
-- Testbench - ECDSA
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 14.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
use work.tld_ecdsa_package.all;
ENTITY tb_ecdsa IS
END tb_ecdsa;
ARCHITECTURE rtl OF tb_ecdsa IS
-- Import entity e_ecdsa
COMPONENT e_ecdsa IS
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
mode_i: IN std_logic;
hash_i: IN std_logic_vector(M-1 DOWNTO 0);
r_i: IN std_logic_vector(M-1 DOWNTO 0);
s_i: IN std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic;
valid_o: OUT std_logic;
sign_r_o: OUT std_logic_vector(M-1 DOWNTO 0);
sign_s_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL r, s: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, mode, done, valid, enable_keys_i: std_logic := '0';
SIGNAL hash: std_logic_vector (M-1 DOWNTO 0) ;
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 1;
BEGIN
-- Instantiate ecdsa entity
uut1: e_ecdsa PORT MAP(
clk_i => clk,
rst_i => rst,
enable_i => enable,
mode_i => mode,
hash_i => hash,
r_i => r,
s_i => s,
ready_o => done,
valid_o => valid,
sign_r_o => r,
sign_s_o => s
);
-- clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
tb : PROCESS
-- Procedure to generate random value for k
PROCEDURE gen_random(X : out std_logic_vector (M-1 DOWNTO 0); w: natural; s1, s2: inout Natural) IS
VARIABLE i_x, aux: integer;
VARIABLE rand: real;
BEGIN
aux := w/16;
FOR i IN 1 TO aux LOOP
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(65536)));-- real(2**16)));
x(i*16-1 DOWNTO (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16);
END LOOP;
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16))));
x(w-1 DOWNTO aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16));
END PROCEDURE;
-- Internal signals
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
VARIABLE seed1, seed2: positive;
VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer;
VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0;
VARIABLE avg_cycles: real;
VARIABLE initial_time, final_time: time;
VARIABLE xx: std_logic_vector (M-1 DOWNTO 0) ;
BEGIN
min_cycles:= 2**20;
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Loop over all test cases
FOR I IN 1 TO NUMBER_TESTS LOOP
-- Generate random input for k
gen_random(xx, M, seed1, seed2);
WHILE (xx = ZERO) LOOP
gen_random(xx, M, seed1, seed2);
END LOOP;
--hash <= xx;
hash <= "000" & x"CD06203260EEE9549351BD29733E7D1E2ED49D88";
--hash <= "101000111";
-- Start test 1:
-- Count runtime
--enable <= '1';
--initial_time := now;
--WAIT FOR PERIOD;
--enable <= '0';
--WAIT UNTIL (done = '1');
--final_time := now;
--cycles := (final_time - initial_time)/PERIOD;
--total_cycles := total_cycles+cycles;
--ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) & " TotalCycles: "
-- & integer'image(total_cycles) SEVERITY WARNING;
--IF cycles > max_cycles THEN
-- max_cycles:= cycles;
--END IF;
--IF cycles < min_cycles THEN
-- min_cycles:= cycles;
--END IF;
-- Start test 2:
-- Sign and verify
--WAIT FOR 2*PERIOD;
enable <= '1';
mode <= '0';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL done = '1';
WAIT FOR 2*PERIOD;
WAIT FOR PERIOD;
enable <= '1';
mode <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL done = '1';
WAIT FOR 2*PERIOD;
IF ( valid = '0' ) THEN
write(TX_LOC,string'("ERROR!!! Signature invalid"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
END LOOP;
WAIT FOR DELAY;
avg_cycles := real(total_cycles)/real(NUMBER_TESTS);
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!. MinCycles: " & integer'image(min_cycles) &
" MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) &
" AvgCycles: " & real'image(avg_cycles)
SEVERITY FAILURE;
END PROCESS;
END;
| gpl-3.0 | 63a4927d93d6f384f02b950bffadeab8 | 0.486526 | 3.822949 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/synth/blk_mem_gen_2.vhd | 1 | 14,007 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_2;
ARCHITECTURE blk_mem_gen_2_arch OF blk_mem_gen_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_2_arch : ARCHITECTURE IS "blk_mem_gen_2,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_2_arch: ARCHITECTURE IS "blk_mem_gen_2,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.9418 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.9418 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_2_arch;
| mit | c2c52eb52316461d1e327a50ff90deda | 0.630256 | 3.023964 | false | false | false | false |
Caian/Minesweeper | Projeto/game_lfsr.vhd | 1 | 3,353 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity game_lfsr is
port(
-- Comum
clock, rstn, enabled : in std_logic;
-- Estado do mouse
mouse_pos_x, mouse_pos_y : in std_logic_vector(9 downto 0);
-- Saida
random_x, random_y : out std_logic_vector(4 downto 0)
);
end entity;
architecture game_lfsr_logic of game_lfsr is
signal seed : std_logic_vector(31 downto 0) :=
"10101100011111110100010011010110";
signal mix : std_logic_vector(31 downto 0);
signal reg0 : std_logic_vector(3 downto 0);
signal reg1 : std_logic;
signal reg2 : std_logic;
signal reg3 : std_logic_vector(24 downto 0);
signal reg4 : std_logic;
begin
random_x <= reg0(3) & reg3(15) & reg3(18) & reg3(9) & reg4;
random_y <= reg3(23) & reg3(17) & reg3(7) & reg3(1) & reg1;
mix(0) <= mouse_pos_x(7) xor mouse_pos_y(2);
mix(1) <= mouse_pos_x(6) xor mouse_pos_y(6);
mix(2) <= mouse_pos_x(2) xor mouse_pos_y(7);
mix(3) <= mouse_pos_x(4) xor mouse_pos_y(4);
mix(4) <= mouse_pos_x(3) xor mouse_pos_y(8);
mix(5) <= mouse_pos_x(4) xor mouse_pos_y(2);
mix(6) <= mouse_pos_x(5) xor mouse_pos_y(5);
mix(7) <= mouse_pos_x(7) xor mouse_pos_y(3);
mix(8) <= mouse_pos_x(8) xor mouse_pos_y(6);
mix(9) <= mouse_pos_x(2) xor mouse_pos_y(3);
mix(10) <= mouse_pos_x(3) xor mouse_pos_y(2);
mix(11) <= mouse_pos_x(5) xor mouse_pos_y(1);
mix(12) <= mouse_pos_x(7) xor mouse_pos_y(1);
mix(13) <= mouse_pos_x(2) xor mouse_pos_y(9);
mix(14) <= mouse_pos_x(3) xor mouse_pos_y(0);
mix(15) <= mouse_pos_x(1) xor mouse_pos_y(7);
mix(16) <= mouse_pos_x(1) xor mouse_pos_y(8);
mix(17) <= mouse_pos_x(3) xor mouse_pos_y(6);
mix(18) <= mouse_pos_x(5) xor mouse_pos_y(4);
mix(19) <= mouse_pos_x(7) xor mouse_pos_y(3);
mix(20) <= mouse_pos_x(5) xor mouse_pos_y(6);
mix(21) <= mouse_pos_x(3) xor mouse_pos_y(8);
mix(22) <= mouse_pos_x(7) xor mouse_pos_y(1);
mix(23) <= mouse_pos_x(9) xor mouse_pos_y(2);
mix(24) <= mouse_pos_x(2) xor mouse_pos_y(3);
mix(25) <= mouse_pos_x(3) xor mouse_pos_y(6);
mix(26) <= mouse_pos_x(4) xor mouse_pos_y(7);
mix(27) <= mouse_pos_x(6) xor mouse_pos_y(5);
mix(28) <= mouse_pos_x(8) xor mouse_pos_y(4);
mix(29) <= mouse_pos_x(3) xor mouse_pos_y(8);
mix(30) <= mouse_pos_x(6) xor mouse_pos_y(9);
mix(31) <= mouse_pos_x(1) xor mouse_pos_y(3);
process(clock, rstn)
begin
if rstn = '0' then
reg0 <= seed(3 downto 0);
reg1 <= seed(4);
reg2 <= seed(5);
reg3 <= seed(30 downto 6);
reg4 <= seed(31);
elsif rising_edge(clock) then
seed <= seed + mix;
if enabled = '1' then
reg4 <= reg0(0);
reg3 <= (reg4 xor reg0(0)) & reg3(24 downto 1);
reg2 <= (reg3(0) xor reg0(0));
reg1 <= (reg2 xor reg0(0));
reg0 <= (reg1 xor reg0(0)) & reg0(3 downto 1);
else
reg0 <= seed(3 downto 0);
reg1 <= seed(4);
reg2 <= seed(5);
reg3 <= seed(30 downto 6);
reg4 <= seed(31);
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 2ccca264704d488a6190ffd6df8f456c | 0.551745 | 2.407035 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/synth/fifo_generator_1.vhd | 1 | 38,472 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_1 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_1;
ARCHITECTURE fifo_generator_1_arch OF fifo_generator_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_1_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_1_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_1_arch : ARCHITECTURE IS "fifo_generator_1,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_1_arch: ARCHITECTURE IS "fifo_generator_1,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=7,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=94,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=94,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=63,C_PROG_FULL_THRESH_NEGATE_VAL=62,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=7,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=7,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 7,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 94,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 94,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 63,
C_PROG_FULL_THRESH_NEGATE_VAL => 62,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 7,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 7,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_1_arch;
| mit | 135492ec79c8e3a37e2c3424e02e157d | 0.627937 | 2.91764 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_gf2m_point_doubling.vhd | 1 | 4,563 | ----------------------------------------------------------------------------------------------------
-- Testbench - gf2m Point Doubling
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 18.08.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
use work.tld_ecdsa_package.all;
ENTITY tb_gf2m_point_doubling IS
END tb_gf2m_point_doubling;
ARCHITECTURE rtl OF tb_gf2m_point_doubling IS
-- Import entity e_k163_point_doubling
COMPONENT e_gf2m_point_doubling IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y2_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Internal signals
SIGNAL xP, yP, xR, yR: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, done: std_logic := '0';
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate point doubling entity
doubling: e_gf2m_point_doubling GENERIC MAP (
MODULO => P
) PORT MAP(
clk_i => clk,
rst_i => rst,
enable_i => enable,
x1_i => xP,
y1_i => yP,
x2_io => xR,
y2_o => yR,
ready_o => done
);
-- Clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
-- Internal signals
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
BEGIN
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Test #1:
xP <= "000000010";
yP <= "000001111";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( xR /= "010010101" or (yR /= "100011000") ) THEN
write(TX_LOC,string'("TEST #1 ERROR!!! (010010101, 100011000) != (000000010, 000001111)^2"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Test #2:
xP <= "111111111";
yP <= "111111111";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( xR /= "111111111" or (yR /= "111111111") ) THEN
write(TX_LOC,string'("TEST #2 ERROR!!! (111111111, 111111111) != (111111111, 111111111)^2"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Test #3:
xP <= "011101110";
yP <= "010101111";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( xR /= "011001101" or (yR /= "100010001") ) THEN
write(TX_LOC,string'("TEST #3 ERROR!!! (011001101, 100010001) != (011101110, 010101111)^2"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!"
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | 4ce97037cfaab3bbe0adbb10ea53e261 | 0.49748 | 3.786722 | false | true | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_fifo.vhd | 2 | 4,798 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- NR_IQ_FIFOS are instantiated, they contain frames of one priority each
-- Input Control FIFO is a first-word-fall-through fifo, input data is immediately on output
-- Input Control FIFO stores output ports, length and memory start address of corresponding frame
-- switch to next word either if succesfully sent in input config arbitration module,
-- memory overflow or fifo overflow (see iq_overflow module)
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity input_queue_fifo is
Generic (
IQ_FIFO_DATA_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
wr_priority : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rd_en : in std_logic;
overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
dout : out std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
rd_priority : in std_logic;
full : out std_logic_vector(NR_IQ_FIFOS-1 downto 0);
empty : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end input_queue_fifo;
architecture rtl of input_queue_fifo is
component fifo_generator_1 is
port (
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
din : in std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
signal rd_en_sig : std_logic_vector(NR_IQ_FIFOS-1 downto 0) := (others => '0');
signal wr_en_sig : std_logic_vector(NR_IQ_FIFOS-1 downto 0) := (others => '0');
-- internal register, to be connected to a processor for more flexibility
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
init_p : process(rd_en, wr_priority, overflow, wr_en, rd_priority, high_priority_border_value_reg)
variable wr_temp : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := (others => '0');
variable rd_temp : std_logic_vector(0 downto 0) := (others => '0');
begin
rd_temp(0) := rd_priority;
wr_temp := wr_priority;
for i in 0 to NR_IQ_FIFOS-1 loop
-- read access
if (rd_en = '1' and to_integer(unsigned(rd_temp)) = i) or (overflow(i) = '1') then
rd_en_sig(i) <= '1';
else
rd_en_sig(i) <= '0';
end if;
-- write access
if NR_IQ_FIFOS = 1 then
wr_en_sig(0) <= wr_en;
else
if i = 0 then
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= '0';
else
wr_en_sig(i) <= wr_en;
end if;
else
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= wr_en;
else
wr_en_sig(i) <= '0';
end if;
end if;
end if;
end loop;
end process;
Xfifo : for i in 0 to NR_IQ_FIFOS-1 generate
input_queue_fifo_ip : fifo_generator_1
PORT MAP (
clk => clk,
rst => reset,
wr_en => wr_en_sig(i),
rd_en => rd_en_sig(i),
din => din,
dout => dout((i+1)*IQ_FIFO_DATA_WIDTH-1 downto i*IQ_FIFO_DATA_WIDTH),
full => full(i),
empty => empty(i)
);
end generate Xfifo;
end rtl;
| mit | d18b5e52515625411078ae13a6c98407 | 0.484368 | 3.894481 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/arbiter.vhd | 1 | 6,736 | ------------------------------------------------------
-- A four level, round-robin arbiter. This was
-- orginally coded by WD Peterson in VHDL.
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity arbiter is
port (
clk, rst :in std_logic;
req0, req1 :in std_logic;
req2, req3 :in std_logic;
gnt0, gnt1 :out std_logic;
gnt2, gnt3 :out std_logic
);
end entity;
architecture behavior of arbiter is
----------------Internal Registers-----------------
signal gnt, lgnt :std_logic_vector (1 downto 0);
signal comreq, lcomreq :std_logic;
signal beg, ledge :std_logic;
signal lgnt0, lgnt1 :std_logic;
signal lgnt2, lgnt3 :std_logic;
signal lmask0, lmask1 :std_logic;
signal lasmask :std_logic;
begin
----------------Code Starts Here------------------
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
lgnt0 <= '0';
lgnt1 <= '0';
lgnt2 <= '0';
lgnt3 <= '0';
else
lgnt0 <=(not lcomreq and not lmask1 and not lmask0 and
not req3 and not req2 and not req1 and req0)
or (not lcomreq and not lmask1 and lmask0 and
not req3 and not req2 and req0)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req0)
or (not lcomreq and lmask1 and lmask0 and req0)
or (lcomreq and lgnt0);
lgnt1 <=(not lcomreq and not lmask1 and not lmask0 and req1)
or (not lcomreq and not lmask1 and lmask0 and
not req3 and not req2 and req1 and not req0)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req1 and not req0)
or (not lcomreq and lmask1 and lmask0 and
req1 and not req0)
or (lcomreq and lgnt1);
lgnt2 <=(not lcomreq and not lmask1 and not lmask0 and
req2 and not req1)
or (not lcomreq and not lmask1 and lmask0 and req2)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req2 and not req1 and not req0)
or (not lcomreq and lmask1 and lmask0 and
req2 and not req1 and not req0)
or (lcomreq and lgnt2);
lgnt3 <=(not lcomreq and not lmask1 and not lmask0 and
req3 and not req2 and not req1)
or (not lcomreq and not lmask1 and lmask0 and
req3 and not req2)
or (not lcomreq and lmask1 and not lmask0 and req3)
or (not lcomreq and lmask1 and lmask0 and
req3 and not req2 and not req1 and not req0)
or (lcomreq and lgnt3);
end if;
end if;
end process;
------------------------------------------------------
-- lasmask state machine.
------------------------------------------------------
beg <= (req3 or req2 or req1 or req0) and not lcomreq;
process (clk)
begin
if (rising_edge(clk)) then
lasmask <= (beg and not ledge and not lasmask);
ledge <= (beg and not ledge and lasmask)
or (beg and ledge and not lasmask);
end if;
end process;
------------------------------------------------------
-- comreq logic.
------------------------------------------------------
lcomreq <= (req3 and lgnt3)
or (req2 and lgnt2)
or (req1 and lgnt1)
or (req0 and lgnt0);
------------------------------------------------------
-- Encoder logic.
------------------------------------------------------
lgnt <= ((lgnt3 or lgnt2) & (lgnt3 or lgnt1));
------------------------------------------------------
-- lmask register.
------------------------------------------------------
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
lmask1 <= '0';
lmask0 <= '0';
elsif (lasmask = '1') then
lmask1 <= lgnt(1);
lmask0 <= lgnt(0);
else
lmask1 <= lmask1;
lmask0 <= lmask0;
end if;
end if;
end process;
comreq <= lcomreq;
gnt <= lgnt;
------------------------------------------------------
-- Drive the outputs
------------------------------------------------------
gnt3 <= lgnt3;
gnt2 <= lgnt2;
gnt1 <= lgnt1;
gnt0 <= lgnt0;
end architecture;
------------------------------------------------------
-- Arbiter test bench
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity arbiter_tb is
end entity;
architecture test of arbiter_tb is
signal clk :std_logic := '0';
signal rst :std_logic := '1';
signal req0, req1 :std_logic := '0';
signal req2, req3 :std_logic := '0';
signal gnt0, gnt1 :std_logic := '0';
signal gnt2, gnt3 :std_logic := '0';
component arbiter is
port (
clk, rst :in std_logic;
req0, req1 :in std_logic;
req2, req3 :in std_logic;
gnt0, gnt1 :out std_logic;
gnt2, gnt3 :out std_logic
);
end component;
constant PERIOD :time := 20 ns;
begin
-- Clock generator
clk <= not clk after PERIOD/2;
rst <= '0' after PERIOD;
req0 <= '1' after PERIOD*1, '0' after PERIOD*2,
'1' after PERIOD*3, '0' after PERIOD*7;
req1 <= '1' after PERIOD*3, '0' after PERIOD*4;
req2 <= '1' after PERIOD*4, '0' after PERIOD*5;
req3 <= '1' after PERIOD*5, '0' after PERIOD*6;
-- Connect the DUT
Inst_arbiter : arbiter
port map (
clk => clk,
rst => rst,
req0 => req0,
req1 => req1,
req2 => req2,
req3 => req3,
gnt0 => gnt0,
gnt1 => gnt1,
gnt2 => gnt2,
gnt3 => gnt3
);
end architecture;
| mit | f744f1dc24b2f411c1fc0e3ecd24759f | 0.429632 | 4.402614 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_uart.vhd | 1 | 6,283 | ---------------------------------------------------------------------------------------------------
-- Testbench for the UART Connection (Receiver & Transmitter)
--
-- Author: Leander Schulz ([email protected])
-- Date: 28.10.2017
-- Last change: 28.10.2017
---------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_uart IS
END ENTITY tb_uart;
ARCHITECTURE tb_uart_arch OF tb_uart IS
--- Import Receiver
COMPONENT e_uart_receive_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
uart_i : IN std_logic;
mode_o : OUT std_logic;
r_o : OUT std_logic_vector(M-1 DOWNTO 0);
s_o : OUT std_logic_vector(M-1 DOWNTO 0);
m_o : OUT std_logic_vector(M-1 DOWNTO 0);
ready_o : OUT std_logic
);
END COMPONENT e_uart_receive_mux;
--- Import Transmitter
COMPONENT e_uart_transmit_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
enable_i : IN std_logic;
r_i : IN std_logic_vector(M-1 DOWNTO 0);
s_i : IN std_logic_vector(M-1 DOWNTO 0);
v_i : IN std_logic;
uart_o : OUT std_logic
);
END COMPONENT e_uart_transmit_mux;
--- Internal Signals
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL s_rx : std_logic := '1';
SIGNAL s_tx : std_logic;
SIGNAL s_mode : std_logic;
SIGNAL s_enable : std_logic := '0';
SIGNAL s_r : std_logic_vector(M-1 DOWNTO 0) ;
SIGNAL s_s : std_logic_vector(M-1 DOWNTO 0) ;
SIGNAL s_m_o : std_logic_vector(M-1 DOWNTO 0) ;
SIGNAL s_verify : std_logic := '0';
--- test cases
SIGNAL s_r_1 : std_logic_vector(167 DOWNTO 0) := x"07d7796309aee88283dbabf698ba6b6f8e26de11ae";
SIGNAL s_s_1 : std_logic_vector(167 DOWNTO 0) := x"0771e308d5acbc5064bd42e14a021862ebbc85eea6";
SIGNAL s_m_1 : std_logic_vector(167 DOWNTO 0) := x"0748656c6c6f20454344534120576f726c64212121";
BEGIN
--- Instance of Receiver
receiver_inst : e_uart_receive_mux
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
uart_i => s_rx,
mode_o => s_mode,
r_o => s_r,
s_o => s_s,
m_o => s_m_o,
ready_o => OPEN
);
--- Instance of Transmitter
transmitter_inst : e_uart_transmit_mux
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
mode_i => s_mode,
enable_i => s_enable,
r_i => s_r,
s_i => s_s,
v_i => s_verify,
uart_o => s_tx
);
--- generate clock
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
rx_gen : PROCESS IS
--- helper procedure
PROCEDURE p_send (
SIGNAL s_mode_i : IN std_logic;
SIGNAL s_r : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_s : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_m : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_rx : OUT std_logic
) IS
BEGIN
-- send mode
ASSERT FALSE REPORT "Send Mode" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR i IN 0 TO 7 LOOP
IF s_mode_i = '0' THEN
s_rx <= '0';
ELSE
s_rx <= '1';
END IF;
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
IF s_mode_i = '1' THEN
-- send r
ASSERT FALSE REPORT "Send Point R" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_r(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
-- send s
ASSERT FALSE REPORT "Send Point S" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_s(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END IF;
-- send m
ASSERT FALSE REPORT "Send Message" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
ASSERT (i*8+j)<168 SEVERITY WARNING;
s_rx <= s_m(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END p_send;
-- BEGIN TESTING ---
BEGIN
-- intitialize
s_rx <= '1';
WAIT FOR 100 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 880 ns;
-- Test Case 1
s_mode <= '0';
p_send(s_mode,s_r_1,s_s_1,s_m_1,s_rx); -- ignoring r and s
WAIT FOR 100 us;
-- Test Case 2
s_mode <= '1';
p_send(s_mode,s_r_1,s_s_1,s_m_1,s_rx);
-- start transmission
s_enable <= '1';
WAIT;
END PROCESS rx_gen;
END ARCHITECTURE tb_uart_arch; | gpl-3.0 | 4fc8282d87a855338608b13b47f5e966 | 0.424797 | 3.753286 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_module_receive.vhd | 1 | 7,523 | ----------------------------------------------------------------------------------------------------
-- Entity - UART Receive Mux Module Testbench
-- Testbench of e_uart_receive_mux
--
-- Generic:
-- baud_rate : baud rate of UART
-- Ports:
-- clk_i : clock signal
-- rst_i : global reset
-- rx_i : RX input of UART
-- mode_i : toggle SIG (0) and VALID (1)
-- wrreq_o : write request for FIFO input of data
-- fifo_o : parallel byte-aligned data output
-- sig_o : 163bit signature, only used in VALID mode
-- rdy_o : marks if receipt of data has finished and outputs are ready
--
-- Author: Leander Schulz ([email protected])
-- Date: 08.08.2017
-- Last change: 28.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_uart_receive_mux IS
END ENTITY tb_uart_receive_mux;
ARCHITECTURE tb_uart_receive_mux_arch OF tb_uart_receive_mux IS
-- IMPORT UART COMPONENT
COMPONENT e_uart_receive_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
uart_i : IN std_logic;
mode_o : OUT std_logic;
r_o : OUT std_logic_vector(M-1 DOWNTO 0);
s_o : OUT std_logic_vector(M-1 DOWNTO 0);
m_o : OUT std_logic_vector(M-1 DOWNTO 0);
ready_o : OUT std_logic
);
END COMPONENT e_uart_receive_mux;
-- TB internal signals
SIGNAL s_clk : std_logic;
SIGNAL s_rx : std_logic := '1';
SIGNAL s_rst : std_logic;
SIGNAL s_mode : std_logic;
SIGNAL s_data : std_logic_vector(7 DOWNTO 0);
SIGNAL s_r_o : std_logic_vector(M-1 DOWNTO 0);
SIGNAL s_s_o : std_logic_vector(M-1 DOWNTO 0);
SIGNAL s_m_o : std_logic_vector(M-1 DOWNTO 0);
SIGNAL s_rdy_o : std_logic;
PROCEDURE p_send_byte (
SIGNAL s_in : in std_logic_vector(7 downto 0);
SIGNAL s_rx : out std_logic
) IS
BEGIN
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= s_in(0); -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= s_in(1); -- Bit 1
WAIT FOR 2000 ns;
s_rx <= s_in(2); -- Bit 2
WAIT FOR 2000 ns;
s_rx <= s_in(3); -- Bit 3
WAIT FOR 2000 ns;
s_rx <= s_in(4); -- Bit 4
WAIT FOR 2000 ns;
s_rx <= s_in(5); -- Bit 5
WAIT FOR 2000 ns;
s_rx <= s_in(6); -- Bit 6
WAIT FOR 2000 ns;
s_rx <= s_in(7); -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
END p_send_byte;
-- baud table:
-- 9600 baud ^= 104166ns ^= 5208 cycles
-- 115200 baud ^= 8680ns ^= 434 cycles
-- 500000 baud ^= 2000ns ^= 100 cycles
BEGIN
module_instance : e_uart_receive_mux
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
uart_i => s_rx,
mode_o => s_mode,
r_o => s_r_o,
s_o => s_s_o,
m_o => s_m_o,
ready_o => s_rdy_o
);
clk_gen : PROCESS
BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS clk_gen;
rx_gen : PROCESS
BEGIN
s_rx <= '1';
WAIT FOR 100 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 880 ns;
-- set mode to 1 (verify)
s_data <= "11111111";
p_send_byte(s_data,s_rx);
ASSERT FALSE REPORT "R Byte 1-21" SEVERITY NOTE;
s_data <= "00000001";
p_send_byte(s_data,s_rx);
s_data <= "00000010";
p_send_byte(s_data,s_rx);
s_data <= "00000011";
p_send_byte(s_data,s_rx);
s_data <= "00000100";
p_send_byte(s_data,s_rx);
s_data <= "00000101";
p_send_byte(s_data,s_rx);
s_data <= "00000110";
p_send_byte(s_data,s_rx);
s_data <= "00000111";
p_send_byte(s_data,s_rx);
s_data <= "00001000";
p_send_byte(s_data,s_rx); -- byte 8
s_data <= "00001001";
p_send_byte(s_data,s_rx);
s_data <= "00001010";
p_send_byte(s_data,s_rx);
s_data <= "00001011";
p_send_byte(s_data,s_rx);
s_data <= "00001100";
p_send_byte(s_data,s_rx);
s_data <= "00001101";
p_send_byte(s_data,s_rx);
s_data <= "00001110";
p_send_byte(s_data,s_rx);
s_data <= "00001111";
p_send_byte(s_data,s_rx);
s_data <= "00010000";
p_send_byte(s_data,s_rx); -- byte 16
s_data <= "00010001";
p_send_byte(s_data,s_rx);
s_data <= "00010010";
p_send_byte(s_data,s_rx);
s_data <= "00010011";
p_send_byte(s_data,s_rx);
s_data <= "00010100";
p_send_byte(s_data,s_rx);
s_data <= "00010101";
p_send_byte(s_data,s_rx); -- byte 21
ASSERT FALSE REPORT "S Byte 1-21" SEVERITY NOTE;
s_data <= "10000001";
p_send_byte(s_data,s_rx);
s_data <= "10000010";
p_send_byte(s_data,s_rx);
s_data <= "10000011";
p_send_byte(s_data,s_rx);
s_data <= "10000100";
p_send_byte(s_data,s_rx);
s_data <= "10000101";
p_send_byte(s_data,s_rx);
s_data <= "10000110";
p_send_byte(s_data,s_rx);
s_data <= "10000111";
p_send_byte(s_data,s_rx);
s_data <= "10001000";
p_send_byte(s_data,s_rx); -- byte 8
s_data <= "10001001";
p_send_byte(s_data,s_rx);
s_data <= "10001010";
p_send_byte(s_data,s_rx);
s_data <= "10001011";
p_send_byte(s_data,s_rx);
s_data <= "10001100";
p_send_byte(s_data,s_rx);
s_data <= "10001101";
p_send_byte(s_data,s_rx);
s_data <= "10001110";
p_send_byte(s_data,s_rx);
s_data <= "10001111";
p_send_byte(s_data,s_rx);
s_data <= "10010000";
p_send_byte(s_data,s_rx); -- byte 16
s_data <= "10010001";
p_send_byte(s_data,s_rx);
s_data <= "10010010";
p_send_byte(s_data,s_rx);
s_data <= "10010011";
p_send_byte(s_data,s_rx);
s_data <= "10010100";
p_send_byte(s_data,s_rx);
s_data <= "10010101";
p_send_byte(s_data,s_rx); -- byte 21
ASSERT FALSE REPORT "Message Bytes" SEVERITY NOTE;
s_data <= "11010101";
p_send_byte(s_data,s_rx);
s_data <= "10011010";
p_send_byte(s_data,s_rx);
s_data <= "10111011";
p_send_byte(s_data,s_rx);
-- reset between mode switching
WAIT FOR 200000 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 200000 ns;
-- Switching mode_i to 0 (sign)
s_data <= "00000000";
p_send_byte(s_data,s_rx);
ASSERT FALSE REPORT "Verify - Message Bytes" SEVERITY NOTE;
s_data <= "11010101";
p_send_byte(s_data,s_rx);
s_data <= "10011010";
p_send_byte(s_data,s_rx);
s_data <= "10111011";
p_send_byte(s_data,s_rx);
WAIT;
END PROCESS rx_gen;
END ARCHITECTURE tb_uart_receive_mux_arch;
| gpl-3.0 | 1807eebcd84f82492e0d1d6937501a87 | 0.475342 | 3.115114 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/tri_mode_ethernet_mac_0_example_design.vhd | 1 | 37,467 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the Verilog example design for the Tri-Mode
-- Ethernet MAC core. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a real hardware test environment.
--
-- This level:
--
-- * Instantiates the FIFO Block wrapper, containing the
-- block level wrapper and an RX and TX FIFO with an
-- AXI-S interface;
--
-- * Instantiates a simple AXI-S example design,
-- providing an address swap and a simple
-- loopback function;
--
-- * Instantiates transmitter clocking circuitry
-- -the User side of the FIFOs are clocked at gtx_clk
-- at all times
--
-- * Instantiates a state machine which drives the AXI Lite
-- interface to bring the TEMAC up in the correct state
--
-- * Serializes the Statistics vectors to prevent logic being
-- optimized out
--
-- * Ties unused inputs off to reduce the number of IO
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- --------------------------------------------------
-- | EXAMPLE DESIGN WRAPPER |
-- | |
-- | |
-- | ------------------- ------------------- |
-- | | | | | |
-- | | Clocking | | Resets | |
-- | | | | | |
-- | ------------------- ------------------- |
-- | -------------------------------------|
-- | |FIFO BLOCK WRAPPER |
-- | | |
-- | | |
-- | | ----------------------|
-- | | | SUPPORT LEVEL |
-- | -------- | | |
-- | | | | | |
-- | | AXI |->|------------->| |
-- | | LITE | | | |
-- | | SM | | | |
-- | | |<-|<-------------| |
-- | | | | | |
-- | -------- | | |
-- | | | |
-- | -------- | ---------- | |
-- | | | | | | | |
-- | | |->|->| |->| |
-- | | PAT | | | | | |
-- | | GEN | | | | | |
-- | |(ADDR | | | AXI-S | | |
-- | | SWAP)| | | FIFO | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | |<-|<-| |<-| |
-- | | | | | | | |
-- | -------- | ---------- | |
-- | | | |
-- | | ----------------------|
-- | -------------------------------------|
-- --------------------------------------------------
--------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example_design level wrapper.
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_example_design is
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
config_board : in std_logic;
--serial_command : in std_logic; -- tied to pause_req_s
serial_response : out std_logic;
gen_tx_data : in std_logic;
chk_tx_data : in std_logic;
reset_error : in std_logic;
frame_error : out std_logic;
frame_errorn : out std_logic;
activity_flash : out std_logic;
activity_flashn : out std_logic
);
end tri_mode_ethernet_mac_0_example_design;
architecture wrapper of tri_mode_ethernet_mac_0_example_design is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the basic pattern generator
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_basic_pat_gen
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
check_resetn : in std_logic;
enable_pat_gen : in std_logic;
enable_pat_chk : in std_logic;
enable_address_swap : in std_logic;
speed : in std_logic_vector(1 downto 0);
-- data from the RX data path
rx_axis_tdata : in std_logic_vector(7 downto 0);
rx_axis_tvalid : in std_logic;
rx_axis_tlast : in std_logic;
rx_axis_tuser : in std_logic;
rx_axis_tready : out std_logic;
-- data TO the TX data path
tx_axis_tdata : out std_logic_vector(7 downto 0);
tx_axis_tvalid : out std_logic;
tx_axis_tlast : out std_logic;
tx_axis_tready : in std_logic;
frame_error : out std_logic;
activity_flash : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the AXI-Lite State machine
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_lite_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0);
s_axi_awvalid : out std_logic;
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0);
s_axi_wvalid : out std_logic;
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0);
s_axi_arvalid : out std_logic;
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the clocking logic
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design_clocks is
port (
-- clocks
clk_in_p : in std_logic;
clk_in_n : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
dcm_locked : out std_logic;
-- clock outputs
gtx_clk_bufg : out std_logic;
refclk_bufg : out std_logic;
s_axi_aclk : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset logic
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal s_axi_aclk : std_logic;
signal rx_mac_aclk : std_logic;
signal tx_mac_aclk : std_logic;
signal phy_resetn_int : std_logic;
-- resets (and reset generation)
signal s_axi_resetn : std_logic;
signal chk_resetn : std_logic;
signal gtx_resetn : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal dcm_locked : std_logic;
signal glbl_rst_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
signal glbl_rst_intn : std_logic;
-- USER side RX AXI-S interface
signal rx_fifo_clock : std_logic;
signal rx_fifo_resetn : std_logic;
signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal rx_axis_fifo_tvalid : std_logic;
signal rx_axis_fifo_tlast : std_logic;
signal rx_axis_fifo_tready : std_logic;
-- USER side TX AXI-S interface
signal tx_fifo_clock : std_logic;
signal tx_fifo_resetn : std_logic;
signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal tx_axis_fifo_tvalid : std_logic;
signal tx_axis_fifo_tlast : std_logic;
signal tx_axis_fifo_tready : std_logic;
-- RX Statistics serialisation signals
signal rx_statistics_valid : std_logic;
signal rx_statistics_valid_reg : std_logic;
signal rx_statistics_vector : std_logic_vector(27 downto 0);
signal rx_stats : std_logic_vector(27 downto 0);
signal rx_stats_shift : std_logic_vector(29 downto 0);
signal rx_stats_toggle : std_logic := '0';
signal rx_stats_toggle_sync : std_logic;
signal rx_stats_toggle_sync_reg : std_logic := '0';
-- TX Statistics serialisation signals
signal tx_statistics_valid : std_logic;
signal tx_statistics_valid_reg : std_logic;
signal tx_statistics_vector : std_logic_vector(31 downto 0);
signal tx_stats : std_logic_vector(31 downto 0);
signal tx_stats_shift : std_logic_vector(33 downto 0);
signal tx_stats_toggle : std_logic := '0';
signal tx_stats_toggle_sync : std_logic;
signal tx_stats_toggle_sync_reg : std_logic := '0';
-- Pause interface DESerialisation
signal pause_shift : std_logic_vector(18 downto 0);
signal pause_req : std_logic;
signal pause_val : std_logic_vector(15 downto 0);
-- AXI-Lite interface
signal s_axi_awaddr : std_logic_vector(11 downto 0);
signal s_axi_awvalid : std_logic;
signal s_axi_awready : std_logic;
signal s_axi_wdata : std_logic_vector(31 downto 0);
signal s_axi_wvalid : std_logic;
signal s_axi_wready : std_logic;
signal s_axi_bresp : std_logic_vector(1 downto 0);
signal s_axi_bvalid : std_logic;
signal s_axi_bready : std_logic;
signal s_axi_araddr : std_logic_vector(11 downto 0);
signal s_axi_arvalid : std_logic;
signal s_axi_arready : std_logic;
signal s_axi_rdata : std_logic_vector(31 downto 0);
signal s_axi_rresp : std_logic_vector(1 downto 0);
signal s_axi_rvalid : std_logic;
signal s_axi_rready : std_logic;
-- signal tie offs
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example
signal int_frame_error : std_logic;
signal int_activity_flash : std_logic;
-- set board defaults - only updated when reprogrammed
signal enable_address_swap : std_logic := '1';
signal enable_phy_loopback : std_logic := '0';
------------------------------------------------------------------------------
-- Begin architecture
------------------------------------------------------------------------------
begin
frame_error <= int_frame_error;
frame_errorn <= not int_frame_error;
activity_flash <= int_activity_flash;
activity_flashn <= not int_activity_flash;
capture_board_modea : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if config_board = '1' then
enable_address_swap <= gen_tx_data;
end if;
end if;
end process capture_board_modea;
capture_board_modeb : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if config_board = '1' then
enable_phy_loopback <= chk_tx_data;
end if;
end if;
end process capture_board_modeb;
----------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
----------------------------------------------------------------------------
example_clocks : tri_mode_ethernet_mac_0_example_design_clocks
port map (
-- differential clock inputs
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
-- asynchronous control/resets
glbl_rst => glbl_rst,
dcm_locked => dcm_locked,
-- clock outputs
gtx_clk_bufg => gtx_clk_bufg,
refclk_bufg => refclk_bufg,
s_axi_aclk => s_axi_aclk
);
-- generate the user side clocks for the axi fifos
tx_fifo_clock <= gtx_clk_bufg;
rx_fifo_clock <= gtx_clk_bufg;
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
example_resets : tri_mode_ethernet_mac_0_example_design_resets
port map (
-- clocks
s_axi_aclk => s_axi_aclk,
gtx_clk => gtx_clk_bufg,
-- asynchronous resets
glbl_rst => glbl_rst,
reset_error => reset_error,
rx_reset => rx_reset,
tx_reset => tx_reset,
dcm_locked => dcm_locked,
-- synchronous reset outputs
glbl_rst_intn => glbl_rst_intn,
gtx_resetn => gtx_resetn,
s_axi_resetn => s_axi_resetn,
phy_resetn => phy_resetn,
chk_resetn => chk_resetn
);
-- generate the user side resets for the axi fifos
tx_fifo_resetn <= gtx_resetn;
rx_fifo_resetn <= gtx_resetn;
------------------------------------------------------------------------------
-- Serialize the stats vectors
-- This is a single bit approach, retimed onto gtx_clk
-- this code is only present to prevent code being stripped..
------------------------------------------------------------------------------
-- RX STATS
-- first capture the stats on the appropriate clock
capture_rx_stats : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
rx_statistics_valid_reg <= rx_statistics_valid;
if rx_statistics_valid_reg = '0' and rx_statistics_valid = '1' then
rx_stats <= rx_statistics_vector;
rx_stats_toggle <= not rx_stats_toggle;
end if;
end if;
end process capture_rx_stats;
rx_stats_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => gtx_clk_bufg,
data_in => rx_stats_toggle,
data_out => rx_stats_toggle_sync
);
reg_rx_toggle : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
rx_stats_toggle_sync_reg <= rx_stats_toggle_sync;
end if;
end process reg_rx_toggle;
-- when an update is rxd load shifter (plus start/stop bit)
-- shifter always runs (no power concerns as this is an example design)
gen_shift_rx : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if (rx_stats_toggle_sync_reg xor rx_stats_toggle_sync) = '1' then
rx_stats_shift <= '1' & rx_stats & '1';
else
rx_stats_shift <= rx_stats_shift(28 downto 0) & '0';
end if;
end if;
end process gen_shift_rx;
rx_statistics_s <= rx_stats_shift(29);
-- TX STATS
-- first capture the stats on the appropriate clock
capture_tx_stats : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
tx_statistics_valid_reg <= tx_statistics_valid;
if tx_statistics_valid_reg = '0' and tx_statistics_valid = '1' then
tx_stats <= tx_statistics_vector;
tx_stats_toggle <= not tx_stats_toggle;
end if;
end if;
end process capture_tx_stats;
tx_stats_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => gtx_clk_bufg,
data_in => tx_stats_toggle,
data_out => tx_stats_toggle_sync
);
reg_tx_toggle : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
tx_stats_toggle_sync_reg <= tx_stats_toggle_sync;
end if;
end process reg_tx_toggle;
-- when an update is txd load shifter (plus start bit)
-- shifter always runs (no power concerns as this is an example design)
gen_shift_tx : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if (tx_stats_toggle_sync_reg /= tx_stats_toggle_sync) then
tx_stats_shift <= '1' & tx_stats & '1';
else
tx_stats_shift <= tx_stats_shift(32 downto 0) & '0';
end if;
end if;
end process gen_shift_tx;
tx_statistics_s <= tx_stats_shift(33);
------------------------------------------------------------------------------
-- DESerialize the Pause interface
-- This is a single bit approachtimed on gtx_clk
-- this code is only present to prevent code being stripped..
------------------------------------------------------------------------------
-- the serialised pause info has a start bit followed by the quanta and a stop bit
-- capture the quanta when the start bit hits the msb and the stop bit is in the lsb
gen_shift_pause : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
pause_shift <= pause_shift(17 downto 0) & pause_req_s;
end if;
end process gen_shift_pause;
grab_pause : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if (pause_shift(18) = '0' and pause_shift(17) = '1' and pause_shift(0) = '1') then
pause_req <= '1';
pause_val <= pause_shift(16 downto 1);
else
pause_req <= '0';
pause_val <= (others => '0');
end if;
end if;
end process grab_pause;
------------------------------------------------------------------------------
-- Instantiate the AXI-LITE Controller
----------------------------------------------------------------------------
axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm
port map (
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
mac_speed => mac_speed,
update_speed => update_speed,
serial_command => pause_req_s,
serial_response => serial_response,
phy_loopback => enable_phy_loopback,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block
port map (
gtx_clk => gtx_clk_bufg,
-- asynchronous reset
glbl_rstn => glbl_rst_intn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
-- Receiver => AXI-S Interface
------------------------------------------
rx_fifo_clock => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
-- Transmitter => AXI-S Interface
---------------------------------------------
tx_fifo_clock => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
------------------------------------------------------------------------------
-- Instantiate the address swapping module and simple pattern generator
------------------------------------------------------------------------------
basic_pat_gen_inst : tri_mode_ethernet_mac_0_basic_pat_gen
port map (
axi_tclk => tx_fifo_clock,
axi_tresetn => tx_fifo_resetn,
check_resetn => chk_resetn,
enable_pat_gen => gen_tx_data,
enable_pat_chk => chk_tx_data,
enable_address_swap => enable_address_swap,
speed => mac_speed,
rx_axis_tdata => rx_axis_fifo_tdata,
rx_axis_tvalid => rx_axis_fifo_tvalid,
rx_axis_tlast => rx_axis_fifo_tlast,
rx_axis_tuser => '0',
rx_axis_tready => rx_axis_fifo_tready,
tx_axis_tdata => tx_axis_fifo_tdata,
tx_axis_tvalid => tx_axis_fifo_tvalid,
tx_axis_tlast => tx_axis_fifo_tlast,
tx_axis_tready => tx_axis_fifo_tready,
frame_error => int_frame_error,
activity_flash => int_activity_flash
);
end wrapper;
| mit | 6fb79fc93f3249559569339ed9d30f49 | 0.43617 | 4.419842 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_squarer.vhd | 1 | 3,445 | ----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Classic Squaring
-- Computes the polynomial multiplication A.A mod f IN GF(2**m)
--
-- Ports:
-- a_i : Input to square
-- c_o : Square of input
--
-- Example:
-- (x^2 + x + 1)^2 = (x^4+x^2+1)
-- 1 1 1 = 1 0 1 0 1
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/classic_squarer.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 26.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) polynomial reduction
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_reducer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
-- Input SIGNAL
d_i: IN std_logic_vector(2*M-2 DOWNTO 0);
-- Output SIGNAL
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_reducer;
ARCHITECTURE rtl OF e_gf2m_reducer IS
-- Initial reduction matrix from polynomial F
CONSTANT R: matrix_reduction_return := reduction_matrix(MODULO);
BEGIN
-- GENERATE M-1 XORs FOR each redcutions matrix row
gen_xors: FOR j IN 0 TO M-1 GENERATE
l1: PROCESS(d_i)
VARIABLE aux: std_logic;
BEGIN
-- Store j-bit from input
aux := d_i(j);
-- Compute target bit FOR each reduction matrix column
FOR i IN 0 TO M-2 LOOP
aux := aux xor (d_i(M+i) and R(j)(i));
END LOOP;
c_o(j) <= aux;
END PROCESS;
END GENERATE;
END rtl;
------------------------------------------------------------
-- GF(2^M) classic squaring entity
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0) := ONE(M-1 DOWNTO 0)
);
PORT (
-- Input SIGNAL
a_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output SIGNAL
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_classic_squarer;
ARCHITECTURE rtl OF e_gf2m_classic_squarer IS
-- Import entity e_gf2m_reducer
COMPONENT e_gf2m_reducer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
d_i: IN std_logic_vector(2*M-2 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
SIGNAL d: std_logic_vector(2*M-2 DOWNTO 0);
BEGIN
d(0) <= a_i(0);
-- Polynomial multiplication
-- Calculates: x * x
-- 1 1 1 = 1 0 1 0 1
-- - -
-- - -
-- - -
square: FOR i IN 1 TO M-1 GENERATE
d(2*i-1) <= '0';
d(2*i) <= a_i(i);
END GENERATE;
-- Instantiate polynomial reducer
reducer: e_gf2m_reducer GENERIC MAP (
MODULO => MODULO
) PORT MAP(
d_i => d,
c_o => c_o
);
END rtl; | gpl-3.0 | f503feaffeb7395268906aa9e61cd01e | 0.476052 | 3.60733 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_funcsim.vhdl | 1 | 182,145 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:40:02 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_funcsim.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_0blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10) => '0',
ADDRARDADDR(9) => '0',
ADDRARDADDR(8 downto 5) => O1(3 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8 downto 5) => I1(3 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9 downto 8) => din(4 downto 3),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2 downto 0) => din(2 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9 downto 8) => din(9 downto 8),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2 downto 0) => din(7 downto 5),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(10) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(9 downto 8) => dout(4 downto 3),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(2 downto 0) => dout(2 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(10) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(9 downto 8) => dout(9 downto 8),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(2 downto 0) => dout(7 downto 5),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rd_rst,
RSTRAMB => rd_rst,
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_0rd_bin_cntr;
architecture STRUCTURE of fifo_generator_0rd_bin_cntr is
signal \^o1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute counter : integer;
attribute counter of \gc0.count_reg[0]\ : label is 2;
attribute counter of \gc0.count_reg[1]\ : label is 2;
attribute counter of \gc0.count_reg[2]\ : label is 2;
attribute counter of \gc0.count_reg[3]\ : label is 2;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair5";
begin
O1(3 downto 0) <= \^o1\(3 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(0),
Q => \^o1\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(1),
Q => \^o1\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(2),
Q => \^o1\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(3),
Q => \^o1\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => rd_rst,
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(3),
Q => \^q\(3)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(1),
I1 => \^o1\(0),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(1),
I1 => \^o1\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(2),
I1 => \^o1\(3),
O => D(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_handshaking_flags is
port (
valid : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_handshaking_flags : entity is "rd_handshaking_flags";
end fifo_generator_0rd_handshaking_flags;
architecture STRUCTURE of fifo_generator_0rd_handshaking_flags is
begin
\gv.ram_valid_d1_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => ram_valid_i,
Q => valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_valid_i : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_generator_0rd_status_flags_as;
architecture STRUCTURE of fifo_generator_0rd_status_flags_as is
signal \^empty\ : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count_d1[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_1\ : label is "soft_lutpair3";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= \^empty\;
p_18_out <= \^p_18_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst,
I1 => \^p_18_out\,
I2 => rd_en,
O => tmp_ram_rd_en
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^empty\,
O => ram_valid_i
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => rd_rst,
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => rd_rst,
Q => \^empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0reset_blk_ramfifo is
port (
rst_full_gen_i : out STD_LOGIC;
rst_d2 : out STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_0reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_0reset_blk_ramfifo is
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => wr_rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => wr_rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => wr_rst,
Q => rst_d3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff;
architecture STRUCTURE of fifo_generator_0synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_0;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_1 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_1;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_1 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => \^d\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_2 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_2;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_2 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => \^d\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_bin_cntr is
port (
ram_full_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_full_gen_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
I1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_0wr_bin_cntr;
architecture STRUCTURE of fifo_generator_0wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal n_0_ram_full_i_i_4 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RETAIN_INVERTER : boolean;
attribute RETAIN_INVERTER of \gic0.gc0.count[0]_i_1\ : label is std.standard.true;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute counter : integer;
attribute counter of \gic0.gc0.count_reg[0]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[1]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[2]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[3]\ : label is 3;
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => wr_rst,
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(0),
Q => O1(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(1),
Q => O1(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(2),
Q => O1(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => p_8_out(3),
Q => O1(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => wr_rst,
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800880088008"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => O3(1),
I3 => wr_pntr_plus2(1),
I4 => n_0_ram_full_i_i_4,
I5 => I1,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => O3(2),
I2 => wr_pntr_plus2(0),
I3 => O3(0),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000900"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => O3(3),
I2 => rst_full_gen_i,
I3 => wr_en,
I4 => p_0_out,
O => n_0_ram_full_i_i_3
);
ram_full_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => p_8_out(3),
I1 => O3(3),
I2 => rst_full_gen_i,
O => n_0_ram_full_i_i_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_status_flags_as is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_generator_0wr_status_flags_as;
architecture STRUCTURE of fifo_generator_0wr_status_flags_as is
signal \^p_0_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_0_out <= \^p_0_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_0_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => \^p_0_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_0blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_0blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0clk_x_pntrs is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 2 downto 0 );
I4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_generator_0clk_x_pntrs;
architecture STRUCTURE of fifo_generator_0clk_x_pntrs is
signal \^o3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal n_0_ram_empty_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_i_i_3 : STD_LOGIC;
signal n_0_ram_empty_i_i_4 : STD_LOGIC;
signal n_0_ram_empty_i_i_5 : STD_LOGIC;
signal \n_0_rd_pntr_bin[0]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_bin[1]_i_1\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in1_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair2";
begin
O3(3 downto 0) <= \^o3\(3 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_generator_0synchronizer_ff
port map (
I1(3 downto 0) => wr_pntr_gc(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_generator_0synchronizer_ff_0
port map (
I1(3 downto 0) => rd_pntr_gc(3 downto 0),
Q(3) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_3_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_generator_0synchronizer_ff_1
port map (
D(1 downto 0) => p_0_in(3 downto 2),
I1(3 downto 0) => Q(3 downto 0),
Q(2) => \n_2_gsync_stage[2].rd_stg_inst\,
Q(1) => \n_3_gsync_stage[2].rd_stg_inst\,
Q(0) => \n_4_gsync_stage[2].rd_stg_inst\,
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_generator_0synchronizer_ff_2
port map (
D(1) => \n_0_gsync_stage[2].wr_stg_inst\,
D(0) => \n_1_gsync_stage[2].wr_stg_inst\,
I1(3) => \n_0_gsync_stage[1].wr_stg_inst\,
I1(2) => \n_1_gsync_stage[1].wr_stg_inst\,
I1(1) => \n_2_gsync_stage[1].wr_stg_inst\,
I1(0) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_2_gsync_stage[2].wr_stg_inst\,
Q(1) => \n_3_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_4_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0010FFFF00100010"
)
port map (
I0 => n_0_ram_empty_i_i_2,
I1 => n_0_ram_empty_i_i_3,
I2 => rd_en,
I3 => p_18_out,
I4 => n_0_ram_empty_i_i_4,
I5 => n_0_ram_empty_i_i_5,
O => O1
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(1),
I1 => I2(1),
I2 => p_1_out(0),
I3 => I2(0),
O => n_0_ram_empty_i_i_2
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(2),
I1 => I2(2),
I2 => p_1_out(3),
I3 => I2(3),
O => n_0_ram_empty_i_i_3
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(0),
I1 => I1(0),
I2 => p_1_out(2),
I3 => I1(2),
O => n_0_ram_empty_i_i_4
);
ram_empty_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_1_out(1),
I1 => I1(1),
I2 => p_1_out(3),
I3 => I1(3),
O => n_0_ram_empty_i_i_5
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^o3\(2),
I1 => I3(2),
I2 => \^o3\(1),
I3 => I3(1),
I4 => I3(0),
I5 => \^o3\(0),
O => O2
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].wr_stg_inst\,
I1 => \n_4_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
I3 => \n_2_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[0]_i_1\
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].wr_stg_inst\,
I1 => \n_3_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[1]_i_1\
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[0]_i_1\,
Q => \^o3\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[1]_i_1\,
Q => \^o3\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(3)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => rd_pntr_gc(3)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].rd_stg_inst\,
I1 => \n_4_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(3),
I3 => \n_2_gsync_stage[2].rd_stg_inst\,
O => p_0_in(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].rd_stg_inst\,
I1 => \n_3_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(3),
O => p_0_in(1)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(0),
Q => p_1_out(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(1),
Q => p_1_out(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(2),
Q => p_1_out(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(3),
Q => p_1_out(3)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(0),
I1 => I4(1),
O => p_0_in1_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(1),
I1 => I4(2),
O => p_0_in1_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(2),
I1 => I4(3),
O => p_0_in1_out(2)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I4(3),
Q => wr_pntr_gc(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
valid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_logic : entity is "rd_logic";
end fifo_generator_0rd_logic;
architecture STRUCTURE of fifo_generator_0rd_logic is
signal p_14_out : STD_LOGIC;
signal ram_valid_i : STD_LOGIC;
begin
\gras.rsts\: entity work.fifo_generator_0rd_status_flags_as
port map (
E(0) => p_14_out,
I1 => I1,
empty => empty,
p_18_out => p_18_out,
ram_valid_i => ram_valid_i,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\grhf.rhf\: entity work.fifo_generator_0rd_handshaking_flags
port map (
ram_valid_i => ram_valid_i,
rd_clk => rd_clk,
rd_rst => rd_rst,
valid => valid
);
rpntr: entity work.fifo_generator_0rd_bin_cntr
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => p_14_out,
O1(3 downto 0) => O1(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_logic is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_full_gen_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
I1 : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_logic : entity is "wr_logic";
end fifo_generator_0wr_logic;
architecture STRUCTURE of fifo_generator_0wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.fifo_generator_0wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_generator_0wr_bin_cntr
port map (
E(0) => \^e\(0),
I1 => I1,
O1(3 downto 0) => O1(3 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(2 downto 0) => Q(2 downto 0),
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_0blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_0blk_mem_gen_prim_width
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_0blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_0blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end fifo_generator_0blk_mem_gen_v8_2_synth;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_0blk_mem_gen_top
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \fifo_generator_0blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.fifo_generator_0blk_mem_gen_v8_2_synth
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0memory is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0memory : entity is "memory";
end fifo_generator_0memory;
architecture STRUCTURE of fifo_generator_0memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\fifo_generator_0blk_mem_gen_v8_2__parameterized0\
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_0fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_0fifo_generator_ramfifo is
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_10_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_1_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_8_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_9_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_generator_0clk_x_pntrs
port map (
D(2) => \n_8_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_9_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_10_gntv_or_sync_fifo.gl0.rd\,
I1(3 downto 0) => p_20_out(3 downto 0),
I2(3 downto 0) => rd_pntr_plus1(3 downto 0),
I3(2 downto 0) => p_8_out(2 downto 0),
I4(3 downto 0) => p_9_out(3 downto 0),
O1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O2 => \n_1_gntv_or_sync_fifo.gcx.clkx\,
O3(3 downto 0) => p_0_out(3 downto 0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_0rd_logic
port map (
D(2) => \n_8_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_9_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_10_gntv_or_sync_fifo.gl0.rd\,
I1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O1(3 downto 0) => p_20_out(3 downto 0),
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
valid => valid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_0wr_logic
port map (
E(0) => p_3_out,
I1 => \n_1_gntv_or_sync_fifo.gcx.clkx\,
O1(3 downto 0) => p_9_out(3 downto 0),
O3(3 downto 0) => p_0_out(3 downto 0),
Q(2 downto 0) => p_8_out(2 downto 0),
full => full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_0memory
port map (
E(0) => p_3_out,
I1(3 downto 0) => p_9_out(3 downto 0),
O1(3 downto 0) => p_20_out(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.fifo_generator_0reset_blk_ramfifo
port map (
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_0fifo_generator_top;
architecture STRUCTURE of fifo_generator_0fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_0fifo_generator_ramfifo
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_generator_0fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_generator_0fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_0fifo_generator_top
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_OVERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_RD_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 13;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_generator_0fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_0fifo_generator_v12_0_synth
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0 is
port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_0 : entity is "fifo_generator_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_0 : entity is "fifo_generator_0,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_generator_0 : entity is "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_generator_0;
architecture STRUCTURE of fifo_generator_0 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 16;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 2;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 2;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 10;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 13;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 12;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_generator_0fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(3 downto 0) => NLW_U0_data_count_UNCONNECTED(3 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(15 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(15 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(1 downto 0) => NLW_U0_m_axis_tkeep_UNCONNECTED(1 downto 0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(1 downto 0) => NLW_U0_m_axis_tstrb_UNCONNECTED(1 downto 0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(3 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(3 downto 0),
rd_en => rd_en,
rd_rst => rd_rst,
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(15) => '0',
s_axis_tdata(14) => '0',
s_axis_tdata(13) => '0',
s_axis_tdata(12) => '0',
s_axis_tdata(11) => '0',
s_axis_tdata(10) => '0',
s_axis_tdata(9) => '0',
s_axis_tdata(8) => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(1) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(1) => '0',
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => valid,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(3 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(3 downto 0),
wr_en => wr_en,
wr_rst => wr_rst,
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit | 0159e80f45e609e79a7b7d2d1dea0665 | 0.6289 | 2.86689 | false | false | false | false |
titto-thomas/Pipeline_RISC | LmSmBlock.vhdl | 1 | 11,673 | ----------------------------------------
-- Datapath : IITB - Pipelined - RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 2/4/2015
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LmSmBlock is
port (
clock, reset : in std_logic;
Ir0_8 : in std_logic_vector(8 downto 0);
Ir12_15 : in std_logic_vector(3 downto 0);
M1_Sel, M2_Sel, M3_Sel : in std_logic;
M4_Sel, M9_Sel, M7_Sel, M8_Sel : in std_logic_vector(1 downto 0);
PC_en, IF_en, MemRead, MemWrite, RF_Write : in std_logic;
M1_Sel_ls, M2_Sel_ls, M3_Sel_ls : out std_logic;
M4_Sel_ls, M9_Sel_ls, M7_Sel_ls, M8_Sel_ls : out std_logic_vector(1 downto 0);
PC_en_ls, IF_en_ls, MemRead_ls, MemWrite_ls, RF_Write_ls : out std_logic;
LM_reg, SM_reg : out std_logic_vector(2 downto 0);
iteration : out integer
);
end LmSmBlock;
architecture behave of LmSmBlock is
signal dummy_ite : integer range 0 to 8 := 0;
signal local : std_logic_vector( 7 downto 0) := x"00";
begin
iteration <= dummy_ite;
Main : process( clock, reset, Ir0_8, Ir12_15, M1_Sel, M2_Sel, M3_Sel, M4_Sel, M9_Sel, M7_Sel, M8_Sel, PC_en, IF_en, MemRead, MemWrite, RF_Write )
begin
if clock = '1' then
if Ir12_15 = x"7" then
LM_reg <= "000";
if ( dummy_ite = 0 ) then
M2_Sel_ls <= '1';
if ( Ir0_8 = x"00" & '0' ) then
M1_Sel_ls <= '0';
M3_Sel_ls <= '0';
M4_Sel_ls <= "00";
M9_Sel_ls <= "00";
M7_Sel_ls <= "00";
M8_Sel_ls <= "00";
PC_en_ls <= '1';
IF_en_ls <= '1';
MemRead_ls <= '0';
MemWrite_ls <= '0';
RF_Write_ls <= '0';
SM_reg <= "000";
local <= x"00";
else
M1_Sel_ls <= '1';
M3_Sel_ls <= '0';
M4_Sel_ls <= "00";
M9_Sel_ls <= "01";
M7_Sel_ls <= "00";
M8_Sel_ls <= "01";
MemRead_ls <= '0';
MemWrite_ls <= '1';
RF_Write_ls <= '0';
if Ir0_8(0) = '1' then
SM_reg <= "000";
if ( Ir0_8(7 downto 1) /= "0000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 1) & '0';
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(1) = '1' then
SM_reg <= "001";
if ( Ir0_8(7 downto 2) /= "000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 2) & "00";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(2) = '1' then
SM_reg <= "010";
if ( Ir0_8(7 downto 3) /= "00000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 3) & "000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(3) = '1' then
SM_reg <= "011";
if ( Ir0_8(7 downto 4) /= "0000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 4) & "0000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(4) = '1' then
SM_reg <= "100";
if ( Ir0_8(7 downto 5) /= "000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 5) & "00000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(5) = '1' then
SM_reg <= "101";
if ( Ir0_8(7 downto 6) /= "00" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 6) & "000000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(6) = '1' then
SM_reg <= "110";
if ( Ir0_8(7) /= '0' ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7) & "0000000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
else
local <= x"00";
SM_reg <= "111";
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
end if;
else
M1_Sel_ls <= '1';
M3_Sel_ls <= '0';
M4_Sel_ls <= "00";
M9_Sel_ls <= "01";
M7_Sel_ls <= "01";
M8_Sel_ls <= "11";
MemRead_ls <= '0';
MemWrite_ls <= '1';
RF_Write_ls <= '0';
if local(1) = '1' then
SM_reg <= "001";
local(1) <= '0';
if ( local(7 downto 2) /= "000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(2) = '1' then
SM_reg <= "010";
local(2) <= '0';
if ( local(7 downto 3) /= "00000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(3) = '1' then
SM_reg <= "011";
local(3) <= '0';
if ( local(7 downto 4) /= "0000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(4) = '1' then
SM_reg <= "100";
local(4) <= '0';
if ( local(7 downto 5) /= "000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(5) = '1' then
SM_reg <= "101";
local(5) <= '0';
if ( local(7 downto 6) /= "00" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(6) = '1' then
SM_reg <= "110";
local(6) <= '0';
if ( local(7) /= '0' ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
else
local(7) <= '0';
SM_reg <= "111";
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
end if;
elsif Ir12_15 = x"6" then
SM_reg <= "000";
if ( dummy_ite = 0 ) then
M2_Sel_ls <= '1';
if ( Ir0_8 = x"00" & '0' ) then
M1_Sel_ls <= '0';
M3_Sel_ls <= '0';
M4_Sel_ls <= "00";
M9_Sel_ls <= "00";
M7_Sel_ls <= "00";
M8_Sel_ls <= "00";
PC_en_ls <= '1';
IF_en_ls <= '1';
MemRead_ls <= '0';
MemWrite_ls <= '0';
RF_Write_ls <= '0';
LM_reg <= "000";
local <= x"00";
else
M1_Sel_ls <= '1';
M3_Sel_ls <= '1';
M4_Sel_ls <= "00";
M9_Sel_ls <= "00";
M7_Sel_ls <= "00";
M8_Sel_ls <= "01";
MemRead_ls <= '1';
MemWrite_ls <= '0';
RF_Write_ls <= '1';
if Ir0_8(0) = '1' then
LM_reg <= "000";
if ( Ir0_8(7 downto 1) /= "0000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 1) & '0';
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(1) = '1' then
LM_reg <= "001";
if ( Ir0_8(7 downto 2) /= "000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 2) & "00";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(2) = '1' then
LM_reg <= "010";
if ( Ir0_8(7 downto 3) /= "00000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 3) & "000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(3) = '1' then
LM_reg <= "011";
if ( Ir0_8(7 downto 4) /= "0000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 4) & "0000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(4) = '1' then
LM_reg <= "100";
if ( Ir0_8(7 downto 5) /= "000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 5) & "00000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(5) = '1' then
LM_reg <= "101";
if ( Ir0_8(7 downto 6) /= "00" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7 downto 6) & "000000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif Ir0_8(6) = '1' then
LM_reg <= "110";
if ( Ir0_8(7) /= '0' ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= 1;
local <= Ir0_8(7) & "0000000";
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
else
local <= x"00";
LM_reg <= "111";
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
end if;
else
M1_Sel_ls <= '1';
M3_Sel_ls <= '1';
M4_Sel_ls <= "00";
M9_Sel_ls <= "00";
M7_Sel_ls <= "01";
M8_Sel_ls <= "11";
MemRead_ls <= '1';
MemWrite_ls <= '0';
RF_Write_ls <= '1';
if local(1) = '1' then
LM_reg <= "001";
local(1) <= '0';
if ( local(7 downto 2) /= "000000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(2) = '1' then
LM_reg <= "010";
local(2) <= '0';
if ( local(7 downto 3) /= "00000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(3) = '1' then
LM_reg <= "011";
local(3) <= '0';
if ( local(7 downto 4) /= "0000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(4) = '1' then
LM_reg <= "100";
local(4) <= '0';
if ( local(7 downto 5) /= "000" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(5) = '1' then
LM_reg <= "101";
local(5) <= '0';
if ( local(7 downto 6) /= "00" ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
elsif local(6) = '1' then
LM_reg <= "110";
local(6) <= '0';
if ( local(7) /= '0' ) then
PC_en_ls <= '0';
IF_en_ls <= '0';
dummy_ite <= dummy_ite + 1;
else
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
else
local(7) <= '0';
LM_reg <= "111";
PC_en_ls <= '1';
IF_en_ls <= '1';
dummy_ite <= 0;
end if;
end if;
else
M1_Sel_ls <= M1_Sel;
M2_Sel_ls <= M2_Sel;
M3_Sel_ls <= M3_Sel;
M4_Sel_ls <= M4_Sel;
M9_Sel_ls <= M9_Sel;
M7_Sel_ls <= M7_Sel;
M8_Sel_ls <= M8_Sel;
PC_en_ls <= PC_en;
IF_en_ls <= IF_en;
MemRead_ls <= MemRead;
MemWrite_ls <= MemWrite;
RF_Write_ls <= RF_Write;
end if;
end if;
end process Main;
end behave;
| gpl-2.0 | bb3571e615195b4bff06e22c5a7b230c | 0.419344 | 2.374009 | false | false | false | false |
caiopo/mips-multiciclo | src/blocoOperativo.vhd | 1 | 6,161 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer: Prof. Dr. Eng. Rafael Luiz Cancian
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity blocoOperativo is
port(
clock, reset: in std_logic;
PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst, EscReg, ULAFonteA: in std_logic;
ULAFonteB, ULAOp, FontePC: in std_logic_vector(1 downto 0);
opcode: out std_logic_vector(5 downto 0)
);
end entity;
architecture estrutural of blocoOperativo is
component ula is
generic(largura: natural := 8);
port(
entradaA, entradaB: in std_logic_vector(largura-1 downto 0);
Operacao: in std_logic_vector(2 downto 0);
saida: out std_logic_vector(largura-1 downto 0);
zero: out std_logic
);
end component;
component operacaoULA is
port(
ULAOp: in std_logic_vector(1 downto 0);
funct: in std_logic_vector(5 downto 0);
Operacao: out std_logic_vector(2 downto 0)
);
end component;
component memoria is
port(
clock: in std_logic;
ReadMem, WrtMem: in std_logic;
DataWrt: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
DataRd: out std_logic_vector(31 downto 0)
);
end component;
component deslocadorEsquerda is
generic(largura: natural := 8);
port(
entrada: in std_logic_vector(largura-1 downto 0);
saida: out std_logic_vector(largura-1 downto 0)
);
end component;
component multiplexador4x1 is
generic(largura: natural := 8);
port(
entrada0, entrada1, entrada2, entrada3: in std_logic_vector(largura-1 downto 0);
selecao: in std_logic_vector(1 downto 0);
saida: out std_logic_vector(largura-1 downto 0)
);
end component;
component multiplexador2x1 is
generic(largura: natural := 8);
port(
entrada0, entrada1: in std_logic_vector(largura-1 downto 0);
selecao: in std_logic;
saida: out std_logic_vector(largura-1 downto 0)
);
end component;
component bancoRegistradores is
generic(
largura: natural := 8;
bitsRegSerLido: natural := 2
);
port(
clock, reset: in std_logic;
EscReg: in std_logic;
RegSerLido1, RegSerLido2, RegSerEscrito: in std_logic_vector(bitsRegSerLido-1 downto 0);
DadoEscrita: in std_logic_vector(largura-1 downto 0);
DadoLido1, DadoLido2: out std_logic_vector(largura-1 downto 0)
);
end component;
component registrador is
generic(largura: natural := 8);
port(
clock, reset: in std_logic;
en: in std_logic;
d: in std_logic_vector(largura-1 downto 0);
q: out std_logic_vector(largura-1 downto 0)
);
end component;
component extensaoSinal is
generic(
larguraOriginal: natural := 8;
larguraExtendida: natural := 8);
port(
entrada: in std_logic_vector(larguraOriginal-1 downto 0);
saida: out std_logic_vector(larguraExtendida-1 downto 0)
);
end component;
signal zeroULA, enablePC: std_logic;
signal entradaPC, saidaRegPC, saidaMem, saidaMuxPC, saidaRegULA, saidaRegInstr: std_logic_vector(31 downto 0);
signal regLido1, regLido2, saidaRegDadosMem, dadoEscReg, dadoEscMem, saidaRegA, saidaRegB: std_logic_vector(31 downto 0);
signal saidaMuxAULA, saidaMuxBULA, saidaExtensaoSinal, saidaExtensaoSinalDesl, saidaULA: std_logic_vector(31 downto 0);
--signal saidaRegULA : std_logic_vector(31 downto 0);
signal saidaMuxRegSerEscrito: std_logic_vector(4 downto 0);
signal ctrlULA : std_logic_vector(2 downto 0);
signal deslEsq26to28 : std_logic_vector(31 downto 0);
constant quatro : std_logic_vector(31 downto 0) := (3 => '1', others => '0');
begin
enablePC <= PCEsc or (PCEscCond and zeroULA);
regPC: registrador generic map(32) port map(clock, reset, enablePC, entradaPC, saidaRegPC);
muxPC: multiplexador2x1 generic map(32) port map (saidaRegPC, saidaRegULA, IouD, saidaMuxPC);
mem: memoria port map (clock, LerMem, EscMem, dadoEscMem, saidaMuxPC, saidaMem);
regIntrucao: registrador generic map(32) port map(clock, reset, IREsc, saidaMem, saidaRegInstr);
muxRegSerEscrito: multiplexador2x1 generic map (5) port map(saidaRegInstr(20 downto 16), saidaRegInstr(15 downto 11), RegDst, saidaMuxRegSerEscrito);
bancoReg: bancoRegistradores generic map (32, 5) port map(clock, reset, EscReg, saidaRegInstr(25 downto 21), saidaRegInstr(20 downto 16),
saidaMuxRegSerEscrito, regLido1, regLido2);
regDadosMemoria: registrador generic map (32) port map(clock, reset, '1', saidaMem, saidaRegDadosMem);
muxDadoEscReg: multiplexador2x1 generic map(32) port map (saidaRegULA, saidaRegDadosMem, MemParaReg, dadoEscReg);
regA: registrador generic map (32) port map (clock, reset, '1', regLido1, saidaRegA);
regB: registrador generic map (32) port map (clock, reset, '1', regLido2, saidaRegB);
muxAEntradaULA : multiplexador2x1 generic map(32) port map (saidaRegPC, saidaRegA, ULAFonteA, saidaMuxAULA);
muxBEntradaULA: multiplexador4x1 generic map(32) port map (saidaRegB, quatro, saidaExtensaoSinal, saidaExtensaoSinalDesl, ULAFonteB, saidaMuxBULA);
extensorDeSinal : extensaoSinal generic map (16, 32) port map (saidaRegInstr(15 downto 0), saidaExtensaoSinal);
saidaExtensaoSinalDesl <= saidaExtensaoSinal(29 downto 0)&"00";
opULA: OperacaoULA port map(ULAOp, saidaRegInstr(5 downto 0), ctrlULA);
UnLogArit: ula generic map (32) port map (saidaMuxAULA, saidaMuxBULA, ctrlULA, saidaULA, zeroULA);
regSaidaULA: registrador generic map (32) port map (clock, reset, '1', saidaULA, saidaRegULA);
deslEsq26to28 <= saidaRegPC(31 downto 28)&saidaRegInstr(25 downto 0)&"00";
muxSaidaULA: multiplexador4x1 generic map (32) port map (saidaULA, saidaRegULA, deslEsq26to28, (others => '0'), FontePC, entradaPC);
opcode <= saidaRegInstr(31 downto 26);
end architecture;
| mit | 7680ab4c8b68d3d6f8b6c2ce29c67e74 | 0.696316 | 3.500568 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_axi_pipe.vhd | 1 | 7,241 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_pipe.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: A simple pipeline module to simplify the timing where a pattern
-- generator and address swap module can be muxed into the data path
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_axi_pipe is
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
rx_axis_fifo_tdata_in : in std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid_in : in std_logic;
rx_axis_fifo_tlast_in : in std_logic;
rx_axis_fifo_tready_in : out std_logic;
rx_axis_fifo_tdata_out : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid_out : out std_logic;
rx_axis_fifo_tlast_out : out std_logic;
rx_axis_fifo_tready_out : in std_logic
);
end tri_mode_ethernet_mac_0_axi_pipe;
architecture rtl of tri_mode_ethernet_mac_0_axi_pipe is
signal rd_addr : unsigned(5 downto 0) := (others => '0');
signal wr_addr : unsigned(5 downto 0) := (others => '0');
signal wea : std_logic;
signal rx_axis_fifo_tready_int : std_logic;
signal rx_axis_fifo_tvalid_int : std_logic;
signal rd_block : unsigned(1 downto 0) := (others => '0');
signal wr_block : unsigned(1 downto 0) := (others => '0');
begin
rx_axis_fifo_tready_in <= rx_axis_fifo_tready_int;
rx_axis_fifo_tvalid_out <= rx_axis_fifo_tvalid_int;
-- should always write when valid data is accepted
wr_enable : process (rx_axis_fifo_tvalid_in, rx_axis_fifo_tready_int)
begin
wea <= rx_axis_fifo_tvalid_in and rx_axis_fifo_tready_int;
end process wr_enable;
-- simply increment the write address after any valid write
wr_addr_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
wr_addr <= (others => '0');
elsif rx_axis_fifo_tvalid_in = '1' and rx_axis_fifo_tready_int = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end process wr_addr_p;
-- simply increment the read address after any validated read
rd_addr_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
rd_addr <= (others => '0');
elsif rx_axis_fifo_tvalid_int = '1' and rx_axis_fifo_tready_out = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end process rd_addr_p;
wr_block <= wr_addr(5 downto 4);
rd_block <= rd_addr(5 downto 4) -1;
-- need to generate the ready output - this is entirely dependant upon the full state
-- of the fifo
tready_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
rx_axis_fifo_tready_int <= '0';
else
if wr_block = rd_block then
rx_axis_fifo_tready_int <= '0';
else
rx_axis_fifo_tready_int <= '1';
end if;
end if;
end if;
end process tready_p;
-- need to generate the valid output - this is entirely dependant upon the full state
-- of the fifo
tvalid_p : process (rd_addr, wr_addr)
begin
if wr_addr = rd_addr then
rx_axis_fifo_tvalid_int <= '0';
else
rx_axis_fifo_tvalid_int <= '1';
end if;
end process tvalid_p;
LUT6_gen : for I in 0 to 7 generate
begin
RAM64X1D_inst : RAM64X1D
port map (
DPO => rx_axis_fifo_tdata_out(I),
SPO => open,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
D => rx_axis_fifo_tdata_in(I),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
WCLK => axi_tclk,
WE => wea
);
end generate;
RAM64X1D_inst : RAM64X1D
port map (
DPO => rx_axis_fifo_tlast_out,
SPO => open,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
D => rx_axis_fifo_tlast_in,
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
WCLK => axi_tclk,
WE => wea
);
end rtl;
| mit | b78951b2c1be42c98bfdecab7b263389 | 0.585969 | 3.642354 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_Vactcapofkplusone.vhd | 1 | 1,674 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Vactcapofkplusone;
architecture struct of kn_kalman_Vactcapofkplusone is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
signal Z2 : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vrefofkplusone, datab => Vactcapdashofkplusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => Z1, datab => Kofkplusone, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Vactcapdashofkplusone, datab => Z2, result => Vactcapofkplusone);
end struct;
| gpl-2.0 | 1bf6d019686bc968926d4f3e5ec031ec | 0.651135 | 3.451546 | false | false | false | false |
lfmunoz/4dsp_sip_interface | fmc116_ctrl.vhd | 1 | 16,779 | -------------------------------------------------------------------------------------
-- FILE NAME : fmc116_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc116_ctrl
-- architecture - fmc116_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- fmc116_ctrl
-- Notes: fmc116_ctrl
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
-- Library declarations
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity fmc116_ctrl is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
--External trigger
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
ext_trigger_buf : out std_logic;
--FIFO Control
adc_clk : in std_logic;
fifo_wr_en : out std_logic_vector(15 downto 0);
fifo_empty : in std_logic_vector(15 downto 0);
fifo_full : in std_logic_vector(15 downto 0);
--FMC Status
pg_m2c : in std_logic;
prsnt_m2c_l : in std_logic
);
end fmc116_ctrl;
architecture fmc116_ctrl_syn of fmc116_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component fmc11x_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component;
component pulse2pulse is
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component pulse2pulse;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_COMMAND : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_CONTROL : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_NB_BURSTS : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_BURST_SIZE : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_FMC_INFO : std_logic_vector(31 downto 0) := x"00000004";
constant EXT_TRIGGER_DISABLE : std_logic_vector(1 downto 0) := "00";
constant EXT_TRIGGER_RISE : std_logic_vector(1 downto 0) := "01";
constant EXT_TRIGGER_FALL : std_logic_vector(1 downto 0) := "10";
constant EXT_TRIGGER_BOTH : std_logic_vector(1 downto 0) := "11";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal adc_en_reg : std_logic_vector(15 downto 0);
signal trigger_sel_reg : std_logic_vector(1 downto 0);
signal nb_bursts_reg : std_logic_vector(31 downto 0);
signal burst_size_reg : std_logic_vector(31 downto 0);
signal cmd_reg : std_logic_vector(31 downto 0);
signal adc_cmd : std_logic_vector(31 downto 0);
signal arm : std_logic;
signal disarm : std_logic;
signal sw_trigger : std_logic;
signal armed : std_logic;
signal adc_en : std_logic_vector(15 downto 0);
signal unlim_bursts : std_logic;
signal nb_bursts_cnt : std_logic_vector(31 downto 0);
signal burst_size_cnt : std_logic_vector(31 downto 0);
signal trigger : std_logic;
signal ext_trigger : std_logic;
signal ext_trigger_prev0 : std_logic;
signal ext_trigger_prev1 : std_logic;
signal ext_trigger_re : std_logic;
signal ext_trigger_fe : std_logic;
begin
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc11x_stellar_cmd_inst : fmc11x_stellar_cmd
generic map
(
start_addr =>start_addr,
stop_addr =>stop_addr
)
port map
(
reset =>rst,
--command if
clk_cmd =>clk_cmd,
out_cmd =>out_cmd,
out_cmd_val =>out_cmd_val,
in_cmd =>in_cmd,
in_cmd_val =>in_cmd_val,
--register interface
clk_reg =>clk_cmd,
out_reg =>out_reg,
out_reg_val =>out_reg_val,
out_reg_val_ack =>out_reg_val_ack,
out_reg_addr =>out_reg_addr,
in_reg =>in_reg,
in_reg_val =>in_reg_val,
in_reg_req =>in_reg_req,
in_reg_addr =>in_reg_addr,
wr_ack => wr_ack,
mbx_in_reg =>(others=>'0'),
mbx_in_val =>'0'
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
cmd_reg <= (others => '0');
adc_en_reg <= (others => '0');
trigger_sel_reg <= (others => '0');
nb_bursts_reg <= (others => '0');
burst_size_reg <= (others => '0');
in_reg_val <= '0';
in_reg <= (others => '0');
wr_ack <= '0';
elsif (rising_edge(clk_cmd)) then
-- Write
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_COMMAND) then
cmd_reg <= out_reg;
else
cmd_reg <= (others => '0');
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_CONTROL) then
adc_en_reg <= out_reg(15 downto 0);
trigger_sel_reg <= out_reg(17 downto 16);
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_NB_BURSTS) then
nb_bursts_reg <= out_reg;
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_BURST_SIZE) then
burst_size_reg <= out_reg;
end if;
-- write ack directly on request:
if (out_reg_val_ack = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
-- Read
if (in_reg_req = '1' and in_reg_addr = ADDR_COMMAND) then
in_reg_val <= '1';
in_reg <= cmd_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_CONTROL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 12) &
or_reduce(fifo_full) &
and_reduce(fifo_empty) &
trigger_sel_reg &
adc_en_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_NB_BURSTS) then
in_reg_val <= '1';
in_reg <= nb_bursts_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_BURST_SIZE) then
in_reg_val <= '1';
in_reg <= burst_size_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_FMC_INFO) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 30) & pg_m2c & not prsnt_m2c_l;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Transfer command pulses to other ADC0 clock domain
----------------------------------------------------------------------------------------------------
adc0_cmd_pls: for i in 0 to 31 generate
pulse2pulse_inst : pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => adc_clk,
rst => rst,
pulsein => cmd_reg(i),
inbusy => open,
pulseout => adc_cmd(i)
);
end generate;
----------------------------------------------------------------------------------------------------
-- Map pulses
----------------------------------------------------------------------------------------------------
arm <= adc_cmd(0);
disarm <= adc_cmd(1);
sw_trigger <= adc_cmd(2);
----------------------------------------------------------------------------------------------------
-- LVDS Trigger Input
----------------------------------------------------------------------------------------------------
ibufds_trig : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => ext_trigger_p,
ib => ext_trigger_n,
o => ext_trigger
);
-----------------------------------------------------------------------------------
-- ADC triggering and burst control
-----------------------------------------------------------------------------------
process (rst, adc_clk)
begin
if (rst = '1') then
ext_trigger_prev0 <= '0';
ext_trigger_prev1 <= '0';
ext_trigger_re <= '0';
ext_trigger_fe <= '0';
trigger <= '0';
armed <= '0';
adc_en <= (others => '0');
unlim_bursts <= '0';
nb_bursts_cnt <= (others => '0');
burst_size_cnt <= (others => '0');
fifo_wr_en <= (others => '0');
elsif (rising_edge(adc_clk)) then
ext_trigger_prev0 <= ext_trigger;
ext_trigger_prev1 <= ext_trigger_prev0;
-- Generate pulse on rising edge external trigger
if (ext_trigger_prev0 = '1' and ext_trigger_prev1 = '0') then
ext_trigger_re <= '1';
else
ext_trigger_re <= '0';
end if;
-- Generate pulse on falling edge external trigger
if (ext_trigger_prev0 = '0' and ext_trigger_prev1 = '1') then
ext_trigger_fe <= '1';
else
ext_trigger_fe <= '0';
end if;
-- Select the trigger source
if (armed = '1' and sw_trigger = '1') then
trigger <= '1';
elsif (armed = '1' and ext_trigger_re = '1' and (trigger_sel_reg = EXT_TRIGGER_RISE or trigger_sel_reg = EXT_TRIGGER_BOTH) ) then
trigger <= '1';
elsif (armed = '1' and ext_trigger_fe = '1' and (trigger_sel_reg = EXT_TRIGGER_FALL or trigger_sel_reg = EXT_TRIGGER_BOTH) ) then
trigger <= '1';
else
trigger <= '0';
end if;
-- Latch channel enable
if (arm = '1' and armed = '0') then
adc_en <= adc_en_reg;
end if;
if (arm = '1' and armed = '0') then
armed <= '1';
elsif (disarm = '1' and armed = '1') then
armed <= '0';
elsif (unlim_bursts = '0' and nb_bursts_cnt = 0 and burst_size_cnt = 0) then
armed <= '0';
end if;
-- No of burst set to 0 means unlimited amount of bustst
if (armed = '0') then
unlim_bursts <= not or_reduce(nb_bursts_reg);
end if;
-- When not (yet) armed copy the register into the counter
if (armed = '0') then
nb_bursts_cnt <= nb_bursts_reg;
elsif (trigger = '1' and burst_size_cnt = 0 and nb_bursts_cnt /= 0) then
nb_bursts_cnt <= nb_bursts_cnt - '1';
end if;
-- Conversion start when the burst size counter is unequal to 0
-- Load the burst size counter on a trigger, when the previous burst is
-- finished and one or more channels are selected.
if (armed = '0') then
burst_size_cnt <= (others => '0');
elsif (trigger = '1' and burst_size_cnt = 0 and (nb_bursts_cnt /= 0 or unlim_bursts = '1')) then
burst_size_cnt <= burst_size_reg;
-- Decrease the burst size counter every conversion
elsif (burst_size_cnt /= 0) then
burst_size_cnt <= burst_size_cnt - 1;
end if;
if (trigger = '1' and burst_size_cnt = 0 and (nb_bursts_cnt /= 0 or unlim_bursts = '1')) then
fifo_wr_en <= adc_en;
elsif (burst_size_cnt = 1) then
fifo_wr_en <= (others => '0');
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
ext_trigger_buf <= ext_trigger;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc116_ctrl_syn;
| mit | d84f9ad525dbaa12fc0330e4a884471b | 0.472078 | 3.964792 | false | false | false | false |
rkujawa/cr2amiga | clk_gen.vhd | 1 | 599 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clk_gen is
port( clk : in STD_LOGIC;
clkmod : out STD_LOGIC;
divval : in integer);
end clk_gen;
architecture Behavioral of clk_gen is
signal counter,divide : integer := 0;
begin
divide <= divval;
process(clk)
begin
if( rising_edge(clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
clkmod <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
clkmod <= '1';
else
clkmod <= '0';
counter <= 0;
end if;
end if;
end process;
end Behavioral; | mit | e22acf5ca796116de02668acbbd6d082 | 0.626043 | 2.786047 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_axi_pat_gen.vhd | 1 | 14,498 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_pat_gen.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a very simple pattern generator which will generate packets
-- with the supplied dest_addr and src_addr and incrementing data. The packet size
-- increments between the min and max size (which can be set to the same value if a
-- specific size is required
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_axi_pat_gen is
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_pat_gen : in std_logic;
speed : in std_logic_vector(1 downto 0);
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end tri_mode_ethernet_mac_0_axi_pat_gen;
architecture rtl of tri_mode_ethernet_mac_0_axi_pat_gen is
-- State machine
type state_typ is (IDLE,
HEADER,
SIZE,
SET_DATA,
OVERHEAD);
function Sel (Cond : boolean; A,B : integer) return integer is
begin
if Cond then
return A;
else
return B;
end if;
end function Sel;
-- work out the adjustment required to get the right packet size.
constant PKT_ADJUST : integer := Sel(ENABLE_VLAN,22,18);
-- generate the vlan fields
constant VLAN_HEADER : bit_vector(31 downto 0) := X"8100" & VLAN_PRIORITY & '0' & VLAN_ID;
-- generate the require header count compare
constant HEADER_LENGTH : integer := Sel(ENABLE_VLAN,15,11);
-- generate the required bandwidth controls based on speed
-- we want to use less than 100% bandwidth to avoid loopback overflow
constant BW_1G : integer := 230;
constant BW_100M : integer := 23;
constant BW_10M : integer := 2;
signal next_gen_state : state_typ;
signal gen_state : state_typ;
signal byte_count : unsigned(11 downto 0);
signal header_count : unsigned(3 downto 0);
signal overhead_count : unsigned(4 downto 0);
signal pkt_size : unsigned(11 downto 0);
signal lut_data : std_logic_vector(7 downto 0);
signal tvalid_int : std_logic;
-- rate control signals
signal basic_rc_counter : unsigned(7 downto 0);
signal add_credit : std_logic;
signal credit_count : unsigned(12 downto 0);
signal axi_treset : std_logic;
constant dummy : bit_vector(47 downto 0) := (others => '0');
begin
axi_treset <= not axi_tresetn;
-- need a packet counter - max size limited to 11 bits
byte_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
byte_count <= (others => '0');
elsif gen_state = SET_DATA and byte_count /= X"000" and tready = '1' then
byte_count <= byte_count - X"001";
elsif gen_state = HEADER then
byte_count <= pkt_size;
end if;
end if;
end process byte_count_p;
-- need a smaller count to manage the header insertion
header_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
header_count <= (others => '0');
elsif gen_state = HEADER and header_count /= X"F" and (tready = '1' or tvalid_int = '0') then
header_count <= header_count + X"1";
elsif gen_state = SIZE and tready = '1' then
header_count <= (others => '0');
end if;
end if;
end process header_count_p;
-- need a smaller count to manage the overhead
overhead_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
overhead_count <= (others => '0');
elsif gen_state = OVERHEAD and overhead_count /= "00000" and tready = '1' then
overhead_count <= overhead_count - "00001";
elsif gen_state = IDLE then
overhead_count <= "11000"; -- 24 in decimal
end if;
end if;
end process overhead_count_p;
-- need a smaller count to manage the header insertion
-- adjust parameter values by 18 to allow for header and crc
-- so the pkt_size can be sued directly in the size field
pkt_size_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
pkt_size <= MIN_SIZE - PKT_ADJUST;
elsif gen_state = SET_DATA and next_gen_state /= SET_DATA then
if pkt_size = MAX_SIZE - PKT_ADJUST then
pkt_size <= MIN_SIZE - PKT_ADJUST;
else
pkt_size <= pkt_size + "001";
end if;
end if;
end if;
end process pkt_size_p;
-- store the parametised values in a lut (64 deep)
-- this should mean the values could be adjusted in fpga_editor etc..
LUT6_gen : for I in 0 to 7 generate
begin
LUT6_inst : LUT6
generic map (
INIT => dummy &
VLAN_HEADER(I) &
VLAN_HEADER(I+8) &
VLAN_HEADER(I+16) &
VLAN_HEADER(I+24) &
SRC_ADDR(I) &
SRC_ADDR(I+8) &
SRC_ADDR(I+16) &
SRC_ADDR(I+24) &
SRC_ADDR(I+32) &
SRC_ADDR(I+40) &
DEST_ADDR(I) &
DEST_ADDR(I+8) &
DEST_ADDR(I+16) &
DEST_ADDR(I+24) &
DEST_ADDR(I+32) &
DEST_ADDR(I+40)
)
port map (
O => lut_data(I),
I0 => header_count(0),
I1 => header_count(1),
I2 => header_count(2),
I3 => header_count(3),
I4 => '0',
I5 => '0'
);
end generate;
-- rate control logic
-- first we need an always active counter to provide the credit control
basic_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' or enable_pat_gen = '0' then
basic_rc_counter <= (others => '1');
else
basic_rc_counter <= basic_rc_counter + X"01";
end if;
end if;
end process basic_count_p;
-- now we need to set the compare level depending upon the selected speed
-- the credits are applied using a simple less-than check
gen_inc_control_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if speed(1) = '1' then
if basic_rc_counter < X"E6" then -- decimal 230
add_credit <= '1';
else
add_credit <= '0';
end if;
elsif speed(0) = '1' then
if basic_rc_counter < X"17" then -- decimal 23
add_credit <= '1';
else
add_credit <= '0';
end if;
else
if basic_rc_counter < X"02" then
add_credit <= '1';
else
add_credit <= '0';
end if;
end if;
end if;
end process gen_inc_control_p;
-- basic credit counter - -ve value means do not send a frame
credit_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
credit_count <= (others => '0');
else
-- if we are in frame
if gen_state /= IDLE then
if add_credit = '0' and credit_count(12 downto 10) /= "110" then -- stop decrementing at -2048
credit_count <= credit_count - "0000000000001";
end if;
else
if add_credit = '1' and credit_count(12 downto 11) /= "01" then -- stop incrementing at 2048
credit_count <= credit_count + 1;
end if;
end if;
end if;
end if;
end process credit_count_p;
-- simple state machine to control the data
-- on the transition from IDLE we reset the counters and increment the packet size
next_s : process(gen_state, enable_pat_gen, header_count, tready, byte_count, tvalid_int, overhead_count, credit_count)
begin
next_gen_state <= gen_state;
case gen_state is
when IDLE =>
if enable_pat_gen = '1' and tvalid_int = '0' and credit_count(12) = '0' then
next_gen_state <= HEADER;
end if;
when HEADER =>
if header_count = HEADER_LENGTH and tready = '1' then
next_gen_state <= SIZE;
end if;
when SIZE =>
if header_count = X"0" and tready = '1' then
next_gen_state <= SET_DATA;
end if;
when SET_DATA =>
if byte_count = X"001" and tready = '1' then -- may need to be 1
next_gen_state <= OVERHEAD;
end if;
when OVERHEAD =>
if overhead_count = "00001" and tready = '1' then
next_gen_state <= IDLE;
end if;
end case;
end process;
state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
gen_state <= IDLE;
else
gen_state <= next_gen_state;
end if;
end if;
end process state_p;
-- now generate the TVALID output
valid_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
tvalid_int <= '0';
elsif gen_state /= IDLE and gen_state /= OVERHEAD then
tvalid_int <= '1';
elsif tready = '1' then
tvalid_int <= '0';
end if;
end if;
end process valid_p;
-- now generate the TDATA output
data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if gen_state = HEADER and (tready = '1' or tvalid_int = '0') then
tdata <= lut_data;
elsif gen_state = SIZE and tready = '1' then
if header_count(3) = '1' then
tdata <= "00000" & std_logic_vector(pkt_size(10 downto 8));
else
tdata <= std_logic_vector(pkt_size(7 downto 0));
end if;
elsif tready = '1' then
tdata <= std_logic_vector(byte_count(7 downto 0));
end if;
end if;
end process data_p;
-- now generate the TLAST output
last_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
tlast <= '0';
elsif byte_count = "001" and tready = '1' then
tlast <= '1';
elsif tready = '1' then
tlast <= '0';
end if;
end if;
end process last_p;
tvalid <= tvalid_int;
end rtl;
| mit | 20c9dc23a10ef4224d93d6234d541ed1 | 0.538971 | 4.089704 | false | false | false | false |
Caian/Minesweeper | Projeto/vga_mouse_dec.vhd | 1 | 10,573 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity vga_mouse_dec is
port(
-- Pixel atual a ser desenhado
vga_x, vga_y : in std_logic_vector(9 downto 0);
-- Posicao atual do mouse
mouse_pos_x, mouse_pos_y : in std_logic_vector(9 downto 0);
-- Indice da cor do mouse na paleta de cores
mouse_color_index : out std_logic_vector(3 downto 0);
-- Indica se o pixel pertence ao mouse
mouse_visible : out std_logic
);
end entity;
architecture vga_mouse_dec_logic of vga_mouse_dec is
signal subx, suby : std_logic_vector(10 downto 0);
begin
subx <= ('0' & vga_x) - ('0' & mouse_pos_x);
suby <= ('0' & vga_y) - ('0' & mouse_pos_y);
process (subx, suby)
begin
if subx >= 0 and subx < 12 and suby >= 0 and suby < 20 then
case subx(3 downto 0) & suby(4 downto 0) is
when "000000000" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000011" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001100011" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001100100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010000100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001100101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010000101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010100101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000110" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001100110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010000110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010100110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011000110" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000000111" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000100111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001000111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001100111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010000111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010100111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011000111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011100111" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001000" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001001000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001101000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010001000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010101000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100001000" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001001001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001101001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010001001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010101001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100001001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100101001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001001010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001101010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010001010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010101010" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011101010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "100001010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "100101010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "101001010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001011" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001001011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001101011" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010001011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "010101011" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001011" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "001001100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010001100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010101100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001100" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101100" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000101101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010001101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010101101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011001101" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101101" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "000001110" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010101110" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011001110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101110" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100001110" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "010101111" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011001111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "011101111" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100001111" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011010000" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011110000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100010000" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100110000" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011010001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011110001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100010001" =>
mouse_visible <= '1';
mouse_color_index <= "1011";
when "100110001" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "011110010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when "100010010" =>
mouse_visible <= '1';
mouse_color_index <= "1110";
when others =>
mouse_visible <= '0';
mouse_color_index <= "1111";
end case;
else
mouse_visible <= '0';
mouse_color_index <= "1111";
end if;
end process;
end architecture;
| gpl-2.0 | 0e68fe6ef557ca662763688fe5bcc17e | 0.514518 | 3.262265 | false | false | false | false |
lennartbublies/ecdsa | src/e_baud_clock.vhd | 1 | 1,757 | -------------------------------------------------------------------------------
-- Module: e_baud_clock
-- Purpose: Generates a continous clock signal from baud rate
--
-- Author: Leander Schulz
-- Date: 06.09.2016
-- Last change: 06.09.2016
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY e_baud_clock IS
GENERIC(
baud_rate : IN NATURAL RANGE 1200 TO 500000);
PORT( clk_i : IN std_logic; -- system clock
rst_i : IN std_logic; -- asynchronous reset
baud_clk_o : OUT std_logic); -- generated baud rate clock
END ENTITY e_baud_clock;
ARCHITECTURE bclk_arch OF e_baud_clock IS
SUBTYPE max_cycles IS INTEGER RANGE 0 TO 50000000;
SIGNAL clk_count : max_cycles := 0;
CONSTANT clk_period : INTEGER := 20; -- 1.000.000.000 ns / 50 MHz
-- symbol_length in ns
-- (e.g. 104.166ns at 9600 Baud):
CONSTANT symbol_length : INTEGER := 1000000000 / baud_rate;
-- symbol_cycles = number of clock periods per symbol
-- (e.g. 5208 cycles at 9600 Baud)
CONSTANT symbol_cycles : max_cycles := symbol_length / clk_period;
BEGIN
p_generator : PROCESS(clk_i,rst_i)
BEGIN
IF rst_i = '1' THEN
baud_clk_o <= '0';
clk_count <= 0;
ELSIF rising_edge(clk_i) THEN
IF clk_count < symbol_cycles THEN
baud_clk_o <= '0';
clk_count <= clk_count + 1;
ELSE
baud_clk_o <= '1';
clk_count <= 0;
END IF;
END IF;
END PROCESS p_generator;
END ARCHITECTURE bclk_arch;
| gpl-3.0 | e76be11f48d9cd8f597b3df7b45c757e | 0.498577 | 4.029817 | false | false | false | false |
gihankarunarathne/vhdl-learn | tute_I/Tutorial_I/Variable_Logic_fn.vhd | 1 | 1,183 | ----------------------------------------------------------------------------------
-- Company: UOM
-- Engineer: Gihan Karunarathne
--
-- Create Date: 13:42:15 08/21/2013
-- Design Name:
-- Module Name: Variable_Logic_fn - Behavioral
-- Project Name: Tutorial I
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Variable_Logic_fn is
port( input: in STD_LOGIC_VECTOR ( 2 downto 0);
D: in STD_LOGIC;
Z: out STD_LOGIC
);
end Variable_Logic_fn;
architecture Behavioral of Variable_Logic_fn is
begin
Z <= '0' when input="000" else
D when input="001" else
'1' when input="010" else
'0' when input="011" else
not D when input="100" else
'0' when input="101" else
'0' when input="110" else
'0' when input="111";
end Behavioral; | mit | aaff0ac179e047a88ffa18f057e35ed8 | 0.573964 | 3.662539 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_nm_sipo_register.vhd | 1 | 2,599 | ----------------------------------------------------------------------------------------------------
-- Testbench - SIPO Register (Serial In Parallel Out)
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 18.08.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_nm_sipo_register IS
END tb_nm_sipo_register;
ARCHITECTURE rtl OF tb_nm_sipo_register IS
-- Import entity e_sipo_register
COMPONENT e_nm_sipo_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
data_i : IN std_logic_vector(U-1 DOWNTO 0);
data_o : OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL sipo: std_logic_vector(31 DOWNTO 0) := (OTHERS=>'0');
SIGNAL data: std_logic_vector(7 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable: std_logic := '0';
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate sipo register entity
sipo_register: e_nm_sipo_register PORT MAP(
clk_i => clk,
rst_i => rst,
enable_i => enable,
data_i => data,
data_o => sipo
);
-- Clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
BEGIN
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
enable <= '1';
WAIT FOR PERIOD;
data <= x"9A";
WAIT FOR PERIOD;
data <= x"8B";
WAIT FOR PERIOD;
data <= x"7C";
WAIT FOR PERIOD;
data <= x"6D";
WAIT FOR PERIOD;
enable <= '0';
WAIT FOR DELAY;
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!"
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | 7adfc69052724c9fb94df913c8b9053d | 0.507888 | 4.010802 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_fifo.vhd | 2 | 4,507 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 15:14:45
-- Design Name:
-- Module Name: output_queue_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013
--
-- Description: wrapper for the output queue fifo
-- the output queue fifo stores the length and output queue memory address of frames received
-- from the switching fabric temporarily until they can be tranismitted via the mac
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity output_queue_fifo is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
oqfifo_in_enable : in std_logic;
oqfifo_in_data : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqfifo_out_enable : in std_logic;
oqfifo_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_out_rd_prio : in std_logic;
oqfifo_out_full : out std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqfifo_out_empty : out std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_fifo;
architecture rtl of output_queue_fifo is
component fifo_generator_2 is
port (
clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
din : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
signal rd_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal wr_en_sig : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '0');
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
init_p : process(oqfifo_out_enable, oqfifo_in_wr_prio, oqfifo_in_enable, oqfifo_out_rd_prio, high_priority_border_value_reg)
variable wr_temp : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := (others => '0');
variable rd_temp : std_logic_vector(0 downto 0) := (others => '0');
begin
rd_temp(0) := oqfifo_out_rd_prio;
wr_temp := oqfifo_in_wr_prio;
for i in 0 to NR_OQ_FIFOS-1 loop
-- read access
if (oqfifo_out_enable = '1' and to_integer(unsigned(rd_temp)) = i) then
rd_en_sig(i) <= '1';
else
rd_en_sig(i) <= '0';
end if;
-- write access
if NR_OQ_FIFOS = 1 then
wr_en_sig(0) <= oqfifo_in_enable;
else
if i = 0 then
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= '0';
else
wr_en_sig(i) <= oqfifo_in_enable;
end if;
else
if wr_temp >= high_priority_border_value_reg then
wr_en_sig(i) <= oqfifo_in_enable;
else
wr_en_sig(i) <= '0';
end if;
end if;
end if;
end loop;
end process;
Xfifo : for i in 0 to NR_OQ_FIFOS-1 generate
output_queue_fifo_ip : fifo_generator_2
PORT MAP (
clk => clk,
rst => reset,
wr_en => wr_en_sig(i),
rd_en => rd_en_sig(i),
din => oqfifo_in_data,
dout => oqfifo_out_data((i+1)*OQ_FIFO_DATA_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH),
full => oqfifo_out_full(i),
empty => oqfifo_out_empty(i)
);
end generate Xfifo;
end rtl;
| mit | bb5ece7d93b0c1a94e82b196e57a07c8 | 0.489683 | 3.784215 | false | false | false | false |
Caian/Minesweeper | Projeto/mouse_ctrl.vhd | 1 | 5,751 | -------------------------------------------------------------------------------
-- Title : MC613
-- Project : Mouse Controller
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : mouse_ctrl.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/04/12
-------------------------------------------------------------------------------
-- Description:
-- PS2 mouse basic I/O control
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity mouse_ctrl is
generic(
-- This is the system clock value in kHz. Should be at least 1MHz.
-- Recommended value is 24000 kHz (CLOCK_24 (DE1 pins: PIN_A12 and
-- PIN_B12))
clkfreq : integer
);
port(
ps2_data : inout std_logic; -- PS2 data pin
ps2_clk : inout std_logic; -- PS2 clock pin
clk : in std_logic; -- system clock (same frequency as defined in
-- 'clkfreq' generic)
en : in std_logic; -- Enable
resetn : in std_logic; -- Reset when '0'
newdata : out std_logic; -- Rises when a new data package has arrived
-- from the mouse
-- Mouse buttons state ('1' when pressed):
-- bt_on(0): Left mouse button
-- bt_on(1): Right mouse button
-- bt_on(2): Middle mouse button (if it exists)
bt_on : out std_logic_vector(2 downto 0);
-- Signals that an overflow occured on this package in one of the
-- coordinates
ox, oy : out std_logic;
-- New position relative to the last package. Nine bit values in two's
-- complement for each coordinate.
dx, dy : out std_logic_vector(8 downto 0);
-- Wheel movement relative to last package. 4 bit value in two's
-- complement. Wheel up is a negative value, down is positive.
wheel : out std_logic_vector(3 downto 0)
);
end;
architecture rtl of mouse_ctrl is
component ps2_iobase
generic(
clkfreq : integer -- This is the system clock value in kHz
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
idata_rdy : in std_logic;
idata : in std_logic_vector(7 downto 0);
send_rdy : out std_logic;
odata_rdy : out std_logic;
odata : out std_logic_vector(7 downto 0)
);
end component;
signal sigsend, sigsendrdy, signewdata,
sigreseting, xn, yn, sigwheel : std_logic;
signal hdata, ddata : std_logic_vector(7 downto 0);
begin
ps2io : ps2_iobase generic map(clkfreq) port map(
ps2_data, ps2_clk, clk, en, resetn, sigsend, hdata,
sigsendrdy, signewdata, ddata
);
-- Send Reset to mouse
process(clk, en, resetn)
type rststatename is (
SETCMD, SEND, WAITACK, NEXTCMD, CLEAR
);
constant ncmd : integer := 11; -- Total number of commands to send
type commands is array (0 to ncmd - 1) of integer;
constant cmd : commands := (
16#FF#, 16#F5#, -- Reset and disable reporting
16#F3#, 200, 16#F3#, 100, 16#F3#, 80, 16#F2#, -- Wheel enabling
16#F6#, 16#F4# -- Restore defaults and enable reporting
);
variable state : rststatename;
variable count : integer range 0 to ncmd := 0;
begin
if(rising_edge(clk)) then
hdata <= X"00";
sigsend <= '0';
sigreseting <= '1';
case state is
when SETCMD =>
hdata <= std_logic_vector(to_unsigned(cmd(count), 8));
if sigsendrdy = '1' then
state := SEND;
else
state := SETCMD;
end if;
when SEND =>
hdata <= std_logic_vector(to_unsigned(cmd(count), 8));
sigsend <= '1';
state := WAITACK;
when WAITACK =>
if signewdata = '1' then
-- Wheel detection
if cmd(count) = 16#F2# then
-- If device ID is 0x00, it has no wheel
if ddata = X"00" then
sigwheel <= '0';
state := NEXTCMD;
-- If device ID is 0x03, it has a wheel
elsif ddata = X"03" then
sigwheel <= '1';
state := NEXTCMD;
end if;
else
state := NEXTCMD;
end if;
end if;
when NEXTCMD =>
count := count + 1;
if count = ncmd then
state := CLEAR;
else
state := SETCMD;
end if;
when CLEAR =>
sigreseting <= '0';
count := 0;
end case;
end if;
if resetn = '0' or en = '0' then
state := SETCMD;
count := 0;
sigwheel <= '0';
end if;
end process;
-- Get update packages
process(signewdata, sigreseting, en, resetn)
variable count : integer range 0 to 4;
begin
if(rising_edge(signewdata) and sigreseting = '0'
and en = '1') then
newdata <= '0';
case count is
when 0 =>
bt_on <= ddata(2 downto 0);
xn <= ddata(4);
yn <= ddata(5);
ox <= ddata(6);
oy <= ddata(7);
when 1 =>
dx <= xn & ddata;
when 2 =>
dy <= yn & ddata;
when 3 =>
wheel <= ddata(3 downto 0);
when others =>
NULL;
end case;
count := count + 1;
if (sigwheel = '0' and count > 2) or count > 3 then
count := 0;
newdata <= '1';
end if;
end if;
if resetn = '0' or en = '0' then
bt_on <= (others => '0');
dx <= (others => '0');
dy <= (others => '0');
wheel <= (others => '0');
xn <= '0';
yn <= '0';
ox <= '0';
oy <= '0';
count := 0;
newdata <= '0';
end if;
end process;
end rtl; | gpl-2.0 | 95981a580d1078752c9a777bfeba87d3 | 0.522692 | 3.165107 | false | false | false | false |
diecaptain/kalman_mppt | kr_regbuf.vhd | 1 | 630 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity kr_regbuf is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0) );
end kr_regbuf;
architecture behav of kr_regbuf is
begin
process ( clock, reset, load, I)
begin
if (reset = '1') then
Y <= "00000000000000000000000000000000";
elsif (clock'event and clock = '1') then
if (load = '1') then
Y <= I;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 21e884b5ed902b8d81d7ee37e202cb77 | 0.579365 | 3.579545 | false | false | false | false |
lennartbublies/ecdsa | src/e_uart_transmit.vhd | 1 | 8,311 | -------------------------------------------------------------------------------
-- Module: e_uart_transmit
-- Purpose: Transmits Key when a message will be signed or
-- 1 Byte True/False when a message will be verified
--
-- GENERIC:
-- baud_rate - baud rate of uart transmission
-- M - Key length in Bit
-- PORT:
-- clk_i - global clock signal
-- rst_i - global low active async reset
-- mode_i - ecdsa mode (sign/verify)
-- start_i - starts the transmission of ascii char
-- data_i - data byte to send
-- tx_o - sequential transmission signal
-- reg_o - switch between registers
-- reg_ena_o - register enable
--
-- Author: Leander Schulz ([email protected])
-- Date: 01.09.2017
-- Last change: 22.10.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY e_uart_transmit IS
GENERIC(
baud_rate : IN NATURAL RANGE 1200 TO 500000;
M : integer
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
verify_i : IN std_logic;
start_i : IN std_logic;
data_i : IN std_logic_vector (7 DOWNTO 0);
tx_o : OUT std_logic;
reg_o : OUT std_logic;
reg_ena_o : OUT std_logic);
END ENTITY e_uart_transmit;
ARCHITECTURE td_arch OF e_uart_transmit IS
-- import e_baud_clock
-- clock signal from baud rate used to transmit data
COMPONENT e_baud_clock IS
GENERIC(baud_rate : IN NATURAL RANGE 1200 TO 500000);
PORT( clk_i : IN std_logic;
rst_i : IN std_logic;
baud_clk_o : OUT std_logic);
END COMPONENT e_baud_clock;
TYPE state_type IS (idle, start, transmit, stop); -- wait_edge
SIGNAL s_curr, s_next : state_type := idle;
SIGNAL s_iter : natural range 0 TO 9 := 0;
SIGNAL s_baud_clk : std_logic;
SIGNAL s_baud_rst : std_logic := '1';
SIGNAL s_data_i : std_logic_vector (7 DOWNTO 0);
-- reg_o, reg_ena_o
-- p_calc_bytes
CONSTANT param_bytes_a : NATURAL RANGE 1 TO 128 := M / 8;
CONSTANT param_bytes_b : NATURAL RANGE 0 TO 7 := M MOD 8; -- for check if M is byte aligned
SIGNAL param_bytes : NATURAL RANGE 1 TO 128;
TYPE phase_state_type IS (idle, phase1, phase2, stop);
SIGNAL s_phase, s_phase_next : phase_state_type;
SIGNAL s_cnt_phas1 : NATURAL RANGE 0 TO 128;
SIGNAL s_phas1_tmp : NATURAL RANGE 0 TO 128;
SIGNAL s_cnt_phas2 : NATURAL RANGE 0 TO 128;
SIGNAL s_phas2_tmp : NATURAL RANGE 0 TO 128;
-- verify signals
SIGNAL s_verify : std_logic := '0';
BEGIN
-- save data to send
p_store_data_i : PROCESS(clk_i,rst_i,s_next,data_i)
BEGIN
IF rst_i = '1' THEN
s_data_i <= "00000000";
ELSIF rising_edge(clk_i) THEN
IF s_curr = start THEN
s_verify <= verify_i;
IF mode_i = '0' THEN
s_data_i <= data_i;
ELSE
s_data_i <= "00000000";
END IF;
END IF;
END IF;
END PROCESS p_store_data_i;
-- tx output
p_transmit_byte : PROCESS(clk_i,rst_i,s_curr,s_baud_clk,s_iter,s_verify)
BEGIN
IF rst_i = '1' THEN
tx_o <= '1';
s_iter <= 0;
reg_ena_o <= '0';
ELSIF rising_edge(clk_i) THEN
IF s_curr = idle THEN
tx_o <= '1';
reg_ena_o <= '0';
ELSIF s_curr = start THEN
tx_o <= '0';
reg_ena_o <= '1';
ELSIF s_curr = transmit THEN
reg_ena_o <= '0';
IF s_baud_clk = '1' THEN
IF s_iter < 8 THEN
-- -- -- TX OUTPUT HERE -- -- -->
IF mode_i = '0' THEN
tx_o <= s_data_i(s_iter);
ELSE
tx_o <= s_verify;
END IF;
-- <-- -- TX OUTPUT HERE -- -- --
END IF;
s_iter <= s_iter + 1;
END IF;
ELSIF s_curr = stop THEN
reg_ena_o <= '0';
tx_o <= '1';
s_iter <= 0;
END IF;
END IF;
END PROCESS p_transmit_byte;
p_fsm_transition : PROCESS(rst_i,s_curr,start_i,s_baud_clk,s_iter,s_phase,s_cnt_phas2)
BEGIN
s_next <= s_curr;
s_baud_rst <= '0';
CASE s_curr IS
WHEN idle =>
IF rst_i = '0' AND (start_i = '1' OR s_phase = phase1 OR (s_phase = phase2 AND s_cnt_phas2 /= 0)) THEN
s_baud_rst <= '1';
s_next <= start;
END IF;
WHEN start =>
s_baud_rst <= '0';
s_next <= transmit;
WHEN transmit =>
IF s_iter = 9 THEN
s_next <= stop;
END IF;
WHEN stop =>
IF s_baud_clk = '1' THEN
s_next <= idle;
END IF;
END CASE;
END PROCESS p_fsm_transition;
p_fsm_store : PROCESS(clk_i,rst_i,s_next)
BEGIN
IF rst_i = '1' THEN
s_curr <= idle;
ELSIF rising_edge(clk_i) THEN
s_curr <= s_next;
END IF;
END PROCESS p_fsm_store;
baud_clock_inst : e_baud_clock
GENERIC MAP(baud_rate => baud_rate)
PORT MAP( clk_i => clk_i,
rst_i => s_baud_rst,
baud_clk_o => s_baud_clk
);
-- calculate bytes to read
p_calc_bytes : PROCESS(param_bytes)
BEGIN
IF (param_bytes_b = 0) THEN
param_bytes <= param_bytes_a;
ELSE
param_bytes <= param_bytes_a+1;
END IF;
END PROCESS p_calc_bytes;
-- register control -----------------------------------------
-- fsm
p_reg_fsm : PROCESS(rst_i,s_phase,start_i,mode_i,s_curr,s_next,param_bytes,s_cnt_phas1,s_cnt_phas2,s_phas1_tmp,s_phas2_tmp)
BEGIN
s_phase_next <= s_phase;
s_cnt_phas1 <= s_phas1_tmp;
s_cnt_phas2 <= s_phas2_tmp;
CASE s_phase IS
WHEN idle =>
s_cnt_phas1 <= param_bytes;
s_cnt_phas2 <= param_bytes;
IF rst_i = '0' AND start_i = '1' AND mode_i = '0' THEN
s_phase_next <= phase1;
END IF;
WHEN phase1 =>
IF s_cnt_phas1 = 0 THEN
s_phase_next <= phase2;
END IF;
IF s_curr = stop AND s_next = idle THEN
s_cnt_phas1 <= s_phas1_tmp - 1;
END IF;
WHEN phase2 =>
IF s_cnt_phas2 = 0 THEN
s_phase_next <= stop;
END IF;
IF s_curr = stop AND s_next = idle THEN
s_cnt_phas2 <= s_phas2_tmp - 1;
END IF;
WHEN stop =>
s_phase_next <= idle;
END CASE;
END PROCESS p_reg_fsm;
p_reg_store : PROCESS(rst_i,clk_i,s_phas1_tmp) --ALL)
BEGIN
IF rst_i = '1' THEN
s_phase <= idle;
ELSIF rising_edge(clk_i) THEN
s_phase <= s_phase_next;
s_phas1_tmp <= s_cnt_phas1;
s_phas2_tmp <= s_cnt_phas2;
END IF;
END PROCESS p_reg_store;
p_reg_output : PROCESS(clk_i,rst_i,s_phase)
BEGIN
IF rst_i = '1' THEN
reg_o <= '0';
ELSIF rising_edge(clk_i) THEN
IF s_phase = idle THEN
reg_o <= '0';
ELSIF s_phase = phase1 THEN
reg_o <= '0';
ELSIF s_phase = phase2 THEN
reg_o <= '1';
ELSIF s_phase = stop THEN
reg_o <= '0';
END IF;
END IF;
END PROCESS p_reg_output;
END ARCHITECTURE td_arch; -----------------------------------------------------
| gpl-3.0 | 22a70b60fb00cff854185b6dda69133e | 0.446396 | 3.679062 | false | false | false | false |
lennartbublies/ecdsa | src/e_uart_receive_mux.vhd | 1 | 3,277 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Multiplexer for UART
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 29.06.2017
-- Last change: 25.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_uart_receive_mux IS
PORT (
-- Clock and reset
clk_i : IN std_logic;
rst_i : IN std_logic;
-- UART
uart_i : IN std_logic;
-- Set mode
mode_o : OUT std_logic;
-- Output
r_o : OUT std_logic_vector(M-1 DOWNTO 0); -- M-1
s_o : OUT std_logic_vector(M-1 DOWNTO 0);
m_o : OUT std_logic_vector(M-1 DOWNTO 0);
-- Ready flag
ready_o : OUT std_logic
);
END e_uart_receive_mux;
ARCHITECTURE rtl OF e_uart_receive_mux IS
-- Import entity e_sipo_register
COMPONENT e_nm_sipo_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
data_i : IN std_logic_vector(U-1 DOWNTO 0);
data_o : OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- IMPORT UART COMPONENT
COMPONENT e_uart_receiver IS
GENERIC (
baud_rate : IN NATURAL RANGE 1200 TO 500000;
N : IN NATURAL RANGE 1 TO 256;
M : IN NATURAL RANGE 1 TO 256);
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
rx_i : IN std_logic;
mode_o : OUT std_logic;
data_o : OUT std_logic_vector (7 DOWNTO 0);
ena_r_o : OUT std_logic;
ena_s_o : OUT std_logic;
ena_m_o : OUT std_logic;
rdy_o : OUT std_logic);
END COMPONENT e_uart_receiver;
-- Internal signals
SIGNAL uart_data: std_logic_vector(7 DOWNTO 0) := (OTHERS=>'0');
SIGNAL enable_r_register, enable_s_register, enable_m_register: std_logic := '0';
BEGIN
-- Instantiate sipo register entity for r register
r_register: e_nm_sipo_register PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_r_register,
data_i => uart_data,
data_o => r_o
);
-- Instantiate sipo register entity for s register
s_register: e_nm_sipo_register PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_s_register,
data_i => uart_data,
data_o => s_o
);
-- Instantiate sipo register entity for m register
m_register: e_nm_sipo_register PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_m_register,
data_i => uart_data,
data_o => m_o
);
-- Instantiate UART Receiver
uart_receiver : e_uart_receiver
GENERIC MAP (
baud_rate => BAUD_RATE,
N => 21, -- length of message
M => M) -- length of key
PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
rx_i => uart_i,
mode_o => mode_o,
data_o => uart_data,
ena_r_o => enable_r_register,
ena_s_o => enable_s_register,
ena_m_o => enable_m_register,
rdy_o => ready_o
);
END rtl;
| gpl-3.0 | 412e0a2a2f2d3bc6ecbb3872a502396f | 0.523955 | 3.270459 | false | false | false | false |
caiopo/mips-multiciclo | src/bancoRegistradores.vhd | 1 | 1,922 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bancoRegistradores is
generic(
largura: natural := 8;
bitsRegSerLido: natural := 2
);
port(
clock, reset: in std_logic;
EscReg: in std_logic;
RegSerLido1, RegSerLido2, RegSerEscrito: in std_logic_vector(bitsRegSerLido-1 downto 0);
DadoEscrita: in std_logic_vector(largura-1 downto 0);
DadoLido1, DadoLido2: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of bancoRegistradores is
type TypeBancoRegistradores is array(0 to 2**bitsRegSerLido) of std_logic_vector(largura-1 downto 0);
signal actual_state, next_state: TypeBancoRegistradores;
begin
-- state register
StateRegister: process(clock, reset)
begin
if reset = '1' then
for i in actual_state'range loop
actual_state(i) <= (others => '0');
end loop;
elsif rising_edge(clock) then
actual_state <= next_state;
end if;
end process;
-- next state logic
NextStateLogic: process(actual_state, EscReg, RegSerEscrito, DadoEscrita) is
begin
next_state <= actual_state;
for i in actual_state'range loop
if EscReg = '1' then
if i = to_integer(unsigned(RegSerEscrito)) then
next_state(i) <= DadoEscrita;
end if;
end if;
end loop;
end process;
-- output logic
DadoLido1 <= actual_state(to_integer(unsigned(RegSerLido1)));
DadoLido2 <= actual_state(to_integer(unsigned(RegSerlido2)));
end architecture;
| mit | a64587fd967c28545c3e239c5aa15ce4 | 0.636837 | 3.546125 | false | false | false | false |
bazk/hwsat | templates/control.vhd | 1 | 5,815 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control_{{ current_var.name }} is
port (
clk: in std_logic;
reset: in std_logic;
lclear: out std_logic;
lchange: out std_logic;
lcontra: out std_logic;
gclear: in std_logic;
gchange: in std_logic;
gcontra: in std_logic;
{% for var in variables %}
{{ var.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
eil: in std_logic;
eol: out std_logic;
eir: in std_logic;
eor: out std_logic;
ldebug_num_decisions: out integer;
ldebug_num_conflicts: out integer;
ldebug_num_backtracks: out integer
);
end control_{{ current_var.name }};
architecture behavioral of control_{{ current_var.name }} is
component imp_{{ current_var.name }}
port (
clk: in std_logic;
reset: in std_logic;
clear: in std_logic;
change: out std_logic;
contra: out std_logic;
{% for var in variables %}
{{ var.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
value: in std_logic_vector(0 to 1)
);
end component;
for imp_{{ current_var.name }}_0: imp_{{ current_var.name }} use entity work.imp_{{ current_var.name }};
signal current_state: std_logic_vector(0 to 2);
signal cur_var: std_logic_vector(0 to 1);
signal debug_num_decisions: integer;
signal debug_num_conflicts: integer;
signal debug_num_backtracks: integer;
begin
imp_{{ current_var.name }}_0: imp_{{ current_var.name }} port map (
clk => clk,
reset => reset,
clear => gclear,
change => lchange,
contra => lcontra,
{% for var in variables %}
{{ var.name }} => {{ var.name }},
{% endfor %}
value => current_state(0 to 1)
);
cur_var <= {{ current_var.name }};
ldebug_num_decisions <= debug_num_decisions;
ldebug_num_conflicts <= debug_num_conflicts;
ldebug_num_backtracks <= debug_num_backtracks;
process (clk, reset)
begin
if (reset='1') then
current_state <= "000"; -- init
eol <= '0';
eor <= '0';
debug_num_decisions <= 0;
debug_num_conflicts <= 0;
debug_num_backtracks <= 0;
elsif (rising_edge(clk)) then
case current_state is
when "000" => -- init
if (eil='0' and eir='0') then
eol <= '0';
eor <= '0';
lclear <= '0';
elsif (eir='1') then
eol <= '1';
eor <= '0';
lclear <= '0';
elsif (eil='1' and (cur_var(0) or cur_var(1))='1') then
eol <= '0';
eor <= '1';
lclear <= '0';
elsif (eil='1' and (cur_var(0) or cur_var(1))='0') then
eol <= '0';
eor <= '0';
lclear <= '0';
current_state <= "101"; -- active1
debug_num_decisions <= debug_num_decisions + 1;
end if;
when "101" => -- active1
if (gchange='1' and gcontra='0') then
eol <= '0';
eor <= '0';
lclear <= '0';
elsif (gcontra='1') then
eol <= '0';
eor <= '0';
lclear <= '1';
current_state <= "011"; -- active0
debug_num_conflicts <= debug_num_conflicts + 1;
debug_num_decisions <= debug_num_decisions + 1;
elsif (gchange='0' and gcontra='0') then
eol <= '0';
eor <= '1';
lclear <= '0';
current_state <= "100"; -- passive1
end if;
when "100" => -- passive1
if (eir='0') then
eol <= '0';
eor <= '0';
lclear <= '0';
elsif (eir='1') then
eol <= '0';
eor <= '0';
lclear <= '1';
current_state <= "011"; -- active0
debug_num_decisions <= debug_num_decisions + 1;
end if;
when "011" => -- active0
if (gchange='1') then
eol <= '0';
eor <= '0';
lclear <= '0';
elsif (gcontra='1') then
eol <= '1';
eor <= '0';
lclear <= '0';
current_state <= "000"; -- init
debug_num_conflicts <= debug_num_conflicts + 1;
debug_num_backtracks <= debug_num_backtracks + 1;
elsif (gchange='0' and gcontra='0') then
eol <= '0';
eor <= '1';
lclear <= '0';
current_state <= "010"; -- passive0
end if;
when "010" => -- passive0
if (eir='0') then
eol <= '0';
eor <= '0';
lclear <= '0';
elsif (eir='1') then
eol <= '1';
eor <= '0';
lclear <= '0';
current_state <= "000"; -- init
debug_num_backtracks <= debug_num_backtracks + 1;
end if;
when others =>
current_state <= "000"; -- init
end case;
end if;
end process;
end behavioral; | gpl-3.0 | 73eaa53a4f8ea3cf05b3dd0075ae8782 | 0.409114 | 4.333085 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s4/moore/moore_t.vhd | 1 | 960 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: moore_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity moore_t is
end entity;
architecture arch_moore_t of moore_t is
component moore is
port (d, clk, reset: in std_logic;
z: out std_logic);
end component moore;
signal data: std_logic_vector(0 to 9) := "1100010110";
signal clk, r, d, z: std_logic := '0';
signal clk_t: std_logic := '0';
for all:moore use entity work.moore(arch_moore);
begin
m : moore port map (d, clk, r, z);
clk <= not clk after 50 ns;
clk_t <= not clk_t after 40 ns;
process (clk_t)
variable i : natural := 0;
begin
if clk_t = '1' and clk_t'event then
d <= data(i);
i := i + 1;
end if;
end process;
end architecture arch_moore_t;
| gpl-3.0 | b6ce640a53fba209a64bb726720a26f1 | 0.535417 | 3.189369 | false | false | false | false |
caiopo/mips-multiciclo | src/bram.vhd | 1 | 6,776 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: bram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY bram IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END bram;
ARCHITECTURE SYN OF bram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL bram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | ef086834cc7a1743fbfc325029a4cae3 | 0.670897 | 3.545788 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_mem_check.vhd | 2 | 7,298 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 16:17:41
-- Design Name:
-- Module Name: output_queue_overflow_check - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module checks upon a request if another frame can be accepted from the switching fabric
-- No accept uppon a request will be returned if either the FIFO is full or there is not enough place in the memory
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity output_queue_mem_check is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_MEM_PTR_START : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
req : in std_logic;
req_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
req_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
accept_frame : out std_logic;
mem_wr_ptr : in std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH-1 downto 0);
fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
fifo_full : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_mem_check;
architecture rtl of output_queue_mem_check is
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
signal debug_rd_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_wr_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_mem_space : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_length : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
begin
-- upon a request signal from switch fabric check if the frame can be accepted
-- accept_frame = req AND (fifo_empty OR (NOT fifo_full AND (mem_rd_ptr - mem_wr_ptr >= req_length)))
-- mem_check_p : process (clk)
-- variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
-- variable temp_mem_full : std_logic;
-- variable temp_accept : std_logic;
-- begin
-- if clk'event and clk = '1' then
-- if reset = '1' then
-- accept_frame <= '0';
-- else
-- temp_accept := req;
-- for i in 0 to NR_OQ_FIFOS-1 loop
-- mem_rd_ptr := fifo_data(i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
-- if mem_rd_ptr - mem_wr_ptr >= req_length then
-- temp_mem_full := '0';
-- else
-- temp_mem_full := '1';
-- end if;
-- if temp_accept = '1' then
-- temp_accept := fifo_empty(i) or (not fifo_full(i) and not temp_mem_full);
-- else
-- temp_accept := '0';
-- end if;
-- end loop;
-- accept_frame <= temp_accept;
-- end if;
-- end if;
-- end process;
mem_check_p : process (clk)
variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable tmp_mem_wr_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable temp_mem_full : std_logic;
variable temp_accept : std_logic;
begin
if clk'event and clk = '1' then
if reset = '1' then
accept_frame <= '0';
else
temp_accept := req;
if NR_OQ_FIFOS = 1 then
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
if mem_rd_ptr - mem_wr_ptr >= req_length then
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
elsif NR_OQ_FIFOS = 2 then
if req_prio >= high_priority_border_value_reg then
mem_rd_ptr := fifo_data(OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(2*OQ_MEM_ADDR_WIDTH-1 downto OQ_MEM_ADDR_WIDTH);
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(1) or (not fifo_full(1) and not temp_mem_full);
else
temp_accept := '0';
end if;
else
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
debug_rd_reg <= fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_wr_reg <= mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_length <= req_length;
debug_mem_space <= mem_rd_ptr - tmp_mem_wr_ptr;
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
end if;
end if;
accept_frame <= temp_accept;
end if;
end if;
end process;
end rtl;
| mit | 470ce92df57609da03d43c0f616bd9d8 | 0.481913 | 3.865466 | false | false | false | false |
lfmunoz/4dsp_sip_interface | fmc116_ltc2656_ctrl.vhd | 1 | 17,870 | ----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity fmc116_ltc2656_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
PRESEL : std_logic_vector(7 downto 0) := x"00"
);
port (
rst : in std_logic;
clk : in std_logic;
serial_clk : in std_logic;
sclk_ext : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
dac_n_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end fmc116_ltc2656_ctrl;
architecture fmc116_ltc2656_ctrl_syn of fmc116_ltc2656_ctrl is
component fmc11x_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ltc2656_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(3 downto 0);
douta : out std_logic_vector(23 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000100";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"00000FF";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"00000FF";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
--signal sclk_prebuf : std_logic;
--signal serial_clk : std_logic;
--signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal serial_val_ack : std_logic;
signal serial_val_ack_sclk : std_logic;
signal busy_del1 : std_logic;
signal busy_del2 : std_logic;
signal init_done_sclk_del : std_logic;
signal wr_cmd_ack : std_logic;
signal wr_ack_requested : std_logic;
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(15 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(23+PRESEL'length downto 0);
signal init_address : std_logic_vector(3 downto 0);
signal init_data : std_logic_vector(23 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
-- process (clk)
-- -- Divide by 2^4 = 16, CLKmax = 16 x 20MHz
-- variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
-- begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
-- end process;
--
-- bufg_sclk : bufg
-- port map (
-- i => sclk_prebuf,
-- o => serial_clk
-- );
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc11x_stellar_cmd_inst : fmc11x_stellar_cmd
generic map
(
start_addr =>start_addr,
stop_addr =>stop_addr
)
port map
(
reset =>rst,
--command if
clk_cmd =>clk_cmd,
out_cmd =>out_cmd,
out_cmd_val =>out_cmd_val,
in_cmd =>in_cmd,
in_cmd_val =>in_cmd_val,
--register interface
clk_reg =>clk_cmd,
out_reg =>out_reg,
out_reg_val =>out_reg_val,
out_reg_val_ack =>out_reg_val_ack,
out_reg_addr =>out_reg_addr,
in_reg =>in_reg,
in_reg_val =>in_reg_val,
in_reg_req =>in_reg_req,
in_reg_addr =>in_reg_addr,
wr_ack => wr_ack,
mbx_in_reg =>(others=>'0'),
mbx_in_val =>'0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
wr_ack <= '0';
wr_cmd_ack <= '0';
wr_ack_requested <= '0';
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
wr_cmd_ack <= '1';
else
wr_cmd_ack <= '0';
end if;
-- only send a write Ack on request:
if (out_reg_val_ack = '1') then
wr_ack_requested <= '1';
elsif(wr_ack = '1') then
wr_ack_requested <= '0';
end if;
if (wr_cmd_ack = '1' and wr_ack_requested = '1') then
wr_ack <= '1';
elsif(serial_val_ack = '1' and inst_rw = '0' and wr_ack_requested = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & '0' & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(7 downto 0);
data_reg <= out_reg(15 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '0'; -- NO READ THROUGH SPI SUPPORTED
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(7 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
-- Detect the end of a serial write, don't send an Ack after completing the initialisation.
process (serial_clk)
begin
if (rising_edge(serial_clk)) then
busy_del1 <= busy;
busy_del2 <= busy_del1;
init_done_sclk_del <= init_done_sclk;
if(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '1' and init_done_sclk = '1') then
serial_val_ack_sclk <= '1';
elsif(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '0' and init_done_sclk = '0') then
serial_val_ack_sclk <= '1';
else
serial_val_ack_sclk <= '0';
end if;
end if;
end process;
-- Transfer end write pulse to other clock domain
pulse2pulse_inst2 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => serial_val_ack_sclk,
pulseout => serial_val_ack,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= PRESEL & init_data(23 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(23 downto 16) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= PRESEL & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ltc2656_init_mem_inst : ltc2656_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc116_ltc2656_ctrl_syn;
| mit | e482c1054dda3bdd29f18064e07a8060 | 0.476889 | 3.626954 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s2/decoder/decoder.vhd | 1 | 861 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 15-02-2016
-- Module Name: decoder.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder is
port (i : in std_logic_vector (1 downto 0);
o : out std_logic_vector (3 downto 0));
end entity;
architecture gate_arch_decoder of decoder is
begin
o(0) <= (not i(0)) and (not i(1));
o(1) <= i(0) and (not i(1));
o(2) <= (not i(0)) and i(1);
o(3) <= i(0) and i(1);
end architecture;
architecture beh_arch_decoder of decoder is
begin
with i select
o <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"XXXX" when others;
end architecture beh_arch_decoder;
| gpl-3.0 | 9692466bb01265158638e00e546df3f3 | 0.500581 | 3.350195 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/control.vhd | 1 | 6,898 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-05-2016
-- Module Name: control.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity control is
port (clk : in std_logic;
cond : in std_logic;
op : in std_logic_vector (3 downto 0);
PCen : out std_logic;
PCwrite : out std_logic;
IorD : out std_logic_vector (1 downto 0);
memread : out std_logic;
memwrite : out std_logic;
memtoreg : out std_logic_vector (1 downto 0);
IRe : out std_logic;
PCscr : out std_logic_vector (1 downto 0);
ALUop : out std_logic_vector (3 downto 0);
ALUsrcB : out std_logic_vector (1 downto 0);
ALUsrcA : out std_logic_vector (1 downto 0);
AluFunc : out std_logic_vector (1 downto 0);
regdest : out std_logic_vector (1 downto 0);
regwrite : out std_logic);
end control;
architecture rtl of control is
type state is (RST, S0, S1, S2, S3, SR0, SI0, SI10, SI11, SI20, SI210, SI220, SI221, SI30, SI31, SJ0);
signal current_state, next_state : state := RST;
begin
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process(current_state)
begin
case current_state is
when RST =>
next_state <= S0;
when S0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '1';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "01";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S1;
when S1 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '1';
PCscr <= "00";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S2;
when S2 =>
PCen <= '1';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S3;
when S3 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "01";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
if op = "1111" then
next_state <= SR0;
elsif op = "0000" then
next_state <= SJ0;
else
next_state <= SI0;
end if;
when SR0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= op;
ALUsrcB <= "00";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "01";
regwrite <= '1';
next_state <= S0;
when SJ0 =>
PCen <= '1';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "00";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when SI0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
if op (3 downto 2) = "00" and op(1 downto 0) /= "00" then
next_state <= SI10;
elsif op (3 downto 2) = "01" and op(1 downto 0) /= "11" then
next_state <= SI10;
elsif op = "0111" or op = "1000" then
next_state <= SI20;
else
next_state <= SI30;
end if;
when SI10 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= SI11;
when SI11 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '1';
next_state <= S0;
when SI20 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
if op = "1000" then
next_state <= SI210;
end if;
if op = "0111" then
next_state <= SI220;
end if;
when SI210 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "01";
memread <= '0';
memwrite <= '1';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when SI220 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "01";
memread <= '1';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= SI221;
when SI221 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "01";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '1';
next_state <= S0;
when SI30 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "00";
AluFunc <= "10";
regdest <= "00";
regwrite <= '0';
if cond = '1' then
next_state <= SI31;
else
next_state <= S0;
end if;
when SI31 =>
PCen <= '0';
PCwrite <= '1';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "00";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when others =>
next_state <= current_state;
end case;
end process;
end architecture rtl;
| gpl-3.0 | c9fd8e8cb45cddb5deb98ff21d21d1f2 | 0.447376 | 2.935319 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sim_1/imports/simulation/demo_tb.vhd | 2 | 48,454 | --------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project : Automotive Ethernet Gateway, created from Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : demo_tb.vhd
-- -----------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core
-- to demonstrate the functionality.
--------------------------------------------------------------------------------
--
-- This testbench performs the following operations:
-- - The MDIO interface will respond to a read request with data to prevent the
-- example design thinking it is real hardware
-- - Four frames are then pushed into the receiver from the PHY
-- interface (GMII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
------------------------------------------------------------------------
-- DEMONSTRATION TESTBENCH |
-- |
-- |
-- ---------------------------------------------- |
-- | TOP LEVEL WRAPPER (DUT) | |
-- | ------------------- ---------------- | |
-- | | USER LOOPBACK | | TRI-MODE | | |
-- | | DESIGN EXAMPLE | | ETHERNET MAC | | |
-- | | | | CORE | | |
-- | | | | | | Monitor |
-- | | ------->|--->| Tx |--------> Frames |
-- | | | | | PHY | | |
-- | | | | | I/F | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | Rx | | |
-- | | | | | PHY | | |
-- | | --------|<---| I/F |<-------- Generate |
-- | | | | | | Frames |
-- | ------------------- ---------------- | |
-- --------------------------------^------------- |
-- | |
-- | |
-- Stimulate |
-- Management I/F |
-- (if present) |
-- |
------------------------------------------------------------------------
entity demo_tb is
end demo_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of demo_tb is
constant GMII_DATA_WIDTH : integer := 8;
constant SWITCH_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
GMII_DATA_WIDTH : integer;
SWITCH_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type tri_mode_ethernet_mac_0_frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of tri_mode_ethernet_mac_0_frame_typ;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core transmit interface by the testbench.
------------------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-------------
0 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-------------
1 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"80", VALID => '1', ERROR => '0'), -- Length/Type = Type = 8000
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'),
60 => ( DATA => X"2F", VALID => '1', ERROR => '0'), -- 47th Data byte
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-------------
2 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'),
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '1'), -- Error asserted
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => true),
-------------
-- Frame 3
-------------
3 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal tx_monitor_finished_10M : boolean := false;
signal tx_monitor_finished_100M : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
SWITCH_DATA_WIDTH => SWITCH_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 250 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Simulate the MDIO
------------------------------------------------------------------------------
-- respond with sensible data to mdio reads and accept writes.
-- expect mdio to try and read from reg addr 1 - return all 1's if we don't
-- want any other mdio accesses
-- if any other response then mdio will write to reg_addr 9 then 4 then 0
-- (may check for expected write data?)
-- finally mdio read from reg addr 1 until bit 5 is seen high
-- NOTE - do not check any other bits so could drive all high again..
p_mdio_count : process (mdc, reset)
begin
if (reset = '1') then
mdio_count <= (others => '0');
last_mdio <= '0';
elsif mdc'event and mdc = '1' then
last_mdio <= mdio;
if mdio_count >= "100000" then
mdio_count <= (others => '0');
elsif (mdio_count /= "000000") then
mdio_count <= mdio_count + "000001";
else -- only get here if mdio state is 0 - now look for a start
if mdio = '1' and last_mdio = '0' then
mdio_count <= "000001";
end if;
end if;
end if;
end process p_mdio_count;
mdio <= '1' when (mdio_read = '1' and (mdio_count >= "001110") and (mdio_count <= "011111")) else 'Z';
-- only respond to phy and reg address == 1 (PHY_STATUS)
p_mdio_check : process (mdc, reset)
begin
if (reset = '1') then
mdio_read <= '0';
mdio_addr <= '1'; -- this will go low if the address doesn't match required
mdio_fail <= '0';
elsif mdc'event and mdc = '1' then
if (mdio_count = "000010") then
mdio_addr <= '1'; -- reset at the start of a new access to enable the address to be revalidated
if last_mdio = '1' and mdio = '0' then
mdio_read <= '1';
else -- take a write as a default as won't drive at the wrong time
mdio_read <= '0';
end if;
elsif mdio_count <= "001100" then
-- check the phy_addr is 7 and the reg_addr is 0
if mdio_count <= "000111" and mdio_count >= "000101" then
if (mdio /= '1') then
mdio_addr <= '0';
end if;
else
if (mdio /= '0') then
mdio_addr <= '0';
end if;
end if;
elsif mdio_count = "001110" then
if mdio_read = '0' and (mdio = '1' or last_mdio = '0') then
assert false
report "ERROR - Write TA phase is incorrect" & cr
severity failure;
end if;
elsif (mdio_count >= "001111") and (mdio_count <= "011110") and mdio_addr = '1' then
if (mdio_read = '0') then
if (mdio_count = "010100") then
if (mdio = '1') then
mdio_fail <= '1';
assert false
report "ERROR - Expected bit 10 of mdio write data to be 0" & cr
severity failure;
end if;
else
if (mdio = '0') then
mdio_fail <= '1';
assert false
report "ERROR - Expected all except bit 10 of mdio write data to be 1" & cr
severity failure;
end if;
end if;
end if;
end if;
end if;
end process p_mdio_check;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
-- drives mii_tx_clk100 at 25 MHz
p_mii_tx_clk100 : process
begin
mii_tx_clk100 <= '0';
wait for 20 ns;
loop
wait for 20 ns;
mii_tx_clk100 <= '1';
wait for 20 ns;
mii_tx_clk100 <= '0';
end loop;
end process p_mii_tx_clk100;
-- drives mii_tx_clk10 at 2.5 MHz
p_mii_tx_clk10 : process
begin
mii_tx_clk10 <= '0';
wait for 10 ns;
loop
wait for 200 ns;
mii_tx_clk10 <= '1';
wait for 200 ns;
mii_tx_clk10 <= '0';
end loop;
end process p_mii_tx_clk10;
-- Select between 10Mb/s and 100Mb/s MII Tx clock frequencies
p_mii_tx_clk : process(phy_speed, mii_tx_clk100, mii_tx_clk10)
begin
if phy_speed = "11" then
mii_tx_clk <= '0';
elsif phy_speed = "01" then
mii_tx_clk <= mii_tx_clk100;
else
mii_tx_clk <= mii_tx_clk10;
end if;
end process p_mii_tx_clk;
-- Receiver and transmitter clocks are the same in this simulation: connect
-- the appropriate Tx clock source (based on operating speed) to the receiver
-- clock
gmii_rx_clk <= gmii_tx_clk when phy_speed = "10" else mii_tx_clk;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, and checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
p_management : process
-- Procedure to reset the MAC
------------------------------
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 400 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin -- process p_management
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
-- reset the core
mac_reset;
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- The stimulus process will now send 4 frames at 1Gb/s.
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
wait;
end process p_management;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Send four frames through the MAC and Design Exampled
-- at each state Ethernet speed
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-------------------------------------------------------
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 3 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
---------------------------------------------------
-- Procedure to check a transmitted frame at 1Gb/s
---------------------------------------------------
procedure check_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_type : string(1 to 4) := (others => ' ');
-- variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- Start comparing transmitted data to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
variable f : tri_mode_ethernet_mac_0_frame_typ; -- temporary frame variable
variable current_frame : natural := 0; -- current frame pointer
begin -- process p_monitor
-- Compare the transmitted frame to the received frames
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-- Repeated for all stated speeds.
-------------------------------------------------------
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset'event and reset = '0';
wait until management_config_finished;
wait for 300 ns;
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end behav;
| mit | dd92dab7c69498785d3a7f1525197a25 | 0.420234 | 3.867965 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_arbitration.vhd | 2 | 8,870 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.12.2013 10:00:16
-- Design Name:
-- Module Name: output_queue_arbitration - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: This module forwards the frames in the output queue memory to the transmitter-side of the MAC
-- The output queue fifo provides the start address in the output queue memory and the length in bytes
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity output_queue_arbitration is
Generic (
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_DATA_WIDTH : integer;
OQ_FIFO_LENGTH_START : integer;
OQ_FIFO_TIMESTAMP_START : integer;
OQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fifo
oqarb_in_fifo_enable : out std_logic;
oqarb_in_fifo_prio : out std_logic;
oqarb_in_fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqarb_in_fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
-- timestamp
oqarb_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oqarb_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- input interface memory
oqarb_in_mem_data : in std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_in_mem_enable : out std_logic;
oqarb_in_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
oqarb_in_mem_prio : out std_logic;
-- output interface mac
oqarb_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_out_valid : out std_logic;
oqarb_out_last : out std_logic;
oqarb_out_ready : in std_logic
);
end output_queue_arbitration;
architecture rtl of output_queue_arbitration is
-- state machine
type state is (
IDLE,
ARBITRATE,
READ_MEM
);
-- state signals
signal cur_state : state;
signal nxt_state : state;
signal empty_const : std_logic_vector(NR_OQ_FIFOS-1 downto 0) := (others => '1');
-- config_output_state machine signals
signal update_cnt_sig : std_logic;
signal reset_frame_length_sig : std_logic;
signal measure_latency_sig : std_logic;
signal choose_fifo_sig : std_logic;
-- process registers
signal frame_length_cnt : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal latency_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal winner_fifo_reg : std_logic_vector(0 downto 0);
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next data_input_state, combinitorial logic
output_logic_p : process(cur_state, oqarb_in_fifo_empty, oqarb_out_ready, frame_length_cnt, oqarb_in_fifo_data, empty_const, winner_fifo_reg)
begin
-- default signal assignments
nxt_state <= IDLE;
update_cnt_sig <= '0';
measure_latency_sig <= '0';
reset_frame_length_sig <= '0';
oqarb_in_fifo_enable <= '0';
oqarb_out_last <= '0';
oqarb_out_valid <= '0';
oqarb_in_fifo_prio <= '0';
choose_fifo_sig <= '0';
case cur_state is
when IDLE =>
if oqarb_in_fifo_empty /= empty_const and oqarb_out_ready = '1' then
nxt_state <= ARBITRATE;
choose_fifo_sig <= '1'; -- choose_fifo_p
end if;
when ARBITRATE =>
nxt_state <= READ_MEM;
update_cnt_sig <= '1'; -- cnt_frame_length_p
measure_latency_sig <= '1'; -- timestamp_p
when READ_MEM =>
if frame_length_cnt >= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START+FRAME_LENGTH_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_LENGTH_START)
and oqarb_out_ready = '1' then
nxt_state <= IDLE;
reset_frame_length_sig <= '1'; -- cnt_frame_length_p
oqarb_in_fifo_enable <= '1';
oqarb_in_fifo_prio <= winner_fifo_reg(0);
oqarb_out_last <= '1';
oqarb_out_valid <= '1';
else
nxt_state <= READ_MEM;
update_cnt_sig <= oqarb_out_ready; -- cnt_frame_length_p
oqarb_out_valid <= oqarb_out_ready;
end if;
end case;
end process output_logic_p;
-- count frame bytes received from fabric
cnt_frame_length_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
frame_length_cnt <= (others => '0');
else
frame_length_cnt <= frame_length_cnt;
if reset_frame_length_sig = '1' then
frame_length_cnt <= (others => '0');
elsif update_cnt_sig = '1' then
frame_length_cnt <= frame_length_cnt + 1;
end if;
end if;
end if;
end process;
-- take transmission timestamp of the message
timestamp_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
latency_reg <= (others => '0');
else
latency_reg <= latency_reg;
if measure_latency_sig = '1' then
latency_reg <= oqarb_in_timestamp_cnt - oqarb_in_fifo_data
(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_TIMESTAMP_START)
+ 50; -- considering the clock cycles through mac, rx, tx_fifo
end if;
end if;
end if;
end process;
-- determine the fifo to be read from
choose_fifo_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
winner_fifo_reg <= (others => '0');
else
winner_fifo_reg <= winner_fifo_reg;
if choose_fifo_sig = '1' then
if NR_OQ_FIFOS = 2 and oqarb_in_fifo_empty(NR_OQ_FIFOS-1) = '0' then -- high priority fifo
winner_fifo_reg(0) <= '1';
else
winner_fifo_reg(0) <= '0';
end if;
end if;
end if;
end if;
end process;
output_p : process(oqarb_in_mem_data, winner_fifo_reg)
begin
if NR_OQ_FIFOS = 1 then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
if winner_fifo_reg(0) = '0' then
oqarb_out_data <= oqarb_in_mem_data(TRANSMITTER_DATA_WIDTH-1 downto 0);
else
oqarb_out_data <= oqarb_in_mem_data(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto TRANSMITTER_DATA_WIDTH);
end if;
end if;
end process;
oqarb_in_mem_enable <= oqarb_out_ready;
oqarb_in_mem_addr <= oqarb_in_fifo_data(to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1
downto to_integer(unsigned(winner_fifo_reg))*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START) + frame_length_cnt;
oqarb_out_latency <= latency_reg;
oqarb_in_mem_prio <= winner_fifo_reg(0);
end rtl;
| mit | 80a3bbc6b58f021ccbaa00709ee5e641 | 0.520068 | 3.958054 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/clocking/aeg_design_clocks.vhd | 2 | 7,348 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_clocks.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates the clocking logic required for the
-- example design.
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity aeg_design_0_clocks is
port (
-- clocks
clk_in_p : in std_logic;
clk_in_n : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
dcm_locked : out std_logic;
-- clock outputs
gtx_clk_bufg : out std_logic;
refclk_bufg : out std_logic;
s_axi_aclk : out std_logic
);
end aeg_design_0_clocks;
architecture RTL of aeg_design_0_clocks is
------------------------------------------------------------------------------
-- Component declaration for the clock generator
------------------------------------------------------------------------------
component aeg_design_0_clk_wiz
port
( -- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component aeg_design_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal clkin1 : std_logic;
signal clkin1_bufg : std_logic;
signal mmcm_rst : std_logic;
signal dcm_locked_int : std_logic;
signal dcm_locked_sync : std_logic;
signal dcm_locked_reg : std_logic := '1';
signal dcm_locked_edge : std_logic := '1';
signal mmcm_reset_in : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFDS
port map
(O => clkin1,
I => clk_in_p,
IB => clk_in_n);
-- route clkin1 through a BUFGCE for the MMCM reset generation logic
bufg_clkin1 : BUFGCE port map (I => clkin1, CE => '1', O => clkin1_bufg);
-- detect a falling edge on dcm_locked (after resyncing to this domain)
lock_sync : aeg_design_0_sync_block
port map (
clk => clkin1_bufg,
data_in => dcm_locked_int,
data_out => dcm_locked_sync
);
-- for the falling edge detect we want to force this at power on so init the flop to 1
dcm_lock_detect_p : process(clkin1_bufg)
begin
if clkin1_bufg'event and clkin1_bufg = '1' then
dcm_locked_reg <= dcm_locked_sync;
dcm_locked_edge <= dcm_locked_reg and not dcm_locked_sync;
end if;
end process dcm_lock_detect_p;
mmcm_reset_in <= glbl_rst or dcm_locked_edge;
-- the MMCM reset should be at least 5ns - that is one cycle of the input clock -
-- since the source of the input reset is unknown (a push switch in board design)
-- this needs to be debounced
mmcm_reset_gen : aeg_design_0_reset_sync
port map (
clk => clkin1_bufg,
enable => '1',
reset_in => mmcm_reset_in,
reset_out => mmcm_rst
);
------------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
------------------------------------------------------------------------------
clock_generator : aeg_design_0_clk_wiz
port map (
-- Clock in ports
CLK_IN1 => clkin1,
-- Clock out ports
CLK_OUT1 => gtx_clk_bufg,
CLK_OUT2 => s_axi_aclk,
CLK_OUT3 => refclk_bufg,
-- Status and control signals
RESET => mmcm_rst,
LOCKED => dcm_locked_int
);
dcm_locked <= dcm_locked_int;
end RTL;
| mit | aafc1e6e8b19e28c9e96fa8bb5d1a6db | 0.546679 | 4.552664 | false | false | false | false |
rkujawa/cr2amiga | clockport.vhd | 1 | 2,273 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clockport is
Port( -- clockport signals
data : inout STD_LOGIC_VECTOR (7 downto 0); -- data pins
addressIn : in STD_LOGIC_VECTOR (3 downto 0); -- address pins
iord : in STD_LOGIC; -- active low when read from device to CPU
iowr : in STD_LOGIC; -- active low when write from CPU to device
cs : in STD_LOGIC;
-- debug signals
--addressOut : out STD_LOGIC_VECTOR (3 downto 0);
-- registers used to exchange data
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
testOut : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg : in STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0)
);
end clockport;
architecture Behavioral of clockport is
signal address : STD_LOGIC_VECTOR (3 downto 0);
-- signal lastID : STD_LOGIC_VECTOR (7 downto 0) := "11000000";
-- signal currID : STD_LOGIC_VECTOR (7 downto 0);
begin
address <= addressIn when cs = '0' and (iord = '0' or iowr = '0');
--addressOut <= address;
--data <= "ZZZZZZZZ";
-- data <= btnReg & "0000" when (iord = '0' and cs = '0') and address = "0001" else
-- "00000001" when (iord = '0' and cs = '0') and address = "1111" else
-- -- somereg when (iord = '0' and cs = '0') AND address = "xxxxxxxx" else
-- "ZZZZZZZZ";
process (iord, cs, address, data)
begin
if iord = '0' and cs = '0' and address = "0000" then -- reg 0, 0xD80001
data <= "11100111";
elsif iord = '0' and cs = '0' and address = "0001" then -- reg 1, 0xD80005
data <= commDataInReg;
elsif iord = '0' and cs = '0' and address = "0010" then -- reg 2, 0xD80009
data <= "00000010";
elsif iord = '0' and cs = '0' and address = "0100" then -- reg 4, 0xD80011
data <= "00000100";
elsif iord = '0' and cs = '0' and address = "1101" then
data <= btnReg;
else
data <= "ZZZZZZZZ";
end if;
end process;
process (iowr, cs, address, data)
begin
if iowr = '0' and cs = '0' and address = "0001" then
commDataOutReg <= data;
-- testOut <= data;
elsif iowr = '0' and cs = '0' and address = "1111" then
ledReg(0) <= data(0);
ledReg(1) <= data(1);
ledReg(2) <= data(2);
ledReg(3) <= data(3);
end if;
end process;
end Behavioral;
| mit | 5d3e96a0ef043df3f04c0be83ec83fe1 | 0.619446 | 2.888183 | false | false | false | false |
titto-thomas/Pipeline_RISC | mux2to1.vhdl | 1 | 665 | --IITB RISC processor---
--Mux Module(2to1)---
-- author: Anakha
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
generic (
nbits : integer);
port (
input0 : in std_logic_vector(nbits-1 downto 0);
input1 : in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel : in std_logic);
end mux2to1;
architecture behave of mux2to1 is
begin -- mux2to1
process(input0,input1,sel)
variable sel_var: std_logic;
begin
sel_var:= sel;
case sel_var is
when '0' =>
output <= input0;
when '1' =>
output <= input1;
when others =>
output <= "Z";
end case;
end process;
end behave;
| gpl-2.0 | a71932f0d380457a01874417aa788ddb | 0.646617 | 2.770833 | false | false | false | false |
lennartbublies/ecdsa | src/e_nm_sipo_register.vhd | 1 | 1,161 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Serial In Parallel Out Register
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_nm_sipo_register IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
data_i : IN std_logic_vector(U-1 DOWNTO 0);
data_o : OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_nm_sipo_register;
ARCHITECTURE rtl OF e_nm_sipo_register IS
SIGNAL temp: std_logic_vector(M-1 DOWNTO 0);
BEGIN
PROCESS(clk_i,rst_i,enable_i)
BEGIN
IF rst_i = '1' THEN
temp <= (OTHERS => '0');
ELSIF(clk_i'event and clk_i='1' and enable_i='1') THEN
temp(M-1 DOWNTO U) <= temp(M-U-1 DOWNTO 0);
temp(U-1 DOWNTO 0) <= data_i(U-1 DOWNTO 0);
END IF;
END PROCESS;
data_o <= temp;
END rtl;
| gpl-3.0 | 64cf30389cdb96f985b9b4c893c6133e | 0.49354 | 3.486486 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/fifo/tri_mode_ethernet_mac_0_rx_client_fifo.vhd | 1 | 33,543 | --------------------------------------------------------------------------------
-- Title : Receiver FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_rx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the receiver side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the rx_mac_aclk. An end-of-frame marker is written to
-- the BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals
-- qualify the frame. A frame which ends with rx_axis_mac_tuser asserted
-- indicates a bad frame and will cause the FIFO write address
-- pointer to be reset to the base address of that frame. In this
-- way the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will
-- be enabled allowing data to be read from the FIFO.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (user side) should
-- always operate at an equal or faster frequency than the write
-- clock (MAC side).
--
-- The FIFO is designed to work with a minimum frame length of 8
-- bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame signaling (encoded by
-- rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64
-- clock cycles
-- * Write AxiStream clock is 125MHz downto 1.25MHz
-- * Read AxiStream clock equal to or faster than write clock,
-- and downto 20MHz
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the Receiver FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_rx_client_fifo is
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_rx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_rx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states
type rd_state_typ is (WAIT_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
QUEUE_SOF_s,
SOF_s,
DATA_s,
EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states
type wr_state_typ is (IDLE_s,
FRAME_s,
GF_s,
BF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe_long is array(0 to 2) of std_logic;
type cntl_pipe_short is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_dv_pipe : cntl_pipe_long;
signal wr_gfbf_pipe : cntl_pipe_short;
signal wr_gf : std_logic;
signal wr_bf : std_logic;
signal wr_eof_bram_pipe : cntl_pipe_short;
signal wr_eof_bram : std_logic;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_valid_pipe : std_logic_vector(1 downto 0);
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal wr_store_frame_tog : std_logic := '0';
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic := '0';
signal rd_store_frame : std_logic;
signal rd_frames : unsigned(8 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal old_rd_addr : std_logic_vector(1 downto 0);
signal update_addr_tog : std_logic;
signal update_addr_tog_sync : std_logic;
signal update_addr_tog_sync_reg : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff_in : unsigned(12 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rx_axis_fifo_tlast_int : std_logic;
signal doa_l_unused : std_logic_vector(8 downto 0);
signal doa_u_unused : std_logic_vector(8 downto 0);
signal rx_fifo_reset : std_logic;
signal rx_mac_reset : std_logic;
--------------------------------------------------------------------------------
-- Begin FIFO architecture
--------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
rx_fifo_reset <= not rx_fifo_resetn;
rx_mac_reset <= not rx_mac_resetn;
------------------------------------------------------------------------------
-- Read state machines and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF.
-- Clock state to next state.
clock_rds_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rx_axis_fifo_tlast <= rx_axis_fifo_tlast_int;
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready,
rx_axis_fifo_tlast_int, rd_valid_pipe)
begin
case rd_state is
when WAIT_s =>
-- Wait until there is a full frame in the FIFO, then
-- start to load the pipeline.
if frame_in_fifo = '1' and rx_axis_fifo_tlast_int = '0' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_s;
when SOF_s =>
-- A new frame begins immediately following end of last frame.
if rx_axis_fifo_tready = '1' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- Read data from the FIFO. When the EOF marker is detected from
-- the BRAM output, move to the EOF state.
if rx_axis_fifo_tready = '1' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- Hold in this state until tready is asserted and the EOF
-- marker (tlast) is accepted on interface.
-- If there is another frame in the FIFO, then it will already be
-- queued into the pipeline so so move straight to SOF state.
if rx_axis_fifo_tready = '1' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- Detect if frame_in_fifo was high 3 reads ago.
-- This is used to ensure we only treat data in the pipeline as valid if
-- frame_in_fifo goes high at or before the EOF marker of the current frame.
-- It may be that there is valid data (i.e a partial frame has been written)
-- but until the end of that frame we do not know if it is a good frame.
rd_valid_pipe_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if (rx_axis_fifo_tready = '1') then
rd_valid_pipe <= rd_valid_pipe(0) & frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- Decode tlast signal from EOF marker.
rd_ll_decode_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tlast_int <= '0';
elsif rx_axis_fifo_tready = '1' then
-- Assert tlast signal when the EOF marker has been detected, and
-- continue to drive it until it has been accepted on the interface.
case rd_state is
when EOF_s =>
rx_axis_fifo_tlast_int <= '1';
when others =>
rx_axis_fifo_tlast_int <= '0';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- Decode the tvalid output based on state.
rd_ll_src_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tvalid <= '0';
else
case rd_state is
when QUEUE_SOF_s =>
rx_axis_fifo_tvalid <= '1';
when SOF_s =>
rx_axis_fifo_tvalid <= '1';
when DATA_s =>
rx_axis_fifo_tvalid <= '1';
when EOF_s =>
rx_axis_fifo_tvalid <= '1';
when others =>
if rx_axis_fifo_tready = '1' then
rx_axis_fifo_tvalid <= '0';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- Decode internal control signals.
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en_p : process(rd_state, rx_axis_fifo_tready)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= rx_axis_fifo_tready;
end case;
end process rd_en_p;
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
-- When the current frame is done, and if there is no frame in the FIFO, then
-- the FIFO must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The
-- pipeline is then reloaded using the QUEUE states.
p_rd_addr_reload : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_addr_reload <= '0';
else
if rd_state = EOF_s and rd_nxt_state = WAIT_s then
rd_addr_reload <= '1';
else
rd_addr_reload <= '0';
end if;
end if;
end if;
end process p_rd_addr_reload;
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- When a frame has been stored we need to synchronize that event to the
-- read clock domain for frame count store.
resync_wr_store_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_fifo_aclk,
data_in => wr_store_frame_tog,
data_out => rd_store_frame_sync
);
p_delay_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
rd_store_frame_delay <= rd_store_frame_sync;
end if;
end process p_delay_rd_store;
-- Edge detect of the resynchronized frame count. This creates a pulse
-- when a new frame has been stored.
p_sync_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_store_frame <= '0';
else
-- Edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
-- This creates a pulse when a new frame has begun to be output.
p_rd_pull_frame : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_pull_frame <= '0';
else
if rd_state = SOF_s and rd_nxt_state /= SOF_s then
rd_pull_frame <= '1';
elsif rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s then
rd_pull_frame <= '1';
else
rd_pull_frame <= '0';
end if;
end if;
end if;
end process p_rd_pull_frame;
-- Up/down counter to monitor the number of frames stored within the FIFO.
-- Note:
-- * increments at the end of a frame write cycle
-- * decrements at the beginning of a frame read cycle
p_rd_frames : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the FIFO in this cycle, and no frame is being
-- read out on the same cycle.
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle.
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
------------------------------------------------------------------------------
-- Write state machines and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are IDLE, FRAME, GF, BF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_state <= IDLE_s;
else
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinatorial.
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf, wr_bf, wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- There is data in incoming pipeline when dv_pipe(1) goes high.
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- If FIFO is full then go to overflow state.
-- If the good or bad flag is detected, then the end of the frame
-- has been reached and the gf or bf state is visited before idle.
-- Otherwise remain in frame state while data is written to FIFO.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= FRAME_s;
end if;
when GF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when BF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- Wait until the good or bad flag received.
if wr_gf = '1' or wr_bf = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- Decode control signals, combinatorial.
-- wr_en is used to enable the BRAM write and loading of the input pipeline.
wr_en <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- Increment the write address when we are receiving valid frame data.
wr_addr_inc <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- If the FIFO overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- The start address is saved when in the idle state.
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- We need to know when a frame is stored, in order to increment the count of
-- frames stored in the FIFO.
p_wr_store_tog : process (rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when data is being written into the FIFO.
wr_addr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_addr <= (others => '0');
else
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- Store the start address.
wr_staddr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_start_addr <= (others => '0');
else
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- Read address is incremented when data is being read from the FIFO.
rd_addr_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 3;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_data_pipe(0) <= rx_axis_mac_tdata;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end process reg_din_p;
-- The valid input enables BRAM write and is a condition for other signals.
reg_dv_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_dv_pipe(0) <= rx_axis_mac_tvalid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_dv_pipe(2) <= wr_dv_pipe(1);
end if;
end process reg_dv_p;
-- End of frame flag set when tlast and tvalid are asserted together.
reg_eof_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_eof_bram_pipe(0) <= rx_axis_mac_tlast;
wr_eof_bram_pipe(1) <= wr_eof_bram_pipe(0);
wr_eof_bram <= wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_eof_p;
-- Upon arrival of EOF flag, the frame is good if tuser signal
-- is low, and bad if tuser signal is high.
reg_gf_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_gfbf_pipe(0) <= rx_axis_mac_tuser;
wr_gfbf_pipe(1) <= wr_gfbf_pipe(0);
wr_gf <= (not wr_gfbf_pipe(1)) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
wr_bf <= wr_gfbf_pipe(1) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_gf_p;
-- Register data outputs from BRAM.
-- No resets to allow for SRL16 target.
reg_dout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram;
rd_data_pipe <= rd_data_delay;
rx_axis_fifo_tdata <= rd_data_pipe;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_eof <= rd_eof_bram(0);
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Overflow functionality
------------------------------------------------------------------------------
-- to minimise the number of read address updates the bottom 6 bits of the
-- read address are not passed across and the write domain will only sample
-- them when bits 5 and 4 of the read address transition from 01 to 10.
-- Since this is for full detection this just means that if the read stops
-- the write will hit full up to 64 locations early
-- need to use two bits and look for an increment transition as reload can cause
-- a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe)
p_rd_addr_tog : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
old_rd_addr <= (others => '0');
update_addr_tog <= '0';
else
old_rd_addr <= std_logic_vector(rd_addr(5 downto 4));
if rd_addr(5 downto 4) = "10" and old_rd_addr = "01" then
update_addr_tog <= not update_addr_tog;
end if;
end if;
end if;
end process p_rd_addr_tog;
sync_rd_addr_tog: tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_mac_aclk,
data_in => update_addr_tog,
data_out => update_addr_tog_sync
);
-- Obtain the difference between write and read pointers.
p_sample_addr : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
update_addr_tog_sync_reg <= '0';
wr_rd_addr(11 downto 6) <= (others => '0');
else
update_addr_tog_sync_reg <= update_addr_tog_sync;
if update_addr_tog_sync_reg /= update_addr_tog_sync then
wr_rd_addr(11 downto 6) <= rd_addr(11 downto 6);
end if;
end if;
end if;
end process p_sample_addr;
wr_rd_addr(5 downto 0) <= "000000";
wr_addr_diff_in <= ('0' & wr_rd_addr) - ('0' & wr_addr);
-- Obtain the difference between write and read pointers.
p_addr_diff : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_addr_diff <= (others => '0');
else
wr_addr_diff <= wr_addr_diff_in(11 downto 0);
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_full <= '0';
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
-- Decode the overflow indicator output.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_wr_fifo_status : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_status <= "0000";
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram;
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
rx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => rx_mac_aclk,
b_clk => rx_fifo_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => rx_mac_reset,
b_rst => rx_fifo_reset,
a_wr => wr_en
);
end RTL;
| mit | 71826aa5990abec74070f22744acebeb | 0.54062 | 3.764646 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/support/tri_mode_ethernet_mac_0_support_resets.vhd | 1 | 6,337 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_support_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the shared resets for the IDELAYCTRL
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_support_resets is
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic -- The reset pulse for the IDELAYCTRL.
);
end tri_mode_ethernet_mac_0_support_resets;
architecture xilinx of tri_mode_ethernet_mac_0_support_resets is
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
signal glbl_rst : std_logic;
signal idelayctrl_reset_in : std_logic; -- Used to trigger reset_sync generation in refclk domain.
signal idelayctrl_reset_sync : std_logic; -- Used to create a reset pulse in the IDELAYCTRL refclk domain.
signal idelay_reset_cnt : std_logic_vector(3 downto 0); -- Counter to create a long IDELAYCTRL reset pulse.
signal idelayctrl_reset : std_logic;
begin
glbl_rst <= not glbl_rstn;
idelayctrl_reset_out <= idelayctrl_reset;
idelayctrl_reset_in <= glbl_rst or not idelayctrl_ready;
-- Create a synchronous reset in the IDELAYCTRL refclk clock domain.
idelayctrl_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map(
clk => refclk,
enable => '1',
reset_in => idelayctrl_reset_in,
reset_out => idelayctrl_reset_sync
);
-- Reset circuitry for the IDELAYCTRL reset.
-- The IDELAYCTRL must experience a pulse which is at least 50 ns in
-- duration. This is ten clock cycles of the 200MHz refclk. Here we
-- drive the reset pulse for 12 clock cycles.
process (refclk)
begin
if refclk'event and refclk = '1' then
if idelayctrl_reset_sync = '1' then
idelay_reset_cnt <= "0000";
idelayctrl_reset <= '1';
else
idelayctrl_reset <= '1';
case idelay_reset_cnt is
when "0000" => idelay_reset_cnt <= "0001";
when "0001" => idelay_reset_cnt <= "0010";
when "0010" => idelay_reset_cnt <= "0011";
when "0011" => idelay_reset_cnt <= "0100";
when "0100" => idelay_reset_cnt <= "0101";
when "0101" => idelay_reset_cnt <= "0110";
when "0110" => idelay_reset_cnt <= "0111";
when "0111" => idelay_reset_cnt <= "1000";
when "1000" => idelay_reset_cnt <= "1001";
when "1001" => idelay_reset_cnt <= "1010";
when "1010" => idelay_reset_cnt <= "1011";
when "1011" => idelay_reset_cnt <= "1100";
when "1100" => idelay_reset_cnt <= "1101";
when "1101" => idelay_reset_cnt <= "1110";
when others => idelay_reset_cnt <= "1110";
idelayctrl_reset <= '0';
end case;
end if;
end if;
end process;
end xilinx;
| mit | 8fdfc60ae6468e7896fc98e3a7fc78a7 | 0.579927 | 4.558993 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_Kofkplusone.vhd | 1 | 1,457 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Kofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
R : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Kofkplusone;
architecture struct of kn_kalman_Kofkplusone is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_inv IS
PORT
( clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
signal Z2 : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_add port map (clock => clock, dataa => Pdashofkplusone, datab => R, result => Z1);
M2 : kn_kalman_inv port map (clock => clock, data => Z1, result => Z2);
M3 : kn_kalman_mult port map (clock => clock, dataa => Pdashofkplusone, datab => Z2, result => Kofkplusone);
end struct;
| gpl-2.0 | 37daae43e1c6967349d0754bb824e5e8 | 0.639671 | 3.237778 | false | false | false | false |
Caian/Minesweeper | Projeto/vga_counter.vhd | 1 | 3,603 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity vga_counter is
port (
-- Sinais de entrada
clk_27M, rstn : in std_logic;
color_index : in std_logic_vector(3 downto 0);
-- Sinais de saida para a VGA
vga_hsync, vga_vsync : out std_logic;
vga_r, vga_g, vga_b : out std_logic_vector(3 downto 0);
vga_clk : buffer std_logic; -- 25.175 MHz
-- Sinais de saida para outros modulos
h_count, h_count_d : buffer std_logic_vector (9 downto 0);
v_count, v_count_d : buffer std_logic_vector (9 downto 0)
);
end entity;
architecture vga_counter_logic of vga_counter is
signal h_count_d2 : std_logic_vector (9 downto 0);
signal v_count_d2 : std_logic_vector (9 downto 0);
signal h_drawarea, v_drawarea, drawarea : std_logic;
signal pixel : std_logic_vector (11 downto 0);
begin
-- Gera o clock de 25.1 MHz pra VGA
divider: work.vga_pll port map (clk_27M, vga_clk);
-- Contador horizontal de pixels
horz_counter: process (vga_clk, rstn)
begin
if rstn = '0' then
h_count <= "0000000000";
h_count_d <= "0000000000";
h_count_d2 <= "0000000000";
elsif vga_clk'event and vga_clk = '1' then
h_count_d2 <= h_count_d;
h_count_d <= h_count;
if h_count = 799 then
h_count <= "0000000000";
else
h_count <= h_count + 1;
end if;
end if;
end process horz_counter;
-- Area horizontal da tela
horz_sync: process (h_count_d2)
begin -- process horz_sync
if h_count_d2 < 640 then
h_drawarea <= '1';
else
h_drawarea <= '0';
end if;
end process horz_sync;
-- Contador vertical de pixels
vert_counter: process (vga_clk, rstn)
begin -- process vert_counter
if rstn = '0' then
v_count <= "0000000000";
v_count_d <= "0000000000";
v_count_d2 <= "0000000000";
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
v_count_d2 <= v_count_d;
v_count_d <= v_count; -- 1 clock cycle delayed counter
if h_count = 699 then
if v_count = 524 then
v_count <= "0000000000";
else
v_count <= v_count + 1;
end if;
end if;
end if;
end process vert_counter;
-- Area vertical da tela
vert_sync: process (v_count_d2)
begin -- process vert_sync
if v_count_d2 < 480 then
v_drawarea <= '1';
else
v_drawarea <= '0';
end if;
end process vert_sync;
-- Sinais de sincronizacao
sync: process (v_count_d2, h_count_d2)
begin -- process sync
if (h_count_d2 >= 659) and (h_count_d2 <= 755) then
vga_hsync <= '0';
else
vga_hsync <= '1';
end if;
if (v_count_d2 >= 493) and (v_count_d2 <= 494) then
vga_vsync <= '0';
else
vga_vsync <= '1';
end if;
end process sync;
-- Gera a cor a partir do indice
PALETTE: vga_palette port map (color_index, pixel);
-- Manda as cores para a VGA
drawarea <= v_drawarea and h_drawarea;
vga_r <= pixel(11 downto 8) and (vga_r'range => drawarea);
vga_g <= pixel(7 downto 4) and (vga_g'range => drawarea);
vga_b <= pixel(3 downto 0) and (vga_b'range => drawarea);
end architecture;
| gpl-2.0 | 9252528a69e73dabde0c3905bc75cd3a | 0.55315 | 3.418406 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/imports/switch_fabric/arbitration_algorithm.vhd | 2 | 32,395 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 20.12.2013 16:58:39
-- Design Name:
-- Module Name: arbitration_round_robin - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- This implementation of a multiple algorithms that determine which of
-- the input ports is allowed to send the to the output port.
-- The algorithm is specified by the ARBITRATION generic:
-- 1: Round Robin
-- 2: Priority based
-- 3: Latency based
-- 4: Weighted prio/latency based
-- 5: Fair Queuing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity arbitration_algorithm is
generic(
NR_PORTS : integer;
LD_NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port(
clk : in std_logic;
reset : in std_logic;
in_start_arb : in std_logic;
in_req_ports : in std_logic_vector(NR_PORTS-1 downto 0);
in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
out_arb_finished : out std_logic;
out_winner_port : out std_logic_vector(LD_NR_PORTS-1 downto 0)
);
end arbitration_algorithm;
architecture rtl of arbitration_algorithm is
-- state machine
type state is (
IDLE,
ARBITRATE
);
signal cur_state : state;
signal nxt_state : state;
type port_weight_type is array(0 to NR_PORTS-1) of integer;
type prio_weight_type is array(0 to 8-1) of integer;
signal port_weight : port_weight_type := (0 => 1,
1 => 1,
2 => 1,
3 => 1);
signal prio_weight : prio_weight_type := (0 => 0,
1 => 3500,
2 => 2500,
3 => 3750,
4 => 5000,
5 => 6250,
6 => 7500,
7 => 8750);
signal arb_finished_reg : std_logic := '0';
signal cur_winner_reg : std_logic_vector(LD_NR_PORTS-1 downto 0);
signal nxt_winner_reg : std_logic_vector(LD_NR_PORTS-1 downto 0);
signal cnt : std_logic_vector(2 downto 0);
signal run_arbitration_sig : std_logic;
signal arb_finished_sig : std_logic;
signal arbitration_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal prev_req_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal arb_req_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal vft0_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0); -- virtual finishing time
signal vft1_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal vft2_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal vft3_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal vst0_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0); -- virtual start time
signal vst1_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal vst2_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal vst3_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal virtual_time_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal timestamp0 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal timestamp1 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal timestamp2 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal timestamp3 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal score0_reg : integer;
signal score1_reg : integer;
signal score2_reg : integer;
signal score3_reg : integer;
begin
timestamp0 <= in_timestamp(63 downto 0);
timestamp1 <= in_timestamp(127 downto 64);
timestamp2 <= in_timestamp(191 downto 128);
timestamp3 <= in_timestamp(255 downto 192);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, in_start_arb, arb_finished_reg)
begin
-- default signal assignments
nxt_state <= IDLE;
out_arb_finished <= '0';
run_arbitration_sig <= '0';
arb_finished_sig <= '0';
case cur_state is
when IDLE => -- waiting for a input port to request access
if in_start_arb = '1' then
nxt_state <= ARBITRATE;
run_arbitration_sig <= '1';
end if;
when ARBITRATE => -- determine the winner input port
if arb_finished_reg = '1' then
nxt_state <= IDLE;
out_arb_finished <= '1';
arb_finished_sig <= '1';
else
nxt_state <= ARBITRATE;
run_arbitration_sig <= '1';
end if;
end case;
end process;
arbitration_p : process(clk)
variable tmp_port : integer := 0;
variable leading_port : integer := 0;
variable leading_port01 : integer := 0;
variable leading_port23 : integer := 0;
variable tmp_prio : integer := 0;
variable tmp_prio0 : integer := 0;
variable tmp_prio1 : integer := 0;
variable tmp_prio2 : integer := 0;
variable tmp_prio3 : integer := 0;
variable leading_prio : integer := 0;
variable tmp_latency : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_latency0 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_latency1 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_latency2 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_latency3 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_timestamp0 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_timestamp1 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_timestamp2 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_timestamp3 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable leading_latency : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable leading_latency01 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable leading_latency23 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
variable tmp_score : integer;
variable tmp_score0 : integer;
variable tmp_score1 : integer;
variable tmp_score2 : integer;
variable tmp_score3 : integer;
variable leading_score : integer;
variable leading_score01 : integer;
variable leading_score23 : integer;
variable tmp_winner : integer;
begin
if (clk'event and clk = '1') then
if reset = '1' then
arb_finished_reg <= '0';
nxt_winner_reg <= (others => '0');
cnt <= (others => '0');
arbitration_timestamp <= (others => '0');
prev_req_reg <= (others => '0');
arb_req_reg <= (others => '0');
vft0_reg <= (others => '0');
vft1_reg <= (others => '0');
vft2_reg <= (others => '0');
vft3_reg <= (others => '0');
vst0_reg <= (others => '0');
vst1_reg <= (others => '0');
vst2_reg <= (others => '0');
vst3_reg <= (others => '0');
virtual_time_reg <= (others => '0');
else
arb_finished_reg <= '0';
nxt_winner_reg <= nxt_winner_reg;
cnt <= cnt;
if ARBITRATION = 1 then -- Round Robin
if run_arbitration_sig = '1' then
for i in 1 to NR_PORTS loop
tmp_port := (to_integer(unsigned(cur_winner_reg))+i) mod NR_PORTS;
if in_req_ports(tmp_port) = '1' then
arb_finished_reg <= '1';
nxt_winner_reg <= std_logic_vector(to_unsigned(tmp_port,LD_NR_PORTS));
end if;
exit when in_req_ports(tmp_port) = '1';
end loop;
end if;
elsif ARBITRATION = 2 then -- Priority based
if run_arbitration_sig = '1' then
leading_port := 0;
leading_prio := 0;
for i in 1 to NR_PORTS loop
tmp_port := (to_integer(unsigned(cur_winner_reg))+i) mod NR_PORTS;
tmp_prio := to_integer(unsigned(in_prio((tmp_port+1)*VLAN_PRIO_WIDTH-1 downto tmp_port*VLAN_PRIO_WIDTH))) + 1;
if in_req_ports(tmp_port) = '1' then
if tmp_prio > leading_prio then
leading_prio := tmp_prio;
leading_port := tmp_port;
end if;
end if;
end loop;
nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
arb_finished_reg <= '1';
end if;
-- elsif ARBITRATION = 3 then -- Latency based -- 4 clock cycles
-- if run_arbitration_sig = '1' then
-- if cnt = 0 then
-- leading_port := 0;
-- leading_latency := (others => '0');
-- end if;
-- tmp_port := (to_integer(unsigned(cur_winner_reg))+to_integer(unsigned(cnt)) + 1) mod NR_PORTS;
-- tmp_timestamp := in_timestamp((tmp_port+1)*TIMESTAMP_WIDTH-1 downto tmp_port*TIMESTAMP_WIDTH);
-- tmp_latency := timestamp_cnt - tmp_timestamp;
-- if in_req_ports(tmp_port) = '1' then
-- if tmp_latency > leading_latency then
-- leading_latency := tmp_latency;
-- leading_port := tmp_port;
-- end if;
-- end if;
-- cnt <= cnt + 1;
-- if cnt = 3 then
-- nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
-- arb_finished_reg <= '1';
-- cnt <= (others => '0');
-- end if;
-- end if;
elsif ARBITRATION = 3 then -- Latency based -- 1 clock cycle
if run_arbitration_sig = '1' then
-- determine latency of each port
leading_port := 0;
leading_latency := (others => '0');
tmp_timestamp0 := in_timestamp(TIMESTAMP_WIDTH-1 downto 0);
tmp_latency0 := timestamp_cnt - tmp_timestamp0;
tmp_timestamp1 := in_timestamp(2*TIMESTAMP_WIDTH-1 downto TIMESTAMP_WIDTH);
tmp_latency1 := timestamp_cnt - tmp_timestamp1;
tmp_timestamp2 := in_timestamp(3*TIMESTAMP_WIDTH-1 downto 2*TIMESTAMP_WIDTH);
tmp_latency2 := timestamp_cnt - tmp_timestamp2;
tmp_timestamp3 := in_timestamp(4*TIMESTAMP_WIDTH-1 downto 3*TIMESTAMP_WIDTH);
tmp_latency3 := timestamp_cnt - tmp_timestamp3;
-- semifinal
leading_latency01 := tmp_latency1;
leading_port01 := 1;
if in_req_ports(1) = '0' or (tmp_latency0 >= tmp_latency1 and in_req_ports(0) = '1') then
leading_latency01 := tmp_latency0;
leading_port01 := 0;
end if;
leading_latency23 := tmp_latency3;
leading_port23 := 3;
if in_req_ports(3) = '0' or (tmp_latency2 >= tmp_latency3 and in_req_ports(2) = '1') then
leading_latency23 := tmp_latency2;
leading_port23 := 2;
end if;
--final
leading_latency := leading_latency23;
leading_port := leading_port23;
if in_req_ports(leading_port23) = '0' or (leading_latency01 >= leading_latency23 and in_req_ports(leading_port01) = '1') then
leading_latency := leading_latency01;
leading_port := leading_port01;
end if;
nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
arb_finished_reg <= '1';
end if;
-- elsif ARBITRATION = 4 then -- Weighted prio/latency based -- 4 clock cycles
-- if run_arbitration_sig = '1' then
-- -- depending on the weigths this is round robin, priority based, latency based or a mixture
-- if cnt = 0 then
-- leading_port := 0;
-- leading_score := 0;
-- end if;
-- tmp_port := (to_integer(unsigned(cur_winner_reg))+to_integer(unsigned(cnt)) + 1) mod NR_PORTS;
-- tmp_timestamp := in_timestamp((tmp_port+1)*TIMESTAMP_WIDTH-1 downto tmp_port*TIMESTAMP_WIDTH);
-- tmp_latency := timestamp_cnt - tmp_timestamp;
-- tmp_prio := to_integer(unsigned(in_prio((tmp_port+1)*VLAN_PRIO_WIDTH-1 downto tmp_port*VLAN_PRIO_WIDTH)));
-- tmp_score := port_weight(tmp_port) * to_integer(unsigned(tmp_latency)) + prio_weight(tmp_prio);
-- if in_req_ports(tmp_port) = '1' then
-- if tmp_score > leading_score then
-- leading_score := tmp_score;
-- leading_port := tmp_port;
-- end if;
-- end if;
-- cnt <= cnt + 1;
-- if cnt = 3 then
-- nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
-- arb_finished_reg <= '1';
-- cnt <= (others => '0');
-- end if;
-- end if;
elsif ARBITRATION = 4 then -- Latency based -- one clock cycle
if run_arbitration_sig = '1' then
-- determine latency of each port
tmp_timestamp0 := in_timestamp(TIMESTAMP_WIDTH-1 downto 0);
tmp_latency0 := timestamp_cnt - tmp_timestamp0;
tmp_prio0 := to_integer(unsigned(in_prio(VLAN_PRIO_WIDTH-1 downto 0)));
tmp_score0 := to_integer(unsigned(tmp_latency0)) + prio_weight(tmp_prio0);
score0_reg <= to_integer(unsigned(tmp_latency0)) + prio_weight(tmp_prio0);
tmp_timestamp1 := in_timestamp(2*TIMESTAMP_WIDTH-1 downto TIMESTAMP_WIDTH);
tmp_latency1 := timestamp_cnt - tmp_timestamp1;
tmp_prio1 := to_integer(unsigned(in_prio(2*VLAN_PRIO_WIDTH-1 downto VLAN_PRIO_WIDTH)));
tmp_score1 := to_integer(unsigned(tmp_latency1)) + prio_weight(tmp_prio1);
score1_reg <= to_integer(unsigned(tmp_latency1)) + prio_weight(tmp_prio1);
tmp_timestamp2 := in_timestamp(3*TIMESTAMP_WIDTH-1 downto 2*TIMESTAMP_WIDTH);
tmp_latency2 := timestamp_cnt - tmp_timestamp2;
tmp_prio2 := to_integer(unsigned(in_prio(3*VLAN_PRIO_WIDTH-1 downto 2*VLAN_PRIO_WIDTH)));
tmp_score2 := to_integer(unsigned(tmp_latency2)) + prio_weight(tmp_prio2);
score2_reg <= to_integer(unsigned(tmp_latency2)) + prio_weight(tmp_prio2);
tmp_timestamp3 := in_timestamp(4*TIMESTAMP_WIDTH-1 downto 3*TIMESTAMP_WIDTH);
tmp_latency3 := timestamp_cnt - tmp_timestamp3;
tmp_prio3 := to_integer(unsigned(in_prio(4*VLAN_PRIO_WIDTH-1 downto 3*VLAN_PRIO_WIDTH)));
tmp_score3 := to_integer(unsigned(tmp_latency3)) + prio_weight(tmp_prio3);
score3_reg <= to_integer(unsigned(tmp_latency3)) + prio_weight(tmp_prio3);
-- semifinal
leading_score01 := tmp_score1;
leading_port01 := 1;
if in_req_ports(1) = '0' or (tmp_score0 >= tmp_score1 and in_req_ports(0) = '1') then
leading_score01 := tmp_score0;
leading_port01 := 0;
end if;
leading_score23 := tmp_score3;
leading_port23 := 3;
if in_req_ports(3) = '0' or (tmp_score2 >= tmp_score3 and in_req_ports(2) = '1') then
leading_score23 := tmp_score2;
leading_port23 := 2;
end if;
-- final
leading_score := leading_score23;
leading_port := leading_port23;
if in_req_ports(leading_port23) = '0' or (leading_score01 >= leading_score23 and in_req_ports(leading_port01) = '1') then
leading_score := leading_score01;
leading_port := leading_port01;
end if;
nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
arb_finished_reg <= '1';
end if;
elsif ARBITRATION = 5 then -- Fair Queuing
prev_req_reg <= in_req_ports;
arbitration_timestamp <= arbitration_timestamp;
if arb_finished_sig = '1' then
arbitration_timestamp <= timestamp_cnt;
end if;
-- port 0
vft0_reg <= vft0_reg;
vst0_reg <= vst0_reg;
if in_req_ports(0) = '0' then -- no request for transmission
elsif in_req_ports(0) = '1' and prev_req_reg(0) = '0' then -- new request, not requested in previous arbtiration round
if cur_winner_reg = 0 then -- message queued behind previous winner message
vft0_reg <= vft0_reg + in_length(FRAME_LENGTH_WIDTH-1 downto 0);
vst0_reg <= vft0_reg;
else -- new arriving message
if arb_req_reg /= 0 then -- more ports requesting access
vft0_reg <= timestamp_cnt - arbitration_timestamp + in_length(FRAME_LENGTH_WIDTH-1 downto 0);
vst0_reg <= timestamp_cnt - arbitration_timestamp;
else -- port 0 is the only port requesting access
vft0_reg(FRAME_LENGTH_WIDTH-1 downto 0) <= in_length(FRAME_LENGTH_WIDTH-1 downto 0);
vft0_reg(TIMESTAMP_WIDTH-1 downto FRAME_LENGTH_WIDTH) <= (others => '0');
vst0_reg <= (others => '0');
end if;
end if;
elsif arb_finished_sig = '1' then -- normalisation of virtual finish and virtual start time, so that vst of winner is 0 -> preventing overflows
if nxt_winner_reg = 0 then
vft0_reg <= vft0_reg - vst0_reg;
vst0_reg <= vst0_reg - vst0_reg;
elsif nxt_winner_reg = 1 then
vft0_reg <= vft0_reg - vst1_reg;
vst0_reg <= vst0_reg - vst1_reg;
elsif nxt_winner_reg = 2 then
vft0_reg <= vft0_reg - vst2_reg;
vst0_reg <= vst0_reg - vst2_reg;
elsif nxt_winner_reg = 3 then
vft0_reg <= vft0_reg - vst3_reg;
vst0_reg <= vst0_reg - vst3_reg;
end if;
end if;
-- port 1
vft1_reg <= vft1_reg;
vst1_reg <= vst1_reg;
if in_req_ports(1) = '0' then
elsif in_req_ports(1) = '1' and prev_req_reg(1) = '0' then
if cur_winner_reg = 1 then -- message queued behind previous winner message
vft1_reg <= vft1_reg + in_length(2*FRAME_LENGTH_WIDTH-1 downto FRAME_LENGTH_WIDTH);
vst1_reg <= vft1_reg;
else -- new arriving message
if arb_req_reg /= 0 then
vft1_reg <= timestamp_cnt - arbitration_timestamp + in_length(2*FRAME_LENGTH_WIDTH-1 downto FRAME_LENGTH_WIDTH);
vst1_reg <= timestamp_cnt - arbitration_timestamp;
else
vft1_reg(FRAME_LENGTH_WIDTH-1 downto 0) <= in_length(2*FRAME_LENGTH_WIDTH-1 downto FRAME_LENGTH_WIDTH);
vft1_reg(TIMESTAMP_WIDTH-1 downto FRAME_LENGTH_WIDTH) <= (others => '0');
vst1_reg <= (others => '0');
end if;
end if;
elsif arb_finished_sig = '1' then
if nxt_winner_reg = 0 then
vft1_reg <= vft1_reg - vst0_reg;
vst1_reg <= vst1_reg - vst0_reg;
elsif nxt_winner_reg = 1 then
vft1_reg <= vft1_reg - vst1_reg;
vst1_reg <= vst1_reg - vst1_reg;
elsif nxt_winner_reg = 2 then
vft1_reg <= vft1_reg - vst2_reg;
vst1_reg <= vst1_reg - vst2_reg;
elsif nxt_winner_reg = 3 then
vft1_reg <= vft1_reg - vst3_reg;
vst1_reg <= vst1_reg - vst3_reg;
end if;
end if;
-- port 2
vft2_reg <= vft2_reg;
vst2_reg <= vst2_reg;
if in_req_ports(2) = '0' then
elsif in_req_ports(2) = '1' and prev_req_reg(2) = '0' then
if cur_winner_reg = 2 then -- message queued behind previous winner message
vft2_reg <= vft2_reg + in_length(3*FRAME_LENGTH_WIDTH-1 downto 2*FRAME_LENGTH_WIDTH);
vst2_reg <= vft2_reg;
else -- new arriving message
if arb_req_reg /= 0 then
vft2_reg <= timestamp_cnt - arbitration_timestamp + in_length(3*FRAME_LENGTH_WIDTH-1 downto 2*FRAME_LENGTH_WIDTH);
vst2_reg <= timestamp_cnt - arbitration_timestamp;
else
vft2_reg(FRAME_LENGTH_WIDTH-1 downto 0) <= in_length(3*FRAME_LENGTH_WIDTH-1 downto 2*FRAME_LENGTH_WIDTH);
vft2_reg(TIMESTAMP_WIDTH-1 downto FRAME_LENGTH_WIDTH) <= (others => '0');
vst2_reg <= (others => '0');
end if;
end if;
elsif arb_finished_sig = '1' then
if nxt_winner_reg = 0 then
vft2_reg <= vft2_reg - vst0_reg;
vst2_reg <= vst2_reg - vst0_reg;
elsif nxt_winner_reg = 1 then
vft2_reg <= vft2_reg - vst1_reg;
vst2_reg <= vst2_reg - vst1_reg;
elsif nxt_winner_reg = 2 then
vft2_reg <= vft2_reg - vst2_reg;
vst2_reg <= vst2_reg - vst2_reg;
elsif nxt_winner_reg = 3 then
vft2_reg <= vft2_reg - vst3_reg;
vst2_reg <= vst2_reg - vst3_reg;
end if;
end if;
-- port 3
vft3_reg <= vft3_reg;
vst3_reg <= vst3_reg;
if in_req_ports(3) = '0' then
elsif in_req_ports(3) = '1' and prev_req_reg(3) = '0' then
if cur_winner_reg = 3 then -- message queued behind previous winner message
vft3_reg <= vft3_reg + in_length(4*FRAME_LENGTH_WIDTH-1 downto 3*FRAME_LENGTH_WIDTH);
vst3_reg <= vft3_reg;
else -- new arriving message
if arb_req_reg /= 0 then
vft3_reg <= timestamp_cnt - arbitration_timestamp + in_length(4*FRAME_LENGTH_WIDTH-1 downto 3*FRAME_LENGTH_WIDTH);
vst3_reg <= timestamp_cnt - arbitration_timestamp;
else
vft3_reg(FRAME_LENGTH_WIDTH-1 downto 0) <= in_length(4*FRAME_LENGTH_WIDTH-1 downto 3*FRAME_LENGTH_WIDTH);
vft3_reg(TIMESTAMP_WIDTH-1 downto FRAME_LENGTH_WIDTH) <= (others => '0');
vst3_reg <= (others => '0');
end if;
end if;
elsif arb_finished_sig = '1' then
if nxt_winner_reg = 0 then
vft3_reg <= vft3_reg - vst0_reg;
vst3_reg <= vst3_reg - vst0_reg;
elsif nxt_winner_reg = 1 then
vft3_reg <= vft3_reg - vst1_reg;
vst3_reg <= vst3_reg - vst1_reg;
elsif nxt_winner_reg = 2 then
vft3_reg <= vft3_reg - vst2_reg;
vst3_reg <= vst3_reg - vst2_reg;
elsif nxt_winner_reg = 3 then
vft3_reg <= vft3_reg - vst3_reg;
vst3_reg <= vst3_reg - vst3_reg;
end if;
end if;
if run_arbitration_sig = '1' then
--cnt <= cnt + 1;
--if cnt = 0 then
leading_port := 0;
leading_score := 0;
--end if;
--if cnt = 1 then
if in_req_ports(0) = '1' then
----if leading_score = 0 or to_integer(unsigned(vft0_reg)) < leading_score then
----leading_port := 0;
leading_score := to_integer(unsigned(vft0_reg));
----end if;
end if;
if in_req_ports(1) = '1' then
if leading_score = 0 or to_integer(unsigned(vft1_reg)) < leading_score then
leading_port := 1;
leading_score := to_integer(unsigned(vft1_reg));
end if;
end if;
if in_req_ports(2) = '1' then
if leading_score = 0 or to_integer(unsigned(vft2_reg)) < leading_score then
leading_port := 2;
leading_score := to_integer(unsigned(vft2_reg));
end if;
end if;
if in_req_ports(3) = '1' then
if leading_score = 0 or to_integer(unsigned(vft3_reg)) < leading_score then
leading_port := 3;
leading_score := to_integer(unsigned(vft3_reg));
end if;
end if;
nxt_winner_reg <= std_logic_vector(to_unsigned(leading_port,LD_NR_PORTS));
arb_finished_reg <= '1';
arb_req_reg <= in_req_ports;
--cnt <= (others => '0');
--end if;
end if;
if run_arbitration_sig = '1' then
if cur_winner_reg = 0 then
virtual_time_reg <= vft0_reg;
elsif cur_winner_reg = 1 then
virtual_time_reg <= vft1_reg;
elsif cur_winner_reg = 2 then
virtual_time_reg <= vft2_reg;
elsif cur_winner_reg = 3 then
virtual_time_reg <= vft3_reg;
end if;
end if;
end if;
end if;
end if;
end process;
update_pre_port_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_winner_reg <= (others => '0');
else
cur_winner_reg <= cur_winner_reg;
if arb_finished_sig = '1' then
cur_winner_reg <= nxt_winner_reg;
end if;
end if;
end if;
end process;
out_winner_port <= nxt_winner_reg;
end rtl;
| mit | 7e2f0999a3c83ebfd4c21cd62bedae07 | 0.443186 | 4.444368 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/fifo/tri_mode_ethernet_mac_0_bram_tdp.vhd | 5 | 4,519 | --------------------------------------------------------------------------------
-- Title : RAM memory for RX and TX client FIFOs
-- Version : 1.0
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_bram_tdp.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a parameterized inferred block RAM
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block RAM
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_bram_tdp is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end tri_mode_ethernet_mac_0_bram_tdp;
architecture rtl of tri_mode_ethernet_mac_0_bram_tdp is
-- Shared memory
constant RAM_DEPTH : integer := 2 ** ADDR_WIDTH;
type mem_type is array ( RAM_DEPTH-1 downto 0 ) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
-- To write use port A
process(a_clk)
begin
if(a_clk'event and a_clk='1') then
if(a_rst='0' and a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
end if;
end process;
-- To read use Port B
process(b_clk)
begin
if(b_clk'event and b_clk='1') then
if (b_rst='1') then
b_dout <= (others => '0');
elsif (b_en='1') then
b_dout <= mem(conv_integer(b_addr));
end if;
end if;
end process;
end rtl;
| mit | f8904c6085d65dcc4106172b8b473c08 | 0.605886 | 4.164977 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_uart_transmit.vhd | 1 | 2,639 | -------------------------------------------------------------------------------
-- Module: tb_uart_transmit
-- Purpose: Testbench for module e_uart_transmit.
--
-- Author: Leander Schulz
-- Date: 07.09.2017
-- Last change: 22.10.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_uart_transmit IS
END ENTITY tb_uart_transmit;
ARCHITECTURE tb_arch OF tb_uart_transmit IS
-- IMPORT UART COMPONENT
COMPONENT e_uart_transmit IS
GENERIC(
baud_rate : IN NATURAL RANGE 1200 TO 500000;
M : integer
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
verify_i : IN std_logic;
start_i : IN std_logic;
data_i : IN std_logic_vector (7 DOWNTO 0);
tx_o : OUT std_logic;
reg_o : OUT std_logic );
END COMPONENT e_uart_transmit;
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL s_mode : std_logic := '0';
SIGNAL s_verify : std_logic := '0';
SIGNAL s_start_bit : std_logic := '0';
SIGNAL s_uart_data : std_logic_vector (7 DOWNTO 0) := "00000000";
SIGNAL s_tx : std_logic;
SIGNAL s_reg_ctrl : std_logic;
BEGIN
-- Instantiate uart transmitter
transmit_instance : e_uart_transmit
GENERIC MAP (
baud_rate => 500000,
M => 8 -- key length [bit]
) PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
mode_i => s_mode,
verify_i => s_verify,
start_i => s_start_bit,
data_i => s_uart_data,
tx_o => s_tx,
reg_o => s_reg_ctrl
);
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
tx_gen : PROCESS
BEGIN
s_uart_data <= "10011001";
WAIT FOR 80 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 200 ns;
s_start_bit <= '1';
WAIT FOR 20 ns;
s_start_bit <= '0';
WAIT FOR 20 us;
s_uart_data <= "01011010";
WAIT FOR 20 us;
s_uart_data <= "01100110";
WAIT FOR 20 us;
s_uart_data <= "01010101";
WAIT;
END PROCESS tx_gen;
END ARCHITECTURE tb_arch;
| gpl-3.0 | b462162410b656d359a7a54b19e355be | 0.435771 | 3.869501 | false | false | false | false |
diecaptain/kalman_mppt | kr_regbuf_enable.vhd | 1 | 737 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity kr_regbuf_enable is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0);
enable : out std_logic );
end kr_regbuf_enable;
architecture behav of kr_regbuf_enable is
begin
process ( clock, reset, load, I)
begin
if (reset = '1') then
Y <= "00000000000000000000000000000000";
enable <= '0';
elsif (clock'event and clock = '1') then
if (load = '1') then
Y <= I;
enable <= '1';
end if;
end if;
end process;
end behav;
| gpl-2.0 | 295ed169f53f284a87c823823c456d73 | 0.561737 | 3.666667 | false | false | false | false |
lfmunoz/4dsp_sip_interface | ip_ctrl.vhd | 1 | 10,356 | -------------------------------------------------------------------------------------
-- FILE NAME : fmc176_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc176_ctrl
-- architecture - fmc176_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- fmc176_ctrl
-- Notes: fmc176_ctrl
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
-------------------------------------------------------------------------------------
-- Specified libraries
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- Entity declaration
-------------------------------------------------------------------------------------
entity stellarip_registers is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
reg0 : out std_logic_vector(31 downto 0);
reg1 : out std_logic_vector(31 downto 0);
reg2 : in std_logic_vector(31 downto 0);
reg3 : in std_logic_vector(31 downto 0);
reg4 : in std_logic_vector(31 downto 0);
reg5 : in std_logic_vector(31 downto 0);
reg6 : in std_logic_vector(31 downto 0);
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end stellarip_registers;
-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture fmc_ctrl_syn of stellarip_registers is
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_REG0 : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_REG1 : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_REG2 : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_REG3 : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_REG4 : std_logic_vector(31 downto 0) := x"00000004";
constant ADDR_REG5 : std_logic_vector(31 downto 0) := x"00000005";
constant ADDR_REG6 : std_logic_vector(31 downto 0) := x"00000006";
constant ADDR_REG7 : std_logic_vector(31 downto 0) := x"00000007";
constant ADDR_REG8 : std_logic_vector(31 downto 0) := x"00000008";
constant ADDR_REG9 : std_logic_vector(31 downto 0) := x"00000009";
constant ADDR_REGA : std_logic_vector(31 downto 0) := x"0000000A";
constant ADDR_REGB : std_logic_vector(31 downto 0) := x"0000000B";
constant ADDR_REGC : std_logic_vector(31 downto 0) := x"0000000C";
constant ADDR_REGD : std_logic_vector(31 downto 0) := x"0000000D";
constant ADDR_REGE : std_logic_vector(31 downto 0) := x"0000000E";
constant ADDR_REGF : std_logic_vector(31 downto 0) := x"0000000F";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal register9 : std_logic_vector(31 downto 0);
signal registerA : std_logic_vector(31 downto 0);
--*************************************************************************************************
begin
--*************************************************************************************************
reg0 <= register0;
reg1 <= register1;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
stellar_cmd_inst:
entity work.gbl_generic_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
out_reg_val_ack => out_reg_val_ack,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
wr_ack => wr_ack,
mbx_in_val => mbx_in_val,
mbx_in_reg => mbx_in_reg
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
-- cmd_reg <= (others => '0');
in_reg_val <= '0';
in_reg <= (others => '0');
wr_ack <= '0';
register0 <= (others=>'0');
register1 <= (others=>'0');
elsif (rising_edge(clk_cmd)) then
------------------------------------------------------------
-- Write
------------------------------------------------------------
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_REG0) then
register0 <= out_reg;
else
register0 <= (others=>'0');
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_REG1) then
register1 <= out_reg;
end if;
-- Write acknowledge
if (out_reg_val_ack = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
------------------------------------------------------------
-- Read
if (in_reg_req = '1' and in_reg_addr = ADDR_REG0) then
in_reg_val <= '1';
in_reg <= register0;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG1) then
in_reg_val <= '1';
in_reg <= register1;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG2) then
in_reg_val <= '1';
in_reg <= reg2;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG3) then
in_reg_val <= '1';
in_reg <= reg3;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG4) then
in_reg_val <= '1';
in_reg <= reg4;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG5) then
in_reg_val <= '1';
in_reg <= reg5;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG6) then
in_reg_val <= '1';
in_reg <= reg6;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
--*************************************************************************************************
end fmc_ctrl_syn;
--*************************************************************************************************
| mit | 60398c9c14a16e97aaaf37932a69c744 | 0.450463 | 4.204629 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/synth/fifo_generator_0.vhd | 1 | 38,606 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_0 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_0_arch : ARCHITECTURE IS "fifo_generator_0,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 16,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 2,
C_AXIS_TKEEP_WIDTH => 2,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
| mit | 27ff301e883088162b06eda8968b7159 | 0.627959 | 2.918286 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/mac/tri_mode_ethernet_mac_0_support_resets.vhd | 2 | 6,315 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_support_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the shared resets for the IDELAYCTRL
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_support_resets is
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic -- The reset pulse for the IDELAYCTRL.
);
end tri_mode_ethernet_mac_0_support_resets;
architecture xilinx of tri_mode_ethernet_mac_0_support_resets is
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component aeg_design_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
signal glbl_rst : std_logic;
signal idelayctrl_reset_in : std_logic; -- Used to trigger reset_sync generation in refclk domain.
signal idelayctrl_reset_sync : std_logic; -- Used to create a reset pulse in the IDELAYCTRL refclk domain.
signal idelay_reset_cnt : std_logic_vector(3 downto 0); -- Counter to create a long IDELAYCTRL reset pulse.
signal idelayctrl_reset : std_logic;
begin
glbl_rst <= not glbl_rstn;
idelayctrl_reset_out <= idelayctrl_reset;
idelayctrl_reset_in <= glbl_rst or not idelayctrl_ready;
-- Create a synchronous reset in the IDELAYCTRL refclk clock domain.
idelayctrl_reset_gen : aeg_design_0_reset_sync
port map(
clk => refclk,
enable => '1',
reset_in => idelayctrl_reset_in,
reset_out => idelayctrl_reset_sync
);
-- Reset circuitry for the IDELAYCTRL reset.
-- The IDELAYCTRL must experience a pulse which is at least 50 ns in
-- duration. This is ten clock cycles of the 200MHz refclk. Here we
-- drive the reset pulse for 12 clock cycles.
process (refclk)
begin
if refclk'event and refclk = '1' then
if idelayctrl_reset_sync = '1' then
idelay_reset_cnt <= "0000";
idelayctrl_reset <= '1';
else
idelayctrl_reset <= '1';
case idelay_reset_cnt is
when "0000" => idelay_reset_cnt <= "0001";
when "0001" => idelay_reset_cnt <= "0010";
when "0010" => idelay_reset_cnt <= "0011";
when "0011" => idelay_reset_cnt <= "0100";
when "0100" => idelay_reset_cnt <= "0101";
when "0101" => idelay_reset_cnt <= "0110";
when "0110" => idelay_reset_cnt <= "0111";
when "0111" => idelay_reset_cnt <= "1000";
when "1000" => idelay_reset_cnt <= "1001";
when "1001" => idelay_reset_cnt <= "1010";
when "1010" => idelay_reset_cnt <= "1011";
when "1011" => idelay_reset_cnt <= "1100";
when "1100" => idelay_reset_cnt <= "1101";
when "1101" => idelay_reset_cnt <= "1110";
when others => idelay_reset_cnt <= "1110";
idelayctrl_reset <= '0';
end case;
end if;
end if;
end process;
end xilinx;
| mit | d972a71a36d206e72a326faa50d1297f | 0.579097 | 4.569465 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/mac/mac_fifo/mac_fifo_interface.vhd | 2 | 5,863 | -- -----------------------------------------------------------------------------
-- Description: this module contains
-- - an rx Fifo interface between the MAC and the input port
-- - an tx Fifo interface between the output port and the MAC
-- to decouple the clocks of the MAC and the switch
-- switch should have a equal or higher clock rate as the MAC
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity mac_fifo_interface is
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FULL_DUPLEX_ONLY : boolean := true
); -- If fifo is to be used only in full duplex set to true for optimised implementation
port (
-- txpath interface
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- support block interface
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic;
-- rxpath interface
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- support block interface
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end mac_fifo_interface;
architecture RTL of mac_fifo_interface is
component switch_input_port_fifo
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer
);
port (
-- User-side interface (read)
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- MAC-side interface (write)
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end component;
component switch_output_port_fifo
generic (
GMII_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer
);
port (
-- User-side interface (write)
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- MAC-side interface (read)
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic
);
end component;
begin
rx_fifo_i : switch_input_port_fifo
generic map(
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH
)
port map(
rx_fifo_out_clk => rx_fifo_out_clk,
rx_fifo_out_reset => rx_fifo_out_reset,
rx_fifo_out_data => rx_fifo_out_data,
rx_fifo_out_valid => rx_fifo_out_valid,
rx_fifo_out_last => rx_fifo_out_last,
rx_fifo_out_error => rx_fifo_out_error,
rx_fifo_in_clk => rx_fifo_in_clk,
rx_fifo_in_reset => rx_fifo_in_reset,
rx_fifo_in_data => rx_fifo_in_data,
rx_fifo_in_valid => rx_fifo_in_valid,
rx_fifo_in_last => rx_fifo_in_last,
rx_fifo_in_error => rx_fifo_in_error
);
tx_fifo_i : switch_output_port_fifo
generic map(
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH
)
port map(
tx_fifo_in_clk => tx_fifo_in_clk,
tx_fifo_in_reset => tx_fifo_in_reset,
tx_fifo_in_data => tx_fifo_in_data,
tx_fifo_in_valid => tx_fifo_in_valid,
tx_fifo_in_last => tx_fifo_in_last,
tx_fifo_in_ready => tx_fifo_in_ready,
tx_fifo_out_clk => tx_fifo_out_clk,
tx_fifo_out_reset => tx_fifo_out_reset,
tx_fifo_out_data => tx_fifo_out_data,
tx_fifo_out_valid => tx_fifo_out_valid,
tx_fifo_out_last => tx_fifo_out_last,
tx_fifo_out_ready => tx_fifo_out_ready,
tx_fifo_out_error => tx_fifo_out_error
);
end RTL;
| mit | 25c160ec6250311b5cb45e38c5b3951e | 0.535903 | 3.212603 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/sim/fifo_generator_1.vhd | 1 | 33,376 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_1 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_1;
ARCHITECTURE fifo_generator_1_arch OF fifo_generator_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_1_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(93 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(93 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 7,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 94,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 94,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 63,
C_PROG_FULL_THRESH_NEGATE_VAL => 62,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 7,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 7,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_1_arch;
| mit | ca4997607894144a3693b9808009e164 | 0.607023 | 3.073014 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/axi4-stream-bfm-master.vhd | 1 | 2,850 | library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
entity axiBfmMaster is
port(aclk,n_areset:in std_ulogic;
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
readResponse,writeResponse:buffer t_bfm;
axiMaster_in:in t_axi4StreamTransactor_s2m;
axiMaster_out:buffer t_axi4StreamTransactor_m2s;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:buffer t_cnt;
dbg_axiTxFsm:out axiBfmStatesTx:=idle
);
end entity axiBfmMaster;
architecture rtl of axiBfmMaster is
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_readResponse,i_writeResponse:t_bfm;
begin
process(n_areset,symbolsPerTransfer,aclk) is begin
if falling_edge(aclk) then
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
else
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
end if;
end process;
axi_bfmTx_ns: process(all) is begin
axiTxState<=next_axiTxState;
if not n_areset then axiTxState<=idle;
else
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
end if;
end process axi_bfmTx_ns;
axi_bfmTx_op: process(all) is begin
i_writeResponse<=writeResponse;
axiMaster_out.tValid<=false;
axiMaster_out.tLast<=false;
axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
end if;
if not n_areset then axiMaster_out.tData<=(others=>'Z');
else
case next_axiTxState is
when payload=>
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
end if;
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
when others=> null;
end case;
end if;
end process axi_bfmTx_op;
process(n_areset,aclk) is begin
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
end if;
end process;
process(aclk) is begin
if rising_edge(aclk) then
writeResponse<=i_writeResponse;
end if;
end process;
dbg_axiTxFSM<=axiTxState;
end architecture rtl;
| mit | 2dc3cc13b04ddbca54946162cb8d5595 | 0.721404 | 3.28341 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/tri_mode_ethernet_mac_0_example_design_clocks.vhd | 1 | 7,492 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_clocks.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates the clocking logic required for the
-- example design.
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_example_design_clocks is
port (
-- clocks
clk_in_p : in std_logic;
clk_in_n : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
dcm_locked : out std_logic;
-- clock outputs
gtx_clk_bufg : out std_logic;
refclk_bufg : out std_logic;
s_axi_aclk : out std_logic
);
end tri_mode_ethernet_mac_0_example_design_clocks;
architecture RTL of tri_mode_ethernet_mac_0_example_design_clocks is
------------------------------------------------------------------------------
-- Component declaration for the clock generator
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_clk_wiz
port
( -- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal clkin1 : std_logic;
signal clkin1_bufg : std_logic;
signal mmcm_rst : std_logic;
signal dcm_locked_int : std_logic;
signal dcm_locked_sync : std_logic;
signal dcm_locked_reg : std_logic := '1';
signal dcm_locked_edge : std_logic := '1';
signal mmcm_reset_in : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFDS
port map
(O => clkin1,
I => clk_in_p,
IB => clk_in_n);
-- route clkin1 through a BUFGCE for the MMCM reset generation logic
bufg_clkin1 : BUFGCE port map (I => clkin1, CE => '1', O => clkin1_bufg);
-- detect a falling edge on dcm_locked (after resyncing to this domain)
lock_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => clkin1_bufg,
data_in => dcm_locked_int,
data_out => dcm_locked_sync
);
-- for the falling edge detect we want to force this at power on so init the flop to 1
dcm_lock_detect_p : process(clkin1_bufg)
begin
if clkin1_bufg'event and clkin1_bufg = '1' then
dcm_locked_reg <= dcm_locked_sync;
dcm_locked_edge <= dcm_locked_reg and not dcm_locked_sync;
end if;
end process dcm_lock_detect_p;
mmcm_reset_in <= glbl_rst or dcm_locked_edge;
-- the MMCM reset should be at least 5ns - that is one cycle of the input clock -
-- since the source of the input reset is unknown (a push switch in board design)
-- this needs to be debounced
mmcm_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => clkin1_bufg,
enable => '1',
reset_in => mmcm_reset_in,
reset_out => mmcm_rst
);
------------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
------------------------------------------------------------------------------
clock_generator : tri_mode_ethernet_mac_0_clk_wiz
port map (
-- Clock in ports
CLK_IN1 => clkin1,
-- Clock out ports
CLK_OUT1 => gtx_clk_bufg,
CLK_OUT2 => s_axi_aclk,
CLK_OUT3 => refclk_bufg,
-- Status and control signals
RESET => mmcm_rst,
LOCKED => dcm_locked_int
);
dcm_locked <= dcm_locked_int;
end RTL;
| mit | 7bcf7b17f6dc8b0900ae88fbaa440e64 | 0.552189 | 4.507822 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/switch_port_tx_path.vhd | 2 | 4,844 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_tx_path - rtl
--
-- Description: to be done
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end switch_port_tx_path;
architecture rtl of switch_port_tx_path is
component tx_path_output_queue
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- tx_path interface to fabric
oq_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oq_in_valid : in std_logic;
oq_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oq_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oq_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_in_req : in std_logic;
oq_in_accept_frame : out std_logic;
-- timestamp
oq_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
oq_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oq_out_valid : out std_logic;
oq_out_ready : in std_logic;
oq_out_last : out std_logic
);
end component;
signal reset : std_logic;
begin
reset <= not tx_path_resetn;
output_queue : tx_path_output_queue
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => tx_path_clock,
reset => reset,
-- tx_path interface to fabric
oq_in_data => tx_in_data,
oq_in_valid => tx_in_valid,
oq_in_length => tx_in_length,
oq_in_prio => tx_in_prio,
oq_in_timestamp => tx_in_timestamp,
oq_in_req => tx_in_req,
oq_in_accept_frame => tx_in_accept_frame,
-- timestamp
oq_in_timestamp_cnt => tx_in_timestamp_cnt,
oq_out_latency => tx_out_latency,
-- tx_path interface to mac
oq_out_data => tx_out_data,
oq_out_valid => tx_out_valid,
oq_out_ready => tx_out_ready,
oq_out_last => tx_out_last
);
end rtl; | mit | 2540b250bedb8e4ea3d7df9333064949 | 0.472956 | 3.980279 | false | false | false | false |
bazk/hwsat | templates/imp.vhd | 1 | 1,182 | library ieee;
use ieee.std_logic_1164.all;
entity imp_{{ current_var.name }} is
port (
clk: in std_logic;
reset: in std_logic;
clear: in std_logic;
change: out std_logic;
contra: out std_logic;
{% for var in variables %}
{{ var.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
value: in std_logic_vector(0 to 1)
);
end imp_{{ current_var.name }};
architecture behavioral of imp_{{ current_var.name }} is
signal imp: std_logic_vector(0 to 1);
signal nxt: std_logic_vector(0 to 1);
signal cur: std_logic_vector(0 to 1);
begin
process (clk, reset, clear)
begin
if (reset='1') then
cur <= "00";
elsif (clear='1') then
cur <= "00";
elsif (rising_edge(clk)) then
cur <= nxt;
end if;
end process;
{{ current_var.name }} <= cur;
imp(0) <= {{ current_var.pos_implications }};
imp(1) <= {{ current_var.neg_implications }};
nxt(0) <= value(0) or imp(0);
nxt(1) <= value(1) or imp(1);
change <= (nxt(0) xor cur(0)) or (nxt(1) xor cur(1));
contra <= cur(0) and cur(1);
end behavioral; | gpl-3.0 | 231960384158dcef91c03cc574e2a08b | 0.539763 | 3.283333 | false | false | false | false |
Caian/Minesweeper | Projeto/game_timeclock.vhd | 1 | 941 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity game_timeclock is
port( clk24, rstn : in std_logic;
clk1 : out std_logic
);
end;
architecture game_timeclock_logic of game_timeclock is
begin
process(clk24, rstn)
constant F_HZ : integer := 1;
constant DIVIDER : integer := 24000000/F_HZ;
variable count : integer range 0 to DIVIDER := 0;
begin
if rstn = '0' then
count := 0;
clk1 <= '0';
elsif rising_edge(clk24) then
if count < DIVIDER / 2 then
clk1 <= '1';
else
clk1 <= '0';
end if;
if count = DIVIDER then
count := 0;
end if;
count := count + 1;
end if;
end process;
end architecture;
| gpl-2.0 | e762ca1d7d7fc696fb465f378846a303 | 0.520723 | 3.397112 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_tld.vhd | 1 | 5,807 | -------------------------------------------------------------------------------
-- Module: tb_tld
-- Purpose: Testbench for Top Level Domain of ECDSA
--
-- Author: Leander Schulz
-- Date: 01.11.2017
-- Last change: 01.11.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_tld IS
END ENTITY tb_tld;
ARCHITECTURE tb_arch OF tb_tld IS
-- import tld of ecdsa
COMPONENT tld_ecdsa IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Uart read/write
uart_rx_i : IN std_logic;
uart_wx_i : OUT std_logic;
rst_led : OUT std_logic
);
END COMPONENT tld_ecdsa;
--internal signals
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL S_rx : std_logic;
SIGNAL S_tx : std_logic;
SIGNAL s_led : std_logic;
SIGNAL s_r : std_logic_vector (167 DOWNTO 0);
SIGNAL s_s : std_logic_vector (167 DOWNTO 0);
SIGNAL s_m : std_logic_vector (167 DOWNTO 0);
SIGNAL s_mode : std_logic;
BEGIN
-- create ecdsa instance
tld_inst : tld_ecdsa
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
uart_rx_i => s_rx,
uart_wx_i => s_tx,
rst_led => s_led
);
-- generate clock signal
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
-- begin testbench tests
testing : PROCESS IS
PROCEDURE p_send (
SIGNAL s_mode : IN std_logic;
SIGNAL s_r : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_s : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_m : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_rx : OUT std_logic
) IS
BEGIN
-- send mode
ASSERT FALSE REPORT "Send Mode" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR i IN 0 TO 7 LOOP
s_rx <= s_mode;
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
IF s_mode = '1' THEN
-- send r
ASSERT FALSE REPORT "Send Point R" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_r(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
-- send s
ASSERT FALSE REPORT "Send Point S" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_s(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END IF;
-- send m
ASSERT FALSE REPORT "Send Message" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
ASSERT (i*8+j)<168 SEVERITY WARNING;
s_rx <= s_m(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END p_send;
BEGIN
-- Initialise Hardware
s_rx <= '1';
WAIT FOR 100 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 80 ns;
-- Test Case 1 --------------------------------------
s_r <= x"020B448AD8BE882CD980816C7EEA289FD3B2D517DB";
s_s <= x"0586558EFE0D6068075EA682084A259E370B4A375B";
--s_m <= x"00CD06203260EEE9549351BD29733E7D1E2ED49D88";
s_m <= x"0669148956365B7FABBC2383ED3ED1678D4E564463";
-- Sign
s_mode <= '0';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- TODO: check tx for valid result
WAIT FOR 3500 us;
-- Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- should evaluate to false
WAIT FOR 3500 us;
-- Test Case 1 - Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
WAIT FOR 3500 us;
-- Test Case 2 --------------------------------------
s_r <= x"020B448AD8BE882CD980816C7EEA289FD3B2D517DB";
s_s <= x"005107642C9D1D591ED4F944040B28EB692B7680A0";
s_m <= x"0669148956365B7FABBC2383ED3ED1678D4E564463";
-- Sign
s_mode <= '0';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- result:
-- 020B448AD8BE882CD980816C7EEA289FD3B2D517DB
-- 0586558EFE0D6068075EA682084A259E370B4A375B
-- 0669148956365B7FABBC2383ED3ED1678D4E564463
WAIT FOR 3500 us;
-- Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- should evaluate to true
WAIT;
END PROCESS testing;
END ARCHITECTURE tb_arch;
| gpl-3.0 | a7819103d5281331c5e0d31da46c59e8 | 0.435509 | 3.780599 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s3/counter/counter_t.vhd | 1 | 851 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: counter_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity counter_t is
end entity;
architecture arch_counter_t of counter_t is
component counter is
generic (N : integer := 4);
port (number : out std_logic_vector (N - 1 downto 0) := (others => '0');
clk, r : in std_logic);
end component counter;
signal clk, r : std_logic := '0';
signal number : std_logic_vector (3 downto 0);
for all:counter use entity work.counter(beh_arch_counter);
begin
c : counter generic map (4) port map (number, clk, r);
clk <= not clk after 50 ns;
end architecture arch_counter_t;
| gpl-3.0 | 971b7b1fbdba84aab55acde69b5e7fd3 | 0.548766 | 3.716157 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_gf2m_point_multiplication.vhd | 1 | 8,915 | ----------------------------------------------------------------------------------------------------
-- Testbench - gf2m Point Multiplication
-- Executes NUMBER_TESTS operations with random values of K.
-- Test k.P = (k-1).P + P, FOR a fixed known P.
--
-- Finally k = n-1, being n = order of point P and test:
-- k.P = (n-1).P = -P = (xP, xP+yP)
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 14.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
use work.tld_ecdsa_package.all;
ENTITY tb_gf2m_point_multupliation IS
END tb_gf2m_point_multupliation;
ARCHITECTURE rtl OF tb_gf2m_point_multupliation IS
-- Import entity e_gf2m_point_multiplication
COMPONENT e_gf2m_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k_i: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_point_addition
COMPONENT e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Internal signals
SIGNAL xP, yP, k, k_minus_1, xQ1, yQ1, xQ2, yQ2, xQ3, yQ3, xP_plus_yP: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, start_add, done, done_2, done_add: std_logic := '0';
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 5;
CONSTANT P_order : std_logic_vector(M-1 DOWNTO 0) := "100" & x"000000000000000000020108a2e0cc0d99f8a5ee";
--CONSTANT P_order : std_logic_vector(M-1 DOWNTO 0) := "000000110";
BEGIN
-- Instantiate first point multiplier entity
uut1: e_gf2m_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk,
rst_i => rst,
enable_i => enable,
xp_i => xP,
yp_i => yP,
k_i => k,
xq_io => xQ1,
yq_io => yQ1,
ready_o => done
);
-- Instantiate seccond point multiplier entity
uut2: e_gf2m_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk,
rst_i => rst,
enable_i => enable,
xp_i => xP,
yp_i => yP,
k_i => k_minus_1,
xq_io => xQ2,
yq_io => yQ2,
ready_o => done_2
);
-- Instantiate point addition entity
uut3: e_gf2m_point_addition GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk,
rst_i => rst,
enable_i => start_add,
x1_i => xP,
y1_i => yP,
x2_i => xQ2,
y2_i => yQ2,
x3_io => xQ3,
y3_o => yQ3,
ready_o => done_add
);
-- Set point P for the computation
k_minus_1 <= k - '1';
xP <= "010" & x"fe13c0537bbc11acaa07d793de4e6d5e5c94eee8";
yP <= "010" & x"89070fb05d38ff58321f2e800536d538ccdaa3d9";
--xP <= "011101110";
--yP <= "010101111";
xP_plus_yP <= xP xor yP;
-- clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
-- Procedure to generate random value for k
PROCEDURE gen_random(X : out std_logic_vector (M-1 DOWNTO 0); w: natural; s1, s2: inout Natural) IS
VARIABLE i_x, aux: integer;
VARIABLE rand: real;
BEGIN
aux := w/16;
FOR i IN 1 TO aux LOOP
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(65536)));-- real(2**16)));
x(i*16-1 DOWNTO (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16);
END LOOP;
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16))));
x(w-1 DOWNTO aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16));
END PROCEDURE;
-- Internal signals
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
VARIABLE seed1, seed2: positive;
VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer;
VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0;
VARIABLE avg_cycles: real;
VARIABLE initial_time, final_time: time;
VARIABLE xx: std_logic_vector (M-1 DOWNTO 0) ;
BEGIN
min_cycles:= 2**20;
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Loop over all test cases
FOR I IN 1 TO NUMBER_TESTS LOOP
-- Generate random input for k
gen_random(xx, M, seed1, seed2);
WHILE (xx >= P_order) LOOP
gen_random(xx, M, seed1, seed2);
END LOOP;
-- Start test 1:
-- Count runtime
k <= xx;
enable <= '1';
initial_time := now;
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1') and (done_2 = '1');
final_time := now;
cycles := (final_time - initial_time)/PERIOD;
total_cycles := total_cycles+cycles;
--ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) & " TotalCycles: " & integer'image(total_cycles) SEVERITY WARNING;
IF cycles > max_cycles THEN
max_cycles:= cycles;
END IF;
IF cycles < min_cycles THEN
min_cycles:= cycles;
END IF;
-- Start test 2:
-- Check if k.P = (k-1).P + P for a known P
-- uut1 computes k.P
-- uut2 computes (k-1).P
-- uut3 computes (k-1).P + P
WAIT FOR PERIOD;
start_add <= '1';
WAIT FOR PERIOD;
start_add <= '0';
WAIT UNTIL done_add = '1';
WAIT FOR 2*PERIOD;
IF ( xQ1 /= xQ3 or (yQ1 /= yQ3) ) THEN
write(TX_LOC,string'("ERROR!!! k.P /= (k-1)*P + P; k = ")); write(TX_LOC, k);
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
END LOOP;
WAIT FOR DELAY;
-- Start test 3:
-- Check if k.P = (n-1).P = -P = (xP, xP+yP)
-- uut1 computes k.P with k = (n-1)
k <= P_order;
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL done = '1';
IF ( xQ1 /= xP or (yQ1 /= xP_plus_yP) ) THEN
write(TX_LOC,string'("ERROR!!! k.P = (n-1).P = -P = (xP, xP+yP) with n order of P")); write(TX_LOC, k);
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 10*PERIOD;
avg_cycles := real(total_cycles)/real(NUMBER_TESTS);
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!. MinCycles: " & integer'image(min_cycles) &
" MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) &
" AvgCycles: " & real'image(avg_cycles)
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | b262db1b95150168a3307860326b0c7e | 0.501402 | 3.487872 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/lookuptable1/example_design/lookuptable1_prod.vhd | 1 | 10,547 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: lookuptable1_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : lookuptable1.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 28
-- C_READ_WIDTH_A : 28
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 7
-- C_READ_WIDTH_B : 7
-- C_WRITE_DEPTH_B : 32768
-- C_READ_DEPTH_B : 32768
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 1
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY lookuptable1_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END lookuptable1_prod;
ARCHITECTURE xilinx OF lookuptable1_prod IS
COMPONENT lookuptable1_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : lookuptable1_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-3.0 | 2a30c41ea128be2b855817b145869c97 | 0.491893 | 3.859129 | false | false | false | false |
titto-thomas/Pipeline_RISC | CondBlock.vhdl | 1 | 882 | ----------------------------------------
-- Conditional update of RF Write : IITB-RISC
-- Author : Titto Thomas
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CondBlock is
port (
OpCode : in std_logic_vector(5 downto 0); -- Opcode (0-2 and 12-15) bits
ALU_val : in std_logic; -- valid signal from ALU
Curr_RFWrite : in std_logic; -- Current value of RF write
Nxt_RFWrite : out std_logic -- Next value for RF write
);
end CondBlock;
architecture Condition of CondBlock is
begin
Main : process(OpCode, ALU_val, Curr_RFWrite)
begin
if ( (Opcode = b"000010" or Opcode = b"000001" or Opcode = b"001010" or Opcode = b"001001") )then
Nxt_RFWrite <= ALU_val;
else
Nxt_RFWrite <= Curr_RFWrite;
end if;
end process Main;
end architecture Condition;
| gpl-2.0 | 26d8adad7c8ee48281397e75bbf5554a | 0.611111 | 3.37931 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/ALU.vhd | 1 | 2,823 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-05-2016
-- Module Name: ALU.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity ALU is
port (A, B : in std_logic_vector (15 downto 0);
OP : in std_logic_vector (3 downto 0);
func : in std_logic_vector (2 downto 0);
result : out std_logic_vector (15 downto 0);
cond : out std_logic);
end ALU;
architecture rtl of ALU is
Signal tResult : std_logic_vector (15 downto 0);
Signal tCond : std_logic;
begin
process(A, B, OP, func)
begin
case OP is
when "0000" | "1111" =>
if func = "000" or func = "111" then
tResult <= A + B;
elsif func = "110" then
tResult <= A - B;
elsif func = "101" then
tResult <= (A AND B);
elsif func = "100" then
tResult <= (A OR B);
elsif func = "011" then
tResult <= (A XOR B);
elsif func = "010" then
tResult <= (A NOR B);
elsif func = "001" then
if A < B then
tResult <= (0 => '1', others => '0');
else
tResult <= (others => '0');
end if;
end if;
tCond <= '0';
when "0001" =>
tResult <= A + B;
tCond <= '0';
when "0010" =>
tResult <= (A AND B);
tCond <= '0';
when "0011" =>
tResult <= (A OR B);
tCond <= '0';
when "0100" =>
tResult <= std_logic_vector(shift_left(unsigned(A), to_integer(unsigned(B))));
tCond <= '0';
when "0101" =>
tResult <= std_logic_vector(shift_right(unsigned(A), to_integer(unsigned(B))));
tCond <= '0';
when "0110" =>
tResult <= std_logic_vector(shift_right(signed(A), to_integer(unsigned(B))));
tCond <= '0';
when "0111" =>
tResult <= A + B;
tcond <= '0';
when "1000" =>
tResult <= A + B;
tcond <= '0';
when "1001" =>
if A = B then
tCond <= '1';
else
tCond <= '0';
end if;
tResult <= A + B;
when "1010" =>
if A = B then
tCond <= '0';
else
tCond <= '1';
end if;
tResult <= A + B;
when "1011" =>
if A < B then
tCond <= '1';
else
tCond <= '0';
end if;
tResult <= A + B;
when "1100" =>
if A > B then
tCond <= '1';
else
tCond <= '0';
end if;
tResult <= A + B;
when "1101" =>
if A > B then
tCond <= '0';
else
tCond <= '1';
end if;
tResult <= A + B;
when "1110" =>
if A < B then
tCond <= '0';
else
tCond <= '1';
end if;
tResult <= A + B;
when others =>
tResult <= (others => '0');
tCond <= '0';
end case;
end process;
result <= tResult;
cond <= tCond;
end architecture;
| gpl-3.0 | f9798be7574e759297a695913340443b | 0.48034 | 2.946764 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_uart_receiver.vhd | 1 | 9,913 | ----------------------------------------------------------------------------------------------------
-- Entity - UART Receive Data Testbench
-- Testbench of e_uart_receiver
--
-- Generic:
-- baud_rate : baud rate of UART
-- Ports:
-- clk_i : clock signal
-- rst_i : global reset
-- rx_i : RX input of UART
-- mode_i : toggle SIG (0) and VALID (1)
-- wrreq_o : write request for FIFO input of data
-- fifo_o : parallel byte-aligned data output
-- sig_o : 163bit signature, only used in VALID mode
-- rdy_o : marks if receipt of data has finished and outputs are ready
--
-- Author: Leander Schulz ([email protected])
-- Date: 08.08.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_uart_receiver IS
END ENTITY tb_uart_receiver;
ARCHITECTURE e_uart_receiver_tb_arch OF tb_uart_receiver IS
-- IMPORT UART COMPONENT
COMPONENT e_uart_receiver IS
GENERIC (
baud_rate : IN NATURAL RANGE 1200 TO 500000;
N : IN NATURAL RANGE 1 TO 256;
M : IN NATURAL RANGE 1 TO 256);
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
rx_i : IN std_logic;
mode_i : IN std_logic;
data_o : OUT std_logic_vector (M-1 DOWNTO 0);
ena_r_o : OUT std_logic;
ena_s_o : OUT std_logic;
ena_m_o : OUT std_logic;
rdy_o : OUT std_logic);
END COMPONENT e_uart_receiver;
-- TB internal signals
SIGNAL s_clk : std_logic;
SIGNAL s_rx : std_logic := '1';
SIGNAL s_rst : std_logic;
SIGNAL s_mode : std_logic := '1';
SIGNAL s_data : std_logic_vector(7 DOWNTO 0);
SIGNAL s_ena_r_o : std_logic;
SIGNAL s_ena_s_o : std_logic;
SIGNAL s_ena_m_o : std_logic;
SIGNAL s_rdy_o : std_logic;
-- baud table:
-- 9600 baud ^= 104166ns ^= 5208 cycles
-- 115200 baud ^= 8680ns ^= 434 cycles
-- 500000 baud ^= 2000ns ^= 100 cycles
BEGIN
uart_receiver: e_uart_receiver
GENERIC MAP (
baud_rate => 500000,
N => 1, -- length of message
M => 9) -- length of key
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
rx_i => s_rx,
mode_i => s_mode,
data_o => s_data,
ena_r_o => s_ena_r_o,
ena_s_o => s_ena_s_o,
ena_m_o => s_ena_m_o,
rdy_o => s_rdy_o
);
clk_gen : PROCESS
BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS clk_gen;
rx_gen : PROCESS
BEGIN
s_rx <= '1';
WAIT FOR 100 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 880 ns;
-- R Byte 1
-- "01100101"
ASSERT FALSE REPORT "R Byte 1" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- R Byte 0
-- "01101001":
ASSERT FALSE REPORT "R Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- S Byte 1
-- "01010101"
ASSERT FALSE REPORT "S Byte 1" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- S Byte 0
-- "01101001":
ASSERT FALSE REPORT "S Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- Message Byte 0
-- "01101001":
ASSERT FALSE REPORT "M Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 5000 ns;
-- change mode to sign
s_mode <= '0';
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 80 ns;
-- Message Byte 2
-- "01111101":
ASSERT FALSE REPORT "M Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '0'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- Message Byte 1
-- "10011001":
ASSERT FALSE REPORT "M Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '1'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
-- Message Byte 0
-- "10101010":
ASSERT FALSE REPORT "M Byte 0" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
s_rx <= '0'; -- LSB (Bit 0)
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 1
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 2
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 3
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 4
WAIT FOR 2000 ns;
s_rx <= '1'; -- Bit 5
WAIT FOR 2000 ns;
s_rx <= '0'; -- Bit 6
WAIT FOR 2000 ns;
s_rx <= '1'; -- MSB (Bit 7)
-- no parity bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- stop Bit
WAIT FOR 2000 ns;
s_rx <= '1'; -- idle
WAIT FOR 3000 ns;
WAIT;
END PROCESS rx_gen;
END ARCHITECTURE e_uart_receiver_tb_arch;
| gpl-3.0 | c0a0435b33ec291dad04c620e1c475a9 | 0.399274 | 3.545422 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/lookuptable1/simulation/lookuptable1_tb.vhd | 1 | 4,541 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: lookuptable1_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY lookuptable1_tb IS
END ENTITY;
ARCHITECTURE lookuptable1_tb_ARCH OF lookuptable1_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
lookuptable1_synth_inst:ENTITY work.lookuptable1_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 9f0d54e34f0d526293e3b6e62c8b11fc | 0.618586 | 4.62895 | false | false | false | false |
caiopo/mips-multiciclo | src/blocoControle.vhd | 1 | 3,412 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer: Prof. Dr. Eng. Rafael Luiz Cancian
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blocoControle is
port(
clock, reset: in std_logic;
PCEscCond, PCEsc, IouD, LerMem, EscMem, MemParaReg, IREsc, RegDst, EscReg, ULAFonteA: out std_logic;
ULAFonteB, ULAOp, FontePC: out std_logic_vector(1 downto 0);
opcode: in std_logic_vector(5 downto 0)
);
end entity;
architecture FSMcomportamental of blocoControle is
type state is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
signal next_state, actual_state : state;
constant lw : std_logic_vector(5 downto 0) := "100011";
constant sw : std_logic_vector(5 downto 0) := "101011";
constant tipoR : std_logic_vector(5 downto 0) := "000000";
constant beq : std_logic_vector(5 downto 0) := "000100";
constant jump : std_logic_vector(5 downto 0) := "000010";
begin
-- state register
process(clock,reset)
begin
if reset = '1' then
actual_state <= s0;
elsif rising_edge(clock) then
actual_state <= next_state;
end if;
end process;
-- next state logig
process(opcode,clock)
begin
case actual_state is
when s0 =>
next_state <= s1;
when s1 =>
if opcode = tipoR then
next_state <= s6;
elsif (opcode = lw) or (opcode = sw) then
next_state <= s2;
elsif opcode = beq then
next_state <= s8;
elsif opcode = jump then
next_state <= s9;
end if;
when s2 =>
if opcode = lw then
next_state <= s3;
else
next_state <= s5;
end if;
when s3 =>
next_state <= s4;
when s4 =>
next_state <= s0;
when s5 =>
next_state <= s0;
when s6 =>
next_state <= s7;
when s7 =>
next_state <= s0;
when s8 =>
next_state <= s0;
when s9 =>
next_state <= s0;
end case;
end process;
-- output logic
process(clock, actual_state)
begin
PCEscCond <= '0';
PCEsc <= '0';
IouD <= '0';
LerMem <= '0';
EscMem <= '0';
MemParaReg <= '0';
IREsc <= '0';
RegDst <= '0';
EscReg <= '0';
ULAFonteA <= '0';
ULAFonteB <= "00";
ULAOp <= "00";
FontePC <= "00";
case actual_state is
when s0 =>
LerMem <= '1';
-- ULAFonteA <= '0';
-- IouD <= '0';
IREsc <= '1';
ULAFonteB <= "01";
-- ULAOp <= "00";
PCEsc <= '1';
-- FontePC <= "00";
when s1 =>
-- ULAFonteA <= '0';
ULAFonteB <= "11";
-- ULAOp <= "00";
when s2 =>
ULAFonteA <= '1';
ULAFonteB <= "10";
-- ULAOp <= "00";
when s3 =>
LerMem <= '1';
IouD <= '1';
when s4 =>
EscReg <= '1';
MemParaReg <= '1';
-- RegDst <= '0';
when s5 =>
EscMem <= '1';
IouD <= '1';
when s6 =>
ULAFonteA <= '1';
-- ULAFonteB <= "00";
ULAOp <= "10";
when s7 =>
RegDst <= '1';
EscReg <= '1';
-- MemParaReg <= '0';
when s8 =>
ULAFonteA <= '1';
-- ULAFonteB <= "00";
ULAOp <= "01";
PCEscCond <= '1';
-- PCEsc <= '0';
FontePC <= "01";
when s9 =>
PCEsc <= '1';
FontePC <= "10";
end case;
end process;
end architecture; | mit | 46a8021f8709833d377cde26305cecfa | 0.536342 | 2.805921 | false | false | false | false |
Caian/Minesweeper | Projeto/game_ctrlunit.vhd | 1 | 17,368 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity game_ctrlunit is
port(
-- Comum
clock, rstn : in std_logic;
-- Conexao com a memoria principal
ram_data_out : in std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_data_in : out std_logic_vector(7 downto 0);
ram_addr : buffer std_logic_vector(10 downto 0);
-- Conexao com a pilha
stack_data_out : in std_logic_vector(13 downto 0);
stack_empty : in std_logic;
stack_mode : out std_logic_vector(1 downto 0);
stack_data_in : buffer std_logic_vector(13 downto 0);
-- Conexao com o RNG
rng_x, rng_y : in std_logic_vector(4 downto 0);
rng_enable : out std_logic;
-- Conexao com o contador de tempo
timer_enable : out std_logic;
-- Conexao com o contador de minas
-- minecnt_enable : out std_logic;
-- minecnt_mode : out std_logic;
flagcnt : buffer std_logic_vector(10 downto 0);
num_mines : in std_logic_vector(8 downto 0);
-- Estado do jogo
game_state : buffer std_logic_vector(1 downto 0);
-- Estado do mouse
mouse_pos_x, mouse_pos_y : in std_logic_vector(9 downto 0);
mouse_click_l, mouse_click_r : in std_logic
);
end entity;
architecture game_ctrlunit_logic of game_ctrlunit is
type State_type IS (
S_0, -- Estado inicial
S_IClr, S_IRng, S_IRdM, S_IChkM, S_IWrM, -- Geracao de minas
S_IRdN, S_IChkN, S_IIncN, S_IWrN, -- Geracao de vizinhos
S_MW, S_MHL, S_MHR, S_MR, S_ML, S_MOpen, -- Botoes do mouse
S_SAmPush, S_SAmProc, S_SAmUpdate, S_SAmOpen, -- SAm
S_GameOver -- Fim de jogo
);
signal st : State_type;
signal buttons_state : std_logic_vector(1 downto 0);
--constant num_mines : natural := 20;
constant num_field : natural := 672;
begin
process(clock, rstn)
variable lin : std_logic_vector(4 downto 0);
variable col : std_logic_vector(5 downto 0);
variable mines : integer range 0 to num_field;
variable free : integer range 0 to num_field;
variable cnt : natural range 0 to 7;
begin
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if rstn = '0' then
st <= S_0;
ram_wren <= '0';
ram_addr <= (others => '0');
ram_data_in <= (others => '0');
stack_mode <= "00";
stack_data_in <= (others => '0');
buttons_state <= "00";
game_state <= "00";
rng_enable <= '0';
timer_enable <= '0';
-- minecnt_enable <= '0';
-- minecnt_mode <= '0';
flagcnt <= "00" & num_mines;
lin := "00111";
col := "000100";
mines := to_integer(unsigned(num_mines));
free := num_field;
cnt := 0;
---------------------------------------------------------------------------
-- Clock
---------------------------------------------------------------------------
elsif rising_edge(clock) then
ram_wren <= '0';
ram_data_in <= (others => '0');
stack_mode <= "00";
stack_data_in <= (others => '0');
-- minecnt_enable <= '0';
-- minecnt_mode <= '0';
case st is
---------------------------------------------------------------------------
-- Estado inicial
---------------------------------------------------------------------------
when S_0 =>
st <= S_IClr;
---------------------------------------------------------------------------
--
--
-- Inicializacao do Campo
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Limpa o campo
---------------------------------------------------------------------------
when S_IClr =>
st <= S_IClr;
ram_wren <= '1';
ram_addr <= lin & col;
ram_data_in <= "01000000";
if col = 35 then
if lin = 27 then
st <= S_IRng;
rng_enable <= '1';
else
lin := lin + 1;
end if;
col := "000100";
else
col := col + 1;
end if;
---------------------------------------------------------------------------
-- Gera posicoes aleatorias (ou quase)
---------------------------------------------------------------------------
when S_IRng =>
st <= S_IRdM;
if free = (num_field - mines) then
st <= S_MW;
else
if rng_y > 20 then
st <= S_IRng;
else
ram_addr <= (rng_y + 7) & (('0' & rng_x) + 4);
end if;
end if;
---------------------------------------------------------------------------
-- Le a posicao da memoria
---------------------------------------------------------------------------
when S_IRdM =>
st <= S_IChkM;
---------------------------------------------------------------------------
-- Verifica se ja nao eh uma mina
---------------------------------------------------------------------------
when S_IChkM =>
st <= S_IWrM;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(3 downto 0) /= "1111" then
--mines := mines - 1;
free := free - 1;
cnt := 0;
ram_data_in <= "01001111";
ram_wren <= '1';
else
st <= S_IRng;
end if;
---------------------------------------------------------------------------
-- Escreve posicao de memoria
---------------------------------------------------------------------------
when S_IWrM =>
st <= S_IChkN;
---------------------------------------------------------------------------
-- Calcula endereco do vizinho
---------------------------------------------------------------------------
when S_IChkN =>
case cnt is
when 0 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
when 1 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) + 1);
when 2 => ram_addr <= (ram_addr(10 downto 6) - 1) &
(ram_addr( 5 downto 0) );
when 3 => ram_addr <= (ram_addr(10 downto 6) - 1) &
(ram_addr( 5 downto 0) );
when 4 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) - 1);
when 5 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) - 1);
when 6 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
when 7 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
end case;
cnt := cnt + 1;
st <= S_IRdN;
---------------------------------------------------------------------------
-- Le o vizinho
---------------------------------------------------------------------------
when S_IRdN =>
st <= S_IIncN;
---------------------------------------------------------------------------
-- Verifica se eh um quadrado normal e incrementa o contador de minas
---------------------------------------------------------------------------
when S_IIncN =>
st <= S_IWrN;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(3 downto 0) /= "1111" then
ram_wren <= '1';
ram_data_in <= ram_data_out(7 downto 4) &
(ram_data_out(3 downto 0) + 1);
end if;
---------------------------------------------------------------------------
-- Escreve o novo numero de minas vistas pelo campo
---------------------------------------------------------------------------
when S_IWrN =>
if cnt = 0 then
st <= S_IRng;
else
st <= S_IChkN;
end if;
---------------------------------------------------------------------------
--
--
-- Tratamento de Botoes
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Aguarda botoes
---------------------------------------------------------------------------
when S_MW =>
if free = 0 then
game_state <= "11";
st <= s_GameOver;
else
buttons_state(1) <= mouse_click_l;
buttons_state(0) <= mouse_click_r;
--ram_addr <= (others => '0');
ram_addr <= mouse_pos_y(8 downto 4) & mouse_pos_x(9 downto 4);
if (buttons_state(1) = '1') then
st <= S_MHL;
elsif (buttons_state(0) = '1') then
st <= S_MHR;
end if;
-- if (buttons_state(1) or buttons_state(0)) = '1' then
-- st <= S_MH;
-- else
-- st <= S_MW;
-- end if;
end if;
---------------------------------------------------------------------------
-- Load and Wait
---------------------------------------------------------------------------
when S_MHL =>
ram_addr <= mouse_pos_y(8 downto 4) &
mouse_pos_x(9 downto 4);
if (not mouse_click_l) = '1' then
st <= S_ML;
else
st <= S_MHL;
end if;
---------------------------------------------------------------------------
-- Load and Wait
---------------------------------------------------------------------------
when S_MHR =>
ram_addr <= mouse_pos_y(8 downto 4) &
mouse_pos_x(9 downto 4);
if (not mouse_click_r) = '1' then
st <= S_MR;
else
st <= S_MHR;
end if;
---------------------------------------------------------------------------
-- Right Mouse
---------------------------------------------------------------------------
when S_MR =>
st <= S_MW;
buttons_state(0) <= '0';
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5) = '0' then
if (ram_data_out(4) = '1') then
flagcnt <= flagcnt + 1;
elsif (ram_data_out(4) = '0') then
flagcnt <= flagcnt - 1;
end if;
ram_wren <= '1';
ram_data_in(4) <= not ram_data_out(4);
ram_data_in(7 downto 5) <= ram_data_out(7 downto 5);
ram_data_in(3 downto 0) <= ram_data_out(3 downto 0);
end if;
---------------------------------------------------------------------------
-- Left Mouse
---------------------------------------------------------------------------
when S_ML =>
st <= S_MOpen;
---------------------------------------------------------------------------
-- Left Mouse
---------------------------------------------------------------------------
when S_MOpen =>
st <= S_MW;
buttons_state(1) <= '0';
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5 downto 4) = "00" then
-- Inicia a contagem de tempo
timer_enable <= '1';
-- Atualiza a memoria principal
ram_wren <= '1';
ram_data_in(5) <= '1';
ram_data_in(7 downto 6) <= ram_data_out(7 downto 6);
ram_data_in(4 downto 0) <= ram_data_out(4 downto 0);
if ram_data_out(3 downto 0) = "1111" then
-- Fim do jogo
game_state <= "10";
st <= S_GameOver;
else
-- Decrementar contador de campos
free := free - 1;
if ram_data_out(3 downto 0) = "0000" then
-- Inicializa o SAm
stack_mode <= "01";
stack_data_in <= "000" & ram_addr;
st <= S_SAmPush;
end if;
end if;
end if;
---------------------------------------------------------------------------
--
--
-- SAm
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- SAm Push
---------------------------------------------------------------------------
when S_SAmPush =>
-- Aguarda a atualizacao da pilha
st <= S_SAmProc;
---------------------------------------------------------------------------
-- SAm Process
---------------------------------------------------------------------------
when S_SAmProc =>
if stack_empty = '1' then
-- Fim do processo de abertura recursiva
st <= S_MW;
else
st <= S_SAmUpdate;
-- Calcula o endereco do proximo elemento a ser empilhado
-- relativo ao elemento atual e seu contador na pilha
case stack_data_out(13 downto 11) is
when "000" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0));
when "001" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0) + 1);
when "010" => ram_addr <= (stack_data_out(10 downto 6)) &
(stack_data_out(5 downto 0) + 1);
when "011" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0) + 1);
when "100" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0));
when "101" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0) - 1);
when "110" => ram_addr <= (stack_data_out(10 downto 6)) &
(stack_data_out(5 downto 0) - 1);
when "111" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0) - 1);
end case;
if stack_data_out(13 downto 11) = "111" then
-- Remove o elemento atual da pilha ao percorrer todos
-- os elementos a sua volta
stack_mode <= "10";
else
-- Sobrescreve o elemento atual na pilha com o novo
-- contador de direcao
stack_mode <= "11";
stack_data_in <= (stack_data_out(13 downto 11) + 1) &
stack_data_out(10 downto 0);
end if;
end if;
---------------------------------------------------------------------------
-- SAm Update
---------------------------------------------------------------------------
when S_SAmUpdate =>
-- Aguarda a atualizacao da pilha (contador atual)
-- e a RAM (informacao sobre o elemento vizinho)
st <= S_SAmOpen;
---------------------------------------------------------------------------
-- SAm Open and Stack
---------------------------------------------------------------------------
when S_SAmOpen =>
st <= S_SAmPush;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5 downto 4) = "00" then
-- Decrementa contador de campos
free := free - 1;
-- Abre o elemento vizinho se for valido
ram_wren <= '1';
ram_data_in(5) <= '1';
ram_data_in(7 downto 6) <= ram_data_out(7 downto 6);
ram_data_in(4 downto 0) <= ram_data_out(4 downto 0);
if ram_data_out(3 downto 0) = "0000" then
-- Empilha o elemento vizinho se for vazio para
-- continuar a abrir os vizinhos dos outros
-- elementos vazios
stack_mode <= "01";
stack_data_in <= "000" & ram_addr;
end if;
end if;
---------------------------------------------------------------------------
--
--
-- Estado Final
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Fim do jogo
---------------------------------------------------------------------------
when S_GameOver =>
st <= S_GameOver;
-- Para a contagem de pontos
if game_state = "11" then
flagcnt <= (others => '0');
end if;
timer_enable <= '0';
---------------------------------------------------------------------------
-- ?
---------------------------------------------------------------------------
when others =>
st <= S_0;
end case;
end if;
end process;
end;
| gpl-2.0 | a053c2972c7b37cdaf2d9d3fe865c450 | 0.339705 | 4.099127 | false | false | false | false |
Caian/Minesweeper | Projeto/decoder.vhd | 1 | 986 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoder is
port( entrada : in std_logic_vector(10 downto 0);
digito1 : out std_logic_vector(3 downto 0);
digito2 : out std_logic_vector(3 downto 0);
digito3 : out std_logic_vector(3 downto 0)
);
end;
architecture logica of decoder is
signal temp : std_logic_vector(10 downto 0);
begin
temp <= (others => '0') when (to_integer(signed(entrada)) < 0) else entrada;
digito1 <= std_logic_vector(to_unsigned(to_integer(unsigned(temp))/100,4));
digito2 <= std_logic_vector(to_unsigned(((to_integer(unsigned(temp)) rem 100)-(to_integer(unsigned(temp)) rem 10))/10,4));
digito3 <= std_logic_vector(to_unsigned(to_integer(unsigned(temp)) rem 10,4));
end architecture;
| gpl-2.0 | 9f4a94b78b027d5e095a93d50f0a1ea2 | 0.603448 | 3.43554 | false | false | false | false |
caiopo/mips-multiciclo | src/ula.vhd | 1 | 1,665 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ula is
generic(largura: natural := 8);
port(
entradaA, entradaB: in std_logic_vector(largura-1 downto 0);
Operacao: in std_logic_vector(2 downto 0);
saida: out std_logic_vector(largura-1 downto 0);
zero: out std_logic
);
end entity;
architecture comportamental of ula is
component somadorSubtrador is
generic(largura: natural := 8);
port(
entradaA, entradaB: in std_logic_vector(largura-1 downto 0);
carryIn: in std_logic;
saida: out std_logic_vector(largura-1 downto 0)
);
end component;
signal saidaSignal, andOr, addSub, slt: std_logic_vector(largura-1 downto 0);
begin
somadorSubtrator: somadorSubtrador generic map (largura)
port map(entradaA, entradaB, Operacao(2), addSub);
andOr <= entradaA and entradaB when Operacao(0)='0' else
entradaA or entradaB;
slt <= (0 => '1', others => '0') when signed(entradaA) < signed(entradaB) else (others => '0');
saidaSignal <= slt when Operacao="111" else
andOr when Operacao(1)='0' else
addSub;
zero <= '1' when saidaSignal=(largura => '0') else '0';
saida <= saidaSignal;
end architecture; | mit | 0d5776a2cb6be7827424c602c0ea9299 | 0.604204 | 3.691796 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_basic_pat_gen.vhd | 1 | 16,610 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_basic_pat_gen.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module allows either a user side loopback, with address swapping,
-- OR the generation of simple packets. The selection being controlled by a top level input
-- which can be sourced fdrom a DIP switch in hardware.
-- The packet generation is controlled by simple parameters giving the ability to set the DA,
-- SA amd max/min size packets. The data portion of each packet is always a simple
-- incrementing pattern.
-- When configured to loopback the first 12 bytes of the packet are accepted and then the
-- packet is output with/without address swapping. Currently, this is hard wired in the address
-- swap logic.
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_basic_pat_gen is
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
check_resetn : in std_logic;
enable_pat_gen : in std_logic;
enable_pat_chk : in std_logic;
enable_address_swap : in std_logic;
speed : in std_logic_vector(1 downto 0);
-- data from the RX data path
rx_axis_tdata : in std_logic_vector(7 downto 0);
rx_axis_tvalid : in std_logic;
rx_axis_tlast : in std_logic;
rx_axis_tuser : in std_logic;
rx_axis_tready : out std_logic;
-- data TO the TX data path
tx_axis_tdata : out std_logic_vector(7 downto 0);
tx_axis_tvalid : out std_logic;
tx_axis_tlast : out std_logic;
tx_axis_tready : in std_logic;
frame_error : out std_logic;
activity_flash : out std_logic
);
end tri_mode_ethernet_mac_0_basic_pat_gen;
architecture rtl of tri_mode_ethernet_mac_0_basic_pat_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
------------------------------------------------------------------------------
-- Component Declaration for the tri_mode_ethernet_mac_0_axi_pipe
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_pipe
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
rx_axis_fifo_tdata_in : in std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid_in : in std_logic;
rx_axis_fifo_tlast_in : in std_logic;
rx_axis_fifo_tready_in : out std_logic;
rx_axis_fifo_tdata_out : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid_out : out std_logic;
rx_axis_fifo_tlast_out : out std_logic;
rx_axis_fifo_tready_out : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the tri_mode_ethernet_mac_0_axi_mux
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_mux
port (
mux_select : in std_logic;
-- mux inputs
tdata0 : in std_logic_vector(7 downto 0);
tvalid0 : in std_logic;
tlast0 : in std_logic;
tready0 : out std_logic;
tdata1 : in std_logic_vector(7 downto 0);
tvalid1 : in std_logic;
tlast1 : in std_logic;
tready1 : out std_logic;
-- mux outputs
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the tri_mode_ethernet_mac_0_axi_pat_gen
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_pat_gen
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_pat_gen : in std_logic;
speed : in std_logic_vector(1 downto 0);
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the tri_mode_ethernet_mac_0_axi_pat_check
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_pat_check
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_pat_chk : in std_logic;
speed : in std_logic_vector(1 downto 0);
tdata : in std_logic_vector(7 downto 0);
tvalid : in std_logic;
tlast : in std_logic;
tready : in std_logic;
tuser : in std_logic;
frame_error : out std_logic;
activity_flash : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the tri_mode_ethernet_mac_0_address_swap
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_address_swap
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_address_swap : in std_logic;
-- data from the RX FIFO
rx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : in std_logic;
rx_axis_fifo_tlast : in std_logic;
rx_axis_fifo_tready : out std_logic;
-- data TO the tx fifo
tx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : out std_logic;
tx_axis_fifo_tlast : out std_logic;
tx_axis_fifo_tready : in std_logic
);
end component;
signal rx_axis_fifo_tdata_int : std_logic_vector(7 downto 0);
signal rx_axis_fifo_tvalid_int : std_logic;
signal rx_axis_fifo_tlast_int : std_logic;
signal rx_axis_fifo_tready_int : std_logic;
signal rx_axis_tready_lcl : std_logic;
signal pat_gen_tdata : std_logic_vector(7 downto 0);
signal pat_gen_tvalid : std_logic;
signal pat_gen_tlast : std_logic;
signal pat_gen_tready : std_logic;
signal pat_gen_tready_int : std_logic;
signal mux_tdata : std_logic_vector(7 downto 0);
signal mux_tvalid : std_logic;
signal mux_tlast : std_logic;
signal mux_tready : std_logic;
signal tx_axis_as_tdata : std_logic_vector(7 downto 0);
signal tx_axis_as_tvalid : std_logic;
signal tx_axis_as_tlast : std_logic;
signal tx_axis_as_tready : std_logic;
begin
rx_axis_tready <= rx_axis_tready_lcl;
tx_axis_tdata <= tx_axis_as_tdata;
tx_axis_tvalid <= tx_axis_as_tvalid;
tx_axis_tlast <= tx_axis_as_tlast;
tx_axis_as_tready <= tx_axis_tready;
pat_gen_tready <= pat_gen_tready_int;
-- basic packet generator - this has parametisable
-- DA and SA fields but the LT and data will be auto-generated
-- based on the min/max size parameters - these can be set
-- to the same value to obtain a specific packet size or will
-- increment from the lower packet size to the upper
axi_pat_gen_inst : tri_mode_ethernet_mac_0_axi_pat_gen
generic map (
DEST_ADDR => DEST_ADDR,
SRC_ADDR => SRC_ADDR,
MAX_SIZE => MAX_SIZE,
MIN_SIZE => MIN_SIZE,
ENABLE_VLAN => ENABLE_VLAN,
VLAN_ID => VLAN_ID,
VLAN_PRIORITY => VLAN_PRIORITY
)
port map (
axi_tclk => axi_tclk,
axi_tresetn => axi_tresetn,
enable_pat_gen => enable_pat_gen,
speed => speed,
tdata => pat_gen_tdata,
tvalid => pat_gen_tvalid,
tlast => pat_gen_tlast,
tready => pat_gen_tready
);
axi_pat_check_inst: tri_mode_ethernet_mac_0_axi_pat_check
generic map (
DEST_ADDR => DEST_ADDR,
SRC_ADDR => SRC_ADDR,
MAX_SIZE => MAX_SIZE,
MIN_SIZE => MIN_SIZE,
ENABLE_VLAN => ENABLE_VLAN,
VLAN_ID => VLAN_ID,
VLAN_PRIORITY => VLAN_PRIORITY
)
port map (
axi_tclk => axi_tclk,
axi_tresetn => check_resetn,
enable_pat_chk => enable_pat_chk,
speed => speed,
tdata => rx_axis_tdata,
tvalid => rx_axis_tvalid,
tlast => rx_axis_tlast,
tready => rx_axis_tready_lcl,
tuser => rx_axis_tuser,
frame_error => frame_error,
activity_flash => activity_flash
);
-- simple mux between the rx_fifo AXI interface and the pat gen output
-- this is not registered as it is passed through a pipeline stage to limit the impact
axi_mux_inst : tri_mode_ethernet_mac_0_axi_mux
port map (
mux_select => enable_pat_gen,
tdata0 => rx_axis_tdata,
tvalid0 => rx_axis_tvalid,
tlast0 => rx_axis_tlast,
tready0 => rx_axis_tready_lcl,
tdata1 => pat_gen_tdata,
tvalid1 => pat_gen_tvalid,
tlast1 => pat_gen_tlast,
tready1 => pat_gen_tready_int,
tdata => mux_tdata,
tvalid => mux_tvalid,
tlast => mux_tlast,
tready => mux_tready
);
-- a pipeline stage has been added to reduce timing issues and allow
-- a pattern generator to be muxed into the path
axi_pipe_inst : tri_mode_ethernet_mac_0_axi_pipe
port map (
axi_tclk => axi_tclk,
axi_tresetn => axi_tresetn,
rx_axis_fifo_tdata_in => mux_tdata,
rx_axis_fifo_tvalid_in => mux_tvalid,
rx_axis_fifo_tlast_in => mux_tlast,
rx_axis_fifo_tready_in => mux_tready,
rx_axis_fifo_tdata_out => rx_axis_fifo_tdata_int,
rx_axis_fifo_tvalid_out => rx_axis_fifo_tvalid_int,
rx_axis_fifo_tlast_out => rx_axis_fifo_tlast_int,
rx_axis_fifo_tready_out => rx_axis_fifo_tready_int
);
-- address swap module: based around a Dual port distributed ram
-- data is written in and the read only starts once the da/sa have been
-- stored. Can cope with a gap of one cycle between packets.
address_swap_inst : tri_mode_ethernet_mac_0_address_swap
port map (
axi_tclk => axi_tclk,
axi_tresetn => axi_tresetn,
enable_address_swap => enable_address_swap,
rx_axis_fifo_tdata => rx_axis_fifo_tdata_int,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid_int,
rx_axis_fifo_tlast => rx_axis_fifo_tlast_int,
rx_axis_fifo_tready => rx_axis_fifo_tready_int,
tx_axis_fifo_tdata => tx_axis_as_tdata,
tx_axis_fifo_tvalid => tx_axis_as_tvalid,
tx_axis_fifo_tlast => tx_axis_as_tlast,
tx_axis_fifo_tready => tx_axis_as_tready
);
end rtl;
| mit | 430bd15cb208e50094dbc8e77a8b87cd | 0.509693 | 4.215736 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s4/mealy/mealy.vhd | 1 | 1,176 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 29-02-2016
-- Module Name: mealy.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mealy is
port (d, clk, reset : in std_logic;
z : out std_logic);
end entity mealy;
architecture arch_mealy of mealy is
type state is (S0, S1, S2, S3);
signal current : state := S0;
begin
process (clk, reset)
begin
if reset = '1' then
current <= S0;
end if;
if clk = '1' and clk'event then
case current is
when S0 =>
if d = '0' then
current <= S0;
else
current <= S1;
end if;
when S1 =>
if d = '0' then
current <= S2;
else
current <= S0;
end if;
when S2 =>
if d = '1' then
current <= S3;
else
current <= S0;
end if;
when S3 =>
if d = '0' then
current <= S2;
else
current <= S1;
end if;
end case;
end if;
end process;
z <= '1' when current = S3 and d = '1' else '0';
end architecture arch_mealy;
| gpl-3.0 | 45b740e0d3579007a99888464673e68c | 0.47449 | 3.152815 | false | false | false | false |
caiopo/mips-multiciclo | src/registrador.vhd | 1 | 971 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity registrador is
generic(largura: natural := 8);
port(
clock, reset: in std_logic;
en: in std_logic;
d: in std_logic_vector(largura-1 downto 0);
q: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of registrador is
begin
process(clock, reset)
begin
if reset='1' then
q <= (others => '0');
elsif rising_edge(clock) and en = '1' then
q <= d;
end if;
end process;
end architecture;
| mit | fe66a8c3566f4af5c203c2b366b80f5c | 0.533471 | 3.792969 | false | false | false | false |
gihankarunarathne/vhdl-learn | tute_I/Tutorial_I/Four_MUX.vhd | 1 | 1,228 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Four_MUX is
Port (
D0 : in STD_LOGIC_VECTOR (3 downto 0);
S0 : in STD_LOGIC_VECTOR (1 downto 0);
D1 : in STD_LOGIC_VECTOR (3 downto 0);
S1 : in STD_LOGIC_VECTOR (1 downto 0);
D2 : in STD_LOGIC_VECTOR (3 downto 0);
S2 : in STD_LOGIC_VECTOR (1 downto 0);
D3 : in STD_LOGIC_VECTOR (3 downto 0);
S3 : in STD_LOGIC_VECTOR (1 downto 0);
D4 : in STD_LOGIC_VECTOR (3 downto 0);
S4 : in STD_LOGIC_VECTOR (1 downto 0);
Z : out STD_LOGIC;
Z0 : inout STD_LOGIC_VECTOR (3 downto 0)
);
end Four_MUX;
architecture Behavioral of Four_MUX is
begin
Z0(0) <= D0(0) when S0="00" else
D0(1) when S0="01" else
D0(2) when S0="10" else
D0(3);
Z0(1) <= D1(0) when S1="00" else
D1(1) when S1="01" else
D1(2) when S1="10" else
D1(3);
Z0(2) <= D2(0) when S2="00" else
D2(1) when S2="01" else
D2(2) when S2="10" else
D2(3);
Z0(3) <= D3(0) when S3="00" else
D3(1) when S3="01" else
D3(2) when S3="10" else
D3(3);
Z <= Z0(0) when S4="00" else
Z0(1) when S4="01" else
Z0(2) when S4="10" else
Z0(3);
end Behavioral;
| mit | 362e507527ef8e7d5712c137d73c380d | 0.54316 | 2.490872 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/fnImportLog2/package0.vhd | 1 | 604 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package package0 is
-- Roundup logarithm with base 2 (first x that 2^x is larger or equal to given number)
function log2 (n : integer) return integer;
end package0;
package body package0 is
function log2 (n : integer) return integer is
variable a, m : integer;
begin
if (n = 1) then
return 0;
end if;
a := 0;
m := 1;
while m < n loop
a := a + 1;
m := m * 2;
end loop;
return a;
end function;
end package0;
| mit | e8fa5a10c0ee0e382adc47aa550d2358 | 0.600993 | 3.393258 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup.vhd | 2 | 14,302 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 12:06:03
-- Design Name: rx_path_lookup.vhd
-- Module Name: rx_path_lookup - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- this module handles the frame lookup
-- according to the header input the output ports for each frame are searched for in the lookup memory
-- the lookup memory constists of one base configuration, frame confiugrations and one default configuration
-- - base configuration gives the entry to the frame configuration
-- - frame configurations returns a one-hot-encoded output ports vector for each valid mac destination address
-- and the priority of the frame
-- - for mac address not in the lookup table the default configuration decides whether to skip this frame or
-- to send it to default output ports
-- transmitting the frame on the receiving port is prevented by setting the corresponding bit in the ports vector to '0'
--
-- for more details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
-- for more detail on the lookup module see switch_port_rxpath_lookup.svg
--
-- base_address is an internal register pointing to the base configuration; lateron it has to be connected to a processor
-- the housekeeping processor also has to take care of writing all the configurations to the lookup memory
-- thereby, an overflow of the memory address space of the binary list must not happen as no overflow control is
-- implemented in the lookup algorithm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_lookup is
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
-- lookup memory address constants
LOWER_ADDR_START : integer := 20;
UPPER_ADDR_START : integer := 40;
DEF_ADDR_START : integer := 0;
ENABLE_START : integer := 63;
PORTS_START : integer := 60;
PRIO_START : integer := 48;
SKIP_FRAME_START : integer := 0;
DEST_MAC_START : integer := 0
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end rx_path_lookup;
architecture rtl of rx_path_lookup is
-- determine the next search address (median) of the binary search
-- upper and lower are the corresponding border memory adresses of the remaining search space
-- return value median = (upper + lower) / 2
function upper_add_lower_by2_f (upper, lower : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0))
return std_logic_vector is
variable x1 : integer;
variable x2 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH downto 0);
variable x3 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
x1 := to_integer(unsigned(upper)) + to_integer(unsigned(lower));
x2 := std_logic_vector(to_unsigned(x1,x2'length));
x3 := x2(LOOKUP_MEM_ADDR_WIDTH downto 1);
return x3;
end upper_add_lower_by2_f;
-- lookup state machine
type state is (
IDLE,
READ_BASE,
LOOKUP,
READ_DEFAULT
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal read_header_sig : std_logic := '0';
signal read_base_sig : std_logic := '0';
signal read_default_sig : std_logic := '0';
signal lookup_valid_sig : std_logic := '0';
signal read_lookup_sig : std_logic := '0';
signal update_sig : std_logic := '0';
signal lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
-- process registers
signal dest_mac_reg : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
signal vlan_enable_reg : std_logic;
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lower_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal default_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal skip_frame_reg : std_logic;
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- alias signals for memory read access
signal mem_lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_default_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_lookup_enable_sig : std_logic;
signal mem_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal mem_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_skip_frame_sig : std_logic;
signal mem_dest_mac_sig : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
-- internal registers (to be connected to the outside, e.g. housekeeping processor)
signal base_address : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0) := "000000000";
begin
-- alias names (signals) for lookup memory output ranges
mem_lower_sig <= mem_data(LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto LOWER_ADDR_START);
mem_upper_sig <= mem_data(UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto UPPER_ADDR_START);
mem_default_sig <= mem_data(DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto DEF_ADDR_START);
mem_lookup_enable_sig <= mem_data(ENABLE_START);
mem_ports_sig <= mem_data(PORTS_START+NR_PORTS-1 downto PORTS_START);
mem_prio_sig <= mem_data(PRIO_START+VLAN_PRIO_WIDTH-1 downto PRIO_START);
mem_skip_frame_sig <= mem_data(SKIP_FRAME_START);
mem_dest_mac_sig <= mem_data(DEST_MAC_START+DEST_MAC_WIDTH-1 downto DEST_MAC_START);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, lookup_in_valid, mem_lookup_enable_sig, mem_default_sig,
BASE_ADDRESS, median_sig, upper_reg, lower_reg, median_reg, default_reg, dest_mac_reg,
mem_dest_mac_sig, mem_upper_sig, mem_lower_sig)
begin
-- default signal assignments
nxt_state <= IDLE;
read_header_sig <= '0'; -- read_header_p
read_base_sig <= '0'; -- write_internal_registers_p
read_default_sig <= '0'; -- output_reg_p
lookup_valid_sig <= '0'; -- output_valid_p
read_lookup_sig <= '0'; -- output_reg_p
update_sig <= '0'; -- write_internal_registers_p
upper_sig <= (others => '0'); -- upper_add_lower_by2_f
lower_sig <= (others => '0'); -- upper_add_lower_by2_f
-- default output values
mem_enable <= '0';
mem_addr <= (others => '1');
case cur_state is
when IDLE => -- waiting for a new header
if lookup_in_valid = '1' then
nxt_state <= READ_BASE;
read_header_sig <= '1'; -- read_header_p
mem_enable <= '1';
mem_addr <= BASE_ADDRESS;
end if;
when READ_BASE => -- read base address, determine if lookup is enabled
read_base_sig <= '1'; -- internal_reg_p
mem_enable <= '1';
if mem_lookup_enable_sig = '0' then -- lookup disabled, read default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= mem_default_sig;
else -- lookup enabled, search for address in the middle of binary lookup list
nxt_state <= LOOKUP;
upper_sig <= mem_upper_sig; -- upper_add_lower_by2_f
lower_sig <= mem_lower_sig; -- upper_add_lower_by2_f
mem_addr <= median_sig; -- upper_add_lower_by2_f
end if;
when LOOKUP => -- lookup the median memory address and check if the memory mac address matches the frame mac address
if dest_mac_reg = mem_dest_mac_sig then -- MAC ADDRESS found -> Algorithm terminates
nxt_state <= IDLE;
read_lookup_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
elsif upper_reg <= lower_reg then -- MAC ADDRESS not found -> Algorithm terminats with default configuration
nxt_state <= READ_DEFAULT;
mem_addr <= default_reg;
mem_enable <= '1';
else -- MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= '1'; -- internal_reg_p
mem_addr <= median_sig; -- upper_add_lower_by2_f
mem_enable <= '1';
nxt_state <= LOOKUP;
if dest_mac_reg > mem_dest_mac_sig then
upper_sig <= upper_reg; -- upper_add_lower_by2_f
lower_sig <= median_reg + 1; -- upper_add_lower_by2_f
else -- dest_mac_reg < mem_dest_mac_sig
upper_sig <= median_reg - 1; -- upper_add_lower_by2_f
lower_sig <= lower_reg; -- upper_add_lower_by2_f
end if;
end if;
when READ_DEFAULT =>
nxt_state <= IDLE;
read_default_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
end case;
end process;
-- handshake protocol to read header from previous module and store header into internal buffer
read_header_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_mac_reg <= (others => '0');
vlan_enable_reg <= '0';
vlan_prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
lookup_in_ready <= '0';
else
dest_mac_reg <= dest_mac_reg;
vlan_enable_reg <= vlan_enable_reg;
vlan_prio_reg <= vlan_prio_reg;
timestamp_reg <= timestamp_reg;
lookup_in_ready <= '0';
if read_header_sig = '1' then
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= '1';
end if;
end if;
end if;
end process;
-- handles access to the internal registers needed for lookup
internal_reg_p : process (clk) -- to be done
begin
if clk'event and clk = '1' then
if reset = '1' then
lower_reg <= (others => '0');
upper_reg <= (others => '0');
default_reg <= (others => '0');
median_reg <= (others => '0');
else
lower_reg <= lower_reg;
upper_reg <= upper_reg;
default_reg <= default_reg;
median_reg <= median_reg;
if read_base_sig = '1' then -- read inital values from base configuration
lower_reg <= mem_lower_sig;
upper_reg <= mem_upper_sig;
default_reg <= mem_default_sig;
median_reg <= median_sig;
elsif update_sig = '1' then -- update registers according to remaining search space
lower_reg <= lower_sig;
upper_reg <= upper_sig;
median_reg <= median_sig;
end if;
end if;
end if;
end process;
-- assign next memory search address: median address in the remaining address search space
median_sig <= upper_add_lower_by2_f(upper_sig, lower_sig);
-- updates the output value registers (ports, priority and skip)
output_reg_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
ports_reg <= (others => '0');
prio_reg <= (others => '0');
skip_frame_reg <= '0';
else
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if read_default_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0';
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= mem_skip_frame_sig;
elsif read_lookup_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0'; -- comment for loopback functionality
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= '0';
end if;
end if;
end if;
end process;
-- sets the output valid bit
output_valid_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
lookup_out_valid <= '0';
else
lookup_out_valid <= '0';
if lookup_valid_sig = '1' then
lookup_out_valid <= '1';
end if;
end if;
end if;
end process;
-- other outputs
lookup_out_ports <= ports_reg;
lookup_out_prio <= prio_reg;
lookup_out_skip <= skip_frame_reg;
lookup_out_timestamp <= timestamp_reg;
end rtl;
| mit | 44cf659b7148fabbe49b46f8c4795afb | 0.619354 | 3.351769 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/tx_path_output_queue.vhd | 2 | 17,817 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 09.12.2013 16:11:09
-- Design Name:
-- Module Name: tx_path_output_queue - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: The output queue module accepts frames from the switching fabric
-- and forwards them to the transmitter side of the MAC
--
-- This module consists of 5 submodules:
-- oq_control: receives data from switching fabric and stores them in the memory and fifo
-- oq_memory: contains the frame data
-- oq_fifo: contains the memory start address of the corresponding frame as well as its length and arriving timestamp
-- priority fifo can be selected
-- oq_mem_check: checks if another frame can be accepted from the switching fabric based on
-- the status of the fifo and memory
-- oq_arbitration: as soon as the MAC is ready, the next frame will be read from the memory and
-- forwarded to the MAC
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_path_output_queue is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer := 12; -- 8 bit: 14, 32 bit: 12
OQ_MEM_ADDR_WIDTH_B : integer := 14
);
Port (
clk : in std_logic;
reset : in std_logic;
-- tx_path interface to fabric
oq_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oq_in_valid : in std_logic;
oq_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oq_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oq_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_in_req : in std_logic;
oq_in_accept_frame : out std_logic;
-- timestamp
oq_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oq_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
oq_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oq_out_valid : out std_logic;
oq_out_ready : in std_logic;
oq_out_last : out std_logic
);
end tx_path_output_queue;
architecture structural of tx_path_output_queue is
constant OQ_FIFO_DATA_WIDTH : integer := OQ_MEM_ADDR_WIDTH_B + TIMESTAMP_WIDTH + FRAME_LENGTH_WIDTH;
constant OQ_FIFO_LENGTH_START : integer := 0;
constant OQ_FIFO_TIMESTAMP_START : integer := OQ_FIFO_LENGTH_START + FRAME_LENGTH_WIDTH;
constant OQ_FIFO_MEM_PTR_START : integer := OQ_FIFO_TIMESTAMP_START + TIMESTAMP_WIDTH;
constant FABRIC2TRANSMITTER_DATA_WIDTH_RATIO : integer := FABRIC_DATA_WIDTH / TRANSMITTER_DATA_WIDTH;
component output_queue_control
Generic (
FABRIC_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_FIFO_DATA_WIDTH : integer;
FABRIC2TRANSMITTER_DATA_WIDTH_RATIO : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fabric
oqctrl_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oqctrl_in_valid : in std_logic;
oqctrl_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oqctrl_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqctrl_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface memory check
oqctrl_out_mem_wr_addr : out std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_B-1 downto 0);
-- output interface memory
oqctrl_out_mem_wenable : out std_logic;
oqctrl_out_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqctrl_out_mem_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- output interface fifo
oqctrl_out_fifo_wenable : out std_logic;
oqctrl_out_fifo_data : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqctrl_out_fifo_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0)
);
end component;
component output_queue_memory
Generic (
NR_OQ_MEM : integer;
VLAN_PRIO_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_MEM_DATA_WIDTH_IN : integer;
OQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
--Port A -> control module
oqmem_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqmem_in_wenable : in std_logic_vector;
oqmem_in_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqmem_in_data : in std_logic_vector(OQ_MEM_DATA_WIDTH_IN-1 downto 0);
oqmem_in_clk : in std_logic;
--Port B -> arbitration module -> mac
oqmem_out_rd_prio : in std_logic;
oqmem_out_enable : in std_logic;
oqmem_out_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
oqmem_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_MEM_DATA_WIDTH_OUT-1 downto 0);
oqmem_out_clk : in std_logic
);
end component;
component output_queue_fifo
Generic (
OQ_FIFO_DATA_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
oqfifo_in_enable : in std_logic;
oqfifo_in_data : in std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqfifo_out_enable : in std_logic;
oqfifo_out_data : out std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
oqfifo_out_rd_prio : in std_logic;
oqfifo_out_full : out std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqfifo_out_empty : out std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end component;
component output_queue_mem_check
Generic (
OQ_FIFO_DATA_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_MEM_PTR_START : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
req : in std_logic;
req_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
req_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
accept_frame : out std_logic;
mem_wr_ptr : in std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH-1 downto 0);
fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
fifo_full : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end component;
component output_queue_arbitration
Generic (
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_DATA_WIDTH : integer;
OQ_FIFO_LENGTH_START : integer;
OQ_FIFO_TIMESTAMP_START : integer;
OQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fifo
oqarb_in_fifo_enable : out std_logic;
oqarb_in_fifo_prio : out std_logic;
oqarb_in_fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
oqarb_in_fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
-- timestamp
oqarb_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
oqarb_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- input interface memory
oqarb_in_mem_data : in std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_in_mem_enable : out std_logic;
oqarb_in_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
oqarb_in_mem_prio : out std_logic;
-- output interface mac
oqarb_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
oqarb_out_valid : out std_logic;
oqarb_out_last : out std_logic;
oqarb_out_ready : in std_logic
);
end component;
signal oqctrl2oqmem_data : std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
signal oqctrl2oqmem_wenable : std_logic_vector(0 downto 0);
signal oqctrl2oqmem_addr : std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal oqctrl2oqfifo_wenable : std_logic;
signal oqctrl2oqfifo_data : std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
signal oqctrl2oqfifo_prio : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal oqmem2oqarb_enable : std_logic;
signal oqmem2oqarb_prio : std_logic;
signal oqmem2oqarb_addr : std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
signal oqmem2oqarb_data : std_logic_vector(NR_OQ_FIFOS*TRANSMITTER_DATA_WIDTH-1 downto 0);
signal oqfifo2oqarb_data : std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
signal oqfifo2oqarb_enable : std_logic;
signal oqfifo2oqarb_empty : std_logic_vector(NR_OQ_FIFOS-1 downto 0);
signal oqfifo2oqarb_prio : std_logic;
signal oqctrl2oqchk_mem_wr_addr : std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_B-1 downto 0);
signal oqfifo2oqchk_full : std_logic_vector(NR_OQ_FIFOS-1 downto 0);
-- attribute mark_debug : string;
-- attribute mark_debug of oqctrl2oqmem_data: signal is "true";
-- attribute mark_debug of oqctrl2oqmem_wenable: signal is "true";
-- attribute mark_debug of oqctrl2oqmem_addr: signal is "true";
-- attribute mark_debug of oqctrl2oqfifo_data: signal is "true";
-- attribute mark_debug of oqmem2oqarb_enable: signal is "true";
-- attribute mark_debug of oqmem2oqarb_addr: signal is "true";
-- attribute mark_debug of oqmem2oqarb_data: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_data: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_enable: signal is "true";
-- attribute mark_debug of oqfifo2oqarb_empty: signal is "true";
-- attribute mark_debug of oqctrl2oqchk_mem_wr_addr: signal is "true";
-- attribute mark_debug of oqfifo2oqchk_full: signal is "true";
begin
oq_control : output_queue_control
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
OQ_MEM_ADDR_WIDTH_A => OQ_MEM_ADDR_WIDTH_A,
OQ_MEM_ADDR_WIDTH_B => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
FABRIC2TRANSMITTER_DATA_WIDTH_RATIO => FABRIC2TRANSMITTER_DATA_WIDTH_RATIO
)
Port map(
clk => clk,
reset => reset,
-- input interface fabric
oqctrl_in_data => oq_in_data,
oqctrl_in_valid => oq_in_valid,
oqctrl_in_length => oq_in_length,
oqctrl_in_prio => oq_in_prio,
oqctrl_in_timestamp => oq_in_timestamp,
-- output interface memory check
oqctrl_out_mem_wr_addr => oqctrl2oqchk_mem_wr_addr,
-- output interface memory
oqctrl_out_mem_wenable => oqctrl2oqmem_wenable(0),
oqctrl_out_mem_addr => oqctrl2oqmem_addr,
oqctrl_out_mem_data => oqctrl2oqmem_data,
-- output interface fifo
oqctrl_out_fifo_wenable => oqctrl2oqfifo_wenable,
oqctrl_out_fifo_data => oqctrl2oqfifo_data,
oqctrl_out_fifo_prio => oqctrl2oqfifo_prio
);
oq_mem : output_queue_memory
Generic map(
NR_OQ_MEM => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
OQ_MEM_ADDR_WIDTH_A => OQ_MEM_ADDR_WIDTH_A,
OQ_MEM_ADDR_WIDTH_B => OQ_MEM_ADDR_WIDTH_B,
OQ_MEM_DATA_WIDTH_IN => FABRIC_DATA_WIDTH,
OQ_MEM_DATA_WIDTH_OUT => TRANSMITTER_DATA_WIDTH
)
Port map(
--Port A -> Control module
oqmem_in_wr_prio => oq_in_prio,
oqmem_in_wenable => oqctrl2oqmem_wenable,
oqmem_in_addr => oqctrl2oqmem_addr,
oqmem_in_data => oqctrl2oqmem_data,
oqmem_in_clk => clk,
--Port B -> Scheduling moudle
oqmem_out_rd_prio => oqmem2oqarb_prio,
oqmem_out_enable => oqmem2oqarb_enable,
oqmem_out_addr => oqmem2oqarb_addr,
oqmem_out_data => oqmem2oqarb_data,
oqmem_out_clk => clk
);
oq_fifo : output_queue_fifo
Generic map(
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
oqfifo_in_enable => oqctrl2oqfifo_wenable,
oqfifo_in_data => oqctrl2oqfifo_data,
oqfifo_in_wr_prio => oqctrl2oqfifo_prio,
oqfifo_out_enable => oqfifo2oqarb_enable,
oqfifo_out_data => oqfifo2oqarb_data,
oqfifo_out_rd_prio => oqfifo2oqarb_prio,
oqfifo_out_full => oqfifo2oqchk_full,
oqfifo_out_empty => oqfifo2oqarb_empty
);
oq_mem_check : output_queue_mem_check
Generic map(
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
OQ_MEM_ADDR_WIDTH => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_MEM_PTR_START => OQ_FIFO_MEM_PTR_START,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
req => oq_in_req,
req_length => oq_in_length,
req_prio => oq_in_prio,
accept_frame => oq_in_accept_frame,
mem_wr_ptr => oqctrl2oqchk_mem_wr_addr,
fifo_data => oqfifo2oqarb_data,
fifo_full => oqfifo2oqchk_full,
fifo_empty => oqfifo2oqarb_empty
);
oq_arbitration : output_queue_arbitration
Generic map(
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
OQ_MEM_ADDR_WIDTH => OQ_MEM_ADDR_WIDTH_B,
OQ_FIFO_DATA_WIDTH => OQ_FIFO_DATA_WIDTH,
OQ_FIFO_LENGTH_START => OQ_FIFO_LENGTH_START,
OQ_FIFO_TIMESTAMP_START => OQ_FIFO_TIMESTAMP_START,
OQ_FIFO_MEM_PTR_START => OQ_FIFO_MEM_PTR_START
)
Port map(
clk => clk,
reset => reset,
-- input interface fifo
oqarb_in_fifo_enable => oqfifo2oqarb_enable,
oqarb_in_fifo_prio => oqfifo2oqarb_prio,
oqarb_in_fifo_empty => oqfifo2oqarb_empty,
oqarb_in_fifo_data => oqfifo2oqarb_data,
-- timestamp
oqarb_in_timestamp_cnt => oq_in_timestamp_cnt,
oqarb_out_latency => oq_out_latency,
-- input interface memory
oqarb_in_mem_data => oqmem2oqarb_data,
oqarb_in_mem_enable => oqmem2oqarb_enable,
oqarb_in_mem_addr => oqmem2oqarb_addr,
oqarb_in_mem_prio => oqmem2oqarb_prio,
-- output interface mac
oqarb_out_data => oq_out_data,
oqarb_out_valid => oq_out_valid,
oqarb_out_last => oq_out_last,
oqarb_out_ready => oq_out_ready
);
end structural;
| mit | 4a99c2ea8b645f6211f84cfb964cd716 | 0.550766 | 3.718848 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/DAQ_MEM/example_design/DAQ_MEM_exdes.vhd | 1 | 4,966 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DAQ_MEM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY DAQ_MEM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END DAQ_MEM_exdes;
ARCHITECTURE xilinx OF DAQ_MEM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT DAQ_MEM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : DAQ_MEM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-3.0 | 187574fdecc6bafa5a5780706d436eb0 | 0.556786 | 4.623836 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/fifo/tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd | 5 | 9,650 | --------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo;
architecture RTL of tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo is
component tri_mode_ethernet_mac_0_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component tri_mode_ethernet_mac_0_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : tri_mode_ethernet_mac_0_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : tri_mode_ethernet_mac_0_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
| mit | c9767c4d3d0ee152d280ca1b4c0f3144 | 0.56456 | 3.89899 | false | false | false | false |
titto-thomas/Pipeline_RISC | mux4to1.vhdl | 1 | 906 | --IITB RISC processor---
--Mux Module(4to1)---
-- author: Anakha
library ieee;
use ieee.std_logic_1164.all;
entity mux4to1 is
generic (
nbits : integer);
port (
input0, input1, input2, input3: in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel0, sel1 : in std_logic);
end mux4to1;
architecture behave of mux4to1 is
begin -- behave
process(input0,input1,input2,input3,sel0,sel1)
variable sel_var : std_logic_vector(1 downto 0);
begin
sel_var(0) := sel0;
sel_var(1) := sel1;
case sel_var is
when "00" =>
output <= input0 ;
when "01" =>
output <= input1;
when "10" =>
output <= input2;
when "11" =>
output <= input3;
when others =>
output <= "Z";
end case;
end process;
end behave ;
| gpl-2.0 | 1f1d48cc33fc0ecfc2800c47b2ad0dc2 | 0.550773 | 3.294545 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sim_1/imports/simulation/aeg_4ports_tb.vhd | 1 | 74,830 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 23.12.2013 11:23:15
-- Design Name:
-- Module Name: aeg_4ports_tb - tb
-- Project Name: automotive ethernet gateway
--
-- Description:
-- testbench for ethernet switch with 4 ports
-- user can select which ports are to be active receiving frames on the rx (input) side (PORT_ENABLED)
-- every port monitors all of its frames on the tx (output) side independetly of active input side
-- the frames are inserted to the rx side by the p_stimulus processes
-- the frames are checked at the tx side by the p_monitor processes for correct syntax
-- every port sends two different kinds of frames back-to-back and periodically
-- the user can select the destination addresses, frame lengths and iterations of the frames
-- the user has the choice to select an input queue priority fifo (NR_IQ_FIFOS = 2)
-- the user has the choice to select an output queue priority fifo (NR_OQ_FIFOS = 2)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
entity aeg_4ports_tb is
end aeg_4ports_tb;
architecture tb of aeg_4ports_tb is
-- aeg user constants
constant NR_PORTS : integer := 4; -- only four in this testbench
constant FABRIC_DATA_WIDTH : integer := 32; -- for other values, the memories and the constants of the address width have to be adjusted
-- input queue + output queue --> mem address width
-- input queue + output queue mem --> change ip data width
-- input queue control --> (de-)comment process at bottom accordingly
constant ARBITRATION : integer := 2; -- 1: Round Robin, 2: Priority based, 3: Latency based,
-- 4: Weighted prio/latency based, to do: 5: Fair Queuing
constant NR_IQ_FIFOS : integer := 2; -- [ 1, 2]
constant NR_OQ_FIFOS : integer := 2; -- [ 1, 2]
constant TIMESTAMP_WIDTH : integer := 64;
-- aeg fixed constants
constant GMII_DATA_WIDTH : integer := 8;
type frame_type is record
dest : std_logic_vector(7 downto 0); -- last byte of destination address
vlan_enable : boolean; -- indicates a vlan frame
vlan_prio : std_logic_vector(2 downto 0); -- vlan priority
frame_length : integer; -- length of the whole frame (including header)
iterations : integer; -- number of back to back transmissions of this frame
interframe_gap : integer; -- number of clock cycles between subsequent frames
end record;
type port_stimulus_type is record -- periodic stimulus of frames frame1 and frame2
frame1 : frame_type;
frame2 : frame_type;
iterations : integer;
end record;
-- aeg_tb stimuli 0123
constant PORT_ENABLED : std_logic_vector := "1111"; -- determines active ports receiving data
constant frame1_0 : frame_type := (
dest => x"01",
vlan_enable => false,
vlan_prio => "000",
frame_length => 64,
iterations => 1,
interframe_gap => 0);
constant frame2_0 : frame_type := (
dest => x"01",
vlan_enable => false,
vlan_prio => "000",
frame_length => 1024,
iterations => 0,
interframe_gap => 0);
constant stim0 : port_stimulus_type := (frame1_0, frame2_0, 1000);
constant frame1_1 : frame_type := (
dest => x"24",
vlan_enable => true,
vlan_prio => "001",
frame_length => 64,
iterations => 1,
interframe_gap => 168);
constant frame2_1 : frame_type := (
dest => x"28",
vlan_enable => false,
vlan_prio => "000",
frame_length => 500,
iterations => 1,
interframe_gap => 1040);
constant stim1 : port_stimulus_type := (frame1_1, frame2_1, 0);
constant frame1_2 : frame_type := (
dest => x"34",
vlan_enable => false,
vlan_prio => "000",
frame_length => 1518,
iterations => 1,
interframe_gap => 3076);
constant frame2_2 : frame_type := (
dest => x"38",
vlan_enable => false,
vlan_prio => "000",
frame_length => 64,
iterations => 0,
interframe_gap => 0);
constant stim2 : port_stimulus_type := (frame1_2, frame2_2, 0);
constant frame1_3 : frame_type := (
dest => x"44",
vlan_enable => true,
vlan_prio => "001",
frame_length => 200,
iterations => 1,
interframe_gap => 440);
constant frame2_3 : frame_type := (
dest => x"48",
vlan_enable => false,
vlan_prio => "000",
frame_length => 750,
iterations => 1,
interframe_gap => 1540);
constant stim3 : port_stimulus_type := (frame1_3, frame2_3, 0);
constant DA : std_logic_vector := x"DA";
constant SA : std_logic_vector := x"5A";
constant MAX_FRAME_LENGTH : integer := 1522;
-- testbench evaluation datatyps
type statistics_type is record
received_messages : integer; -- counter of received messages of this destination address
latency_100 : integer; -- number of messages up to 100 clock cycles
latency101_150 : integer;
latency151_200 : integer;
latency201_250 : integer;
latency251_300 : integer;
latency301_350 : integer;
latency351_400 : integer;
latency401_450 : integer;
latency451_500 : integer;
latency501_600 : integer;
latency601_700 : integer;
latency701_800 : integer;
latency801_900 : integer;
latency901_1000 : integer;
latency1001_1200 : integer;
latency1201_1400 : integer;
latency1401_1600 : integer;
latency1601_1800 : integer;
latency1801_2000 : integer;
latency2001_2200 : integer;
latency2201_2400 : integer;
latency2401_2600 : integer;
latency2601_2800 : integer;
latency2801_3000 : integer;
latency3001_3500 : integer;
latency3501_4000 : integer;
latency4001_4500 : integer;
latency4501_5000 : integer;
latency5001_5500 : integer;
latency5501_6000 : integer;
latency6001_6500 : integer;
latency6501_7000 : integer;
latency7001_7500 : integer;
latency7501_8000 : integer;
latency8001_8500 : integer;
latency8501_9000 : integer;
latency9001_9500 : integer;
latency9501_10000 : integer;
latency10001_12000 : integer;
latency12001_14000 : integer;
latency14001_16000 : integer;
latency16001_18000 : integer;
latency180001_20000 : integer;
latency20001_22500 : integer;
latency22501_25000 : integer;
latency25001_27500 : integer;
latency27501_30000 : integer;
latency30001_32500 : integer;
latency32501_35000 : integer;
latency35000x : integer;
end record;
type statistics_vector_type is array (0 to 255) of statistics_type;
type port_stats_type is record
received_frames : integer;
stat_vec : statistics_vector_type;
end record;
signal port_stats0 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats1 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats2 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats3 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
component automotive_ethernet_gateway is
Generic (
RECEIVER_DATA_WIDTH : integer := 8;
TRANSMITTER_DATA_WIDTH : integer := 8;
FABRIC_DATA_WIDTH : integer := 32;
NR_PORTS : integer := 4;
ARBITRATION : integer := 1;
FRAME_LENGTH_WIDTH : integer := 11;
NR_IQ_FIFOS : integer := 2;
NR_OQ_FIFOS : integer := 2;
TIMESTAMP_WIDTH : integer := 64;
GMII_DATA_WIDTH : integer := 8;
TX_IFG_DELAY_WIDTH : integer := 8;
PAUSE_VAL_WIDTH : integer := 16
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic_vector(NR_PORTS-1 downto 0);
intn : in std_logic_vector(NR_PORTS-1 downto 0);
latency : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_er : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_clk : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_rxd : in std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_er : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
mii_tx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
-- MDIO Interface
-----------------
mdio : inout std_logic_vector(NR_PORTS-1 downto 0);
mdc : out std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
type frame_typ is record
columns : frame_of_data_typ(0 to MAX_FRAME_LENGTH); -- data field
interframe_gap : integer;
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data0 : frame_typ;
shared variable frame_data1 : frame_typ;
shared variable frame_data2 : frame_typ;
shared variable frame_data3 : frame_typ;
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
function init_frame(
dest6 : in std_logic_vector(7 downto 0);
source6 : in std_logic_vector(7 downto 0);
vlan_enable : in boolean;
vlan_priority : in std_logic_vector(2 downto 0);
length : in integer;
interframe_gap : in integer
)
return frame_typ is
variable frame_data : frame_typ;
variable length_type : std_logic_vector(15 downto 0);
variable data_byte : std_logic_vector(15 downto 0);
variable i : integer;
variable vlan_bytes : integer := 0;
begin
if dest6 = x"FF" then
frame_data.columns(0) := ( DATA => dest6, VALID => '1', ERROR => '0'); -- Destination Address,
frame_data.columns(1) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => dest6, VALID => '1', ERROR => '0');
else
frame_data.columns(0) := ( DATA => DA, VALID => '1', ERROR => '0'); -- Destination Address,
frame_data.columns(1) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => DA, VALID => '1', ERROR => '0');
end if;
frame_data.columns(5) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(6) := ( DATA => SA, VALID => '1', ERROR => '0'); -- Source Address
frame_data.columns(7) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(8) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(9) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(10) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(11) := ( DATA => source6, VALID => '1', ERROR => '0');
-- VLAN
if vlan_enable then
vlan_bytes := 4;
frame_data.columns(12) := ( DATA => x"81", VALID => '1', ERROR => '0'); -- VLAN Identifier
frame_data.columns(13) := ( DATA => x"00", VALID => '1', ERROR => '0');
data_byte := x"00" & vlan_priority & "00000"; -- VLAN Priority
frame_data.columns(14) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0');
frame_data.columns(15) := ( DATA => x"00", VALID => '1', ERROR => '0');
end if;
-- Length/Type
length_type := std_logic_vector(to_unsigned(length-18-vlan_bytes,length_type'length));
frame_data.columns(12+vlan_bytes) := ( DATA => length_type(15 downto 8), VALID => '1', ERROR => '0');
frame_data.columns(13+vlan_bytes) := ( DATA => length_type(7 downto 0), VALID => '1', ERROR => '0');
-- Payload
i := 14+vlan_bytes;
while i < length - 4 loop
data_byte := std_logic_vector(to_unsigned(i-13-vlan_bytes ,data_byte'length));
frame_data.columns(i) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0');
i := i+1;
end loop;
-- Padding
while i < 60+vlan_bytes loop
frame_data.columns(i) := ( DATA => X"00", VALID => '1', ERROR => '0');
i := i+1;
end loop;
-- Stop writing
frame_data.columns(i) := ( DATA => X"00", VALID => '0', ERROR => '0');
-- interframe_gap
frame_data.interframe_gap := interframe_gap;
return frame_data;
end init_frame;
function update_stats(
port_stats_in : in port_stats_type;
data : in std_logic_vector(7 downto 0);
latency : in std_logic_vector(63 downto 0)
)
return port_stats_type is
variable port_stats : port_stats_type;
variable data_int : integer;
variable latency_int : integer;
begin
data_int := to_integer(unsigned(data));
latency_int := to_integer(unsigned(latency));
port_stats := port_stats_in;
port_stats.received_frames := port_stats.received_frames + 1;
port_stats.stat_vec(data_int).received_messages := port_stats.stat_vec(data_int).received_messages + 1;
if latency_int <= 100 then
port_stats.stat_vec(data_int).latency_100 := port_stats.stat_vec(data_int).latency_100 + 1;
elsif latency_int <= 150 then
port_stats.stat_vec(data_int).latency101_150 := port_stats.stat_vec(data_int).latency101_150 + 1;
elsif latency_int <= 200 then
port_stats.stat_vec(data_int).latency151_200 := port_stats.stat_vec(data_int).latency151_200 + 1;
elsif latency_int <= 250 then
port_stats.stat_vec(data_int).latency201_250 := port_stats.stat_vec(data_int).latency201_250 + 1;
elsif latency_int <= 300 then
port_stats.stat_vec(data_int).latency251_300 := port_stats.stat_vec(data_int).latency251_300 + 1;
elsif latency_int <= 350 then
port_stats.stat_vec(data_int).latency301_350 := port_stats.stat_vec(data_int).latency301_350 + 1;
elsif latency_int <= 400 then
port_stats.stat_vec(data_int).latency351_400 := port_stats.stat_vec(data_int).latency351_400 + 1;
elsif latency_int <= 450 then
port_stats.stat_vec(data_int).latency401_450 := port_stats.stat_vec(data_int).latency401_450 + 1;
elsif latency_int <= 500 then
port_stats.stat_vec(data_int).latency451_500 := port_stats.stat_vec(data_int).latency451_500 + 1;
elsif latency_int <= 600 then
port_stats.stat_vec(data_int).latency501_600 := port_stats.stat_vec(data_int).latency501_600 + 1;
elsif latency_int <= 700 then
port_stats.stat_vec(data_int).latency601_700 := port_stats.stat_vec(data_int).latency601_700 + 1;
elsif latency_int <= 800 then
port_stats.stat_vec(data_int).latency701_800 := port_stats.stat_vec(data_int).latency701_800 + 1;
elsif latency_int <= 900 then
port_stats.stat_vec(data_int).latency801_900 := port_stats.stat_vec(data_int).latency801_900 + 1;
elsif latency_int <= 1000 then
port_stats.stat_vec(data_int).latency901_1000 := port_stats.stat_vec(data_int).latency901_1000 + 1;
elsif latency_int <= 1200 then
port_stats.stat_vec(data_int).latency1001_1200 := port_stats.stat_vec(data_int).latency1001_1200 + 1;
elsif latency_int <= 1400 then
port_stats.stat_vec(data_int).latency1201_1400 := port_stats.stat_vec(data_int).latency1201_1400 + 1;
elsif latency_int <= 1600 then
port_stats.stat_vec(data_int).latency1401_1600 := port_stats.stat_vec(data_int).latency1401_1600 + 1;
elsif latency_int <= 1800 then
port_stats.stat_vec(data_int).latency1601_1800 := port_stats.stat_vec(data_int).latency1601_1800 + 1;
elsif latency_int <= 2000 then
port_stats.stat_vec(data_int).latency1801_2000 := port_stats.stat_vec(data_int).latency1801_2000 + 1;
elsif latency_int <= 2200 then
port_stats.stat_vec(data_int).latency2001_2200 := port_stats.stat_vec(data_int).latency2001_2200 + 1;
elsif latency_int <= 2400 then
port_stats.stat_vec(data_int).latency2201_2400 := port_stats.stat_vec(data_int).latency2201_2400 + 1;
elsif latency_int <= 2600 then
port_stats.stat_vec(data_int).latency2401_2600 := port_stats.stat_vec(data_int).latency2401_2600 + 1;
elsif latency_int <= 2800 then
port_stats.stat_vec(data_int).latency2601_2800 := port_stats.stat_vec(data_int).latency2601_2800 + 1;
elsif latency_int <= 3000 then
port_stats.stat_vec(data_int).latency2801_3000 := port_stats.stat_vec(data_int).latency2801_3000 + 1;
elsif latency_int <= 3500 then
port_stats.stat_vec(data_int).latency3001_3500 := port_stats.stat_vec(data_int).latency3001_3500 + 1;
elsif latency_int <= 4000 then
port_stats.stat_vec(data_int).latency3501_4000 := port_stats.stat_vec(data_int).latency3501_4000 + 1;
elsif latency_int <= 4500 then
port_stats.stat_vec(data_int).latency4001_4500 := port_stats.stat_vec(data_int).latency4001_4500 + 1;
elsif latency_int <= 5000 then
port_stats.stat_vec(data_int).latency4501_5000 := port_stats.stat_vec(data_int).latency4501_5000 + 1;
elsif latency_int <= 5500 then
port_stats.stat_vec(data_int).latency5001_5500 := port_stats.stat_vec(data_int).latency5001_5500 + 1;
elsif latency_int <= 6000 then
port_stats.stat_vec(data_int).latency5501_6000 := port_stats.stat_vec(data_int).latency5501_6000 + 1;
elsif latency_int <= 6500 then
port_stats.stat_vec(data_int).latency6001_6500 := port_stats.stat_vec(data_int).latency6001_6500 + 1;
elsif latency_int <= 7000 then
port_stats.stat_vec(data_int).latency6501_7000 := port_stats.stat_vec(data_int).latency6501_7000 + 1;
elsif latency_int <= 7500 then
port_stats.stat_vec(data_int).latency7001_7500 := port_stats.stat_vec(data_int).latency7001_7500 + 1;
elsif latency_int <= 8000 then
port_stats.stat_vec(data_int).latency7501_8000 := port_stats.stat_vec(data_int).latency7501_8000 + 1;
elsif latency_int <= 8500 then
port_stats.stat_vec(data_int).latency8001_8500 := port_stats.stat_vec(data_int).latency8001_8500 + 1;
elsif latency_int <= 9000 then
port_stats.stat_vec(data_int).latency8501_9000 := port_stats.stat_vec(data_int).latency8501_9000 + 1;
elsif latency_int <= 9500 then
port_stats.stat_vec(data_int).latency9001_9500 := port_stats.stat_vec(data_int).latency9001_9500 + 1;
elsif latency_int <= 10000 then
port_stats.stat_vec(data_int).latency9501_10000 := port_stats.stat_vec(data_int).latency9501_10000 + 1;
elsif latency_int <= 12000 then
port_stats.stat_vec(data_int).latency10001_12000 := port_stats.stat_vec(data_int).latency10001_12000 + 1;
elsif latency_int <= 14000 then
port_stats.stat_vec(data_int).latency12001_14000 := port_stats.stat_vec(data_int).latency12001_14000 + 1;
elsif latency_int <= 16000 then
port_stats.stat_vec(data_int).latency14001_16000 := port_stats.stat_vec(data_int).latency14001_16000 + 1;
elsif latency_int <= 18000 then
port_stats.stat_vec(data_int).latency16001_18000 := port_stats.stat_vec(data_int).latency16001_18000 + 1;
elsif latency_int <= 20000 then
port_stats.stat_vec(data_int).latency180001_20000 := port_stats.stat_vec(data_int).latency180001_20000 + 1;
elsif latency_int <= 22500 then
port_stats.stat_vec(data_int).latency20001_22500 := port_stats.stat_vec(data_int).latency20001_22500 + 1;
elsif latency_int <= 25000 then
port_stats.stat_vec(data_int).latency22501_25000 := port_stats.stat_vec(data_int).latency22501_25000 + 1;
elsif latency_int <= 27500 then
port_stats.stat_vec(data_int).latency25001_27500 := port_stats.stat_vec(data_int).latency25001_27500 + 1;
elsif latency_int <= 30000 then
port_stats.stat_vec(data_int).latency27501_30000 := port_stats.stat_vec(data_int).latency27501_30000 + 1;
elsif latency_int <= 32500 then
port_stats.stat_vec(data_int).latency30001_32500 := port_stats.stat_vec(data_int).latency30001_32500 + 1;
elsif latency_int <= 35000 then
port_stats.stat_vec(data_int).latency32501_35000 := port_stats.stat_vec(data_int).latency32501_35000 + 1;
else
port_stats.stat_vec(data_int).latency35000x := port_stats.stat_vec(data_int).latency35000x + 1;
end if;
return port_stats;
end update_stats;
-- testbench signals
constant gtx_period : time := 2.5 ns;
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic_vector(3 downto 0) := (others => '0');
-- signal mdc : std_logic_vector(NR_PORTS-1 downto 0);
-- signal mdio : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_clk : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_en : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_er : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_txd : std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_rx_dv : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal gmii_rx_er : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal gmii_rxd : std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0) := (others => '0');
signal mii_tx_clk : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal mdc : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal mdio : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal latency : std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
signal latency0 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency1 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency2 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency3 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- testbench control signals
signal reset_finished : boolean := false;
signal port0_finished : boolean := false;
signal port1_finished : boolean := false;
signal port2_finished : boolean := false;
signal port3_finished : boolean := false;
begin
latency0 <= latency(63 downto 0);
latency1 <= latency(127 downto 64);
latency2 <= latency(191 downto 128);
latency3 <= latency(255 downto 192);
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
generic map(
NR_PORTS => NR_PORTS,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
ARBITRATION => ARBITRATION,
NR_IQ_FIFOS => NR_IQ_FIFOS,
NR_OQ_FIFOS => NR_OQ_FIFOS,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
intn => "0000",
latency => latency,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 2000 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- init process.
-----------------------------------------------------------------------------
p_init : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
wait for 800 ns;
mac_reset;
reset_finished <= true;
wait;
end process p_init;
p_stop : process
begin
wait until port3_finished and port2_finished and port1_finished and port0_finished;
if demo_mode_error /= 0 then
assert false
report "Errors occured"
severity error;
end if;
wait for 100 us;
assert false
report "Simulation stopped"
severity failure;
end process p_stop;
------------------------------------------------------------------------------
-- Stimulus process on port 0 (traffic generator)
------------------------------------------------------------------------------
p_stimulus0 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(7 downto 0) <= "01010101";
gmii_rx_dv(0) <= '1';
gmii_rx_er(0) <= '0';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(7 downto 0) <= "11010101";
gmii_rx_dv(0) <= '1';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
current_col := 0;
gmii_rxd(7 downto 0) <= frame_data0.columns(current_col).data;
gmii_rx_dv(0) <= frame_data0.columns(current_col).valid;
gmii_rx_er(0) <= frame_data0.columns(current_col).error;
fcs := calc_crc(frame_data0.columns(current_col).data, fcs);
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data0.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(7 downto 0) <= frame_data0.columns(current_col).data;
gmii_rx_dv(0) <= frame_data0.columns(current_col).valid;
gmii_rx_er(0) <= frame_data0.columns(current_col).error;
fcs := calc_crc(frame_data0.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(7 downto 0) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(0) <= '1';
gmii_rx_er(0) <= '0';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(7 downto 0) <= (others => '0');
gmii_rx_dv(0) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data0.interframe_gap loop
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
frame_sa := X"00";
if PORT_ENABLED(0) = '0' then
port0_finished <= true;
else
for i in 0 to stim0.iterations-1 loop
for j in 0 to stim0.frame1.iterations-1 loop
frame_data0 := init_frame(stim0.frame1.dest, frame_sa, stim0.frame1.vlan_enable,
stim0.frame1.vlan_prio, stim0.frame1.frame_length, stim0.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim0.frame2.iterations-1 loop
frame_data0 := init_frame(stim0.frame2.dest, frame_sa, stim0.frame2.vlan_enable,
stim0.frame2.vlan_prio, stim0.frame2.frame_length, stim0.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port0_finished <= true;
end if;
end process p_stimulus0;
------------------------------------------------------------------------------
-- Stimulus process on port 1
------------------------------------------------------------------------------
p_stimulus1 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(15 downto 8) <= "01010101";
gmii_rx_dv(1) <= '1';
gmii_rx_er(1) <= '0';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(15 downto 8) <= "11010101";
gmii_rx_dv(1) <= '1';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
current_col := 0;
gmii_rxd(15 downto 8) <= frame_data1.columns(current_col).data;
gmii_rx_dv(1) <= frame_data1.columns(current_col).valid;
gmii_rx_er(1) <= frame_data1.columns(current_col).error;
fcs := calc_crc(frame_data1.columns(current_col).data, fcs);
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data1.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(15 downto 8) <= frame_data1.columns(current_col).data;
gmii_rx_dv(1) <= frame_data1.columns(current_col).valid;
gmii_rx_er(1) <= frame_data1.columns(current_col).error;
fcs := calc_crc(frame_data1.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(15 downto 8) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(1) <= '1';
gmii_rx_er(1) <= '0';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(15 downto 8) <= (others => '0');
gmii_rx_dv(1) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data1.interframe_gap loop
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"01";
if PORT_ENABLED(1) = '0' then
port1_finished <= true;
else
for i in 0 to stim1.iterations-1 loop
for j in 0 to stim1.frame1.iterations-1 loop
frame_data1 := init_frame(stim1.frame1.dest, frame_sa, stim1.frame1.vlan_enable,
stim1.frame1.vlan_prio, stim1.frame1.frame_length, stim1.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim1.frame2.iterations-1 loop
frame_data1 := init_frame(stim1.frame2.dest, frame_sa, stim1.frame2.vlan_enable,
stim1.frame2.vlan_prio, stim1.frame2.frame_length, stim1.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port1_finished <= true;
end if;
end process p_stimulus1;
------------------------------------------------------------------------------
-- Stimulus process on port 2
------------------------------------------------------------------------------
p_stimulus2 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(23 downto 16) <= "01010101";
gmii_rx_dv(2) <= '1';
gmii_rx_er(2) <= '0';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(23 downto 16) <= "11010101";
gmii_rx_dv(2) <= '1';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
current_col := 0;
gmii_rxd(23 downto 16) <= frame_data2.columns(current_col).data;
gmii_rx_dv(2) <= frame_data2.columns(current_col).valid;
gmii_rx_er(2) <= frame_data2.columns(current_col).error;
fcs := calc_crc(frame_data2.columns(current_col).data, fcs);
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data2.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(23 downto 16) <= frame_data2.columns(current_col).data;
gmii_rx_dv(2) <= frame_data2.columns(current_col).valid;
gmii_rx_er(2) <= frame_data2.columns(current_col).error;
fcs := calc_crc(frame_data2.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(23 downto 16) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(2) <= '1';
gmii_rx_er(2) <= '0';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(23 downto 16) <= (others => '0');
gmii_rx_dv(2) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data2.interframe_gap loop
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"02";
if PORT_ENABLED(2) = '0' then
port2_finished <= true;
else
for i in 0 to stim2.iterations-1 loop
for j in 0 to stim2.frame1.iterations-1 loop
frame_data2 := init_frame(stim2.frame1.dest, frame_sa, stim2.frame1.vlan_enable,
stim2.frame1.vlan_prio, stim2.frame1.frame_length, stim2.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim2.frame2.iterations-1 loop
frame_data2 := init_frame(stim2.frame2.dest, frame_sa, stim2.frame2.vlan_enable,
stim2.frame2.vlan_prio, stim2.frame2.frame_length, stim2.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port2_finished <= true;
end if;
end process p_stimulus2;
------------------------------------------------------------------------------
-- Stimulus process on port 3
------------------------------------------------------------------------------
p_stimulus3 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(31 downto 24) <= "01010101";
gmii_rx_dv(3) <= '1';
gmii_rx_er(3) <= '0';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(31 downto 24) <= "11010101";
gmii_rx_dv(3) <= '1';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
current_col := 0;
gmii_rxd(31 downto 24) <= frame_data3.columns(current_col).data;
gmii_rx_dv(3) <= frame_data3.columns(current_col).valid;
gmii_rx_er(3) <= frame_data3.columns(current_col).error;
fcs := calc_crc(frame_data3.columns(current_col).data, fcs);
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data3.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(31 downto 24) <= frame_data3.columns(current_col).data;
gmii_rx_dv(3) <= frame_data3.columns(current_col).valid;
gmii_rx_er(3) <= frame_data3.columns(current_col).error;
fcs := calc_crc(frame_data3.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(31 downto 24) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(3) <= '1';
gmii_rx_er(3) <= '0';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(31 downto 24) <= (others => '0');
gmii_rx_dv(3) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data3.interframe_gap loop
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"03";
if PORT_ENABLED(3) = '0' then
port3_finished <= true;
else
for i in 0 to stim3.iterations-1 loop
for j in 0 to stim3.frame1.iterations-1 loop
frame_data3 := init_frame(stim3.frame1.dest, frame_sa, stim3.frame1.vlan_enable,
stim3.frame1.vlan_prio, stim3.frame1.frame_length, stim3.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim3.frame2.iterations-1 loop
frame_data3 := init_frame(stim3.frame2.dest, frame_sa, stim3.frame2.vlan_enable,
stim3.frame2.vlan_prio, stim3.frame2.frame_length, stim3.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port3_finished <= true;
end if;
end process p_stimulus3;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor0 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(0) /= '1' or gmii_txd(7 downto 0) = "01010101" loop
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(7 downto 0) /= "11010101") then
assert false
report "SFD not present @ Port 0" & cr
severity error;
end if;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(7 downto 0) /= x"FF" then
if gmii_txd(7 downto 0) /= DA then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 0" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats0 <= update_stats(port_stats0, gmii_txd(7 downto 0), latency0);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(7 downto 0) /= SA then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 0" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(7 downto 0) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(7 downto 0);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(7 downto 0) /= x"00" then
demo_mode_error(0) <= '1';
assert false
report "vlan incorrect @ Port 0" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(7 downto 0);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(7 downto 0);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(7 downto 0);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(7 downto 0) /= (byte_cnt mod 256) then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect @ Port 0" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(7 downto 0) /= x"00" then
demo_mode_error(0) <= '1';
assert false
report "Padding incorrect @ Port 0" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd(7 downto 0), fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(0) = '0' then
demo_mode_error(0) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 0" & cr
severity error;
end if;
if gmii_txd(7 downto 0) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 0" & cr
severity error;
end if;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor0;
p_monitor1 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(1) /= '1' or gmii_txd(15 downto 8) = "01010101" loop
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(15 downto 8) /= "11010101") then
assert false
report "SFD not present @ Port 1" & cr
severity error;
end if;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(15 downto 8) /= x"FF" then
if gmii_txd(15 downto 8) /= DA then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 1" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats1 <= update_stats(port_stats1, gmii_txd(15 downto 8), latency1);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(15 downto 8) /= SA then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 1" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(15 downto 8) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(15 downto 8);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(15 downto 8) /= x"00" then
demo_mode_error(1) <= '1';
assert false
report "vlan incorrect @ Port 1" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(15 downto 8);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(15 downto 8);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(15 downto 8);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(15 downto 8) /= (byte_cnt mod 256) then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect @ Port 1" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(15 downto 8) /= x"00" then
demo_mode_error(1) <= '1';
assert false
report "Padding incorrect @ Port 1" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(15 downto 8);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(1) = '0' then
demo_mode_error(1) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 1" & cr
severity error;
end if;
if gmii_txd(15 downto 8) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 1" & cr
severity error;
end if;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor1;
p_monitor2 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(2) /= '1' or gmii_txd(23 downto 16) = "01010101" loop
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(23 downto 16) /= "11010101") then
assert false
report "SFD not present @ Port 2" & cr
severity error;
end if;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(23 downto 16) /= x"FF" then
if gmii_txd(23 downto 16) /= DA then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 2" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats2 <= update_stats(port_stats2, gmii_txd(23 downto 16), latency2);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(23 downto 16) /= SA then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 2" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(23 downto 16) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(23 downto 16);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(23 downto 16) /= x"00" then
demo_mode_error(2) <= '1';
assert false
report "vlan incorrect @ Port 2" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(23 downto 16);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(23 downto 16);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(23 downto 16);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(23 downto 16) /= (byte_cnt mod 256) then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect @ Port 2" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(23 downto 16) /= x"00" then
demo_mode_error(2) <= '1';
assert false
report "Padding incorrect @ Port 2" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(23 downto 16);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop;
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(2) = '0' then
demo_mode_error(2) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 2" & cr
severity error;
end if;
if gmii_txd(23 downto 16) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 2" & cr
severity error;
end if;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor2;
p_monitor3 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(3) /= '1' or gmii_txd(31 downto 24) = "01010101" loop
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(31 downto 24) /= "11010101") then
assert false
report "SFD not present @ Port 3" & cr
severity error;
end if;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(31 downto 24) /= x"FF" then
if gmii_txd(31 downto 24) /= DA then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 3" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats3 <= update_stats(port_stats3, gmii_txd(31 downto 24), latency3);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(31 downto 24) /= SA then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 3" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(31 downto 24) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(31 downto 24);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(31 downto 24) /= x"00" then
demo_mode_error(3) <= '1';
assert false
report "vlan incorrect @ Port 3" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(31 downto 24);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(31 downto 24);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(31 downto 24);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(31 downto 24) /= (byte_cnt mod 256) then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect @ Port 3" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(31 downto 24) /= x"00" then
demo_mode_error(3) <= '1';
assert false
report "Padding incorrect @ Port 3" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(31 downto 24);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(3) = '0' then
demo_mode_error(3) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 3" & cr
severity error;
end if;
if gmii_txd(31 downto 24) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 3" & cr
severity error;
end if;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor3;
end tb;
| mit | 5fad222848f962e4347e07146ef28a7c | 0.477362 | 4.298598 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_Pofkplusone.vhd | 1 | 1,164 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Pofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Pofkplusone;
architecture struct of kn_kalman_Pofkplusone is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_mult port map (clock => clock, dataa => Pdashofkplusone, datab => Kofkplusone, result => Z);
M2 : kn_kalman_sub port map (clock => clock, dataa => Pdashofkplusone, datab => Z, result => Pofkplusone);
end struct;
| gpl-2.0 | 1df1918d5bce50b0baa0aae5003fc59a | 0.652921 | 3.335244 | false | false | false | false |
Caian/Minesweeper | Projeto/counter.vhd | 1 | 1,109 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clock : in std_logic;
rstn : in std_logic;
enable : in std_logic;
-- mode : in std_logic;
cnt_out : out std_logic_vector(9 downto 0)
);
end;
architecture logica of counter is
signal count : std_logic_vector(9 downto 0);
begin
process(clock, rstn, enable)
begin
if rstn = '0' then
count <= (others => '0');
elsif rising_edge(clock) and enable = '1' then
-- case mode is
-- when '1' =>
case count is
when "1111100111" => count <= "1111100111";
when OTHERS => count <= count+1;
end case;
-- when '0' =>
-- case count is
-- when "0000000000" => count <= "0000000000";
-- when OTHERS => count <= count-1;
-- end case;
-- end case;
end if;
end process;
cnt_out <= count;
end architecture;
| gpl-2.0 | 4482c2f7d08a0a87738f245f682f270c | 0.528404 | 3.223837 | false | false | false | false |
lennartbublies/ecdsa | src/e_sha256.vhd | 1 | 3,522 | -- SHA256 Hashing Module
-- Kristian Klomsten Skordal <[email protected]>
-- This module only operates on full 512 bit blocks. Any input data must have
-- been previously padded.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha256_types.all;
use work.sha256_constants.all;
use work.sha256_functions.all;
entity sha256 is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic; -- Ready to process the next block
update : in std_logic; -- Start processing the next block
-- Connections to the input buffer; we assume block RAM that presents
-- valid data the cycle after the address has changed:
word_address : out std_logic_vector(3 downto 0); -- Word 0 .. 15
word_input : in std_logic_vector(31 downto 0);
-- Intermediate/final hash values:
hash_output : out std_logic_vector(255 downto 0);
-- Debug port, used in simulation; leave unconnected:
debug_port : out std_logic_vector(31 downto 0)
);
end entity sha256;
architecture behaviour of sha256 is
-- The module's state machine:
type state_type is (IDLE, BUSY, FINAL);
signal state : state_type;
-- The expanded message blocks, W_j:
signal W : expanded_message_block_array;
signal current_w : std_logic_vector(31 downto 0);
-- Final hash values:
signal h0, h1, h2, h3, h4, h5, h6, h7 : std_logic_vector(31 downto 0);
-- Intermediate hash values:
signal a, b, c, d, e, f, g, h : std_logic_vector(31 downto 0);
-- Current iteration:
signal current_iteration : std_logic_vector(5 downto 0);
begin
word_address <= current_iteration(3 downto 0)
when (current_iteration and b"110000") = b"000000"
else (others => '0');
hash_output <= h0 & h1 & h2 & h3 & h4 & h5 & h6 & h7;
ready <= '1' when state = IDLE else '0';
debug_port <= (others => '0'); -- This is currently not used, yay :-)
hasher: process(clk, reset, enable)
begin
if reset = '1' then
reset_intermediate(h0, h1, h2, h3, h4, h5, h6, h7);
current_iteration <= (others => '0');
state <= IDLE;
elsif rising_edge(clk) and enable = '1' then
case state is
when IDLE =>
-- If new data is available, start hashing it:
if update = '1' then
a <= h0;
b <= h1;
c <= h2;
d <= h3;
e <= h4;
f <= h5;
g <= h6;
h <= h7;
current_iteration <= (others => '0');
state <= BUSY;
end if;
when BUSY =>
-- Load a word of data and store it into the expanded message schedule:
W(index(current_iteration)) <= schedule(word_input, W, current_iteration);
-- Run an interation of the compression function:
compress(a, b, c, d, e, f, g, h,
schedule(word_input, W, current_iteration),
constants(index(current_iteration)));
if current_iteration = b"111111" then
state <= FINAL;
else
current_iteration <= std_logic_vector(unsigned(current_iteration) + 1);
end if;
when FINAL =>
h0 <= std_logic_vector(unsigned(a) + unsigned(h0));
h1 <= std_logic_vector(unsigned(b) + unsigned(h1));
h2 <= std_logic_vector(unsigned(c) + unsigned(h2));
h3 <= std_logic_vector(unsigned(d) + unsigned(h3));
h4 <= std_logic_vector(unsigned(e) + unsigned(h4));
h5 <= std_logic_vector(unsigned(f) + unsigned(h5));
h6 <= std_logic_vector(unsigned(g) + unsigned(h6));
h7 <= std_logic_vector(unsigned(h) + unsigned(h7));
state <= IDLE;
end case;
end if;
end process hasher;
end architecture behaviour;
| gpl-3.0 | 360ca5c995e38edd750e4b174024cc2b | 0.642533 | 3.033592 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/bitStringValuesEnt.vhd | 1 | 539 | library ieee;
use ieee.std_logic_1164.all;
entity BitStringValuesEnt is
generic(
C_1 : std_logic := '1';
C_0 : std_logic := '0';
C_1b1 : std_logic_vector := "1";
C_1b0 : std_logic_vector := "0";
C_16b1 : std_logic_vector := X"0000FFFF";
C_32b0 : std_logic_vector := X"00000000";
C_32b1 : std_logic_vector := X"FFFFFFFF";
C_128b1 : std_logic_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
);
port(
ACLK : in std_logic
);
end BitStringValuesEnt;
| mit | cd9b59e2f511bbd36ef34c91722b5243 | 0.560297 | 2.851852 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_final_fpga.vhd | 1 | 6,707 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_final_fpga is
port
( clock : in std_logic;
Uofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Z0 : in std_logic;
Z1 : in std_logic;
Z2 : in std_logic;
Z3 : in std_logic;
S0 : in std_logic;
S1 : in std_logic;
S2 : in std_logic;
Vrefofkplusone_mux_sel : in std_logic;
Vrefofkplusone_sel : in std_logic;
Vrefofkplusone_reset : in std_logic;
Vactcapofk_mux_sel : in std_logic;
Vactcapofk_sel : in std_logic;
Vactcapofk_reset : in std_logic;
Pofk_mux_sel : in std_logic;
Pofk_sel : in std_logic;
Pofk_reset : in std_logic;
Uofk_mux_sel : in std_logic;
Uofk_sel : in std_logic;
Uofk_reset : in std_logic;
Vactcapofkplusone_sel : in std_logic;
Vactcapofkplusone_reset : in std_logic;
Pofkplusone_sel : in std_logic;
Pofkplusone_reset : in std_logic;
Vactcapofkplusone_enable : out std_logic;
Pofkplusone_enable : out std_logic;
Sout : out std_logic_vector(7 downto 0)
);
end kn_kalman_final_fpga;
architecture struct of kn_kalman_final_fpga is
component kn_kalman_final is
port
( clock : in std_logic;
Uofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vactcapofk_mux_sel : in std_logic;
Vactcapofk_sel : in std_logic;
Vactcapofk_reset : in std_logic;
Pofk_mux_sel : in std_logic;
Pofk_sel : in std_logic;
Pofk_reset : in std_logic;
Vactcapofkplusone_sel : in std_logic;
Vactcapofkplusone_reset : in std_logic;
Pofkplusone_sel : in std_logic;
Pofkplusone_reset : in std_logic;
Pofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone_enable : out std_logic;
Pofkplusone_enable : out std_logic
);
end component;
component demux is
port
( clock : in std_logic;
prod : in std_logic_vector (31 downto 0);
Z0 : in std_logic;
Z1 : in std_logic;
Z2 : in std_logic;
Z3 : in std_logic;
S0 : in std_logic;
S1 : in std_logic;
a : out std_logic_vector (7 downto 0)
);
end component;
component mux is
port
( clock : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
Z : in std_logic;
prod : out std_logic_vector(31 downto 0));
end component;
component kr_regbuf is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0) );
end component;
signal V : std_logic_vector(31 downto 0);
signal N : std_logic_vector(31 downto 0);
signal J : std_logic_vector(31 downto 0);
signal K1,K2 : std_logic_vector(31 downto 0);
signal H1,H2 : std_logic_vector(31 downto 0);
signal Vrefofkplusone_initial : std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
signal Uofk_initial : std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
--signal I1 : std_logic_vector(31 downto 0) := "01000001101000000011110000101001";
--signal I2 : std_logic_vector(31 downto 0) := "00111011000000110001001001101111";
--signal I3 : std_logic_vector(31 downto 0) := "01000000101001110101110000101001";
--signal I4 : std_logic_vector(31 downto 0) := "00111010011110101010101101000110";
--signal I5 : std_logic_vector(31 downto 0) := "00111000110100011011011100010111";
--signal I6 : std_logic_vector(31 downto 0) := "00111100001000111101011100001010";
--signal I7 : std_logic_vector(31 downto 0) := "01000001100110111000010100011111";
begin
M1 : mux
port map
( clock => clock,
a => Vrefofkplusone_initial,
b => Vrefofkplusone,
z => Vrefofkplusone_mux_sel,
prod => H1);
M2 : kr_regbuf
port map
( clock => clock,
reset => Vrefofkplusone_reset,
load => Vrefofkplusone_sel,
I => H1,
Y => K1 );
M3 : mux
port map
( clock => clock,
a => Uofk_initial,
b => Uofk,
z => Uofk_mux_sel,
prod => H2);
M4 : kr_regbuf
port map
( clock => clock,
reset => Uofk_reset,
load => Uofk_sel,
I => H2,
Y => K2 );
M5 : kn_kalman_final
port map
( clock => clock,
Uofk => K2,
Vrefofkplusone => K1,
Vactcapofk_mux_sel => Pofk_mux_sel,
Vactcapofk_sel => Pofk_sel,
Vactcapofk_reset => Pofk_reset,
Pofk_mux_sel => Pofk_mux_sel,
Pofk_sel =>Pofk_sel,
Pofk_reset => Pofk_reset,
Vactcapofkplusone_sel => Vactcapofkplusone_sel,
Vactcapofkplusone_reset => Vactcapofkplusone_reset,
Pofkplusone_sel => Pofkplusone_sel,
Pofkplusone_reset => Pofkplusone_reset,
Pofkplusone => N,
Vactcapofkplusone => V,
Vactcapofkplusone_enable => Vactcapofkplusone_enable,
Pofkplusone_enable => Pofkplusone_enable);
M6 : mux
port map
( clock => clock,
a => V,
b => N,
Z => S2,
prod => J);
M7 : demux
port map
( clock => clock,
prod => J,
Z0 => Z0,
Z1 => Z1,
Z2 => Z2,
Z3 => Z3,
S0 => S0,
S1 => S1,
a => Sout );
end struct; | gpl-2.0 | a8b1b2d1f6f7224f84fc20492b6a55e0 | 0.489339 | 4.23957 | false | false | false | false |
lennartbublies/ecdsa | src/tld_ecdsa.vhd | 1 | 4,270 | ----------------------------------------------------------------------------------------------------
-- TOP LEVEL ENTITY - ECDSA
-- FPDA implementation of ECDSA algorithm
--
-- Ports:
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 02.07.2017
-- Last Change: 10.11.2017
----------------------------------------------------------------------------------------------------
--
-- Pin Assignment:
--
-- clk_i : PIN_N2 (Clock 50 Mhz)
-- rst_i : PIN_G26 (Key 0)
-- uart_rx_i : PIN_C25 (UART Receiver)
-- uart_wx_i : PIN_B25 (UART Transmitter)
-- rst_led : PIN_Y18 (LEDG7)
--
------------------------------------------------------------
-- GF(2^M) ecdsa top level entity
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tld_ecdsa IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Uart read/write
uart_rx_i : IN std_logic;
uart_wx_i : OUT std_logic;
rst_led : OUT std_logic
);
END tld_ecdsa;
ARCHITECTURE rtl OF tld_ecdsa IS
-- Components -----------------------------------------
-- Import entity e_ecdsa
COMPONENT e_ecdsa IS
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
mode_i: IN std_logic;
hash_i: IN std_logic_vector(M-1 DOWNTO 0);
r_i: IN std_logic_vector(M-1 DOWNTO 0);
s_i: IN std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic;
valid_o: OUT std_logic;
sign_r_o: OUT std_logic_vector(M-1 DOWNTO 0);
sign_s_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Import entity e_uart_receive_mux
COMPONENT e_uart_receive_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
uart_i : IN std_logic;
mode_o : OUT std_logic;
r_o : OUT std_logic_vector(M-1 DOWNTO 0);
s_o : OUT std_logic_vector(M-1 DOWNTO 0);
m_o : OUT std_logic_vector(M-1 DOWNTO 0);
ready_o : OUT std_logic
);
END COMPONENT;
-- Import entity e_uart_transmit_mux
COMPONENT e_uart_transmit_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
enable_i : IN std_logic;
r_i : IN std_logic_vector(M-1 DOWNTO 0);
s_i : IN std_logic_vector(M-1 DOWNTO 0);
v_i : IN std_logic;
uart_o : OUT std_logic
);
END COMPONENT;
-- Internal signals -----------------------------------------
SIGNAL s_rst : std_logic;
-- ECDSA Entity
SIGNAL ecdsa_enable, ecdsa_mode, ecdsa_done, ecdsa_valid: std_logic := '0';
SIGNAL ecdsa_r_in, ecdsa_s_in, ecdsa_r_out, ecdsa_s_out, ecdsa_hash: std_logic_vector(M-1 DOWNTO 0);
BEGIN
-- Instantiate ecdsa entity
ecdsa: e_ecdsa PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
enable_i => ecdsa_enable,
mode_i => ecdsa_mode,
hash_i => ecdsa_hash,
r_i => ecdsa_r_in,
s_i => ecdsa_s_in,
ready_o => ecdsa_done,
valid_o => ecdsa_valid,
sign_r_o => ecdsa_r_out,
sign_s_o => ecdsa_s_out
);
-- Instantiate uart entity to receive data
uart_receive: e_uart_receive_mux PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
uart_i => uart_rx_i,
mode_o => ecdsa_mode,
r_o => ecdsa_r_in,
s_o => ecdsa_s_in,
m_o => ecdsa_hash,
ready_o => ecdsa_enable
);
-- Instantiate uart entity to send data
uart_transmit: e_uart_transmit_mux PORT MAP(
clk_i => clk_i,
rst_i => s_rst,
mode_i => ecdsa_mode,
enable_i => ecdsa_done,
r_i => ecdsa_r_out,
s_i => ecdsa_s_out,
v_i => ecdsa_valid,
uart_o => uart_wx_i
);
s_rst <= NOT rst_i;
rst_led <= s_rst;
END;
| gpl-3.0 | b630831f7e6688937edadb81e2eb9b80 | 0.470726 | 3.485714 | false | false | false | false |
Caian/Minesweeper | Projeto/minesweeper.vhd | 1 | 6,192 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity minesweeper is
port( clk27 : in std_logic;
rstn, rstg : in std_logic; --KEY[0]
vga_hsync, vga_vsync : out std_logic;
vga_r, vga_g, vga_b : out std_logic_vector(3 downto 0);
clk24 : in std_logic;
num_mines : in std_logic_vector(8 downto 0);
ps2_dat : inout std_logic;
ps2_clk : inout std_logic;
led : buffer std_logic_vector(3 downto 0);
display7_0, display7_1, display7_2, display7_3 : out std_logic_vector(6 downto 0)
);
end entity;
architecture minesweeper_logic of minesweeper is
signal vga_mem_clk: std_logic;
signal vga_mem_addr: std_logic_vector(10 downto 0);
signal vga_mem_q : std_logic_vector(7 downto 0);
signal ctrlu_clock: std_logic;
signal ctrlu_mem_addr: std_logic_vector(10 downto 0);
signal ctrlu_mem_d : std_logic_vector(7 downto 0);
signal ctrlu_mem_q : std_logic_vector(7 downto 0);
signal ctrlu_mem_wren: std_logic;
signal stack_data_in : std_logic_vector(13 downto 0);
signal stack_data_out : std_logic_vector(13 downto 0);
signal stack_mode : std_logic_vector(1 downto 0);
signal stack_empty : std_logic;
signal rng_enable : std_logic;
signal rng_x, rng_y : std_logic_vector(4 downto 0);
signal mouse_x, mouse_y : std_logic_vector(9 downto 0);
signal game_state : std_logic_vector(1 downto 0);
signal mdig1, mdig2, mdig3 : std_logic_vector(3 downto 0);
signal clock1 : std_logic;
signal tempo, minas : std_logic_vector(9 downto 0);
signal tdig1, tdig2, tdig3 : std_logic_vector(3 downto 0);
signal t_en : std_logic;
-- signal m_mode, m_en : std_logic;
signal flagcnt : std_logic_vector(10 downto 0);
signal ddig1, ddig2, ddig3 : std_logic_vector(3 downto 0);
begin
ctrlu_clock <= clk27;
------------------------------
-- Unidade de controle do jogo
CTRLU: game_ctrlunit
port map(
clock => ctrlu_clock, --clock27
rstn => rstn and rstg,
ram_wren => ctrlu_mem_wren,
ram_addr => ctrlu_mem_addr,
ram_data_in => ctrlu_mem_d,
ram_data_out => ctrlu_mem_q,
stack_data_in => stack_data_in,
stack_data_out => stack_data_out,
stack_mode => stack_mode,
stack_empty => stack_empty,
rng_enable => rng_enable,
rng_x => rng_x,
rng_y => rng_y,
timer_enable => t_en,
-- minecnt_enable => m_mode,
-- minecnt_mode => m_en,
flagcnt => flagcnt,
num_mines => num_mines,
game_state => game_state,
mouse_pos_x => mouse_x,
mouse_pos_y => 480 - mouse_y,
mouse_click_l => led(0),
mouse_click_r => led(1)
);
------------------------------------
-- Decodificador do número de bombas
BOMBAS: decoder port map(
entrada => flagcnt,
digito1 => mdig1,
digito2 => mdig2,
digito3 => mdig3
);
--------------------
-- Contador de minas
--MINA: counter port map(
-- clock => '1',
-- rstn => rstn,
-- enable => '0',
-- mode => '0',
-- cnt_out => minas
-- );
-------------------------------------------
-- Decodificador do número do tempo passado
TEMPO_IN: decoder port map(
entrada => '0' & tempo,
digito1 => tdig1,
digito2 => tdig2,
digito3 => tdig3
);
--------------------
-- Contador de tempo
RELOGIO: counter port map(
clock => clock1,
rstn => rstn and rstg,
enable => t_en,
-- mode => '1',
cnt_out => tempo
);
-------------------------------
-- Unidade de controle do mouse
MOUSE: ps2_mouse port map(
CLOCK_24 => "0" & clk24,
KEY => "000" & rstn,
PS2_DAT => ps2_dat,
PS2_CLK => ps2_clk,
Botoes => led(2 downto 0),
x_out => mouse_x,
y_out => mouse_y
);
-------------------------------------------
-- Decodificador do número inicial de minas
DISPLAY: decoder port map(
entrada => "00" & num_mines,
digito1 => ddig1,
digito2 => ddig2,
digito3 => ddig3
);
--------------------------
-- Displays de 7 segmentos
DISPLAY0: bcd7seg port map(
entrada => ddig3,
saida => display7_0
);
DISPLAY1: bcd7seg port map(
entrada => ddig2,
saida => display7_1
);
DISPLAY2: bcd7seg port map(
entrada => ddig1,
saida => display7_2
);
DISPLAY3: bcd7seg port map(
entrada => "1111",
saida => display7_3
);
---------------------------------------
-- Gerador de numeros pseudo aleatorios
PRNG: game_lfsr port map(
clock => ctrlu_clock,
rstn => rstn and rstg,
enabled => rng_enable,
mouse_pos_x => mouse_x,
mouse_pos_y => mouse_y,
random_x => rng_x,
random_y => rng_y
);
--------------------
-- Memoria principal
MAINRAM: ram port map(
address_a => ctrlu_mem_addr,
address_b => vga_mem_addr,
clock_a => ctrlu_clock,
clock_b => vga_mem_clk,
data_a => ctrlu_mem_d,
data_b => "00000000",
wren_a => ctrlu_mem_wren,
wren_b => '0',
q_a => ctrlu_mem_q,
q_b => vga_mem_q
);
--------------------
-- Pilha da recursao
STEAK: stack port map(
enable => '1',
rstn => rstn,
clock => ctrlu_clock,
mode => stack_mode,
data => stack_data_in,
empty => stack_empty,
q => stack_data_out
);
-----------------------
-- Controlador de video
VGASYS: vga port map (
clk_27Mhz => clk27,
rstn => rstn,
main_mem_clk => vga_mem_clk,
main_mem_addr => vga_mem_addr,
main_mem_data => vga_mem_q,
mouse_pos_x => mouse_x,
mouse_pos_y => 480 - mouse_y,
mouse_click_l => led(0),
time_u => mdig3,
time_d => mdig2,
time_c => mdig1,
mine_u => tdig3,
mine_d => tdig2,
mine_c => tdig1,
game_state => game_state,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
--------------------------
-- Gerador de clock de 1Hz
CNT1HZ: game_timeclock port map (
clk24 => clk24,
rstn => rstn,
clk1 => clock1
);
end;
| gpl-2.0 | 9c711699b309cd939579c7637c156667 | 0.543928 | 2.926276 | false | false | false | false |
lennartbublies/ecdsa | src/e_ecdsa.vhd | 1 | 19,102 | ----------------------------------------------------------------------------------------------------
-- TOP LEVEL ENTITY - ECDSA
-- FPDA implementation of ECDSA algorithm
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable sign or verify
-- mode_i - Switch between sign (0) and verify (1)
-- hash_i - Input hash for sign/verify
-- r_i - R part of signature for verify step
-- s_i - S part of signature for verify step
-- ready_o - Ready flag if sign or validation is complete
-- valid_o - True if signature is valid
-- sign_r_o - R part of signature after sign
-- sign_s_o - S part of signature after sign
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 02.07.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) ecdsa top level entity
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_ecdsa IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Enable computation
enable_i: IN std_logic;
-- Switch between SIGN and VALIDATE
mode_i: IN std_logic;
-- Hash
hash_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Signature
r_i: IN std_logic_vector(M-1 DOWNTO 0);
s_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Ready flag
ready_o: OUT std_logic;
-- Signature valid
valid_o: OUT std_logic;
-- Signature
sign_r_o: OUT std_logic_vector(M-1 DOWNTO 0);
sign_s_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_ecdsa;
ARCHITECTURE rtl OF e_ecdsa IS
-- Components -----------------------------------------
-- Import entity e_gf2m_doubleadd_point_multiplication
--COMPONENT e_gf2m_point_multiplication IS
COMPONENT e_gf2m_doubleadd_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_point_addition
COMPONENT e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_eea_inversion
COMPONENT e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Internal signals -----------------------------------------
--SIGNAL xG : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- X of generator point G = (x, y)
--SIGNAL yG : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Y of generator point G = (x, y)
--SIGNAL dA : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Private key dA = k
-- Parameter to sign a message, ONLY FOR TESTING!
--SIGNAL k : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- k for point generator, should be cryptograic secure randum number!
--SIGNAL xQB : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- X component of public key qB = dB.G = (xQB, yQB)
--SIGNAL yQB : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Y component of public key qB = dB.G = (xQB, yQB)
-- MODE SIGN
SIGNAL xR : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- X component of point R
SIGNAL yR : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Y component of point R
SIGNAL xrda, e_xrda, s : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Temporary results for signature computation
SIGNAL enable_sign_r, done_sign_r: std_logic := '0'; -- Enable/Disable signature computation
SIGNAL enable_sign_darx, done_sign_darx: std_logic := '0';
SIGNAL enable_sign_z2k, done_sign_z2k: std_logic := '0';
-- MODE VERIFY
SIGNAL w : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL U1, U2 : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL enable_verify_invs, done_verify_invs : std_logic := '0';
SIGNAL enable_verify_u12, done_verify_u1, done_verify_u2 : std_logic := '0';
SIGNAL enable_verify_u1gu2qb, done_verify_u1g, done_verify_u2qb : std_logic := '0';
SIGNAL enable_verify_P, done_verify_P : std_logic := '0';
SIGNAL xGU1, yGU1 : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL xQBU2, yQBU2 : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL xP, yP : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
-- Constantsenable_verify_u12
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
-- States for state machine
subtype states IS natural RANGE 0 TO 19;
SIGNAL current_state: states;
BEGIN
-- SIGN -----------------------------------------------------------------
-- Instantiate multiplier to compute R = k.G = (xR, yR)
--sign_pmul_r: e_gf2m_point_multiplication GENERIC MAP (
sign_pmul_r: e_gf2m_doubleadd_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_sign_r,
xp_i => xG,
yp_i => yG,
k => k,
xq_io => xR,
yq_io => yR,
ready_o => done_sign_r
);
-- Instantiate multiplier entity to compute dA * xR
sign_mul_darx: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_sign_darx,
a_i => dA,
b_i => xR,
z_o => xrda,
ready_o => done_sign_darx
);
-- compute e + (dA * xR)
sign_add_edarx: FOR i IN 0 TO M-1 GENERATE
e_xrda(i) <= xrda(i) xor hash_i(i);
END GENERATE;
-- Instantiate divider entity to compute (e + dA*xR)/k
sign_divide_edarx_k: e_gf2m_divider GENERIC MAP (
MODULO => P
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_sign_z2k,
g_i => e_xrda,
h_i => k,
z_o => s,
ready_o => done_sign_z2k
);
sign_r_o <= xR;
sign_s_o <= s;
-- VALIDATE -----------------------------------------------------------------
-- Instantiate inversion entity to compute w = 1/s
verify_invs: e_gf2m_eea_inversion GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_invs,
a_i => s_i,
z_o => w,
ready_o => done_verify_invs
);
-- Instantiate multiplier entity to compute u1 = ew
verify_mul_u1: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_u12,
a_i => hash_i,
b_i => w,
z_o => U1,
ready_o => done_verify_u1
);
-- Instantiate multiplier entity to compute u2 = rw
verify_mul_u2: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_u12,
a_i => r_i,
b_i => w,
z_o => U2,
ready_o => done_verify_u2
);
-- Instantiate multiplier to compute tmp6 = u1.G
--verify_pmul_u1gu2q: e_gf2m_point_multiplication GENERIC MAP (
verify_pmul_u1gu2q: e_gf2m_doubleadd_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_u1gu2qb,
xp_i => xG,
yp_i => yG,
k => U1,
xq_io => xGU1,
yq_io => yGU1,
ready_o => done_verify_u1g
);
-- Instantiate multiplier to compute tmp7 = u2.QB
--verify_pmul_u1gu2qb: e_gf2m_point_multiplication GENERIC MAP (
verify_pmul_u1gu2qb: e_gf2m_doubleadd_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_u1gu2qb,
xp_i => xQB,
yp_i => yQB,
k => U2,
xq_io => xQBU2,
yq_io => yQBU2,
ready_o => done_verify_u2qb
);
-- Instantiate point addition entity to compute (xP, yP) = t1+t2
verify_adder_u1gu2qb: e_gf2m_point_addition GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_verify_P,
x1_i => xGU1,
y1_i => yGU1,
x2_i => xQBU2,
y2_i => yQBU2,
x3_io => xP,
y3_o => yP,
ready_o => done_verify_P
);
-- State machine process
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : SIGN -> compute R = k.G = (xR, yR)
-- 4,5 : SIGN -> compute xrda = dA*xR, e_xrda = e+xrda
-- 6-8 : SIGN -> compute S = e_xrda/k
-- ---> SIGN DONE
-- 9,10 : VERIFY -> compute 1/S
-- 11,12 : VERIFY -> compute u1 = ew and u2 = rw
-- 13,14 : VERIFY -> compute z1=u1.G and z2=u2.xQB
-- 15-17 : VERFIY -> compute v=z1+z2, valid if v=r
-- 18,19 : VERIFY SUCCESSFULL
CASE current_state IS
WHEN 0 TO 1 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '1'; valid_o <= '0';
WHEN 2 => enable_sign_r <= '1'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 3 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 4 => enable_sign_r <= '0'; enable_sign_darx <= '1'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 5 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 6 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '1'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 7 TO 8 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 9 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '1'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 10 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 11 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '1'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 12 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 13 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '1'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 14 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 15 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '1'; ready_o <= '0'; valid_o <= '0';
WHEN 16 TO 17 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '0'; valid_o <= '0';
WHEN 18 TO 19 => enable_sign_r <= '0'; enable_sign_darx <= '0'; enable_sign_z2k <= '0'; enable_verify_invs <= '0'; enable_verify_u12 <= '0'; enable_verify_u1gu2qb <= '0'; enable_verify_P <= '0'; ready_o <= '1'; valid_o <= '1';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
-- SIGN
WHEN 1 =>
IF (enable_i = '1' and mode_i = '0') THEN
current_state <= 2;
ELSIF (enable_i = '1' and mode_i = '1') THEN
current_state <= 9;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (done_sign_r = '1') THEN
-- Validate R: restart if R = 0
--IF (xR = ZERO) THEN -- NECESSARY IF K IS RANDOM VALUE!
-- current_state <= 2;
--ELSE
current_state <= 4;
--END IF;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF (done_sign_darx = '1') THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF (done_sign_z2k = '1') THEN
current_state <= 8;
END IF;
WHEN 8 =>
-- Validate S: restart if S = 0
--IF (s = ZERO) THEN
-- current_state <= 2;
--ELSE
current_state <= 0;
--END IF;
-- VALIDATE
WHEN 9 =>
current_state <= 10;
WHEN 10 =>
IF (done_verify_invs = '1') THEN
current_state <= 11;
END IF;
WHEN 11 =>
current_state <= 12;
WHEN 12 =>
IF (done_verify_u1 = '1' and done_verify_u2 = '1') THEN
current_state <= 13;
END IF;
WHEN 13 =>
current_state <= 14;
WHEN 14 =>
IF (done_verify_u1g = '1' and done_verify_u2qb = '1') THEN
current_state <= 15;
END IF;
WHEN 15 =>
current_state <= 16;
WHEN 16 =>
IF (done_verify_P = '1') THEN
current_state <= 17;
END IF;
WHEN 17 =>
IF (xP = r_i) THEN
current_state <= 18;
ELSE
current_state <= 0;
END IF;
-- Valid
WHEN 18 =>
IF enable_i = '0' THEN
current_state <= 19;
END IF;
WHEN 19 =>
IF (enable_i = '1' and mode_i = '0') THEN
current_state <= 2;
ELSIF (enable_i = '1' and mode_i = '1') THEN
current_state <= 9;
END IF;
END CASE;
END IF;
END PROCESS;
END; | gpl-3.0 | d4aeb23ff134bfd3e7612d80d2a5fbb1 | 0.477594 | 3.409854 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/LUTROM/simulation/LUTROM_synth.vhd | 1 | 6,818 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUTROM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY LUTROM_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE LUTROM_synth_ARCH OF LUTROM_synth IS
COMPONENT LUTROM_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: LUTROM_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | 70d641855784992c0da86f4feb93fd72 | 0.580229 | 3.817469 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/datapath.vhd | 1 | 4,884 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-05-2016
-- Module Name: datapath.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity datapath is
port (clk: in std_logic);
end entity;
architecture structural of datapath is
component ALU is
port (A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0);
OP : in std_logic_vector (3 downto 0);
func : in std_logic_vector (2 downto 0);
result : out std_logic_vector (15 downto 0);
cond : out std_logic);
end component;
component control
port (clk : in std_logic;
cond : in std_logic;
op : in std_logic_vector (3 downto 0);
PCen : out std_logic;
PCwrite : out std_logic;
IorD : out std_logic_vector (1 downto 0);
memread : out std_logic;
memwrite : out std_logic;
memtoreg : out std_logic_vector (1 downto 0);
IRe : out std_logic;
PCscr : out std_logic_vector (1 downto 0);
ALUop : out std_logic_vector (3 downto 0);
ALUsrcB : out std_logic_vector (1 downto 0);
ALUsrcA : out std_logic_vector (1 downto 0);
AluFunc : out std_logic_vector (1 downto 0);
regdest : out std_logic_vector (1 downto 0);
regwrite : out std_logic);
end component;
component memory
port (address : in std_logic_vector (15 downto 0);
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
clk, read, write : in std_logic);
end component;
component regfile
generic (N : integer := 3;
M : integer := 16);
port (readaddr1, readaddr2 : in std_logic_vector (N - 1 downto 0);
writeaddr : in std_logic_vector (N - 1 downto 0);
data : in std_logic_vector (M - 1 downto 0);
write, clk : in std_logic;
O1, O2 : out std_logic_vector (M - 1 downto 0));
end component;
component register_N
generic (N : integer := 16);
port (reset, clk, load : in std_logic;
ldata : in std_logic_vector (N - 1 downto 0);
O : out std_logic_vector (N - 1 downto 0));
end component;
component mux4
generic (N : integer := 16);
port (I00, I01, I10, I11 : in std_logic_vector (N - 1 downto 0);
O : out std_logic_vector (N - 1 downto 0);
S : in std_logic_vector (1 downto 0));
end component;
for all:mux4 use entity work.mux4;
for all:register_N use entity work.register_N;
for all:memory use entity work.memory;
for all:regfile use entity work.regfile;
for all:control use entity work.control;
for all:ALU use entity work.ALU;
signal tmp1,tmp2,tmp3,tmp4,tmp5, tmp6 :std_logic_vector(15 downto 0);
signal PCen, memread, memwrite, IRe, regWrite,cond,PCenOrCond, PCwrite : std_logic;
signal pcInput, pcOutput, outOfAlu, Aout, Bout, AluOutIn, memoryIn : std_logic_vector (15 downto 0);
signal AluA, AluB, writeData, writeRegister, Ain, Bin,memoryDataIn : std_logic_vector (15 downto 0);
signal IRIn, IROut, FuncOfAlu : std_logic_vector (15 downto 0);
signal IorD, regDst, memToReg, AluSrcA, AluSrcB, AluFunc,pcSrc:std_logic_vector (1 downto 0);
signal op: std_logic_vector (3 downto 0);
begin
tmp1 <= "0000000000000" & IROut(8 downto 6);
tmp2 <= "0000000000000" & IROut(5 downto 3);
tmp3 <= "0000" & IROut(11 downto 0);
tmp4 <= "0000000000" & IROut(5 downto 0);
tmp5 <= "0000000000000" & IROut(2 downto 0);
PCenOrCond <= PCen or (cond and PCwrite);
mem : memory port map (memoryIn, Bout, IRIn, clk, memread, memwrite);
m1 : mux4 port map (pcOutput, outOfAlu, (others => '0'), (others => '0'), memoryIn, IorD);
m2 : mux4 port map (outOfAlu, IRIn, (others => '0'), (others => '0'), writeData, memToReg);
m3 : mux4 port map (tmp1, tmp2, (others => '0'), (others => '0'), writeRegister, regDst);
m4 : mux4 port map (pcOutput, Aout, (others => '0'), (others => '0'), AluA, AluSrcA);
m5 : mux4 port map (Bout, "0000000000000001", tmp4, (others => '0'), AluB, AluSrcB);
m6 : mux4 port map (AluOutIn, outOfAlu, tmp3, (others => '0'), pcInput, pcSrc);
outOfAlu <= AluOutIn;
IR : register_N port map ('0' ,clk, IRe, IRIn, IROut);
pc : register_N port map ('0' ,clk, PCenOrCond, pcInput, pcOutput);
A : register_N port map ('0' ,clk, '1', Ain, Aout);
B : register_N port map ('0' ,clk, '1', Bin, Bout);
cu : control port map (clk, cond, IROut(15 downto 12), PCen,PCwrite, IorD, memread, memwrite, memtoreg, IRe, PCsrc, op, ALUsrcB, ALUsrcA, AluFunc, regdst, regwrite);
registerFile : regfile port map (IROut(11 downto 9), IROut(8 downto 6), writeRegister(2 downto 0), writeData, regWrite, clk, Ain,Bin);
mux7foralufunc: mux4 port map ((others => '0'), tmp5, (others => '0'), (others => '0'), FuncOfAlu, AluFunc);
au : ALU port map (AluA, AluB, op, FuncOfAlu(2 downto 0), AluOutIn, cond);
end architecture;
| gpl-3.0 | 88fac48b508c8f686682676af2a79781 | 0.633292 | 3.085281 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s4/moore/moore.vhd | 1 | 1,269 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 29-02-2016
-- Module Name: moore.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity moore is
port (d, clk, reset : in std_logic;
z : out std_logic);
end entity moore;
architecture arch_moore of moore is
type state is (S0, S1, S2, S3, S4);
signal current : state := S0;
begin
process (clk, reset)
begin
if reset = '1' then
current <= S0;
end if;
if clk = '1' and clk'event then
case current is
when S0 =>
if d = '0' then
current <= S0;
else
current <= S1;
end if;
when S1 =>
if d = '0' then
current <= S2;
else
current <= S0;
end if;
when S2 =>
if d = '1' then
current <= S3;
else
current <= S0;
end if;
when S3 =>
if d = '0' then
current <= S2;
else
current <= S4;
end if;
when S4 =>
if d = '0' then
current <= S1;
else
current <= S2;
end if;
end case;
end if;
end process;
z <= '1' when current = S4 else '0';
end architecture arch_moore;
| gpl-3.0 | af72755edadc419793b8dc8e34e379ab | 0.469661 | 3.117936 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/rx_path_input_queue.vhd | 2 | 18,944 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 16:32:15
-- Design Name: rx_path_input_queue.vhd
-- Module Name: rx_path_input_queue - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- Input frame scheduling consisting of 5 submodules:
-- input_queue_control: receive frames and line in queue, remove error-frames
-- input_queue_memory: store the received frames
-- input_queue_fifo: store memory pointer, frame length and output ports of the frames located in the memory
-- depending on needs one fifo or two priority fifos can be selected
-- input_queue_overflow: checks for memory overflow and fifo overflow
-- input_queue_scheduling: decide which frame to offer next to switch fabric and control frame transmission
-- depending on NR_IQ_FIFOS priority behaviour (NR_IQ_FIFOS = 2) or best effort (NR_IQ_FIFOS = 1) is considered
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rx_path_input_queue is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_MEM_ADDR_WIDTH_A : integer := 12;
IQ_MEM_ADDR_WIDTH_B : integer := 10 -- 8 bit: 12, 32 bit: 10
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface data
iq_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iq_in_mac_valid : in std_logic;
iq_in_mac_last : in std_logic;
iq_in_mac_error : in std_logic;
-- input interface control
iq_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iq_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_in_lu_skip : in std_logic;
iq_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_in_lu_valid : in std_logic;
-- output interface arbitration
iq_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iq_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iq_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iq_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iq_out_last : out std_logic;
iq_out_valid : out std_logic
);
end rx_path_input_queue;
architecture structural of rx_path_input_queue is
-- memory and fifo data constants
constant IQ_MEM_DATA_WIDTH_RATIO : integer := FABRIC_DATA_WIDTH / RECEIVER_DATA_WIDTH;
constant IQ_FIFO_DATA_WIDTH : integer := VLAN_PRIO_WIDTH+FRAME_LENGTH_WIDTH+TIMESTAMP_WIDTH+NR_PORTS+IQ_MEM_ADDR_WIDTH_A;
-- fifo address constants
constant IQ_FIFO_PRIO_START : integer := 0;
constant IQ_FIFO_FRAME_LEN_START : integer := IQ_FIFO_PRIO_START + VLAN_PRIO_WIDTH;
constant IQ_FIFO_TIMESTAMP_START : integer := IQ_FIFO_FRAME_LEN_START + FRAME_LENGTH_WIDTH;
constant IQ_FIFO_PORTS_START : integer := IQ_FIFO_TIMESTAMP_START + TIMESTAMP_WIDTH;
constant IQ_FIFO_MEM_PTR_START : integer := IQ_FIFO_PORTS_START + NR_PORTS;
component input_queue_control is
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
IQ_FIFO_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface mac
iqctrl_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iqctrl_in_mac_valid : in std_logic;
iqctrl_in_mac_last : in std_logic;
iqctrl_in_mac_error : in std_logic;
-- input interface lookup
iqctrl_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iqctrl_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqctrl_in_lu_skip : in std_logic;
iqctrl_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqctrl_in_lu_valid : in std_logic;
-- output interface memory
iqctrl_out_mem_wenable : out std_logic;
iqctrl_out_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
iqctrl_out_mem_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
-- output interface fifo
iqctrl_out_fifo_wenable : out std_logic;
iqctrl_out_fifo_data : out std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0)
);
end component;
component input_queue_memory is
Generic (
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
IQ_MEM_DATA_WIDTH_IN : integer;
IQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
iqmem_in_wenable : in std_logic_vector;
iqmem_in_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
iqmem_in_data : in std_logic_vector(IQ_MEM_DATA_WIDTH_IN-1 downto 0);
iqmem_in_clk : in std_logic;
iqmem_out_enable : in std_logic;
iqmem_out_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqmem_out_data : out std_logic_vector(IQ_MEM_DATA_WIDTH_OUT-1 downto 0);
iqmem_out_clk : in std_logic
);
end component;
component input_queue_fifo is
Generic (
IQ_FIFO_DATA_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
wr_priority : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rd_en : in std_logic;
overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
dout : out std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
rd_priority : in std_logic;
full : out std_logic_vector(NR_IQ_FIFOS-1 downto 0);
empty : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end component;
component input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end component;
component input_queue_arbitration is
Generic(
FABRIC_DATA_WIDTH : integer;
IQ_FIFO_DATA_WIDTH : integer;
NR_PORTS : integer;
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
NR_IQ_FIFOS : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface memory
iqarb_in_mem_enable : out std_logic;
iqarb_in_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqarb_in_mem_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- input interface fifo
iqarb_in_fifo_enable : out std_logic;
iqarb_in_fifo_prio : out std_logic;
iqarb_in_fifo_data : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
iqarb_in_fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
iqarb_in_fifo_overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
-- output interface arbitration
iqarb_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iqarb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqarb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqarb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iqarb_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iqarb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iqarb_out_last : out std_logic;
iqarb_out_valid : out std_logic
);
end component;
signal iqctrl2iqmem_data : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal iqctrl2iqmem_wenable : std_logic_vector(0 downto 0);
signal iqctrl2iqmem_addr : std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal iqctrl2iqfifo_wenable : std_logic;
signal iqctrl2iqfifo_data : std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0);
signal iqfifo2iqarb_renable : std_logic;
signal iqfifo2iqarb_data : std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
signal iqfifo2iqarb_prio : std_logic;
signal iqfifo2iqarb_empty : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqfifo2iqovfl_full : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqovfl2iqarb_overflow : std_logic_vector(NR_IQ_FIFOS-1 downto 0);
signal iqmem2iqarb_data : std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
signal iqmem2iqarb_enable : std_logic;
signal iqmem2iqarb_addr : std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
-- attribute mark_debug : string;
-- attribute mark_debug of iqctrl2iqmem_data : signal is "true";
-- attribute mark_debug of iqctrl2iqmem_wenable : signal is "true";
-- attribute mark_debug of iqctrl2iqmem_addr : signal is "true";
-- attribute mark_debug of iqctrl2iqfifo_wenable : signal is "true";
-- attribute mark_debug of iqctrl2iqfifo_data : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_renable : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_data : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_empty : signal is "true";
-- attribute mark_debug of iqfifo2iqarb_overflow : signal is "true";
-- attribute mark_debug of iqmem2iqarb_data : signal is "true";
-- attribute mark_debug of iqmem2iqarb_enable : signal is "true";
-- attribute mark_debug of iqmem2iqarb_addr : signal is "true";
begin
iq_control : input_queue_control
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
IQ_MEM_ADDR_WIDTH => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_DATA_WIDTH_RATIO => IQ_MEM_DATA_WIDTH_RATIO,
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
IQ_FIFO_PRIO_START => IQ_FIFO_PRIO_START,
IQ_FIFO_FRAME_LEN_START => IQ_FIFO_FRAME_LEN_START,
IQ_FIFO_TIMESTAMP_START => IQ_FIFO_TIMESTAMP_START,
IQ_FIFO_PORTS_START => IQ_FIFO_PORTS_START,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START
)
Port map(
clk => clk,
reset => reset,
-- input interface mac
iqctrl_in_mac_data => iq_in_mac_data,
iqctrl_in_mac_valid => iq_in_mac_valid,
iqctrl_in_mac_last => iq_in_mac_last,
iqctrl_in_mac_error => iq_in_mac_error,
-- input interface lookup
iqctrl_in_lu_ports => iq_in_lu_ports,
iqctrl_in_lu_prio => iq_in_lu_prio,
iqctrl_in_lu_skip => iq_in_lu_skip,
iqctrl_in_lu_timestamp => iq_in_lu_timestamp,
iqctrl_in_lu_valid => iq_in_lu_valid,
-- output interface memory
iqctrl_out_mem_wenable => iqctrl2iqmem_wenable(0),
iqctrl_out_mem_addr => iqctrl2iqmem_addr,
iqctrl_out_mem_data => iqctrl2iqmem_data,
-- output interface fifo
iqctrl_out_fifo_wenable => iqctrl2iqfifo_wenable,
iqctrl_out_fifo_data => iqctrl2iqfifo_data
);
iq_mem : input_queue_memory
Generic map(
IQ_MEM_ADDR_WIDTH_A => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_ADDR_WIDTH_B => IQ_MEM_ADDR_WIDTH_B,
IQ_MEM_DATA_WIDTH_IN => RECEIVER_DATA_WIDTH,
IQ_MEM_DATA_WIDTH_OUT => FABRIC_DATA_WIDTH
)
Port map(
--Port A -> Control module
iqmem_in_wenable => iqctrl2iqmem_wenable,
iqmem_in_addr => iqctrl2iqmem_addr,
iqmem_in_data => iqctrl2iqmem_data,
iqmem_in_clk => clk,
--Port B -> Scheduling moudle
iqmem_out_enable => iqmem2iqarb_enable,
iqmem_out_addr => iqmem2iqarb_addr,
iqmem_out_data => iqmem2iqarb_data,
iqmem_out_clk => clk
);
iq_fifo : input_queue_fifo
Generic map(
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH
)
Port map(
clk => clk,
reset => reset,
wr_en => iqctrl2iqfifo_wenable,
din => iqctrl2iqfifo_data,
wr_priority => iqctrl2iqfifo_data(IQ_FIFO_PRIO_START+VLAN_PRIO_WIDTH-1 downto IQ_FIFO_PRIO_START),
rd_en => iqfifo2iqarb_renable,
overflow => iqovfl2iqarb_overflow,
dout => iqfifo2iqarb_data,
rd_priority => iqfifo2iqarb_prio,
full => iqfifo2iqovfl_full,
empty => iqfifo2iqarb_empty
);
iq_overflow : input_queue_overflow
Generic map(
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
IQ_MEM_ADDR_WIDTH => IQ_MEM_ADDR_WIDTH_A,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START,
NR_IQ_FIFOS => NR_IQ_FIFOS
)
Port map(
fifo_full => iqfifo2iqovfl_full,
fifo_empty => iqfifo2iqarb_empty,
mem_wr_addr => iqctrl2iqmem_addr,
mem_rd_addr => iqfifo2iqarb_data,
overflow => iqovfl2iqarb_overflow
);
iq_arbitration : input_queue_arbitration
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
IQ_FIFO_DATA_WIDTH => IQ_FIFO_DATA_WIDTH,
NR_PORTS => NR_PORTS,
IQ_MEM_ADDR_WIDTH_A => IQ_MEM_ADDR_WIDTH_A,
IQ_MEM_ADDR_WIDTH_B => IQ_MEM_ADDR_WIDTH_B,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
IQ_FIFO_PRIO_START => IQ_FIFO_PRIO_START,
IQ_FIFO_FRAME_LEN_START => IQ_FIFO_FRAME_LEN_START,
IQ_FIFO_TIMESTAMP_START => IQ_FIFO_TIMESTAMP_START,
IQ_FIFO_PORTS_START => IQ_FIFO_PORTS_START,
IQ_FIFO_MEM_PTR_START => IQ_FIFO_MEM_PTR_START,
IQ_MEM_DATA_WIDTH_RATIO => IQ_MEM_DATA_WIDTH_RATIO,
NR_IQ_FIFOS => NR_IQ_FIFOS
)
Port map(
clk => clk,
reset => reset,
-- input interface memory
iqarb_in_mem_enable => iqmem2iqarb_enable,
iqarb_in_mem_addr => iqmem2iqarb_addr,
iqarb_in_mem_data => iqmem2iqarb_data,
-- input interface fifo
iqarb_in_fifo_enable => iqfifo2iqarb_renable,
iqarb_in_fifo_prio => iqfifo2iqarb_prio,
iqarb_in_fifo_data => iqfifo2iqarb_data,
iqarb_in_fifo_empty => iqfifo2iqarb_empty,
iqarb_in_fifo_overflow => iqovfl2iqarb_overflow,
-- output interface arbitration
iqarb_out_ports_req => iq_out_ports_req,
iqarb_out_prio => iq_out_prio,
iqarb_out_timestamp => iq_out_timestamp,
iqarb_out_length => iq_out_length,
iqarb_out_ports_gnt => iq_out_ports_gnt,
-- output interface data
iqarb_out_data => iq_out_data,
iqarb_out_last => iq_out_last,
iqarb_out_valid => iq_out_valid
);
end structural;
| mit | 901643ea3035eb9d83ca8fd23fbba499 | 0.54128 | 3.718155 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/aeg_design_switch_port.vhd | 2 | 23,193 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 13:56:52
-- Design Name:
-- Module Name: aeg_design_0_switch_port
-- Description: This module describes one port for the Ethernet switch
-- It consists of:
-- - The rx_path: the logic processing the received data before
-- sending to the fabric
-- - The tx_path: the logic receiving data from the fabric and
-- handling the transmission of frames
-- - The TEMAC receives/sends frames
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity aeg_design_0_switch_port is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end aeg_design_0_switch_port;
architecture rtl of aeg_design_0_switch_port is
component tri_mode_ethernet_mac_block
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end component;
component config_mac_phy_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end component;
component switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
PORT_ID : integer
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
component switch_port_tx_path is
Generic (
FABRIC_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
-- tx_path interface to fabric
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- timestamp
tx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_out_latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- tx_path interface to mac
tx_out_data : out std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_out_valid : out std_logic;
tx_out_ready : in std_logic;
tx_out_last : out std_logic
);
end component;
signal mac2rx_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal mac2rx_valid_sig : std_logic;
signal mac2rx_last_sig : std_logic;
signal mac2rx_error_sig : std_logic;
signal tx2mac_data_sig : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
signal tx2mac_valid_sig : std_logic;
signal tx2mac_ready_sig : std_logic;
signal tx2mac_last_sig : std_logic;
signal s_axi_awaddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_awvalid : std_logic := '0';
signal s_axi_awready : std_logic := '0';
signal s_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_wvalid : std_logic := '0';
signal s_axi_wready : std_logic := '0';
signal s_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_bvalid : std_logic := '0';
signal s_axi_bready : std_logic := '0';
signal s_axi_araddr : std_logic_vector(11 downto 0) := (others => '0');
signal s_axi_arvalid : std_logic := '0';
signal s_axi_arready : std_logic := '0';
signal s_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal s_axi_rvalid : std_logic := '0';
signal s_axi_rready : std_logic := '0';
signal mac_interrupt : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of mac2rx_data_sig : signal is "true";
-- attribute mark_debug of mac2rx_valid_sig : signal is "true";
-- attribute mark_debug of mac2rx_last_sig : signal is "true";
-- attribute mark_debug of mac2rx_error_sig : signal is "true";
begin
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_block : tri_mode_ethernet_mac_block
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
-- Receiver => AXI-S Interface
------------------------------------------
mac_out_clock => rx_path_clock,
mac_out_resetn => rx_path_resetn,
mac_out_data => mac2rx_data_sig,
mac_out_valid => mac2rx_valid_sig,
mac_out_last => mac2rx_last_sig,
mac_out_error => mac2rx_error_sig,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter => AXI-S Interface
---------------------------------------------
mac_in_clock => tx_path_clock,
mac_in_resetn => tx_path_resetn,
mac_in_data => tx2mac_data_sig,
mac_in_valid => tx2mac_valid_sig,
mac_in_ready => tx2mac_ready_sig,
mac_in_last => tx2mac_last_sig,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- GMII Interface
-------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_interrupt => mac_interrupt
);
config_mac_phy : config_mac_phy_sm
port map(
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
phy_interrupt_n => phy_interrupt_n,
mac_interrupt => mac_interrupt,
mac_speed => "01",
update_speed => '0',
serial_command => '0',
serial_response => open,
debug0_sig => debug0_sig,
debug1_sig => debug1_sig,
debug2_sig => debug2_sig,
debug3_sig => debug3_sig,
-- AXI-Lite Interface
-----------
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
rx_path : switch_port_rx_path
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
PORT_ID => PORT_ID
)
Port map(
rx_path_clock => rx_path_clock,
rx_path_resetn => rx_path_resetn,
-- mac to rx_path interface
rx_in_data => mac2rx_data_sig,
rx_in_valid => mac2rx_valid_sig,
rx_in_last => mac2rx_last_sig,
rx_in_error => mac2rx_error_sig,
rx_in_timestamp_cnt => timestamp_cnt,
-- rx_path interface to fabric
rx_out_data => rx_out_data,
rx_out_valid => rx_out_valid,
rx_out_last => rx_out_last,
rx_out_ports_req => rx_out_ports_req,
rx_out_prio => rx_out_prio,
rx_out_timestamp => rx_out_timestamp,
rx_out_length => rx_out_length,
rx_out_ports_gnt => rx_out_ports_gnt
);
tx_path : switch_port_tx_path
Generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
tx_path_clock => tx_path_clock,
tx_path_resetn => tx_path_resetn,
-- tx_path interface to fabric
tx_in_data => tx_in_data,
tx_in_valid => tx_in_valid,
tx_in_length => tx_in_length,
tx_in_prio => tx_in_prio,
tx_in_timestamp => tx_in_timestamp,
tx_in_req => tx_in_req,
tx_in_accept_frame => tx_in_accept_frame,
-- timestamp
tx_in_timestamp_cnt => timestamp_cnt,
tx_out_latency => latency,
-- tx_path interface to mac
tx_out_data => tx2mac_data_sig,
tx_out_valid => tx2mac_valid_sig,
tx_out_ready => tx2mac_ready_sig,
tx_out_last => tx2mac_last_sig
);
end rtl;
| mit | 7dc7deea341d9e975e5797f58a41b624 | 0.457509 | 3.764486 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | priority-updater/src/counter.vhd | 1 | 930 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: counter.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (number : out std_logic_vector (N - 1 downto 0) := (others => '0');
clk, r, en : in std_logic);
end entity counter;
architecture behavioral of counter is
begin
process (clk, r)
variable old_number : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
if r = '1' then
number <= (others => '0');
old_number := (others => '0');
elsif clk = '1' and clk'event and en = '1' then
number <= old_number;
old_number := old_number + (0 => '1');
end if;
end process;
end architecture behavioral;
| gpl-3.0 | f1055550992584cc47adb524c2934d00 | 0.52043 | 3.522727 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sim_1/imports/simulation/aeg_64_byte_full_load_tb.vhd | 2 | 25,342 | --------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project :
--------------------------------------------------------------------------------
-- File : aeg_64_byte_full_load_tb.vhd
-- -----------------------------------------------------------------------------
--
-- This testbench performs the following operations:
--
-- 256 Frames a pushed into the receiver from the PHY interface (GMII).
-- Their destination MAC addresses are in range FF:00:00:00:00:00 to FF:00:00:00:00:FF
-- Each frame is 64 Byte in size and frames are inserted back to back (after the
-- minimum interframe gap)
-- These insertions are done by the stimulus process.
-- The monitor process observes the messages coming out of the transmitter side of
-- the switch and compare to the data expected
-- The lookup module skips every forth frame as it is not in the lookup memory
-- FF:00:00:00:00:FE has an error and should be skipped
entity aeg_64_byte_full_load_tb is
end aeg_64_byte_full_load_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_64_byte_full_load_tb is
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ := (
columns => (
0 => ( DATA => X"FF", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"00", VALID => '1', ERROR => '0'),
2 => ( DATA => X"00", VALID => '1', ERROR => '0'),
3 => ( DATA => X"00", VALID => '1', ERROR => '0'),
4 => ( DATA => X"00", VALID => '1', ERROR => '0'),
5 => ( DATA => X"00", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')
)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_reset : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
management_config_finished <= true;
-- wait for 167.8 us;
-- mac_reset;
wait;
end process p_reset;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to 255 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = 254 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to 253 loop
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end loop;
-- provoking an error to see if tb works correctly
check_frame_1g(255);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
| mit | 79f8c9c82a9a31fe57ee7384fe21c2a4 | 0.458093 | 4.080837 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_3_funcsim.vhdl | 1 | 192,261 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:33:40 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_3_funcsim.vhdl
-- Design : fifo_generator_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_3blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_3blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10) => '0',
ADDRARDADDR(9 downto 5) => O1(4 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9 downto 5) => O2(4 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9 downto 8) => din(4 downto 3),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2 downto 0) => din(2 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9 downto 8) => din(9 downto 8),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2 downto 0) => din(7 downto 5),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(10) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(9 downto 8) => D(4 downto 3),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(2 downto 0) => D(2 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(10) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(9 downto 8) => D(9 downto 8),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(2 downto 0) => D(7 downto 5),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rd_rst,
RSTRAMB => rd_rst,
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
I3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_3rd_bin_cntr;
architecture STRUCTURE of fifo_generator_3rd_bin_cntr is
signal \^o2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair6";
attribute counter : integer;
attribute counter of \gc0.count_reg[0]\ : label is 2;
attribute counter of \gc0.count_reg[1]\ : label is 2;
attribute counter of \gc0.count_reg[2]\ : label is 2;
attribute counter of \gc0.count_reg[3]\ : label is 2;
attribute counter of \gc0.count_reg[4]\ : label is 2;
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair8";
begin
O2(4 downto 0) <= \^o2\(4 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => rd_pntr_plus1(3),
O => plusOp(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(0),
Q => \^o2\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(1),
Q => \^o2\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(2),
Q => \^o2\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(3),
Q => \^o2\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(3),
Q => \^o2\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => rd_rst,
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(4),
Q => \^q\(3)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8484F48F84848484"
)
port map (
I0 => \^o2\(3),
I1 => I1,
I2 => I2(0),
I3 => rd_pntr_plus1(3),
I4 => I3,
I5 => E(0),
O => O1
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(0),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(2),
I1 => \^o2\(3),
O => D(2)
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(3),
I1 => \^o2\(4),
O => D(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3rd_fwft : entity is "rd_fwft";
end fifo_generator_3rd_fwft;
architecture STRUCTURE of fifo_generator_3rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state[1]_i_1\ : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair5";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[9]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair4";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFBFF"
)
port map (
I0 => rd_rst,
I1 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I2 => rd_en,
I3 => curr_fwft_state(0),
I4 => p_18_out,
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => rd_rst,
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"CF08"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => rd_rst,
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5155"
)
port map (
I0 => p_18_out,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\goreg_bm.dout_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
O => O1(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I3 => p_18_out,
O => \n_0_gpregsm1.curr_fwft_state[1]_i_1\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => \n_0_gpregsm1.curr_fwft_state[1]_i_1\,
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_generator_3rd_status_flags_as;
architecture STRUCTURE of fifo_generator_3rd_status_flags_as is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => rd_rst,
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3reset_blk_ramfifo is
port (
rst_full_gen_i : out STD_LOGIC;
rst_d2 : out STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_3reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_3reset_blk_ramfifo is
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => wr_rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => wr_rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => wr_rst,
Q => rst_d3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3synchronizer_ff : entity is "synchronizer_ff";
end fifo_generator_3synchronizer_ff;
architecture STRUCTURE of fifo_generator_3synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_generator_3synchronizer_ff_0;
architecture STRUCTURE of fifo_generator_3synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3synchronizer_ff_1 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_generator_3synchronizer_ff_1;
architecture STRUCTURE of fifo_generator_3synchronizer_ff_1 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => \^q\(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(4),
Q => \^d\(1)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(3),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3synchronizer_ff_2 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_generator_3synchronizer_ff_2;
architecture STRUCTURE of fifo_generator_3synchronizer_ff_2 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => \^q\(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(4),
Q => \^d\(1)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(3),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_3wr_bin_cntr;
architecture STRUCTURE of fifo_generator_3wr_bin_cntr is
signal \^o1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute RETAIN_INVERTER : boolean;
attribute RETAIN_INVERTER of \gic0.gc0.count[0]_i_1\ : label is std.standard.true;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute counter : integer;
attribute counter of \gic0.gc0.count_reg[0]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[1]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[2]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[3]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[4]\ : label is 3;
begin
O1(4 downto 0) <= \^o1\(4 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(3),
O => \plusOp__0\(4)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^q\(0),
PRE => wr_rst,
Q => \^o1\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(1),
Q => \^o1\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(2),
Q => \^o1\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(3),
Q => \^o1\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(4),
Q => \^o1\(4)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^o1\(0),
Q => O2(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^o1\(1),
Q => O2(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^o1\(2),
Q => O2(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^o1\(3),
Q => O2(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^o1\(4),
Q => O2(4)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => wr_rst,
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(4),
Q => \^q\(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3wr_status_flags_as is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_generator_3wr_status_flags_as;
architecture STRUCTURE of fifo_generator_3wr_status_flags_as is
signal \^p_0_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_0_out <= \^p_0_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_0_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => \^p_0_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_3blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_3blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_3blk_mem_gen_prim_wrapper
port map (
D(9 downto 0) => D(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3clk_x_pntrs is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC;
ram_full_i : out STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rst_full_gen_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 4 downto 0 );
I5 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_generator_3clk_x_pntrs;
architecture STRUCTURE of fifo_generator_3clk_x_pntrs is
signal Q : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_4 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_5 : STD_LOGIC;
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal n_0_ram_full_i_i_4 : STD_LOGIC;
signal n_0_ram_full_i_i_5 : STD_LOGIC;
signal n_0_ram_full_i_i_6 : STD_LOGIC;
signal \n_0_rd_pntr_bin[0]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_bin[1]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_bin[2]_i_1\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_5_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_5_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in2_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair2";
begin
\gsync_stage[1].rd_stg_inst\: entity work.fifo_generator_3synchronizer_ff
port map (
I1(4 downto 0) => wr_pntr_gc(4 downto 0),
Q(4 downto 0) => Q(4 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_generator_3synchronizer_ff_0
port map (
I1(4 downto 0) => rd_pntr_gc(4 downto 0),
Q(4) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(3) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_4_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_generator_3synchronizer_ff_1
port map (
D(1 downto 0) => p_0_in(4 downto 3),
I1(4 downto 0) => Q(4 downto 0),
Q(3) => \n_2_gsync_stage[2].rd_stg_inst\,
Q(2) => \n_3_gsync_stage[2].rd_stg_inst\,
Q(1) => \n_4_gsync_stage[2].rd_stg_inst\,
Q(0) => \n_5_gsync_stage[2].rd_stg_inst\,
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_generator_3synchronizer_ff_2
port map (
D(1) => \n_0_gsync_stage[2].wr_stg_inst\,
D(0) => \n_1_gsync_stage[2].wr_stg_inst\,
I1(4) => \n_0_gsync_stage[1].wr_stg_inst\,
I1(3) => \n_1_gsync_stage[1].wr_stg_inst\,
I1(2) => \n_2_gsync_stage[1].wr_stg_inst\,
I1(1) => \n_3_gsync_stage[1].wr_stg_inst\,
I1(0) => \n_4_gsync_stage[1].wr_stg_inst\,
Q(3) => \n_2_gsync_stage[2].wr_stg_inst\,
Q(2) => \n_3_gsync_stage[2].wr_stg_inst\,
Q(1) => \n_4_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_5_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => I2(1),
I1 => p_1_out(1),
I2 => I2(0),
I3 => p_1_out(0),
I4 => n_0_ram_empty_fb_i_i_4,
O => O3
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => I1(0),
I1 => p_1_out(0),
I2 => I1(1),
I3 => p_1_out(1),
I4 => n_0_ram_empty_fb_i_i_5,
O => O1
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(2),
I1 => I2(2),
I2 => p_1_out(4),
I3 => I2(3),
O => n_0_ram_empty_fb_i_i_4
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(4),
I1 => I1(3),
I2 => p_1_out(2),
I3 => I1(2),
O => n_0_ram_empty_fb_i_i_5
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000D55D"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => \p_0_out__0\(3),
I3 => I3(3),
I4 => rst_full_gen_i,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFDFFFFFFFFFFFD"
)
port map (
I0 => wr_en,
I1 => p_0_out,
I2 => n_0_ram_full_i_i_4,
I3 => n_0_ram_full_i_i_5,
I4 => I4(3),
I5 => \p_0_out__0\(3),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => I3(0),
I1 => \p_0_out__0\(0),
I2 => I3(1),
I3 => \p_0_out__0\(1),
I4 => n_0_ram_full_i_i_6,
O => n_0_ram_full_i_i_3
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \p_0_out__0\(1),
I1 => I4(1),
I2 => \p_0_out__0\(0),
I3 => I4(0),
O => n_0_ram_full_i_i_4
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \p_0_out__0\(2),
I1 => I4(2),
I2 => \p_0_out__0\(4),
I3 => I4(4),
O => n_0_ram_full_i_i_5
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \p_0_out__0\(2),
I1 => I3(2),
I2 => \p_0_out__0\(4),
I3 => I3(4),
O => n_0_ram_full_i_i_6
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_3_gsync_stage[2].wr_stg_inst\,
I1 => \n_5_gsync_stage[2].wr_stg_inst\,
I2 => \n_4_gsync_stage[2].wr_stg_inst\,
I3 => \n_0_gsync_stage[2].wr_stg_inst\,
I4 => \n_2_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[0]_i_1\
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].wr_stg_inst\,
I1 => \n_4_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
I3 => \n_2_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[1]_i_1\
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].wr_stg_inst\,
I1 => \n_3_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[2]_i_1\
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[0]_i_1\,
Q => \p_0_out__0\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[1]_i_1\,
Q => \p_0_out__0\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[2]_i_1\,
Q => \p_0_out__0\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \p_0_out__0\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \p_0_out__0\(4)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(3),
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I2(3),
Q => rd_pntr_gc(4)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_3_gsync_stage[2].rd_stg_inst\,
I1 => \n_5_gsync_stage[2].rd_stg_inst\,
I2 => \n_4_gsync_stage[2].rd_stg_inst\,
I3 => p_0_in(4),
I4 => \n_2_gsync_stage[2].rd_stg_inst\,
O => p_0_in(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].rd_stg_inst\,
I1 => \n_4_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(4),
I3 => \n_2_gsync_stage[2].rd_stg_inst\,
O => p_0_in(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].rd_stg_inst\,
I1 => \n_3_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(4),
O => p_0_in(2)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(0),
Q => p_1_out(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(1),
Q => p_1_out(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(2),
Q => p_1_out(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(3),
Q => O2(0)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(4),
Q => p_1_out(4)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I5(0),
I1 => I5(1),
O => p_0_in2_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I5(1),
I1 => I5(2),
O => p_0_in2_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I5(2),
I1 => I5(3),
O => p_0_in2_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I5(3),
I1 => I5(4),
O => p_0_in2_out(3)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in2_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in2_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in2_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in2_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I5(4),
Q => wr_pntr_gc(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3rd_logic is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC;
O2 : in STD_LOGIC_VECTOR ( 0 to 0 );
I2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3rd_logic : entity is "rd_logic";
end fifo_generator_3rd_logic;
architecture STRUCTURE of fifo_generator_3rd_logic is
signal \n_1_gr1.rfwft\ : STD_LOGIC;
signal n_4_rpntr : STD_LOGIC;
signal p_18_out : STD_LOGIC;
begin
\gr1.rfwft\: entity work.fifo_generator_3rd_fwft
port map (
E(0) => \n_1_gr1.rfwft\,
O1(0) => E(0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.fifo_generator_3rd_status_flags_as
port map (
I1 => n_4_rpntr,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_rst => rd_rst
);
rpntr: entity work.fifo_generator_3rd_bin_cntr
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => \n_1_gr1.rfwft\,
I1 => I1,
I2(0) => O2(0),
I3 => I2,
O1 => n_4_rpntr,
O2(4 downto 0) => O1(4 downto 0),
Q(3 downto 0) => Q(3 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3wr_logic is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3wr_logic : entity is "wr_logic";
end fifo_generator_3wr_logic;
architecture STRUCTURE of fifo_generator_3wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.fifo_generator_3wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_generator_3wr_bin_cntr
port map (
E(0) => \^e\(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
Q(4 downto 0) => Q(4 downto 0),
wr_clk => wr_clk,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_3blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_3blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_3blk_mem_gen_prim_width
port map (
D(9 downto 0) => D(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_3blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_3blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_3blk_mem_gen_generic_cstr
port map (
D(9 downto 0) => D(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3blk_mem_gen_v8_2_synth is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end fifo_generator_3blk_mem_gen_v8_2_synth;
architecture STRUCTURE of fifo_generator_3blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_3blk_mem_gen_top
port map (
D(9 downto 0) => D(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_3blk_mem_gen_v8_2__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_3blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \fifo_generator_3blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \fifo_generator_3blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.fifo_generator_3blk_mem_gen_v8_2_synth
port map (
D(9 downto 0) => D(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3memory is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3memory : entity is "memory";
end fifo_generator_3memory;
architecture STRUCTURE of fifo_generator_3memory is
signal doutb : STD_LOGIC_VECTOR ( 9 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\fifo_generator_3blk_mem_gen_v8_2__parameterized0\
port map (
D(9 downto 0) => doutb(9 downto 0),
E(0) => E(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
din(9 downto 0) => din(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(0),
Q => dout(0),
R => rd_rst
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(1),
Q => dout(1),
R => rd_rst
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(2),
Q => dout(2),
R => rd_rst
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(3),
Q => dout(3),
R => rd_rst
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(4),
Q => dout(4),
R => rd_rst
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(5),
Q => dout(5),
R => rd_rst
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(6),
Q => dout(6),
R => rd_rst
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(7),
Q => dout(7),
R => rd_rst
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(8),
Q => dout(8),
R => rd_rst
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I1(0),
D => doutb(9),
Q => dout(9),
R => rd_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_3fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_3fifo_generator_ramfifo is
signal \gwas.wsts/ram_full_i\ : STD_LOGIC;
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_12_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_13_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_14_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_15_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_2_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_generator_3clk_x_pntrs
port map (
D(3) => \n_12_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_13_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_14_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_15_gntv_or_sync_fifo.gl0.rd\,
I1(3) => rd_pntr_plus1(4),
I1(2 downto 0) => rd_pntr_plus1(2 downto 0),
I2(3) => p_20_out(4),
I2(2 downto 0) => p_20_out(2 downto 0),
I3(4 downto 0) => p_8_out(4 downto 0),
I4(4 downto 0) => wr_pntr_plus2(4 downto 0),
I5(4 downto 0) => p_9_out(4 downto 0),
O1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O2(0) => p_1_out(3),
O3 => \n_2_gntv_or_sync_fifo.gcx.clkx\,
p_0_out => p_0_out,
ram_full_i => \gwas.wsts/ram_full_i\,
rd_clk => rd_clk,
rd_rst => rd_rst,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_3rd_logic
port map (
D(3) => \n_12_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_13_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_14_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_15_gntv_or_sync_fifo.gl0.rd\,
E(0) => p_15_out,
I1 => \n_2_gntv_or_sync_fifo.gcx.clkx\,
I2 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O1(4 downto 0) => p_20_out(4 downto 0),
O2(0) => p_1_out(3),
Q(3) => rd_pntr_plus1(4),
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_3wr_logic
port map (
E(0) => p_3_out,
O1(4 downto 0) => p_8_out(4 downto 0),
O2(4 downto 0) => p_9_out(4 downto 0),
Q(4 downto 0) => wr_pntr_plus2(4 downto 0),
full => full,
p_0_out => p_0_out,
ram_full_i => \gwas.wsts/ram_full_i\,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_3memory
port map (
E(0) => p_3_out,
I1(0) => p_15_out,
O1(4 downto 0) => p_20_out(4 downto 0),
O2(4 downto 0) => p_9_out(4 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.fifo_generator_3reset_blk_ramfifo
port map (
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_3fifo_generator_top;
architecture STRUCTURE of fifo_generator_3fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_3fifo_generator_ramfifo
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_3fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_generator_3fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_generator_3fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_3fifo_generator_top
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_3fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 31;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_generator_3fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_generator_3fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_generator_3fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_3fifo_generator_v12_0_synth
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_3 is
port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_3 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_3 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_3 : entity is "fifo_generator_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_3 : entity is "fifo_generator_3,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_generator_3 : entity is "fifo_generator_3,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_generator_3;
architecture STRUCTURE of fifo_generator_3 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 10;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 31;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 30;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_generator_3fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => rd_rst,
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => wr_rst,
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit | 175bc628e1e9c2e0997332b2685b0197 | 0.620651 | 2.852114 | false | false | false | false |
caiopo/mips-multiciclo | src/multiplexador4x1.vhd | 1 | 990 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity multiplexador4x1 is
generic(largura: natural := 8);
port(
entrada0, entrada1, entrada2, entrada3: in std_logic_vector(largura-1 downto 0);
selecao: in std_logic_vector(1 downto 0);
saida: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of multiplexador4x1 is
begin
saida <= entrada0 when selecao="00" else
entrada1 when selecao="01" else
entrada2 when selecao="10" else
entrada3;
end architecture; | mit | bd35197cf98a5726ba03ab5be344a75b | 0.566667 | 4.040816 | false | false | false | false |
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