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lfmunoz/4dsp_sip_interface | gbl_stellar_cmd.vhd | 1 | 12,418 | --------------------------------------------------------------------------------
-- file name : .vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity
-- arch_itecture
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity gbl_stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic := '0'; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity gbl_stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_stellar_cmd of gbl_stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
constant CMD_WR_ACK : std_logic_vector(3 downto 0) := x"5";
constant CMD_WR_EXPECTS_ACK : std_logic_vector(3 downto 0) := x"6";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_wr_ack : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal out_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
signal wr_ack_sig : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
p2p4: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => wr_ack,
inbusy => open,
pulseout => wr_ack_sig
);
p2p5: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr_ack,
inbusy => open,
pulseout => out_reg_val_ack
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
elsif (wr_ack_sig = '1' ) then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= out_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_WR_ACK;
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
elsif (wr_ack_sig = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr_sig <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
register_wr_ack <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr_sig <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
--generate the write requests ack pulse when the address is in the modules range and command is write that expects an ack
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr_ack <= '1';
else
register_wr_ack <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
out_reg_addr <= out_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_stellar_cmd;
| mit | d9045c4d5fce25d5ebd7423c69d9a8de | 0.462313 | 4.025284 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/mac/tri_mode_ethernet_mac_block.vhd | 2 | 18,140 | --------------------------------------------------------------------------------
-- Description:
-- This module contains The Ethernet MAC Block
-- as well as a FIFO block to decouple the switch clock frequency from the MAC
-- clock frequency
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_block is
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
GMII_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer:=28;
TX_STATISTICS_WIDTH : integer:=32;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- mac to rxpath interface
------------------------------------------
mac_out_clock : in std_logic;
mac_out_resetn : in std_logic;
mac_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_out_valid : out std_logic;
mac_out_last : out std_logic;
mac_out_error : out std_logic;
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- txpath to mac interface
---------------------------------------------
mac_in_clock : in std_logic;
mac_in_resetn : in std_logic;
mac_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
mac_in_valid : in std_logic;
mac_in_ready : out std_logic;
mac_in_last : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_interrupt : out std_logic
);
end tri_mode_ethernet_mac_block;
architecture wrapper of tri_mode_ethernet_mac_block is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(RX_STATISTICS_WIDTH-1 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
tx_statistics_vector : out std_logic_vector(TX_STATISTICS_WIDTH-1 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- Reference clock for IDELAYCTRL's
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component mac_fifo_interface
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FULL_DUPLEX_ONLY : boolean := true
); -- If fifo is to be used only in full duplex set to true for optimised implementation
port (
-- txpath interface
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- support block interface
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic;
-- rxpath interface
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- support block interface
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component aeg_design_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
signal mac_out_reset : std_logic;
signal mac_in_reset : std_logic;
-- MAC receiver client I/F
signal sup2rxfifo_data : std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
signal sup2rxfifo_valid : std_logic;
signal sup2rxfifo_last : std_logic;
signal sup2rxfifo_error : std_logic;
-- MAC transmitter client I/F
signal txfifo2sup_data : std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
signal txfifo2sup_valid : std_logic;
signal txfifo2sup_ready : std_logic;
signal txfifo2sup_last : std_logic;
signal txfifo2sup_error : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_mac_aclk <= rx_mac_aclk_int;
tx_mac_aclk <= tx_mac_aclk_int;
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
mac_out_reset <= not mac_out_resetn;
mac_in_reset <= not mac_in_resetn;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
tri_mode_ethernet_mac_i : tri_mode_ethernet_mac_0
port map(
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_enable => open,
rx_statistics_vector => open,
rx_statistics_valid => open,
rx_mac_aclk => rx_mac_aclk_int,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => sup2rxfifo_data,
rx_axis_mac_tvalid => sup2rxfifo_valid,
rx_axis_mac_tlast => sup2rxfifo_last,
rx_axis_mac_tuser => sup2rxfifo_error,
-- Client Transmitter Interface
tx_enable => open,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => open,
tx_statistics_valid => open,
tx_mac_aclk => tx_mac_aclk_int,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => txfifo2sup_data ,
tx_axis_mac_tvalid => txfifo2sup_valid,
tx_axis_mac_tlast => txfifo2sup_last,
tx_axis_mac_tuser => txfifo2sup_error,
tx_axis_mac_tready => txfifo2sup_ready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
-- speed control
speedis100 => open,
speedis10100 => open,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdio => mdio,
mdc => mdc,
-- AXI lite interface
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => mac_interrupt
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : aeg_design_0_reset_sync
port map (
clk => rx_mac_aclk_int,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : aeg_design_0_reset_sync
port map (
clk => tx_mac_aclk_int,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
fifo_interface : mac_fifo_interface
generic map(
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FULL_DUPLEX_ONLY => true
)
port map(
-- txpath interface
tx_fifo_in_clk => mac_in_clock,
tx_fifo_in_reset => mac_in_reset,
tx_fifo_in_data => mac_in_data,
tx_fifo_in_valid => mac_in_valid,
tx_fifo_in_last => mac_in_last,
tx_fifo_in_ready => mac_in_ready,
-- support block interface
tx_fifo_out_clk => tx_mac_aclk_int,
tx_fifo_out_reset => tx_mac_reset,
tx_fifo_out_data => txfifo2sup_data,
tx_fifo_out_valid => txfifo2sup_valid,
tx_fifo_out_last => txfifo2sup_last,
tx_fifo_out_ready => txfifo2sup_ready,
tx_fifo_out_error => txfifo2sup_error(0),
-- rxpath interface
rx_fifo_out_clk => mac_out_clock,
rx_fifo_out_reset => mac_out_reset,
rx_fifo_out_data => mac_out_data,
rx_fifo_out_valid => mac_out_valid,
rx_fifo_out_last => mac_out_last,
rx_fifo_out_error => mac_out_error,
-- support block interface
rx_fifo_in_clk => rx_mac_aclk_int,
rx_fifo_in_reset => rx_mac_reset,
rx_fifo_in_data => sup2rxfifo_data,
rx_fifo_in_valid => sup2rxfifo_valid,
rx_fifo_in_last => sup2rxfifo_last,
rx_fifo_in_error => sup2rxfifo_error
);
end wrapper;
| mit | 148262242fb09a244c3eab86955a136f | 0.46731 | 3.579321 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_control.vhd | 2 | 13,322 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 10:48:52
-- Design Name:
-- Module Name: output_queue_control - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- state machine that controls the storage of data transfered over the switching fabric
-- the frame is stored in the output queue module
-- the length and the frame's start position in the memory are stored in the output queue fifo
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity output_queue_control is
Generic (
FABRIC_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_FIFO_DATA_WIDTH : integer;
FABRIC2TRANSMITTER_DATA_WIDTH_RATIO : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface fabric
oqctrl_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
oqctrl_in_valid : in std_logic;
oqctrl_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
oqctrl_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqctrl_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface memory check
oqctrl_out_mem_wr_addr : out std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_B-1 downto 0);
-- output interface memory
oqctrl_out_mem_wenable : out std_logic;
oqctrl_out_mem_addr : out std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqctrl_out_mem_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- output interface fifo
oqctrl_out_fifo_wenable : out std_logic;
oqctrl_out_fifo_data : out std_logic_vector(OQ_FIFO_DATA_WIDTH-1 downto 0);
oqctrl_out_fifo_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0)
);
end output_queue_control;
architecture rtl of output_queue_control is
-- state machine
type state is (
IDLE,
WRITE_MEM
);
-- state signals
signal cur_state : state;
signal nxt_state : state;
-- config_output_state machine signals
signal read_reg_sig : std_logic := '0';
signal update_cnt_sig : std_logic := '0';
signal reset_frame_length_sig : std_logic := '0';
signal update_mem_ptr_sig : std_logic := '0';
-- process registers
signal frame_length_cnt : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal frame_length_reg : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_start_ptr_reg : std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next data_input_state, combinitorial logic
output_logic_p : process(cur_state, oqctrl_in_valid, frame_length_cnt, frame_length_reg)
begin
-- default signal assignments
nxt_state <= IDLE;
read_reg_sig <= '0';
update_cnt_sig <= '0';
reset_frame_length_sig <= '0';
update_mem_ptr_sig <= '0';
oqctrl_out_mem_wenable <= '0';
oqctrl_out_fifo_wenable <= '0';
case cur_state is
when IDLE =>
if oqctrl_in_valid = '1' then
nxt_state <= WRITE_MEM;
read_reg_sig <= '1'; -- read_reg_p
update_cnt_sig <= '1'; -- cnt_frame_length_p
oqctrl_out_mem_wenable <= '1';
end if;
when WRITE_MEM =>
nxt_state <= WRITE_MEM;
if frame_length_cnt >= frame_length_reg then
nxt_state <= IDLE;
reset_frame_length_sig <= '1'; -- cnt_frame_length_p
oqctrl_out_fifo_wenable <= '1';
update_mem_ptr_sig <= '1'; -- update_mem_ptr_p
elsif oqctrl_in_valid = '1' then
nxt_state <= WRITE_MEM;
update_cnt_sig <= '1'; -- cnt_frame_length_p
oqctrl_out_mem_wenable <= '1';
end if;
end case;
end process output_logic_p;
-- count frame bytes received from fabric
cnt_frame_length_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
frame_length_cnt <= (others => '0');
else
frame_length_cnt <= frame_length_cnt;
if reset_frame_length_sig = '1' then
frame_length_cnt <= (others => '0');
elsif update_cnt_sig = '1' then
frame_length_cnt <= frame_length_cnt + FABRIC2TRANSMITTER_DATA_WIDTH_RATIO;
end if;
end if;
end if;
end process;
-- read the frame length of the incoming frame
read_reg_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
frame_length_reg <= (others => '0');
timestamp_reg <= (others => '0');
prio_reg <= (others => '0');
else
frame_length_reg <= frame_length_reg;
timestamp_reg <= timestamp_reg;
prio_reg <= prio_reg;
if read_reg_sig = '1' then
frame_length_reg <= oqctrl_in_length;
timestamp_reg <= oqctrl_in_timestamp;
prio_reg <= oqctrl_in_prio;
end if;
end if;
end if;
end process;
-- update memory start address of next incoming frame
update_mem_ptr_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
mem_start_ptr_reg <= (others => '0');
else
mem_start_ptr_reg <= mem_start_ptr_reg;
if update_mem_ptr_sig = '1' then
if NR_OQ_FIFOS = 2 and prio_reg >= high_priority_border_value_reg then
mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) <=
mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) +
frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A) + 1;
else
mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) +
frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A) + 1;
end if;
end if;
end if;
end if;
end process;
-- switch fabric 32 bit
output_p : process(high_priority_border_value_reg, mem_start_ptr_reg, frame_length_cnt, timestamp_reg, oqctrl_in_prio, frame_length_reg)
begin
if NR_OQ_FIFOS = 1 then
oqctrl_out_mem_addr <= mem_start_ptr_reg + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
oqctrl_out_fifo_data <= mem_start_ptr_reg & "00" & timestamp_reg & frame_length_reg;
oqctrl_out_mem_wr_addr <= mem_start_ptr_reg & "00";
else
oqctrl_out_mem_wr_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) & "00" &
mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) & "00";
if oqctrl_in_prio >= high_priority_border_value_reg then
oqctrl_out_mem_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A)
+ frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
oqctrl_out_fifo_data <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) & "00" & timestamp_reg & frame_length_reg;
else
oqctrl_out_mem_addr <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0)
+ frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
oqctrl_out_fifo_data <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) & "00" & timestamp_reg & frame_length_reg;
end if;
end if;
end process;
-- switch fabric 16 bit
-- output_p : process(high_priority_border_value_reg, mem_start_ptr_reg, frame_length_cnt, timestamp_reg, oqctrl_in_prio, frame_length_reg)
-- begin
-- if NR_OQ_FIFOS = 1 then
-- oqctrl_out_mem_addr <= mem_start_ptr_reg + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg & "0" & timestamp_reg & frame_length_reg;
-- oqctrl_out_mem_wr_addr <= mem_start_ptr_reg & "0";
-- else
-- oqctrl_out_mem_wr_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) & "0" &
-- mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) & "0";
-- if oqctrl_in_prio >= high_priority_border_value_reg then
-- oqctrl_out_mem_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A)
-- + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) & "0" & timestamp_reg & frame_length_reg;
-- else
-- oqctrl_out_mem_addr <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0)
-- + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) & "0" & timestamp_reg & frame_length_reg;
-- end if;
-- end if;
-- end process;
-- switch fabric 8 bit
-- output_p : process(high_priority_border_value_reg, mem_start_ptr_reg, frame_length_cnt, timestamp_reg, oqctrl_in_prio, frame_length_reg)
-- begin
-- if NR_OQ_FIFOS = 1 then
-- oqctrl_out_mem_addr <= mem_start_ptr_reg + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg & timestamp_reg & frame_length_reg;
-- oqctrl_out_mem_wr_addr <= mem_start_ptr_reg;
-- else
-- oqctrl_out_mem_wr_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) &
-- mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
-- if oqctrl_in_prio >= high_priority_border_value_reg then
-- oqctrl_out_mem_addr <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A)
-- + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH_A-1 downto (NR_OQ_FIFOS-1)*OQ_MEM_ADDR_WIDTH_A) & timestamp_reg & frame_length_reg;
-- else
-- oqctrl_out_mem_addr <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0)
-- + frame_length_cnt(FRAME_LENGTH_WIDTH-1 downto OQ_MEM_ADDR_WIDTH_B - OQ_MEM_ADDR_WIDTH_A);
-- oqctrl_out_fifo_data <= mem_start_ptr_reg(OQ_MEM_ADDR_WIDTH_A-1 downto 0) & timestamp_reg & frame_length_reg;
-- end if;
-- end if;
-- end process;
oqctrl_out_mem_data <= oqctrl_in_data;
oqctrl_out_fifo_prio <= prio_reg;
end rtl;
| mit | 1d4ef939d3663806268588749cfc6afb | 0.541585 | 3.435276 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/reset/aeg_design_resets.vhd | 2 | 8,049 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates fully synchronous resets for each clock domain
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aeg_design_0_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic
);
end aeg_design_0_resets;
architecture RTL of aeg_design_0_resets is
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component aeg_design_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- define internal signals
signal s_axi_pre_resetn : std_logic := '0';
signal s_axi_reset_int : std_logic;
signal combined_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal gtx_clk_reset_int : std_logic;
signal clear_checker : std_logic;
signal chk_pre_resetn : std_logic := '0';
signal chk_reset_int : std_logic;
signal dcm_locked_sync : std_logic;
signal glbl_rst_int : std_logic;
signal phy_resetn_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Synchronise the async dcm_locked into the gtx_clk clock domain
------------------------------------------------------------------------------
dcm_sync : aeg_design_0_sync_block
port map (
clk => gtx_clk,
data_in => dcm_locked,
data_out => dcm_locked_sync
);
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
-- in each case the async reset is first captured and then synchronised
-----------------
-- global reset
glbl_reset_gen : aeg_design_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => glbl_rst,
reset_out => glbl_rst_int
);
glbl_rst_intn <= not glbl_rst_int;
-----------------
-- AXI-Lite reset
axi_lite_reset_gen : aeg_design_0_reset_sync
port map (
clk => s_axi_aclk,
enable => phy_resetn_int,
reset_in => glbl_rst,
reset_out => s_axi_reset_int
);
-- Create fully synchronous reset in the s_axi clock domain.
axi_lite_reset_p : process(s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset_int = '1' then
s_axi_pre_resetn <= '0';
s_axi_resetn <= '0';
else
s_axi_pre_resetn <= '1';
s_axi_resetn <= s_axi_pre_resetn;
end if;
end if;
end process axi_lite_reset_p;
-----------------
-- gtx_clk reset
combined_reset <= glbl_rst or rx_reset or tx_reset;
gtx_reset_gen : aeg_design_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => combined_reset,
reset_out => gtx_clk_reset_int
);
-- Create fully synchronous reset in the gtx_clk domain.
gtx_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gtx_reset_p;
-----------------
-- PHY reset
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
-- this is derived using the 125MHz available and a 6 bit counter
phy_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if glbl_rst_int = '1' then
phy_resetn_int <= '0';
phy_reset_count <= (others => '0');
else
if phy_reset_count /= "111111" then
phy_reset_count <= phy_reset_count + "000001";
else
phy_resetn_int <= '1';
end if;
end if;
end if;
end process phy_reset_p;
phy_resetn <= phy_resetn_int;
end RTL;
| mit | 64a29fa8b70e040ed76d2dac8b7ac0f5 | 0.538576 | 4.329747 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/LUTROM/simulation/bmg_stim_gen.vhd | 1 | 12,587 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (17 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0):= hex_to_std_logic_vector("0",18);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (8191 downto 0) of std_logic_vector(17 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(17 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"LUTROM.mif",
DEFAULT_DATA,
18,
8192);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ_REG(0);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| gpl-3.0 | d80bd04d033099777a64e48c7faa4881 | 0.547787 | 3.684719 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/register.vhd | 1 | 887 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-05-2016
-- Module Name: register.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity register_N is
generic (N : integer := 16);
port (reset, clk, load : in std_logic;
ldata : in std_logic_vector (N - 1 downto 0);
O : out std_logic_vector (N - 1 downto 0));
end entity;
architecture rtl of register_N is
signal storage : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
O <= storage;
process(clk)
begin
if clk'event and clk ='1' then
if reset = '1' then
storage <= (others => '0');
elsif load = '1' then
storage <= ldata;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 1ab23c556a08a969535203f399b0efd9 | 0.518602 | 3.464844 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_nm_piso_register.vhd | 1 | 2,948 | ----------------------------------------------------------------------------------------------------
-- Testbench - PISO Register (Parallel In Serial Out)
--
-- This testbench is written for the use with production parameters. (M=163, U=8)
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 18.08.2017
-- Last Change: 16.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_nm_piso_register IS
END tb_nm_piso_register;
ARCHITECTURE rtl OF tb_nm_piso_register IS
-- Import entity e_piso_register
COMPONENT e_nm_piso_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
load_i : IN std_logic;
data_i : IN std_logic_vector(M-1 DOWNTO 0);
data_o : OUT std_logic_vector(U-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL data: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL piso: std_logic_vector(U-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, load: std_logic := '0';
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 20 ns;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate piso register entity
piso_register: e_nm_piso_register PORT MAP(
clk_i => clk,
rst_i => rst,
enable_i => enable,
load_i => load,
data_i => data,
data_o => piso
);
-- Clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR PERIOD;
clk <= '1';
WAIT FOR PERIOD;
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS IS
PROCEDURE p_ena (
SIGNAL s_ena : INOUT std_logic
) IS
BEGIN
s_ena <= '1';
WAIT FOR PERIOD*2;
s_ena <= '0';
WAIT FOR PERIOD*8;
END p_ena;
BEGIN
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD*4;
data <= "100" & x"0B0A09080706050403020108A2E0CC0D99F8A5EF";
load <= '1';
WAIT FOR PERIOD;
load <= '0';
WAIT FOR PERIOD*4;
FOR i IN 0 TO 22 LOOP
p_ena(enable);
END LOOP;
WAIT FOR DELAY;
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!"
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | 36811d342208da5f6aeae087befe3dad | 0.511194 | 3.915007 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/tri_mode_ethernet_mac_0_clk_wiz.vhd | 1 | 7,364 | -- file: tri_mode_ethernet_mac_0_clk_wiz.vhd
--
-- -----------------------------------------------------------------------------
-- (c) Copyright 2008-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 125.000 0.000 50.0 91.364 85.928
-- CLK_OUT2 100.000 0.000 50.0 70.716 85.928
-- CLK_OUT2 200.000 0.000 50.0
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 200.000 0.010
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_clk_wiz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end tri_mode_ethernet_mac_0_clk_wiz;
architecture xilinx of tri_mode_ethernet_mac_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2 : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 5,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => CLK_IN1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFGCE
port map
(O => CLK_OUT1,
CE => '1',
I => clkout0);
clkout2_buf : BUFGCE
port map
(O => CLK_OUT2,
CE => '1',
I => clkout1);
clkout3_buf : BUFGCE
port map
(O => CLK_OUT3,
CE => '1',
I => clkout2);
end xilinx;
| mit | 2c18f428939042e432bc8a91075ecd12 | 0.556491 | 4.246828 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup_mod.vhd | 1 | 14,503 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 12:06:03
-- Design Name: rx_path_lookup.vhd
-- Module Name: rx_path_lookup - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- this module handles the frame lookup
-- according to the header input the output ports for each frame are searched for in the lookup memory
-- the lookup memory constists of one base configuration, frame confiugrations and one default configuration
-- - base configuration gives the entry to the frame configuration
-- - frame configurations returns a one-hot-encoded output ports vector for each valid mac destination address
-- and the priority of the frame
-- - for mac address not in the lookup table the default configuration decides whether to skip this frame or
-- to send it to default output ports
-- transmitting the frame on the receiving port is prevented by setting the corresponding bit in the ports vector to '0'
--
-- for more details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
-- for more detail on the lookup module see switch_port_rxpath_lookup.svg
--
-- base_address is an internal register pointing to the base configuration; lateron it has to be connected to a processor
-- the housekeeping processor also has to take care of writing all the configurations to the lookup memory
-- thereby, an overflow of the memory address space of the binary list must not happen as no overflow control is
-- implemented in the lookup algorithm
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_lookup is
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
-- lookup memory address constants
LOWER_ADDR_START : integer := 20;
UPPER_ADDR_START : integer := 40;
DEF_ADDR_START : integer := 0;
ENABLE_START : integer := 63;
PORTS_START : integer := 60;
PRIO_START : integer := 48;
SKIP_FRAME_START : integer := 0;
DEST_MAC_START : integer := 0
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end rx_path_lookup;
architecture rtl of rx_path_lookup is
-- determine the next search address (median) of the binary search
-- upper and lower are the corresponding border memory adresses of the remaining search space
-- return value median = (upper + lower) / 2
function upper_add_lower_by2_f (upper, lower : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0))
return std_logic_vector is
variable x1 : integer;
variable x2 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH downto 0);
variable x3 : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
x1 := to_integer(unsigned(upper)) + to_integer(unsigned(lower));
x2 := std_logic_vector(to_unsigned(x1,x2'length));
x3 := x2(LOOKUP_MEM_ADDR_WIDTH downto 1);
return x3;
end upper_add_lower_by2_f;
-- lookup state machine
type state is (
IDLE,
READ_BASE,
LOOKUP,
READ_DEFAULT
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal read_header_sig : std_logic := '0';
signal read_base_sig : std_logic := '0';
signal read_default_sig : std_logic := '0';
signal lookup_valid_sig : std_logic := '0';
signal read_lookup_sig : std_logic := '0';
signal update_sig : std_logic := '0';
signal lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
-- process registers
signal dest_mac_reg : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
signal vlan_enable_reg : std_logic;
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lower_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal upper_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal median_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal default_reg : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal skip_frame_reg : std_logic;
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- alias signals for memory read access
signal mem_lower_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_upper_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_default_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem_lookup_enable_sig : std_logic;
signal mem_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal mem_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal mem_skip_frame_sig : std_logic;
signal mem_dest_mac_sig : std_logic_vector(DEST_MAC_WIDTH-1 downto 0);
-- internal registers (to be connected to the outside, e.g. housekeeping processor)
signal base_address : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0) := "000000000";
signal mem_addr_sig : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
begin
-- alias names (signals) for lookup memory output ranges
mem_lower_sig <= mem_data(LOWER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto LOWER_ADDR_START);
mem_upper_sig <= mem_data(UPPER_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto UPPER_ADDR_START);
mem_default_sig <= mem_data(DEF_ADDR_START+LOOKUP_MEM_ADDR_WIDTH-1 downto DEF_ADDR_START);
mem_lookup_enable_sig <= mem_data(ENABLE_START);
mem_ports_sig <= mem_data(PORTS_START+NR_PORTS-1 downto PORTS_START);
mem_prio_sig <= mem_data(PRIO_START+VLAN_PRIO_WIDTH-1 downto PRIO_START);
mem_skip_frame_sig <= mem_data(SKIP_FRAME_START);
mem_dest_mac_sig <= mem_data(DEST_MAC_START+DEST_MAC_WIDTH-1 downto DEST_MAC_START);
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, lookup_in_valid, mem_lookup_enable_sig, mem_default_sig,
BASE_ADDRESS, median_sig, upper_reg, lower_reg, median_reg, default_reg, dest_mac_reg,
mem_dest_mac_sig, mem_upper_sig, mem_lower_sig)
begin
-- default signal assignments
nxt_state <= IDLE;
read_header_sig <= '0'; -- read_header_p
read_base_sig <= '0'; -- write_internal_registers_p
read_default_sig <= '0'; -- output_reg_p
lookup_valid_sig <= '0'; -- output_valid_p
read_lookup_sig <= '0'; -- output_reg_p
update_sig <= '0'; -- write_internal_registers_p
upper_sig <= (others => '0'); -- upper_add_lower_by2_f
lower_sig <= (others => '0'); -- upper_add_lower_by2_f
-- default output values
mem_enable <= '0';
mem_addr_sig <= (others => '1');
case cur_state is
when IDLE => -- waiting for a new header
if lookup_in_valid = '1' then
nxt_state <= READ_BASE;
read_header_sig <= '1'; -- read_header_p
mem_enable <= '1';
mem_addr_sig <= BASE_ADDRESS;
end if;
when READ_BASE => -- read base address, determine if lookup is enabled
read_base_sig <= '1'; -- internal_reg_p
mem_enable <= '1';
if mem_lookup_enable_sig = '0' then -- lookup disabled, read default configuration
nxt_state <= READ_DEFAULT;
mem_addr_sig <= mem_default_sig;
else -- lookup enabled, search for address in the middle of binary lookup list
nxt_state <= LOOKUP;
upper_sig <= mem_upper_sig; -- upper_add_lower_by2_f
lower_sig <= mem_lower_sig; -- upper_add_lower_by2_f
mem_addr_sig <= median_sig; -- upper_add_lower_by2_f
end if;
when LOOKUP => -- lookup the median memory address and check if the memory mac address matches the frame mac address
if dest_mac_reg = mem_dest_mac_sig then -- MAC ADDRESS found -> Algorithm terminates
nxt_state <= IDLE;
read_lookup_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
elsif upper_reg <= lower_reg then -- MAC ADDRESS not found -> Algorithm terminats with default configuration
nxt_state <= READ_DEFAULT;
mem_addr_sig <= default_reg;
mem_enable <= '1';
else -- MAC ADDRESS not found, Algorithm not terminated yet, continue lookup with decreased search space
update_sig <= '1'; -- internal_reg_p
mem_addr_sig <= median_sig; -- upper_add_lower_by2_f
mem_enable <= '1';
nxt_state <= LOOKUP;
if dest_mac_reg > mem_dest_mac_sig then
upper_sig <= upper_reg; -- upper_add_lower_by2_f
lower_sig <= median_reg + 1; -- upper_add_lower_by2_f
else -- dest_mac_reg < mem_dest_mac_sig
upper_sig <= median_reg - 1; -- upper_add_lower_by2_f
lower_sig <= lower_reg; -- upper_add_lower_by2_f
end if;
end if;
when READ_DEFAULT =>
nxt_state <= IDLE;
read_default_sig <= '1'; -- output_reg_p
lookup_valid_sig <= '1'; -- output_valid_p
end case;
end process;
-- handshake protocol to read header from previous module and store header into internal buffer
read_header_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_mac_reg <= (others => '0');
vlan_enable_reg <= '0';
vlan_prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
lookup_in_ready <= '0';
else
dest_mac_reg <= dest_mac_reg;
vlan_enable_reg <= vlan_enable_reg;
vlan_prio_reg <= vlan_prio_reg;
timestamp_reg <= timestamp_reg;
lookup_in_ready <= '0';
if read_header_sig = '1' then
dest_mac_reg <= lookup_in_dest;
vlan_enable_reg <= lookup_in_vlan_enable;
vlan_prio_reg <= lookup_in_vlan_prio;
timestamp_reg <= lookup_in_timestamp;
lookup_in_ready <= '1';
end if;
end if;
end if;
end process;
-- handles access to the internal registers needed for lookup
internal_reg_p : process (clk) -- to be done
begin
if clk'event and clk = '1' then
if reset = '1' then
lower_reg <= (others => '0');
upper_reg <= (others => '0');
default_reg <= (others => '0');
median_reg <= (others => '0');
mem_addr <= (others => '1');
else
lower_reg <= lower_reg;
upper_reg <= upper_reg;
default_reg <= default_reg;
median_reg <= median_reg;
mem_addr <= mem_addr_sig;
if read_base_sig = '1' then -- read inital values from base configuration
lower_reg <= mem_lower_sig;
upper_reg <= mem_upper_sig;
default_reg <= mem_default_sig;
median_reg <= median_sig;
elsif update_sig = '1' then -- update registers according to remaining search space
lower_reg <= lower_sig;
upper_reg <= upper_sig;
median_reg <= median_sig;
end if;
end if;
end if;
end process;
-- assign next memory search address: median address in the remaining address search space
median_sig <= upper_add_lower_by2_f(upper_sig, lower_sig);
-- updates the output value registers (ports, priority and skip)
output_reg_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
ports_reg <= (others => '0');
prio_reg <= (others => '0');
skip_frame_reg <= '0';
else
ports_reg <= ports_reg;
prio_reg <= prio_reg;
skip_frame_reg <= skip_frame_reg;
if read_default_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0';
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= mem_skip_frame_sig;
elsif read_lookup_sig = '1' then
ports_reg <= mem_ports_sig;
ports_reg(PORT_ID) <= '0'; -- comment for loopback functionality
if lookup_in_vlan_enable = '1' then
prio_reg <= vlan_prio_reg;
else
prio_reg <= mem_prio_sig;
end if;
skip_frame_reg <= '0';
end if;
end if;
end if;
end process;
-- sets the output valid bit
output_valid_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
lookup_out_valid <= '0';
else
lookup_out_valid <= '0';
if lookup_valid_sig = '1' then
lookup_out_valid <= '1';
end if;
end if;
end if;
end process;
-- other outputs
lookup_out_ports <= ports_reg;
lookup_out_prio <= prio_reg;
lookup_out_skip <= skip_frame_reg;
lookup_out_timestamp <= timestamp_reg;
end rtl;
| mit | eed63d40e46995c606a7364ba70e5745 | 0.61801 | 3.35097 | false | false | false | false |
bazk/hwsat | templates/solver_tb.vhd | 1 | 778 | library ieee;
use ieee.std_logic_1164.all;
entity solver_tb is
end solver_tb;
architecture behavioral of solver_tb is
component solver
port (
clk: in std_logic;
reset: in std_logic;
sat: out std_logic;
unsat: out std_logic
);
end component;
for solver_0: solver use entity work.solver;
signal clk, reset, sat, unsat: std_logic := '0';
begin
-- Instantiate solver
solver_0: solver port map (
clk => clk,
reset => reset,
sat => sat,
unsat => unsat
);
-- 166Mhz clock ~= 5.74 ns full-period, 2.87 ns half-period
clk <= '0' when (sat='1' or unsat='1') else not clk after 2.87 ns;
reset <= '0', '1' after 2 ns, '0' after 7 ns;
end behavioral; | gpl-3.0 | d3c25c70d8485e936fe8f7fe76f2315c | 0.566838 | 3.488789 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_point_multiplication.vhd | 1 | 10,301 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Multiplication
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- xp_i - X part of input point
-- yp_i - Y part of input point
-- k_i - Multiplier k
-- xq_io - X part of output point
-- yq_io - Y part of output point
-- ready_o - Ready flag
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/K163_point_multiplication.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) point multiplication
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT (
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k_i: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_multiplication;
ARCHITECTURE rtl of e_gf2m_point_multiplication IS
-- Import entity e_gf2m_point_addition
COMPONENT e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL a, next_a, a_div_2: std_logic_vector(m DOWNTO 0);
SIGNAL b, next_b: std_logic_vector(m-1 DOWNTO 0);
SIGNAL xxP, yyP, next_xQ, next_yQ, xxPxoryyP, square_xxP, square_yyP, y1, x3, y3: std_logic_vector(m-1 DOWNTO 0);
SIGNAL ce_P, ce_Q, ce_ab, load, sel_1, start_addition, addition_done, carry, Q_infinity, aEqual0, bEqual0, a1xorb0: std_logic;
SIGNAL sel_2: std_logic_vector(1 DOWNTO 0);
-- Define all available states
subtype states IS natural RANGE 0 TO 12;
SIGNAL current_state: states;
BEGIN
-- Instantiate point addition entity
-- Calculate (x3, y3) = (xxp, y1) + (xq, yq)
first_component: e_gf2m_point_addition GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_addition,
x1_i => xxP,
y1_i => y1,
x2_i => xq_io,
y2_i => yq_io,
x3_io => x3,
y3_o => y3,
ready_o => addition_done
);
-- Instantiate squarer entity for x part
-- Calculate xxp^2
x_squarer: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => xxP,
c_o => square_xxP
);
-- Instantiate squarer entity for y part
-- Calculate yyp^2
y_squarer: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => yyP,
c_o => square_yyP
);
-- Calculate xxp XOR yyp
xor_gates: FOR i IN 0 TO m-1 GENERATE
xxPxoryyP(i) <= xxP(i) xor yyP(i);
END GENERATE;
WITH sel_1 SELECT y1 <= yyP WHEN '0', xxPxoryyP WHEN OTHERS;
WITH sel_2 SELECT next_yQ <= y3 WHEN "00", yyP WHEN "01", xxPxoryyP WHEN OTHERS;
WITH sel_2 SELECT next_xQ <= x3 WHEN "00", xxP WHEN OTHERS;
register_P: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
xxP <= xp_i;
yyP <= yp_i;
ELSIF ce_P = '1' THEN
xxP <= square_xxP;
yyP <= square_yyP;
END IF;
END IF;
END PROCESS;
register_Q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
Q_infinity <= '1';
ELSIF ce_Q = '1' THEN
xq_io <= next_xQ;
yq_io <= next_yQ;
Q_infinity <= '0';
END IF;
END IF;
END PROCESS;
divide_by_2: FOR i IN 0 TO m-1 GENERATE
a_div_2(i) <= a(i+1);
END GENERATE;
a_div_2(m) <= a(m);
next_a <= (b(m-1)&b) + a_div_2 + carry;
next_b <= zero - (a_div_2(m-1 DOWNTO 0) + carry);
register_ab: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
a <= ('0'&k_i);
b <= zero;
ELSIF ce_ab = '1' THEN
a <= next_a;
b <= next_b;
END IF;
END IF;
END PROCESS;
aEqual0 <= '1' WHEN a = 0 ELSE '0';
bEqual0 <= '1' WHEN b = 0 ELSE '0';
a1xorb0 <= a(1) xor b(0);
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state, addition_done, aEqual0, bEqual0, a(0), a1xorb0, Q_infinity)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Load k, xp, yp, ...
-- 4,5 : Square xxp, yyp, ...
-- 6,7 :
--
CASE current_state IS
WHEN 0 TO 1 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '1';
WHEN 2 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '1'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 3 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 4 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '0'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 5 => sel_1 <= '0'; sel_2 <= "01"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 6 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '1'; ready_o <= '0';
WHEN 7 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 8 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 9 => sel_1 <= '1'; sel_2 <= "10"; carry <= '1'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 10 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '1'; ready_o <= '0';
WHEN 11 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 12 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (aEqual0 = '1') and (bEqual0 = '1') THEN
current_state <= 0;
ELSIF a(0) = '0' THEN
current_state <= 4;
ELSIF (a1xorb0 = '0') and (Q_infinity = '1') THEN
current_state <= 5;
ELSIF (a1xorb0 = '0') and (Q_infinity = '0') THEN
current_state <= 6;
ELSIF (a1xorb0 = '1') and (Q_infinity = '1') THEN
current_state <= 9;
ELSE
current_state <= 10;
END IF;
WHEN 4 =>
current_state <= 3;
WHEN 5 =>
current_state <= 3;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF addition_done = '1' THEN
current_state <= 8;
END IF;
WHEN 8 =>
current_state <= 3;
WHEN 9 =>
current_state <= 3;
WHEN 10 =>
current_state <= 11;
WHEN 11 =>
IF addition_done = '1' THEN
current_state <= 12;
END IF;
WHEN 12 =>
current_state <= 3;
END CASE;
END IF;
END PROCESS;
END rtl;
| gpl-3.0 | 0ef3da26cefbf3de35989162f4eae1a0 | 0.438113 | 3.382923 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/synth/fifo_generator_3.vhd | 1 | 38,540 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_3 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_3;
ARCHITECTURE fifo_generator_3_arch OF fifo_generator_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_3_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_3_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_3_arch : ARCHITECTURE IS "fifo_generator_3,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_3_arch: ARCHITECTURE IS "fifo_generator_3,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=31,C_PROG_FULL_THRESH_NEGATE_VAL=30,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_3_arch;
| mit | 6fc17d2c9f9afb963b4fa1b29dc14d7c | 0.627919 | 2.916162 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/singleportRAM.vhd | 1 | 963 | -- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_sp is
generic(
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 9
);
port(
-- Port A
a_clk : in std_logic;
a_we : in std_logic;
a_en : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
a_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end bram_sp;
architecture rtl of bram_sp is
-- Shared memory
type mem_type is array ((2 ** ADDR_WIDTH) - 1 downto 0) of std_logic_vector(DATA_WIDTH - 1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_clk)
begin
if (a_clk'event and a_clk = '1') then
if (a_we = '1' and a_en = '1') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
end rtl;
| mit | 75fd9faa2f700cf7dd0d300d6a372957 | 0.637591 | 2.574866 | false | false | false | false |
bazk/hwsat | templates/solver.vhd | 1 | 4,684 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity solver is
port (
clk: in std_logic;
reset: in std_logic;
sat: out std_logic;
unsat: out std_logic
);
end solver;
architecture behavioral of solver is
{% for var in variables %}
component control_{{ var.name }}
port (
clk: in std_logic;
reset: in std_logic;
lclear: out std_logic;
lchange: out std_logic;
lcontra: out std_logic;
gclear: in std_logic;
gchange: in std_logic;
gcontra: in std_logic;
{% for var2 in variables -%}
{{ var2.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
eil: in std_logic;
eol: out std_logic;
eir: in std_logic;
eor: out std_logic;
ldebug_num_decisions: out integer;
ldebug_num_conflicts: out integer;
ldebug_num_backtracks: out integer
);
end component;
for control_{{ var.name }}_0: control_{{ var.name }} use entity work.control_{{ var.name }};
signal lclear_{{ var.name }}, lchange_{{ var.name }}, lcontra_{{ var.name }}: std_logic;
signal {{ var.name }}: std_logic_vector(0 to 1);
signal channel_{{ loop.index }}_0, channel_{{ loop.index }}_1: std_logic;
signal ldebug_num_decisions_{{ var.name }}, ldebug_num_conflicts_{{ var.name }}, ldebug_num_backtracks_{{ var.name }}: integer;
{% endfor %}
signal gclear, gchange, gcontra: std_logic;
signal is_sat, is_unsat: std_logic;
signal gdebug_num_decisions, gdebug_num_conflicts, gdebug_num_backtracks, gdebug_counter: integer;
begin
{% for var in variables %}
control_{{ var.name }}_0: control_{{ var.name }} port map (
clk => clk,
reset => reset,
lclear => lclear_{{ var.name }},
lchange => lchange_{{ var.name }},
lcontra => lcontra_{{ var.name }},
gclear => gclear,
gchange => gchange,
gcontra => gcontra,
{% for var2 in variables -%}
{{ var2.name }} => {{ var2.name }},
{% endfor %}
{% if loop.index > 1 %}
eil => channel_{{ loop.index-1 }}_0,
eol => channel_{{ loop.index-1 }}_1,
{% else %}
eil => '1',
eol => is_unsat,
{% endif %}
{% if loop.index < len_variables %}
eor => channel_{{ loop.index }}_0,
eir => channel_{{ loop.index }}_1,
{% else %}
eor => is_sat,
eir => '0',
{% endif %}
ldebug_num_decisions => ldebug_num_decisions_{{ var.name }},
ldebug_num_conflicts => ldebug_num_conflicts_{{ var.name }},
ldebug_num_backtracks => ldebug_num_backtracks_{{ var.name }}
);
{% endfor %}
gclear <= {% for var in variables %} lclear_{{ var.name }} or{% endfor %} '0';
gchange <= {% for var in variables %} lchange_{{ var.name }} or{% endfor %} '0';
gcontra <= {% for var in variables %} lcontra_{{ var.name }} or{% endfor %} '0';
sat <= is_sat;
unsat <= is_unsat;
process (clk, reset)
begin
if (reset='1') then
gdebug_num_decisions <= 0;
gdebug_num_conflicts <= 0;
gdebug_num_backtracks <= 0;
gdebug_counter <= 0;
else
if (gdebug_counter >= 8192) or (is_sat='1') or (is_unsat='1') then
gdebug_num_decisions <= {% for var in variables %} ldebug_num_decisions_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
gdebug_num_conflicts <= {% for var in variables %} ldebug_num_conflicts_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
gdebug_num_backtracks <= {% for var in variables %} ldebug_num_backtracks_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
report "STATS " & integer'image(gdebug_num_decisions) & " " & integer'image(gdebug_num_conflicts) & " " & integer'image(gdebug_num_backtracks);
gdebug_counter <= 0;
else
gdebug_counter <= gdebug_counter + 1;
end if;
if (is_sat='1') then
report "RESULT SAT";
{% for var in variables %}
if ({{ var.name }}="10") then
report "VALUE {{ var.name }}";
elsif ({{ var.name }}="01") then
report "VALUE -{{ var.name }}";
end if;
{% endfor %}
elsif (is_unsat='1') then
report "RESULT UNSAT";
end if;
end if;
end process;
end behavioral; | gpl-3.0 | f9c31a905b1fbd74504bc726b95de9c9 | 0.511956 | 3.896839 | false | false | false | false |
titto-thomas/Pipeline_RISC | FrwdBlock.vhd | 1 | 4,299 | ----------------------------------------
-- Conditional update of RF Write : IITB-RISC
-- Author : Titto Thomas
-- Date : 23/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FrwdBlock is
port (
clock, reset : in std_logic;
iteration : in std_logic_vector(3 downto 0);
MA_M4_Sel, WB_M4_Sel : in std_logic_vector(1 downto 0); -- M4 sel lines
MA_RFWrite, WB_RFWrite : in std_logic; -- RF write
OpCode : in std_logic_vector(5 downto 0); -- Opcode (12-15 & 0-1)
Curr_M7_Sel, Curr_M8_Sel : in std_logic_vector(1 downto 0); -- Current Mux select lines
MA_Ir911, WB_Ir911, Ir35, Ir68, Ir911 : in std_logic_vector(2 downto 0); -- Source and destination registers
MA_ALUout, MA_MemOut, WB_ALUout, WB_MemOut : in std_logic_vector(15 downto 0); -- ALUout and Data memory out
M7_In, M8_In : out std_logic_vector(15 downto 0); -- Inputs for M7 and M8
Nxt_M7_Sel, Nxt_M8_Sel : out std_logic_vector(1 downto 0) -- Updated Mux select lines
);
end FrwdBlock;
architecture behave of FrwdBlock is
signal ite : integer range 0 to 8 := 0;
begin --behave
ite <= to_integer(unsigned(iteration));
Main : process ( clock, reset )
begin
if clock = '1' then
if ( Opcode(5 downto 2) = x"0" or Opcode(5 downto 2) = x"1" or Opcode(5 downto 2) = x"2" ) then
if (( MA_Ir911 = Ir35 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1') )then
M8_In <= MA_ALUout;
Nxt_M8_Sel <= b"10";
if (( MA_Ir911 = Ir68 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1')) then
Nxt_M7_Sel <= b"11";
M7_In <= MA_ALUout;
elsif (( WB_Ir911 = Ir68 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1')) then
Nxt_M7_Sel <= b"11";
M7_In <= WB_MemOut;
else
Nxt_M7_Sel <= Curr_M7_Sel;
M7_In <= x"0000";
end if;
elsif (( MA_Ir911 = Ir68 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1') ) then
M7_In <= MA_ALUout;
Nxt_M7_Sel <= b"11";
if (( MA_Ir911 = Ir35 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1')) then
Nxt_M8_Sel <= b"10";
M8_In <= MA_ALUout;
elsif (( WB_Ir911 = Ir35 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1')) then
Nxt_M8_Sel <= b"10";
M8_In <= WB_MemOut;
else
Nxt_M8_Sel <= Curr_M8_Sel;
M8_In <= x"0000";
end if;
elsif (( WB_Ir911 = Ir35 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1') ) then
M8_In <= WB_Memout;
Nxt_M8_Sel <= b"10";
if (( MA_Ir911 = Ir68 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1')) then
Nxt_M7_Sel <= b"11";
M7_In <= MA_ALUout;
elsif (( WB_Ir911 = Ir68 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1')) then
Nxt_M7_Sel <= b"11";
M7_In <= WB_MemOut;
else
Nxt_M7_Sel <= Curr_M7_Sel;
M7_In <= x"0000";
end if;
elsif (( WB_Ir911 = Ir68 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1') ) then
M7_In <= WB_Memout;
Nxt_M7_Sel <= b"11";
if (( MA_Ir911 = Ir35 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1')) then
Nxt_M8_Sel <= b"10";
M8_In <= MA_ALUout;
elsif (( WB_Ir911 = Ir35 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1')) then
Nxt_M8_Sel <= b"10";
M8_In <= WB_MemOut;
else
Nxt_M8_Sel <= Curr_M8_Sel;
M8_In <= x"0000";
end if;
else
Nxt_M7_Sel <= Curr_M7_Sel;
Nxt_M8_Sel <= Curr_M8_Sel;
M7_In <= MA_ALUout;
M8_In <= MA_ALUout;
end if;
elsif ( Opcode(5 downto 2) = x"6" or Opcode(5 downto 2) = x"7" ) and ite = 0 then -- Need to rethink !!!
M7_In <= MA_ALUout;
Nxt_M7_Sel <= Curr_M7_Sel;
if (( MA_Ir911 = Ir911 ) and (MA_M4_Sel = b"01") and (MA_RFWrite = '1') )then
M8_In <= MA_ALUout;
Nxt_M8_Sel <= b"10";
elsif (( MA_Ir911 = Ir911 ) and (MA_M4_Sel = b"00") and (MA_RFWrite = '1') )then
M8_In <= MA_Memout;
Nxt_M8_Sel <= b"10";
elsif (( WB_Ir911 = Ir911 ) and (WB_M4_Sel = b"00") and (WB_RFWrite = '1') ) then
M8_In <= WB_MemOut;
Nxt_M8_Sel <= b"10";
elsif (( WB_Ir911 = Ir911 ) and (WB_M4_Sel = b"01") and (WB_RFWrite = '1') ) then
M8_In <= WB_ALUout;
Nxt_M8_Sel <= b"10";
else
Nxt_M8_Sel <= Curr_M8_Sel;
M8_In <= MA_ALUout;
end if;
else
Nxt_M7_Sel <= Curr_M7_Sel;
Nxt_M8_Sel <= Curr_M8_Sel;
M7_In <= MA_ALUout;
M8_In <= MA_ALUout;
end if;
end if;
end process Main;
end behave;
| gpl-2.0 | 480bbd5e48442da53691bd5674332683 | 0.552454 | 2.39099 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/LUTROM/example_design/LUTROM_prod.vhd | 1 | 9,901 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: LUTROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : LUTROM.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 18
-- C_READ_WIDTH_A : 18
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 18
-- C_READ_WIDTH_B : 18
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY LUTROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END LUTROM_prod;
ARCHITECTURE xilinx OF LUTROM_prod IS
COMPONENT LUTROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : LUTROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 274f963d654d8e9cc64730f06b8d2108 | 0.494698 | 3.842064 | false | false | false | false |
lennartbublies/ecdsa | src/e_sha256_constants.vhd | 1 | 1,776 | -- SHA256 Hashing Module - Constants
-- Kristian Klomsten Skordal <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use work.sha256_types.all;
package sha256_constants is
-- Initial intermediate hash values:
constant INITIAL_A : std_logic_vector(31 downto 0) := x"6a09e667";
constant INITIAL_B : std_logic_vector(31 downto 0) := x"bb67ae85";
constant INITIAL_C : std_logic_vector(31 downto 0) := x"3c6ef372";
constant INITIAL_D : std_logic_vector(31 downto 0) := x"a54ff53a";
constant INITIAL_E : std_logic_vector(31 downto 0) := x"510e527f";
constant INITIAL_F : std_logic_vector(31 downto 0) := x"9b05688c";
constant INITIAL_G : std_logic_vector(31 downto 0) := x"1f83d9ab";
constant INITIAL_H : std_logic_vector(31 downto 0) := x"5be0cd19";
-- Array of constants used in the algorithm:
constant constants : constant_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
-- TODO: Store in block ROM
end package;
| gpl-3.0 | 02ece12a8bc99bbc28bdb7e5e75febfa | 0.697635 | 2.184502 | false | false | false | false |
titto-thomas/Pipeline_RISC | Memory.vhdl | 1 | 1,409 | ----------------------------------------
-- Memory Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Memory is
port (
clock : in std_logic; -- clock
write : in std_logic; -- write to the memory
read : in std_logic; -- read from the memory
address : in std_logic_vector(15 downto 0); -- address of the memory being read
data_in : in std_logic_vector(15 downto 0); -- data input
data_out : out std_logic_vector(15 downto 0) -- data output
);
end Memory;
architecture RAM of Memory is
type mem_type is array (65535 downto 0) of std_logic_vector(15 downto 0); -- the size of the memory in use
signal mem : mem_type;
begin
data_out <= mem(to_integer(unsigned(address))) when (read = '1') else (others => 'Z'); -- give the memory content as the output
------------------- writing the data to the register ------------------------------------
Memory_Write : process(clock)
begin
if (rising_edge(clock)) then
if (write = '1') then
mem (to_integer(unsigned(address))) <= data_in ; -- write the input data on the corresponding location
end if;
end if;
end process Memory_Write;
-----------------------------------------------------------------------------------------
end architecture RAM;
| gpl-2.0 | f0fe63be9c62a20a80e3e5a012eea3be | 0.549326 | 3.903047 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/sim/blk_mem_gen_0.vhd | 1 | 12,112 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 512,
C_READ_DEPTH_A => 512,
C_ADDRA_WIDTH => 9,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 512,
C_READ_DEPTH_B => 512,
C_ADDRB_WIDTH => 9,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.966099 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | 72a7130a11e04f49e623ffbc9269e4b8 | 0.612533 | 3.211029 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/dependencies0/subunit0/subunit0_arch.vhd | 1 | 231 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ARCHITECTURE rtl OF subunit0 IS
BEGIN
a_ready <= b_ready;
b_data <= a_data;
b_last <= a_last;
b_strb <= a_strb;
b_valid <= a_valid;
END ARCHITECTURE rtl; | mit | bc40d7fb2be935f2db27acfed855de26 | 0.679654 | 2.483871 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sim_1/imports/simulation/aeg_tb.vhd | 2 | 21,800 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 28.11.2013 13:51:50
-- Design Name:
-- Module Name: aeg1500_tb - Behavioral
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado
--
-- Description: test automotive ethernet gateway
-- test one port in a user side loopback
-- the number of test frames and the frames size are arbitrary
----------------------------------------------------------------------------------
entity aeg_tb is
end aeg_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_tb is
-- aeg_tb properties
constant NR_TEST_FRAMES : integer := 20; -- number of frames sent
constant FRAME_LENGTH : integer := 64; -- ethernet frame size
constant MAX_FRAME_LENGTH : integer := 1522;
constant PAYLOAD_LENGTH : integer := FRAME_LENGTH - 18;
-- aeg constants
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic--;
-- Main example design controls
-------------------------------
--reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to MAX_FRAME_LENGTH);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ;
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_init : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
procedure init_frame is
variable length_type : std_logic_vector(15 downto 0);
variable data_byte : std_logic_vector(15 downto 0);
variable i : integer;
begin
frame_data.columns(0) := ( DATA => X"12", VALID => '1', ERROR => '0'); -- Destination Address (DA)'),
frame_data.columns(1) := ( DATA => X"34", VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => X"56", VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => X"78", VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(5) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(6) := ( DATA => X"5A", VALID => '1', ERROR => '0'); -- Source Address (5A)
frame_data.columns(7) := ( DATA => X"02", VALID => '1', ERROR => '0');
frame_data.columns(8) := ( DATA => X"03", VALID => '1', ERROR => '0');
frame_data.columns(9) := ( DATA => X"04", VALID => '1', ERROR => '0');
frame_data.columns(10) := ( DATA => X"05", VALID => '1', ERROR => '0');
frame_data.columns(11) := ( DATA => X"06", VALID => '1', ERROR => '0');
length_type := std_logic_vector(to_unsigned(PAYLOAD_LENGTH,length_type'length));
frame_data.columns(12) := ( DATA => length_type(15 downto 8), VALID => '1', ERROR => '0');
frame_data.columns(13) := ( DATA => length_type(7 downto 0), VALID => '1', ERROR => '0'); -- Length/Type
i := 14;
while i < PAYLOAD_LENGTH + 14 loop
data_byte := std_logic_vector(to_unsigned(i-13 ,data_byte'length));
frame_data.columns(i) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0'); -- Payload
i := i+1;
end loop;
while i < 60 loop
frame_data.columns(i) := ( DATA => X"00", VALID => '1', ERROR => '0'); -- Padding
i := i+1;
end loop;
frame_data.columns(i) := ( DATA => X"00", VALID => '0', ERROR => '0'); -- Stop writing
end procedure init_frame;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
init_frame;
management_config_finished <= true;
wait;
end process p_init;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = NR_TEST_FRAMES-3 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
if dest_address6 mod 4 /= 3 and dest_address6 /= NR_TEST_FRAMES-3 then
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
| mit | e6e0caacfb3c29b21bbae7f5aae2ba7b | 0.481927 | 4.219899 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s3/counter/counter.vhd | 1 | 932 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: counter.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (number : out std_logic_vector (N - 1 downto 0) := (others => '0');
clk, r : in std_logic);
end entity counter;
architecture beh_arch_counter of counter is
begin
process (clk, r)
variable old_number : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
if r = '1' then
number <= (others => '0');
old_number := (others => '0');
end if;
if clk = '1' and clk'event then
old_number := old_number + (0 => '1');
number <= old_number;
end if;
end process;
end architecture beh_arch_counter;
| gpl-3.0 | b0a8f3e1772d0bcc17ed4fc9ecf6f3ba | 0.521459 | 3.464684 | false | false | false | false |
diecaptain/kalman_mppt | k_kalman_final.vhd | 1 | 3,508 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_kalman_final is
port
( clock : in std_logic;
Uofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
pofk : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end k_kalman_final;
architecture struct of k_kalman_final is
component kn_kalman_Vactcapdashofkplusone is
port
( clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pdashofkplusone is
port
( clock : in std_logic;
Pofk : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Kofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
R : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end component;
signal I1 : std_logic_vector (31 downto 0) := "00111101010011001100110011001101";
signal I2 : std_logic_vector (31 downto 0) := "00111100001000111101011100001010";
signal I3 : std_logic_vector (31 downto 0) := "00111000110100011011011100010111";
signal X1,X2,X3 : std_logic_vector (31 downto 0);
begin
M1 : kn_kalman_Vactcapdashofkplusone
port map ( clock => clock,
Vactcapofk => Vactcapofk,
M => I1,
Uofk => Uofk,
Vactcapdashofkplusone => X1 );
M2 : kn_kalman_Pdashofkplusone
port map ( clock => clock,
Pofk => Pofk,
Q => I2,
Pdashofkplusone => X2 );
M3 : kn_kalman_Kofkplusone
port map ( clock => clock,
Pdashofkplusone => X2,
R => I3,
Kofkplusone => X3 );
M4 : kn_kalman_Pofkplusone
port map ( clock => clock,
Pdashofkplusone => X2,
Kofkplusone => X3,
Pofkplusone => Pofkplusone );
M5 : kn_kalman_Vactcapofkplusone
port map ( clock => clock,
Vactcapdashofkplusone => X1,
Vrefofkplusone => Vrefofkplusone,
Kofkplusone => X3,
Vactcapofkplusone => Vactcapofkplusone );
end struct; | gpl-2.0 | b9796c166998854e8014f235344c320c | 0.572121 | 4.320197 | false | false | false | false |
lennartbublies/ecdsa | src/e_ecdsa_key_generation.vhd | 1 | 3,343 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Key Generation
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable sign or verify
-- k_i - Input private key_generation
-- xQ_o - x component of public key
-- yQ_o - y component of public key
-- ready_o - Ready flag if sign or validation is complete
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 02.07.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) ecdsa top level entity
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_ecdsa_key_generation IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Enable computation
enable_i: IN std_logic;
-- Private Key
k_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Public Key
xQ_o: INOUT std_logic_vector(M-1 DOWNTO 0);
yQ_o: INOUT std_logic_vector(M-1 DOWNTO 0);
-- Ready flag
ready_o: OUT std_logic
);
END e_ecdsa_key_generation;
ARCHITECTURE rtl OF e_ecdsa_key_generation IS
-- Components -----------------------------------------
-- Import entity e_gf2m_doubleadd_point_multiplication
COMPONENT e_gf2m_point_multiplication IS
--COMPONENT e_gf2m_doubleadd_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Internal signals -----------------------------------------
--SIGNAL k : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- k for point generator, should be cryptograic secure randum number!
SIGNAL xG : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- X of generator point G = (x, y)
SIGNAL yG : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0'); -- Y of generator point G = (x, y)
BEGIN
-- Set parameter of sect163k1
xG <= "010" & x"FE13C0537BBC11ACAA07D793DE4E6D5E5C94EEE8";
yG <= "010" & x"89070FB05D38FF58321F2E800536D538CCDAA3D9";
--k <= "000" & x"CD06203260EEE9549351BD29733E7D1E2ED49D88";
-- Instantiate multiplier to compute (xQ, yQ) = dP
key_generation: e_gf2m_point_multiplication GENERIC MAP (
--key_generation: e_gf2m_doubleadd_point_multiplication GENERIC MAP (
MODULO => P
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_i,
xp_i => xG,
yp_i => yG,
k => k_i,
xq_io => xQ_o,
yq_io => yQ_o,
ready_o => ready_o
);
END; | gpl-3.0 | 64133629a60b95528b471d7a59d1239d | 0.507927 | 3.602371 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_eea_inversion.vhd | 1 | 7,044 | ----------------------------------------------------------------------------------------------------
-- Entity - GF(2^M) Extended Euclidean Inversion
-- Computes the 1/x mod F IN GF(2**M)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- a_i - Input value
-- z_o - Inversion of input value
-- ready_o - Ready flag
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 26.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) eea inversion data path
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_eea_inversion_data_path IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
-- Input signals
r, s: IN std_logic_vector(M DOWNTO 0);
u, v: IN std_logic_vector(M DOWNTO 0);
d: IN STD_LOGIC_VECTOR (logM DOWNTO 0);
-- Output signals
new_r, new_s: OUT std_logic_vector(M DOWNTO 0);
new_u, new_v: OUT std_logic_vector(M DOWNTO 0);
new_d: OUT STD_LOGIC_VECTOR (logM DOWNTO 0)
);
END e_gf2m_eea_inversion_data_path;
ARCHITECTURE rtl of e_gf2m_eea_inversion_data_path IS
CONSTANT zero: std_logic_vector(logM DOWNTO 0):= (OTHERS => '0');
BEGIN
PROCESS(r,s,u,v,d)
BEGIN
IF R(m) = '0' THEN
new_R <= R(M-1 DOWNTO 0) & '0';
new_U <= U(M-1 DOWNTO 0) & '0';
new_S <= S;
new_V <= V;
new_d <= d + 1;
ELSE
IF d = ZERO THEN
IF S(m) = '1' THEN
new_R <= (S(M-1 DOWNTO 0) xor R(M-1 DOWNTO 0)) & '0';
new_U <= (V(M-1 DOWNTO 0) xor U(M-1 DOWNTO 0)) & '0';
ELSE
new_R <= S(M-1 DOWNTO 0) & '0';
new_U <= V(M-1 DOWNTO 0) & '0';
END IF;
new_S <= R;
new_V <= U;
new_d <= (0=> '1', OTHERS => '0');
ELSE
new_R <= R;
new_U <= '0' & U(M DOWNTO 1);
IF S(m) = '1' THEN
new_S <= (S(M-1 DOWNTO 0) xor R(M-1 DOWNTO 0)) & '0';
new_V <= (V xor U);
ELSE
new_S <= S(M-1 DOWNTO 0) & '0';
new_V <= V;
END IF;
new_d <= d - 1;
END IF;
END IF;
END PROCESS;
END rtl;
------------------------------------------------------------
-- GF(2^M) eea inversion
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0) := ONE(M-1 DOWNTO 0)
);
PORT (
-- Clock, reset and enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
a_i: IN std_logic_vector (M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_eea_inversion;
ARCHITECTURE rtl of e_gf2m_eea_inversion IS
COMPONENT e_gf2m_eea_inversion_data_path
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
r, s : IN std_logic_vector(M DOWNTO 0);
u, v : IN std_logic_vector(M DOWNTO 0);
d : IN std_logic_vector(logM DOWNTO 0);
new_r, new_s : OUT std_logic_vector(M DOWNTO 0);
new_u, new_v : OUT std_logic_vector(M DOWNTO 0);
new_d : OUT std_logic_vector(logM DOWNTO 0)
);
END COMPONENT;
SIGNAL count: natural RANGE 0 TO 2*M;
TYPE states IS RANGE 0 TO 3;
SIGNAL current_state: states;
SIGNAL first_step, capture: std_logic;
SIGNAL r, s, new_r, new_s : std_logic_vector(M DOWNTO 0);
SIGNAL u, v, new_u, new_v: std_logic_vector(M DOWNTO 0);
SIGNAL d, new_d: std_logic_vector(logM DOWNTO 0);
BEGIN
-- Instantiate inversion data path
data_path_block: e_gf2m_eea_inversion_data_path GENERIC MAP (
MODULO => MODULO
) PORT MAP(
r => r,
s => s,
u => u,
v => v,
d => d,
new_r => new_r,
new_s => new_s,
new_u => new_u,
new_v => new_v,
new_d => new_d
);
z_o <= u(M-1 DOWNTO 0);
PROCESS(clk_i, rst_i, a_i, first_step)
BEGIN
-- Reset entity on reset
IF rst_i = '1' THEN
r <= (OTHERS => '0');
s <= (OTHERS => '0');
u <= (OTHERS => '0');
v <= (OTHERS => '0');
d <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF first_step = '1' THEN
r <= ('0' & a_i);
s <= ('1' & MODULO);
u <= (0 => '1', OTHERS => '0');
v <= (OTHERS => '0');
d <= (OTHERS => '0');
ELSIF capture = '1' THEN
--IF capture = '1' THEN
r <= new_r; s <= new_s;
u <= new_u; v <= new_v;
d <= new_d;
END IF;
END IF;
END PROCESS;
counter: PROCESS(rst_i, clk_i)
BEGIN
IF rst_i = '1' THEN
count <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
IF first_step = '1' THEN
count <= 0;
ELSIF capture = '1' THEN
count <= count+1;
END IF;
END IF;
END PROCESS counter;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state, count)
BEGIN
-- Handle current state
CASE current_state IS
WHEN 0 TO 1 => first_step <= '0'; ready_o <= '1'; capture <= '0';
WHEN 2 => first_step <= '1'; ready_o <= '0'; capture <= '0';
WHEN 3 => first_step <= '0'; ready_o <= '0'; capture <= '1';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF count = 2*M-1 THEN
current_state <= 0;
END IF;
END CASE;
END IF;
END PROCESS control_unit;
END rtl; | gpl-3.0 | c4bea6dc109be3339470a5eb1e2f4ca5 | 0.425894 | 3.608607 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/automotive_ethernet_gateway.vhd | 2 | 26,733 | --------------------------------------------------------------------------------
-- File : automotive_ethernet_gateway.vhd
-- Author : Andreas Ettner
-- -----------------------------------------------------------------------------
-- Description: This module is the top level layer of the automotive ethernet
-- gateway switch. It contains following modules:
--
-- This level:
--
-- * Instantiates the switch_ports and switch_fabric
--
-- * Instantiates the clocking circuitry and resets
--
-- * Instantiates a state machine which drives the AXI Lite
-- interface to bring the TEMACs up in the correct state
--
-- * Instantiates a global counter to measure the latency of messages through the switch
-- // IMPORTANT: comment the latency port for hardware implementations
-- decomment the latency port for simulations
-- remove the latency port as soon as vivado supports vhdl2008 which allows
-- signal addressing of submodules in test benches
--
-- Constant generic values are defined in this module for global values (switch width, number of ports, MAC values)
-- More values are defined in the corresponding submodules
--
-- Debugging with Integrated Logic Analyser (ILA) might cause an error because of a path name larger than 260 bytes
-- Solution: Create a virtual drive with the .xpr in its root (use the subst command in the cmd console)
-- run implementation on the virtual drive
-- To avoid an waveform error when debugging, restart vivado after implementation on the original drive
--------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity automotive_ethernet_gateway is
Generic (
RECEIVER_DATA_WIDTH : integer := 8;
TRANSMITTER_DATA_WIDTH : integer := 8;
FABRIC_DATA_WIDTH : integer := 32;
NR_PORTS : integer := 4;
ARBITRATION : integer := 2; -- 1: Round Robin, 2: Priority based, 3: Latency based,
-- 4: Weighted prio/latency based, 5: to do: Fair Queuing
FRAME_LENGTH_WIDTH : integer := 11;
NR_IQ_FIFOS : integer := 1;
NR_OQ_FIFOS : integer := 1;
VLAN_PRIO_WIDTH : integer := 3;
TIMESTAMP_WIDTH : integer := 64;
GMII_DATA_WIDTH : integer := 8;
TX_IFG_DELAY_WIDTH : integer := 8;
PAUSE_VAL_WIDTH : integer := 16;
CONFIG_VECTOR_WIDTH : integer := 80
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic_vector(NR_PORTS-1 downto 0);
intn : in std_logic_vector(NR_PORTS-1 downto 0);
debug0 : out std_logic;
debug1 : out std_logic;
debug2 : out std_logic;
debug3 : out std_logic;
--latency : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0); -- COMMENT THIS LINE for hardware implementation
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_er : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_clk : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_rxd : in std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_er : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
mii_tx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
-- MDIO Interface
-----------------
mdio : inout std_logic_vector(NR_PORTS-1 downto 0);
mdc : out std_logic_vector(NR_PORTS-1 downto 0)
);
end automotive_ethernet_gateway;
architecture wrapper of automotive_ethernet_gateway is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
component timer
Generic (
TIMESTAMP_WIDTH : integer
);
Port (
refclk : in std_logic;
resetn : in std_logic;
clk_cycle_cnt : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for a switch port
------------------------------------------------------------------------------
component aeg_design_0_switch_port
Generic (
RECEIVER_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer;
PORT_ID : integer
);
Port (
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
latency : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
-- Receiver Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
-- RX Switch Fabric Intrface
------------------------------------------
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- Transmitter Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(TX_IFG_DELAY_WIDTH-1 downto 0);
-- TX Switch Fabric Intrface
---------------------------------------------
tx_path_clock : in std_logic;
tx_path_resetn : in std_logic;
tx_in_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
tx_in_valid : in std_logic;
tx_in_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
tx_in_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
tx_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
tx_in_req : in std_logic;
tx_in_accept_frame : out std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(PAUSE_VAL_WIDTH-1 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
phy_interrupt_n : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the switch fabric
------------------------------------------------------------------------------
component aeg_design_0_switch_fabric
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
fabric_clk : in std_logic;
fabric_resetn : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
fabric_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_ports_req : in std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
fabric_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_in_ports_gnt : out std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
-- data TO the TX data path
fabric_out_prio : out std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_out_timestamp : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_out_data : out std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_out_valid : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_length : out std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_out_req : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_accept_frame : in std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the clocking logic
------------------------------------------------------------------------------
component aeg_design_0_clocks is
port (
-- clocks
clk_in_p : in std_logic;
clk_in_n : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
dcm_locked : out std_logic;
-- clock outputs
gtx_clk_bufg : out std_logic;
refclk_bufg : out std_logic;
s_axi_aclk : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset logic
------------------------------------------------------------------------------
component aeg_design_0_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Shareable logic component declarations
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support_resets
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic
);
end component;
-- Internal signals
signal idelayctrl_reset : std_logic;
signal idelayctrl_ready : std_logic;
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal s_axi_aclk : std_logic;
signal rx_mac_aclk : std_logic;
signal tx_mac_aclk : std_logic;
signal phy_resetn_sig : std_logic;
-- resets (and reset generation)
signal s_axi_resetn : std_logic;
signal gtx_resetn : std_logic;
signal rx_reset : std_logic := '0';
signal tx_reset : std_logic := '0';
signal dcm_locked : std_logic;
signal glbl_rst_intn : std_logic;
-- USER side RX AXI-S interface
signal rx2fabric_data : std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
signal rx2fabric_valid : std_logic_vector(NR_PORTS-1 downto 0);
signal rx2fabric_last : std_logic_vector(NR_PORTS-1 downto 0);
signal rx2fabric_ports_req : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
signal rx2fabric_prio : std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
signal rx2fabric_timestamp : std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
signal rx2fabric_length : std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
signal rx2fabric_ports_gnt : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
-- USER side TX AXI-S interface
signal fabric2tx_prio : std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
signal fabric2tx_timestamp : std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
signal fabric2tx_data : std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
signal fabric2tx_valid : std_logic_vector(NR_PORTS-1 downto 0);
signal fabric2tx_length : std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
signal fabric2tx_req : std_logic_vector(NR_PORTS-1 downto 0);
signal fabric2tx_accept_frame : std_logic_vector(NR_PORTS-1 downto 0);
-- ifg_delay
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example
signal rx_configuration_vector : std_logic_vector(CONFIG_VECTOR_WIDTH*NR_PORTS-1 downto 0);
signal tx_configuration_vector : std_logic_vector(CONFIG_VECTOR_WIDTH*NR_PORTS-1 downto 0);
-- evaluation signals
signal timestamp_cnt : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency : std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0); -- COMMENT THIS LINE for simulation
signal debug0_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal debug1_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal debug2_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal debug3_sig : std_logic_vector(NR_PORTS-1 downto 0);
begin
-- Instantiate the sharable reset logic
tri_mode_ethernet_mac_support_resets_i : tri_mode_ethernet_mac_0_support_resets
port map(
glbl_rstn => glbl_rst_intn,
refclk => refclk_bufg,
idelayctrl_ready => idelayctrl_ready,
idelayctrl_reset_out => idelayctrl_reset
);
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
tri_mode_ethernet_mac_idelayctrl_common_i : IDELAYCTRL
port map (
RDY => idelayctrl_ready,
REFCLK => refclk_bufg,
RST => idelayctrl_reset
);
----------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
----------------------------------------------------------------------------
aeg_clocks : aeg_design_0_clocks
port map (
-- differential clock inputs
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
-- asynchronous control/resets
glbl_rst => glbl_rst,
dcm_locked => dcm_locked,
-- clock outputs
gtx_clk_bufg => gtx_clk_bufg,
refclk_bufg => refclk_bufg,
s_axi_aclk => s_axi_aclk
);
------------------------------------------------------------------------------
-- Generate resets
------------------------------------------------------------------------------
aeg_resets : aeg_design_0_resets
port map (
-- clocks
s_axi_aclk => s_axi_aclk,
gtx_clk => gtx_clk_bufg,
-- asynchronous resets
glbl_rst => glbl_rst,
rx_reset => rx_reset,
tx_reset => tx_reset,
dcm_locked => dcm_locked,
-- synchronous reset outputs
glbl_rst_intn => glbl_rst_intn,
gtx_resetn => gtx_resetn,
s_axi_resetn => s_axi_resetn,
phy_resetn => phy_resetn_sig
);
-- generate the user side resets
phy_resetn <= (others => phy_resetn_sig);
timer_i : timer
Generic map(
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
refclk => gtx_clk_bufg,
resetn => glbl_rst_intn,
clk_cycle_cnt => timestamp_cnt
);
Xports : for PORT_ID in 0 to NR_PORTS-1 generate
switch_port : aeg_design_0_switch_port
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
TRANSMITTER_DATA_WIDTH => TRANSMITTER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
NR_OQ_FIFOS => NR_OQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH,
PORT_ID => PORT_ID
)
port map (
gtx_clk => gtx_clk_bufg,
-- asynchronous reset
glbl_rstn => glbl_rst_intn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
timestamp_cnt => timestamp_cnt,
latency => latency((PORT_ID+1)*TIMESTAMP_WIDTH-1 downto PORT_ID*TIMESTAMP_WIDTH),
debug0_sig => debug0_sig(PORT_ID),
debug1_sig => debug1_sig(PORT_ID),
debug2_sig => debug2_sig(PORT_ID),
debug3_sig => debug3_sig(PORT_ID),
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => open,
-- Receiver
------------------------------------------
rx_path_clock => gtx_clk_bufg,
rx_path_resetn => gtx_resetn,
rx_out_data => rx2fabric_data((PORT_ID+1)*FABRIC_DATA_WIDTH-1 downto PORT_ID*FABRIC_DATA_WIDTH),
rx_out_valid => rx2fabric_valid(PORT_ID),
rx_out_last => rx2fabric_last(PORT_ID),
rx_out_ports_req => rx2fabric_ports_req((PORT_ID+1)*NR_PORTS-1 downto PORT_ID*NR_PORTS),
rx_out_prio => rx2fabric_prio((PORT_ID+1)*VLAN_PRIO_WIDTH-1 downto PORT_ID*VLAN_PRIO_WIDTH),
rx_out_timestamp => rx2fabric_timestamp((PORT_ID+1)*TIMESTAMP_WIDTH-1 downto PORT_ID*TIMESTAMP_WIDTH),
rx_out_length => rx2fabric_length((PORT_ID+1)*FRAME_LENGTH_WIDTH-1 downto PORT_ID*FRAME_LENGTH_WIDTH),
rx_out_ports_gnt => rx2fabric_ports_gnt((PORT_ID+1)*NR_PORTS-1 downto PORT_ID*NR_PORTS),
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => open,
tx_ifg_delay => tx_ifg_delay,
-- Transmitter
---------------------------------------------
tx_path_clock => gtx_clk_bufg,
tx_path_resetn => gtx_resetn,
tx_in_data => fabric2tx_data((PORT_ID+1)*FABRIC_DATA_WIDTH-1 downto PORT_ID*FABRIC_DATA_WIDTH),
tx_in_valid => fabric2tx_valid(PORT_ID),
tx_in_length => fabric2tx_length((PORT_ID+1)*FRAME_LENGTH_WIDTH-1 downto PORT_ID*FRAME_LENGTH_WIDTH),
tx_in_prio => fabric2tx_prio((PORT_ID+1)*VLAN_PRIO_WIDTH-1 downto PORT_ID*VLAN_PRIO_WIDTH),
tx_in_timestamp => fabric2tx_timestamp((PORT_ID+1)*TIMESTAMP_WIDTH-1 downto PORT_ID*TIMESTAMP_WIDTH),
tx_in_req => fabric2tx_req(PORT_ID),
tx_in_accept_frame => fabric2tx_accept_frame(PORT_ID),
-- MAC Control Interface
--------------------------
pause_req => '0',
pause_val => (others => '0'),
-- GMII Interface
-------------------
gmii_txd => gmii_txd((PORT_ID+1)*GMII_DATA_WIDTH-1 downto PORT_ID*GMII_DATA_WIDTH),
gmii_tx_en => gmii_tx_en(PORT_ID),
gmii_tx_er => gmii_tx_er(PORT_ID),
gmii_tx_clk => gmii_tx_clk(PORT_ID),
gmii_rxd => gmii_rxd((PORT_ID+1)*GMII_DATA_WIDTH-1 downto PORT_ID*GMII_DATA_WIDTH),
gmii_rx_dv => gmii_rx_dv(PORT_ID),
gmii_rx_er => gmii_rx_er(PORT_ID),
gmii_rx_clk => gmii_rx_clk(PORT_ID),
mii_tx_clk => mii_tx_clk(PORT_ID),
phy_interrupt_n => intn(PORT_ID),
-- MDIO Interface
-------------------
mdio => mdio(PORT_ID),
mdc => mdc(PORT_ID),
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn
);
end generate Xports;
------------------------------------------------------------------------------
-- Instantiate the switching fabric
------------------------------------------------------------------------------
switch_fabric : aeg_design_0_switch_fabric
generic map (
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
ARBITRATION => ARBITRATION,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map (
fabric_clk => gtx_clk_bufg,
fabric_resetn => gtx_resetn,
timestamp_cnt => timestamp_cnt,
-- rxpath interface
fabric_in_data => rx2fabric_data,
fabric_in_valid => rx2fabric_valid,
fabric_in_last => rx2fabric_last,
fabric_in_ports_req => rx2fabric_ports_req,
fabric_in_prio => rx2fabric_prio,
fabric_in_timestamp => rx2fabric_timestamp,
fabric_in_length => rx2fabric_length,
fabric_in_ports_gnt => rx2fabric_ports_gnt,
-- txpath interface
fabric_out_prio => fabric2tx_prio,
fabric_out_timestamp => fabric2tx_timestamp,
fabric_out_data => fabric2tx_data,
fabric_out_valid => fabric2tx_valid,
fabric_out_length => fabric2tx_length,
fabric_out_req => fabric2tx_req,
fabric_out_accept_frame => fabric2tx_accept_frame
);
debug0 <= intn(0);
-- debug1 <= intn(1);
-- debug2 <= intn(2);
-- debug3 <= intn(3);
--debug0 <= debug0_sig(0);
debug1 <= debug1_sig(0);
debug2 <= debug2_sig(0);
debug3 <= debug3_sig(0);
end wrapper;
| mit | 7abcc1229430302ab0d2cdc74a0f5fe9 | 0.481951 | 4.096384 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/LUTROM/example_design/LUTROM_exdes.vhd | 1 | 4,322 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUTROM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY LUTROM_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END LUTROM_exdes;
ARCHITECTURE xilinx OF LUTROM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT LUTROM IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : LUTROM
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 4a4c7727affbc7f64a0f4aae1f143193 | 0.574734 | 4.85073 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_fabric/aeg_design_switch_fabric.vhd | 2 | 7,462 | --------------------------------------------------------------------------------
-- File : aeg_design_switch_fabric.vhd
-- Author : Andreas Ettner
-- -----------------------------------------------------------------------------
-- Description:
-- the switching fabric consists of one fabric_arbitration module for each output port
-- the arbitration module decides which input port is allowed to transmit data to
-- its output port
-- the switching module instantiates the fabric_arbitration modules and handles the
-- wiring between the input ports and the arbitration modules
--
-- further information can be found in file switch_fabric.svg
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity aeg_design_0_switch_fabric is
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
fabric_clk : in std_logic;
fabric_resetn : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
fabric_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
fabric_in_ports_req : in std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
fabric_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_in_ports_gnt : out std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
-- data TO the TX data path
fabric_out_prio : out std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
fabric_out_timestamp : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
fabric_out_data : out std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
fabric_out_valid : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_length : out std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
fabric_out_req : out std_logic_vector(NR_PORTS-1 downto 0);
fabric_out_accept_frame : in std_logic_vector(NR_PORTS-1 downto 0)
);
end aeg_design_0_switch_fabric;
architecture structural of aeg_design_0_switch_fabric is
component switch_fabric_arbitration is
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
clk : in std_logic;
reset : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
farb_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
farb_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_ports_req : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
farb_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
farb_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
farb_in_ports_gnt : out std_logic_vector(NR_PORTS-1 downto 0);
-- data TO the TX data path
farb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
farb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
farb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
farb_out_valid : out std_logic;
farb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
farb_out_req : out std_logic;
farb_out_accept_frame : in std_logic
);
end component;
signal reset : std_logic;
signal ports_req_sig : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
signal ports_gnt_sig : std_logic_vector(NR_PORTS*NR_PORTS-1 downto 0);
begin
reset <= not fabric_resetn;
-- reorder req and grant symbols
-- as one req/gnt signal of each input port should be connected to one arbitration module
assign_p : process(ports_gnt_sig, fabric_in_ports_req)
begin
for i in 0 to NR_PORTS-1 loop
for o in 0 to NR_PORTS-1 loop
ports_req_sig(i*NR_PORTS+o) <= fabric_in_ports_req(o*NR_PORTS+i);
fabric_in_ports_gnt(i*NR_PORTS+o) <= ports_gnt_sig(o*NR_PORTS+i);
end loop;
end loop;
end process;
-- connect the signals from the input port to the arbitration modules
Xarb : for INST in 0 to NR_PORTS-1 generate
fabric_arbitration : switch_fabric_arbitration
generic map(
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
ARBITRATION => ARBITRATION,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map(
clk => fabric_clk,
reset => reset,
timestamp_cnt => timestamp_cnt,
-- data from the input ports
farb_in_data => fabric_in_data,
farb_in_valid => fabric_in_valid,
farb_in_last => fabric_in_last,
farb_in_ports_req => ports_req_sig((INST+1)*NR_PORTS-1 downto INST*NR_PORTS),
farb_in_prio => fabric_in_prio,
farb_in_timestamp => fabric_in_timestamp,
farb_in_length => fabric_in_length,
farb_in_ports_gnt => ports_gnt_sig((INST+1)*NR_PORTS-1 downto INST*NR_PORTS),
-- data to the output port
farb_out_prio => fabric_out_prio((INST+1)*VLAN_PRIO_WIDTH-1 downto INST*VLAN_PRIO_WIDTH),
farb_out_timestamp => fabric_out_timestamp((INST+1)*TIMESTAMP_WIDTH-1 downto INST*TIMESTAMP_WIDTH),
farb_out_data => fabric_out_data((INST+1)*FABRIC_DATA_WIDTH-1 downto INST*FABRIC_DATA_WIDTH),
farb_out_valid => fabric_out_valid(INST),
farb_out_length => fabric_out_length((INST+1)*FRAME_LENGTH_WIDTH-1 downto INST*FRAME_LENGTH_WIDTH),
farb_out_req => fabric_out_req(INST),
farb_out_accept_frame => fabric_out_accept_frame(INST)
);
end generate Xarb;
end structural;
| mit | 7f20f46bbbab9748c40b21065c9a3e2e | 0.553471 | 3.884435 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/mac/mac_fifo/switch_output_port_fifo.vhd | 2 | 3,654 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 12.12.2013 10:41:20
-- Design Name:
-- Module Name: switch_output_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between switch port on the transmit path and MAC
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 32 entries
--
-- see switch_mac_txfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_output_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
TRANSMITTER_DATA_WIDTH : integer
);
port (
-- User-side interface (write)
tx_fifo_in_clk : in std_logic;
tx_fifo_in_reset : in std_logic;
tx_fifo_in_data : in std_logic_vector(TRANSMITTER_DATA_WIDTH-1 downto 0);
tx_fifo_in_valid : in std_logic;
tx_fifo_in_last : in std_logic;
tx_fifo_in_ready : out std_logic;
-- MAC-side interface (read)
tx_fifo_out_clk : in std_logic;
tx_fifo_out_reset : in std_logic;
tx_fifo_out_data : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_out_valid : out std_logic;
tx_fifo_out_last : out std_logic;
tx_fifo_out_ready : in std_logic;
tx_fifo_out_error : out std_logic
);
end switch_output_port_fifo;
architecture rtl of switch_output_port_fifo is
component fifo_generator_3 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal din_sig : std_logic_vector(TRANSMITTER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal full_sig : std_logic;
signal empty_sig : std_logic;
begin
din_sig <= '0' & tx_fifo_in_last & tx_fifo_in_data;
-- module output ports
tx_fifo_out_error <= dout_sig(GMII_DATA_WIDTH+2-1);
tx_fifo_out_last <= dout_sig(GMII_DATA_WIDTH+1-1);
tx_fifo_out_data <= dout_sig(GMII_DATA_WIDTH-1 downto 0);
tx_fifo_in_ready <= not full_sig;
tx_fifo_out_valid <= not empty_sig;
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_3
PORT MAP (
wr_clk => tx_fifo_in_clk,
wr_rst => tx_fifo_in_reset,
wr_en => tx_fifo_in_valid,
din => din_sig,
full => full_sig,
rd_clk => tx_fifo_out_clk,
rd_rst => tx_fifo_out_reset,
rd_en => tx_fifo_out_ready,
dout => dout_sig,
empty => empty_sig
);
end rtl;
| mit | a8c1ae079a98ae535b999e403dcda4cb | 0.514778 | 3.456954 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/axi_lite_sm/tri_mode_ethernet_mac_0_axi_lite_sm.vhd | 1 | 36,859 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_axi_lite_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end tri_mode_ethernet_mac_0_axi_lite_sm;
architecture rtl of tri_mode_ethernet_mac_0_axi_lite_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
CHANGE_SPEED,
MDIO_RD,
MDIO_POLL_CHECK,
MDIO_1G,
MDIO_10_100,
MDIO_RESTART,
MDIO_LOOPBACK,
MDIO_STATS,
MDIO_STATS_POLL_CHECK,
RESET_MAC_RX,
RESET_MAC_TX,
CNFG_MDIO,
CNFG_FLOW,
CNFG_FILTER,
CNFG_FRM_FILTER_1,
CNFG_FRM_FILTER_2,
CNFG_FRM_FILTER_3,
CNFG_FRM_FILTER_MASK_1,
CNFG_FRM_FILTER_MASK_2,
CNFG_FRM_FILTER_MASK_3,
CHECK_SPEED);
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Flow control configuration register address (0x40C0)
constant CONFIG_FLOW_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"40C";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- Unicast Word 0 configuration register address (0x7000)
constant CONFIG_UNI0_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"700";
-- Unicast Word 1 configuration register address (0x7040)
constant CONFIG_UNI1_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"704";
-- Address Filter configuration register address (0x7080)
constant CONFIG_ADDR_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"708";
-- Frame filter bytes (3 to 0) register address (0x710)
constant CONFIG_FRAME_FILTER_1 : std_logic_vector(16 downto 0) := "00000" & X"710";
-- Frame filter bytes (7 to 4) register address (0x714)
constant CONFIG_FRAME_FILTER_2 : std_logic_vector(16 downto 0) := "00000" & X"714";
-- Frame filter bytes (11 to 8) register address (0x718)
constant CONFIG_FRAME_FILTER_3 : std_logic_vector(16 downto 0) := "00000" & X"718";
-- Frame filter mask bytes (3 to 0) register address (0x750)
constant CONFIG_FRAME_FILTER_MASK_1 : std_logic_vector(16 downto 0) := "00000" & X"750";
-- Frame filter mask bytes (7 to 4) register address (0x754)
constant CONFIG_FRAME_FILTER_MASK_2 : std_logic_vector(16 downto 0) := "00000" & X"754";
-- Frame filter mask bytes (11 to 8) register address (0x758)
constant CONFIG_FRAME_FILTER_MASK_3 : std_logic_vector(16 downto 0) := "00000" & X"758";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0);
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0);
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal speedis10 : std_logic;
signal speedis100 : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
signal design_on_board : std_logic_vector(3 downto 0) := X"0";
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
speedis10 <= '1' when speed = "00" else '0';
speedis100 <= '1' when speed = "01" else '0';
update_speed_sync_inst :tri_mode_ethernet_mac_0_sync_block
port map (
clk => s_axi_aclk,
data_in => update_speed,
data_out => update_speed_sync
);
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write 2E to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
-- enable mdio)
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000068";
axi_state <= CHANGE_SPEED;
end if;
when CHANGE_SPEED =>
-- program the MAC to the required speed
assert false
report "Programming MAC speed" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= speed & X"0000000" & "00";
axi_state <= MDIO_RD;
when MDIO_RD =>
-- read phy status - if response is all ones then do not perform any
-- further MDIO accesses
assert false
report "Checking for PHY" & cr
severity note;
drive_mdio <= '1'; -- switch axi transactions to use mdio values..
start_mdio <= '1';
writenread <= '0';
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_POLL_CHECK;
when MDIO_POLL_CHECK =>
if axi_rd_data(15 downto 0) = X"ffff" then
-- if status is all ones then no PHY exists at this address
-- (this is used by the tri_mode_ethernet_mac_0_demo_tb to avoid performing lots of phy accesses)
design_on_board <= X"0";
axi_state <= RESET_MAC_RX;
else
design_on_board <= X"8";
axi_state <= MDIO_1G;
end if;
when MDIO_1G =>
-- set 1G advertisement
assert false
report "Setting PHY 1G advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_1000BASET_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- 0x200 is 1G full duplex, 0x100 is 1G half duplex
-- only advertise the mode we want..
axi_wr_data <= X"0000" & "000000" & speed(1) & '0' & X"00";
axi_state <= MDIO_10_100;
when MDIO_10_100 =>
-- set 10/100 advertisement
assert false
report "Setting PHY 10/100M advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_ABILITY_REG;
mdio_op <= MDIO_OP_WR;
-- bit8 : full 100M, bit7 : half 100M, bit6 : full 10M, bit5 : half 10M
-- only advertise the mode we want..
axi_wr_data <= X"00000" & "000" & speedis100 & '0' & speedis10 & "000000";
axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
if phy_loopback = '1' then
-- bit15: software reset, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "10" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= MDIO_LOOPBACK;
else
-- bit15: software reset, bit12 : AN enable (set after power up)
axi_wr_data <= X"0000" & X"9" & X"000";
axi_state <= MDIO_STATS;
end if;
when MDIO_LOOPBACK =>
-- set phy loopback
assert false
report "Applying PHY loopback" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- bit14: loopback, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "01" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= RESET_MAC_RX;
when MDIO_STATS =>
start_mdio <= '1';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= RESET_MAC_RX;
else
axi_state <= MDIO_STATS;
end if;
-- once here the PHY is ACTIVE - NOTE only IEEE registers are used
when RESET_MAC_RX =>
assert false
report "Reseting MAC RX" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= RECEIVER_ADD;
axi_wr_data <= X"90000000";
axi_state <= RESET_MAC_TX;
when RESET_MAC_TX =>
assert false
report "Reseting MAC TX" & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= TRANSMITTER_ADD;
axi_wr_data <= X"90000000";
axi_state <= CNFG_MDIO;
when CNFG_MDIO =>
-- set up MDC frequency. Write 2E to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
-- enable mdio)
assert false
report "Setting MDC Frequency to 2.5MHZ...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000068";
axi_state <= CNFG_FLOW;
when CNFG_FLOW =>
assert false
report "Disabling Flow control...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= (others => '0');
axi_state <= CNFG_FILTER;
when CNFG_FILTER =>
if design_on_board = X"0" then
assert false
report "Setting core to non-promiscuous mode...." & cr
severity note;
else
assert false
report "Setting core to promiscuous mode...." & cr
severity note;
end if;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= design_on_board & X"0000000";
axi_state <= CNFG_FRM_FILTER_1;
when CNFG_FRM_FILTER_1 =>
assert false
report "Configuring FRAME FILTER 1 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_1;
axi_wr_data <= X"040302DA";
axi_state <= CNFG_FRM_FILTER_MASK_1;
when CNFG_FRM_FILTER_MASK_1 =>
assert false
report "Configuring FRAME FILTER mask 1 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_1;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CNFG_FRM_FILTER_2;
when CNFG_FRM_FILTER_2 =>
assert false
report "Configuring FRAME FILTER 2 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_2;
axi_wr_data <= X"025A0605";
axi_state <= CNFG_FRM_FILTER_MASK_2;
when CNFG_FRM_FILTER_MASK_2 =>
assert false
report "Configuring FRAME FILTER mask 2 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_2;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CNFG_FRM_FILTER_3;
when CNFG_FRM_FILTER_3 =>
assert false
report "Configuring FRAME FILTER 3 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_3;
axi_wr_data <= X"06050403";
axi_state <= CNFG_FRM_FILTER_MASK_3;
when CNFG_FRM_FILTER_MASK_3 =>
assert false
report "Configuring FRAME FILTER mask 3 ..." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FRAME_FILTER_MASK_3;
axi_wr_data <= X"FFFFFFFF";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
if update_speed_reg = '1' then
axi_state <= CHANGE_SPEED;
speed <= mac_speed;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
| mit | 4bc4265117c24f169c5691d21dbce1ec | 0.474348 | 4.313012 | false | true | false | false |
titto-thomas/Pipeline_RISC | testbench(ADC,ADZ).vhdl | 1 | 2,255 | ----------------------------------------
-- Main Processor - Testbench : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture behave of testbench is
component pipeline_RISC is
port (
clock, reset : in std_logic; -- clock and reset signals
InstrData, InstrAddress, DataData, DataAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, InstrWrite, DataWrite : in std_logic -- Program / Execution mode
);
end component;
signal clock, reset, mode, InstrWrite, DataWrite : std_logic := '0';
signal InstrData, InstrAddress, DataData, DataAddress : std_logic_vector(15 downto 0);
begin --behave
DUT : pipeline_RISC port map (clock, reset, InstrData, InstrAddress, DataData, DataAddress, mode, InstrWrite, DataWrite);
clock <= not clock after 5 ns;
Main : process
begin
reset <= '1';
InstrData <= x"4201";
InstrAddress <= x"0000";
DataData <= x"0000";
DataAddress <= x"0000";
mode <= '1';
InstrWrite <= '0';
DataWrite <= '0';
InstrWrite <= '1';
wait for 10 ns;
InstrData <= x"4402";
InstrAddress <= x"0001";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0002";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0003";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0004";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0005";
wait for 10 ns;
InstrData <= x"0850";
InstrAddress <= x"0006";
wait for 10 ns;
InstrData <= x"06D4";
InstrAddress <= x"0005";
wait for 100 ns;
InstrData <= x"031A";
InstrAddress <= x"0007";
wait for 10 ns;
InstrData <= x"0319";
InstrAddress <= x"0008";
wait for 10 ns;
InstrData <= x"1A7F";
InstrAddress <= x"0009";
wait for 10 ns;
InstrData <= x"031A";
InstrAddress <= x"000A";
wait for 10 ns;
InstrWrite <= '0';
DataWrite <= '1';
DataData <= x"1234";
DataAddress <= x"0001";
wait for 10 ns;
DataData <= x"ABCD";
DataAddress <= x"0002";
wait for 10 ns;
DataWrite <= '0';
reset <= '0';
mode <= '0';
wait ;
end process;
end behave;
| gpl-2.0 | 80caa3b32a5868ad07c988edb095c22a | 0.619512 | 3.258671 | false | false | false | false |
lfmunoz/4dsp_sip_interface | pulse2pulse.vhd | 5 | 4,426 |
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
entity pulse2pulse is
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end pulse2pulse;
architecture syn of pulse2pulse is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal out_set :std_logic;
signal out_set_prev :std_logic;
signal out_set_prev2 :std_logic;
signal in_set :std_logic;
signal outreset :std_logic;
signal in_reset :std_logic;
signal in_reset_prev :std_logic;
signal in_reset_prev2:std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
--*********************************************************************************
begin
--*********************************************************************************
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_proc:process(in_clk,rst)
begin
if(rst = '1') then
in_reset <= '0';
in_reset_prev <= '0';
in_reset_prev2<= '0';
in_set <= '0';
elsif(in_clk'event and in_clk = '1') then
--regitser a pulse on the pulse in port
--reset the signal when the ouput has registerred the pulse
if (in_reset_prev = '1' and in_reset_prev2 = '1') then
in_set <= '0';
elsif (pulsein = '1') then
in_set <= '1';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
in_reset <= outreset;
in_reset_prev <= in_reset;
in_reset_prev2 <= in_reset_prev;
end if;
end process in_proc;
out_proc:process(out_clk,rst)
begin
if(rst = '1') then
out_set <= '0';
out_set_prev <= '0';
out_set_prev2 <= '0';
outreset <= '0';
pulseout <= '0';
elsif(out_clk'event and out_clk = '1') then
--generate a pulse on the outpput when the
--set signal has travelled through the synchronising fip flops
if (out_set_prev = '1' and out_set_prev2 = '0') then
pulseout <= '1';
else
pulseout <= '0';
end if;
--feedback the corret reception of the set signal to reset the set pulse
if (out_set_prev = '1' and out_set_prev2 = '1') then
outreset <= '1';
elsif (out_set_prev = '0' and out_set_prev2 = '0') then
outreset <= '0';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
out_set <= in_set;
out_set_prev <= out_set;
out_set_prev2 <= out_set_prev;
end if;
end process out_proc;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
inbusy <= in_set or in_reset_prev;
-------------------
-------------------
end syn; | mit | 81fa35288ccc71ba8f713c04b136f082 | 0.372571 | 4.863736 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_module_transmit.vhd | 1 | 3,865 | -------------------------------------------------------------------------------
-- Module: tb_module_transmit
-- Purpose: Testbench for module e_uart_transmit_mux.
--
-- Author: Leander Schulz
-- Date: 15.09.2017
-- Last change: 22.10.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_module_transmit IS
END ENTITY tb_module_transmit;
ARCHITECTURE tb_arch OF tb_module_transmit IS
--CONSTANT M : integer := 8;
-- IMPORT e_uart_transmit_mux COMPONENT
COMPONENT e_uart_transmit_mux IS
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
enable_i : IN std_logic;
r_i : IN std_logic_vector(M-1 DOWNTO 0);
s_i : IN std_logic_vector(M-1 DOWNTO 0);
v_i : IN std_logic;
uart_o : OUT std_logic
);
END COMPONENT e_uart_transmit_mux;
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL s_mode : std_logic := '0';
SIGNAL s_enable : std_logic := '0';
-- bytes from int(1) to int(20) + '111'
SIGNAL s_r_i : std_logic_vector(M-1 DOWNTO 0) := "1110000000100000010000000110000010000000101000001100000011100001000000010010000101000001011000011000000110100001110000011110001000000010001000100100001001100010100";
SIGNAL s_s_i : std_logic_vector(M-1 DOWNTO 0) := "101" & x"1B1A19181716151413121118A2E0CC0D99F8A5EF";
SIGNAL s_verify : std_logic := '0';
SIGNAL s_tx : std_logic;
BEGIN
-- Instantiate uart transmitter
transmit_instance : e_uart_transmit_mux
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
mode_i => s_mode,
enable_i => s_enable,
r_i => s_r_i,
s_i => s_s_i,
v_i => s_verify,
uart_o => s_tx
);
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
tx_gen : PROCESS
BEGIN
-- Simulate Transmission of example keys
-- Simulation time ~ 850us
WAIT FOR 80 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 200 ns;
s_enable <= '1';
WAIT FOR 20 ns;
s_enable <= '0';
WAIT FOR 990000 ns;
-- Simulation of verify (mode = 1; verify = True = 1)
s_mode <= '1';
s_verify <= '1';
-- run
WAIT FOR 100 ns;
s_enable <= '1';
WAIT FOR 20 ns;
s_enable <= '0';
WAIT FOR 500 ns;
ASSERT (s_tx /= '1') REPORT "TX not Zero!" SEVERITY FAILURE;
WAIT FOR 2500 ns;
ASSERT (s_tx /= '0') REPORT "TX not One!" SEVERITY FAILURE;
WAIT FOR 100000 ns;
-- Simulation of verify (mode = 1; verify = False = 0)
s_mode <= '1';
s_verify <= '0';
-- run
WAIT FOR 100 ns;
s_enable <= '1';
WAIT FOR 20 ns;
s_enable <= '0';
WAIT FOR 500 ns;
ASSERT (s_tx /= '1') REPORT "TX not Zero!" SEVERITY FAILURE;
WAIT FOR 2500 ns;
ASSERT (s_tx /= '1') REPORT "TX not Zero!" SEVERITY FAILURE;
WAIT FOR 100000 ns;
-- Simulate Transmission of example keys
-- Simulation time ~ 850us
s_mode <= '0';
s_enable <= '1';
WAIT FOR 20 ns;
s_enable <= '0';
WAIT;
END PROCESS tx_gen;
END ARCHITECTURE tb_arch;
| gpl-3.0 | ce6f6415d01859b9f2900113a0110326 | 0.470116 | 3.907988 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_overflow.vhd | 2 | 2,174 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.4
--
-- Description:
-- combinatioral path to check for overflow of the iq_memory and iq_fifos
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end input_queue_overflow;
architecture rtl of input_queue_overflow is
begin
-- overflow if the memory currently written to is one address below current fifo word
-- or if fifo is full
overflow_detection_p : process(mem_rd_addr, mem_wr_addr, fifo_empty, fifo_full)
begin
for i in 0 to NR_IQ_FIFOS-1 loop
if fifo_empty(i) = '0' and mem_rd_addr(i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1
downto i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START) - mem_wr_addr = 1 then
overflow(i) <= '1';
elsif fifo_full(i) = '1' then
overflow(i) <= '1';
else
overflow(i) <= '0';
end if;
end loop;
end process;
end rtl;
| mit | 1af4bbee9ae70fa600c91a8f136ccee4 | 0.536339 | 3.774306 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/lookuptable1/example_design/lookuptable1_exdes.vhd | 1 | 5,419 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: lookuptable1_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY lookuptable1_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END lookuptable1_exdes;
ARCHITECTURE xilinx OF lookuptable1_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT lookuptable1 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : lookuptable1
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-3.0 | 566efe2da2961f0fa53a3a06d6eda4e4 | 0.553423 | 4.607993 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_point_addition.vhd | 1 | 9,317 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Addition
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- x1_i - X part of first point
-- y1_i - Y part of first point
-- x2_i - X part of seccond point
-- y2_i - Y part of thirs point
-- x3_io - X part of output point
-- y3_o - Y part of output point
-- ready_o - Ready flag
--
-- Math:
-- s = (py-qy)/(px-qx)
-- rx = s^2 - s - (px-qx)
-- ry = s * (px - rx) - rx - py
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/K163_addition.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 27.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) elliptic curve point addition
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT(
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_addition;
ARCHITECTURE rtl of e_gf2m_point_addition IS
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Temporary signals for divider and multiplier
SIGNAL div_in1, div_in2, lambda, lambda_square, mult_in2, mult_out: std_logic_vector(M-1 DOWNTO 0);
SIGNAL x3_tmp, y3_tmp, next_xq, next_yq: std_logic_vector(M-1 DOWNTO 0);
-- Signals to switch between multiplier and divider
SIGNAL start_div, div_done, start_mult, mult_done: std_logic;
SIGNAL load, ch_q: std_logic;
SIGNAL sel: std_logic_vector(1 DOWNTO 0);
-- Define all available states
subtype states IS natural RANGE 0 TO 10;
SIGNAL current_state: states;
BEGIN
-- Output register
register_q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
x3_io <= (OTHERS=>'1');
y3_o <= (OTHERS=>'1');
ELSIF ch_q = '1' THEN
x3_io <= next_xq;
y3_o <= next_yq;
END IF;
END IF;
END PROCESS;
-- Instantiate divider entity
-- Calculate s = (py-qy)/(px-qx)
divider: e_gf2m_divider GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_div,
g_i => div_in1,
h_i => div_in2,
z_o => lambda,
ready_o => div_done
);
-- Instantiate squarer
-- Calculate s^2
lambda_square_computation: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => lambda,
c_o => lambda_square
);
-- Instantiate multiplier entity
-- Calculate s * (px - rx)
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_mult,
a_i => lambda,
b_i => mult_in2,
z_o => mult_out,
ready_o => mult_done
);
-- Set divider input from entity input
-- Calculate (py-qy) and (px-qx)
divider_inputs: FOR i IN 0 TO M-1 GENERATE
div_in1(i) <= y1_i(i) xor y2_i(i);
div_in2(i) <= x1_i(i) xor x2_i(i);
END GENERATE;
-- Set multiplier input from entity input
-- Calculate (px - rx)
multiplier_inputs: FOR i IN 0 TO M-1 GENERATE
mult_in2(i) <= x1_i(i) xor x3_tmp(i);
END GENERATE;
-- Set x3(0)
--x3_tmp(0) <= not(lambda_square(0) xor lambda(0) xor div_in2(0));
-- Set output
-- Calculate rx = s^2 - s - (px-qx)
x_output: FOR i IN 0 TO M-1 GENERATE
x3_tmp(i) <= lambda_square(i) xor lambda(i) xor div_in2(i) xor a(i);
END GENERATE;
-- Calculate ry = s * (px - rx) - rx - py
y_output: FOR i IN 0 TO M-1 GENERATE
y3_tmp(i) <= mult_out(i) xor x3_tmp(i) xor y1_i(i);
END GENERATE;
WITH sel SELECT next_yq <= y3_tmp WHEN "00", y1_i WHEN "01", y2_i WHEN OTHERS;
WITH sel SELECT next_xq <= x3_tmp WHEN "00", x1_i WHEN "01", x2_i WHEN OTHERS;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate s = (py-qy)/(px-qx), s^2
-- 4,5,6 : Calculate rx/ry
CASE current_state IS
WHEN 0 TO 1 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '1';
WHEN 2 => load <= '1'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 3 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 4 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '1'; start_mult <= '0'; ready_o <= '0';
WHEN 5 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 6 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '1'; ready_o <= '0';
WHEN 7 => load <= '0'; sel <= "00"; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 8 => load <= '0'; sel <= "00"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 9 => load <= '0'; sel <= "11"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 10 => load <= '0'; sel <= "01"; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (x1_i = ONES) OR (y1_i = ONES) THEN
current_state <= 9;
ELSIF (x2_i = ONES) OR (y2_i = ONES) THEN
current_state <= 10;
ELSE
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF div_done = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF mult_done = '1' THEN
current_state <= 8;
END IF;
WHEN 8 =>
current_state <= 0;
WHEN 9 =>
current_state <= 0;
WHEN 10 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS;
END rtl;
| gpl-3.0 | ecc400f6a67cc23dfc949839a71cf9ec | 0.461415 | 3.440547 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_gf2m_eea_inversion.vhd | 1 | 6,200 | ----------------------------------------------------------------------------------------------------
-- Testbench - GF(2^M) Extended Euclidean Inversion
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_eea_inversion IS
END tb_eea_inversion;
ARCHITECTURE rtl OF tb_eea_inversion IS
-- Import entity e_gf2m_eea_inversion
COMPONENT e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_classic_gf2m_multiplier
COMPONENT e_gf2m_classic_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL x, z, z_by_x : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, done: std_logic;
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate eea inversion entity
uut1: e_gf2m_eea_inversion GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP (
clk_i => clk,
rst_i => rst,
enable_i => enable,
a_i => x,
z_o => z,
ready_o => done
);
-- Instantiate classic multiplication entity
uut2: e_gf2m_classic_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP (
a_i => x,
b_i => z,
c_o => z_by_x
);
-- Create clock signal
PROCESS -- clock process FOR clk
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
PROCEDURE gen_random(X : OUT std_logic_vector (M-1 DOWNTO 0); w: natural; s1, s2: inout Natural) IS
VARIABLE i_x, aux: integer;
VARIABLE rand: real;
BEGIN
aux := W/16;
FOR i IN 1 TO aux LOOP
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(65536)));-- real(2**16)));
x(i*16-1 DOWNTO (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16);
END LOOP;
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16))));
x(w-1 DOWNTO aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16));
END PROCEDURE;
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
VARIABLE seed1, seed2: positive;
VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer;
VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0;
VARIABLE avg_cycles: real;
VARIABLE initial_time, final_time: time;
VARIABLE xx: std_logic_vector (M-1 DOWNTO 0) ;
BEGIN
min_cycles:= 2**20;
enable <= '0'; rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Generate random test cases
FOR I IN 1 TO NUMBER_TESTS LOOP
gen_random(xx, M, seed1, seed2);
WHILE (xx = ZERO) LOOP
gen_random(xx, M, seed1, seed2);
END LOOP;
x <= xx;
-- Check needed number of cycles
enable <= '1'; initial_time := now;
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL done = '1';
final_time := now;
cycles := (final_time - initial_time)/PERIOD;
total_cycles := total_cycles+cycles;
ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) &
" TotalCycles: " & integer'image(total_cycles) SEVERITY WARNING;
IF cycles > max_cycles THEN
max_cycles:= cycles;
END IF;
IF cycles < min_cycles THEN
min_cycles:= cycles;
END IF;
WAIT FOR 2*PERIOD;
-- Validate if x * x^-1 = 1
IF ( ONE /= z_by_x) THEN
write(TX_LOC,string'("ERROR!!! z_by_x=")); write(TX_LOC, z_by_x);
write(TX_LOC,string'("/= ONE="));
write(TX_LOC,string'("( z=")); write(TX_LOC, z);
write(TX_LOC,string'(") using: ( A =")); write(TX_LOC, x);
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
END LOOP;
WAIT FOR DELAY;
avg_cycles := real(total_cycles)/real(NUMBER_TESTS);
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!. MinCycles: " & integer'image(min_cycles) &
" MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) &
" AvgCycles: " & real'image(avg_cycles)
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | bbffbca1142f62f3b6c4219bf45701b6 | 0.49371 | 3.803681 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/timer.vhd | 2 | 1,415 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 16.01.2014 10:36:58
-- Design Name:
-- Module Name: timer - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.4
--
-- Description: This module provides a global timer to take timestamp and calculate latencies
-- the counter increments every clock cycle (125 MHz -> 8 ns)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity timer is
Generic (
TIMESTAMP_WIDTH : integer
);
Port (
refclk : in std_logic;
resetn : in std_logic;
clk_cycle_cnt : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0)
);
end timer;
architecture rtl of timer is
signal cnt_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
begin
-- timestamp counter
cnt_p : process (refclk)
begin
if refclk'event and refclk = '1' then
if resetn = '0' then
cnt_reg <= (others => '0');
else
cnt_reg <= cnt_reg + 1;
end if;
end if;
end process;
clk_cycle_cnt <= cnt_reg;
end rtl;
| mit | 4caefb619b28f0a37133ae84b35416c7 | 0.50318 | 4.435737 | false | false | false | false |
lfmunoz/4dsp_sip_interface | fmc230_ctrl.vhd | 1 | 19,000 | -------------------------------------------------------------------------------------
-- FILE NAME : fmc230_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc230_ctrl
-- architecture - fmc230_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- fmc230_ctrl
-- Notes: fmc230_ctrl
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
-- Library declarations
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity fmc230_ctrl is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
--Additional clock
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
clk_to_fpga_buf : out std_logic;
--External trigger
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
ext_trigger_buf : out std_logic;
--DAC0 WFM Control
dac0_clk : in std_logic;
wfm0_load_size : out std_logic_vector(31 downto 0);
wfm0_load_start : out std_logic;
wfm0_offload_size : out std_logic_vector(31 downto 0);
wfm0_offload_start : out std_logic;
wfm0_offload_stop : out std_logic;
dac0_phy_en : out std_logic;
--DAC1 WFM Control
dac1_clk : in std_logic;
wfm1_load_size : out std_logic_vector(31 downto 0);
wfm1_load_start : out std_logic;
wfm1_offload_size : out std_logic_vector(31 downto 0);
wfm1_offload_start : out std_logic;
wfm1_offload_stop : out std_logic;
dac1_phy_en : out std_logic;
pg_m2c : in std_logic;
prsnt_m2c_l : in std_logic
);
end fmc230_ctrl;
architecture fmc230_ctrl_syn of fmc230_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component fmc230_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc230_stellar_cmd;
component pulse2pulse is
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component pulse2pulse;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_COMMAND : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_CONTROL : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_NB_BURSTS : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_BURST_SIZE : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_FMC_INFO : std_logic_vector(31 downto 0) := x"00000004";
constant EXT_TRIGGER_DISABLE : std_logic_vector(1 downto 0) := "00";
constant EXT_TRIGGER_RISE : std_logic_vector(1 downto 0) := "01";
constant EXT_TRIGGER_FALL : std_logic_vector(1 downto 0) := "10";
constant EXT_TRIGGER_BOTH : std_logic_vector(1 downto 0) := "11";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_val_ack: std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal wr_ack : std_logic;
signal dac0_en_reg : std_logic;
signal dac1_en_reg : std_logic;
signal trigger_sel_reg : std_logic_vector(1 downto 0);
signal nb_bursts_reg : std_logic_vector(31 downto 0);
signal burst_size_reg : std_logic_vector(31 downto 0);
signal cmd_reg : std_logic_vector(31 downto 0);
signal dac0_cmd : std_logic_vector(31 downto 0);
signal dac1_cmd : std_logic_vector(31 downto 0);
signal arm : std_logic;
signal disarm : std_logic;
signal sw_trigger : std_logic;
signal wfm0_arm : std_logic;
signal wfm0_disarm : std_logic;
signal wfm0_load : std_logic;
signal wfm1_arm : std_logic;
signal wfm1_disarm : std_logic;
signal wfm1_load : std_logic;
signal armed : std_logic;
signal adc0_en : std_logic;
signal adc1_en : std_logic;
signal adc2_en : std_logic;
signal adc3_en : std_logic;
signal dac0_en : std_logic;
signal dac1_en : std_logic;
signal unlim_bursts : std_logic;
signal nb_bursts_cnt : std_logic_vector(31 downto 0);
signal burst_size_cnt : std_logic_vector(31 downto 0);
signal trigger : std_logic;
signal clk_to_fpga : std_logic;
signal ext_trigger : std_logic;
signal ext_trigger_prev0 : std_logic;
signal ext_trigger_prev1 : std_logic;
signal ext_trigger_re : std_logic;
signal ext_trigger_fe : std_logic;
begin
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc230_stellar_cmd_inst : fmc230_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_val_ack => out_reg_val_ack,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
wr_ack => wr_ack,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
cmd_reg <= (others => '0');
dac0_en_reg <= '0';
dac1_en_reg <= '0';
trigger_sel_reg <= (others => '0');
nb_bursts_reg <= (others => '0');
burst_size_reg <= (others => '0');
in_reg_val <= '0';
in_reg <= (others => '0');
wr_ack <= '0';
elsif (rising_edge(clk_cmd)) then
-- Write
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_COMMAND) then
cmd_reg <= out_reg;
else
cmd_reg <= (others => '0');
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_CONTROL) then
dac0_en_reg <= out_reg(4);
dac1_en_reg <= out_reg(5);
trigger_sel_reg <= out_reg(7 downto 6);
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_NB_BURSTS) then
nb_bursts_reg <= out_reg;
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_BURST_SIZE) then
burst_size_reg <= out_reg;
end if;
-- Write acknowledge
if (out_reg_val_ack = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
-- Read
if (in_reg_req = '1' and in_reg_addr = ADDR_COMMAND) then
in_reg_val <= '1';
in_reg <= cmd_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_CONTROL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 24) &
trigger_sel_reg & dac1_en_reg & dac0_en_reg & conv_std_logic_vector(0, 4);
elsif (in_reg_req = '1' and in_reg_addr = ADDR_NB_BURSTS) then
in_reg_val <= '1';
in_reg <= nb_bursts_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_BURST_SIZE) then
in_reg_val <= '1';
in_reg <= burst_size_reg;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_FMC_INFO) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 30) & pg_m2c & not prsnt_m2c_l;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Transfer command pulses to other DAC0 clock domain
----------------------------------------------------------------------------------------------------
dac0_cmd_pls: for i in 0 to 31 generate
pulse2pulse_inst : pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => dac0_clk,
rst => rst,
pulsein => cmd_reg(i),
inbusy => open,
pulseout => dac0_cmd(i)
);
end generate;
----------------------------------------------------------------------------------------------------
-- Transfer command pulses to other DAC1 clock domain
----------------------------------------------------------------------------------------------------
dac1_cmd_pls: for i in 0 to 31 generate
pulse2pulse_inst : pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => dac1_clk,
rst => rst,
pulsein => cmd_reg(i),
inbusy => open,
pulseout => dac1_cmd(i)
);
end generate;
----------------------------------------------------------------------------------------------------
-- Map pulses
----------------------------------------------------------------------------------------------------
arm <= cmd_reg(0);
disarm <= cmd_reg(1);
sw_trigger <= cmd_reg(2);
wfm0_arm <= dac0_cmd(0);
wfm0_disarm <= dac0_cmd(1);
wfm0_load <= dac0_cmd(3);
wfm1_arm <= dac1_cmd(0);
wfm1_disarm <= dac1_cmd(1);
wfm1_load <= dac1_cmd(3);
----------------------------------------------------------------------------------------------------
-- LVDS Clock Input
----------------------------------------------------------------------------------------------------
ibufds_clock : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => clk_to_fpga_p,
ib => clk_to_fpga_n,
o => clk_to_fpga
);
----------------------------------------------------------------------------------------------------
-- LVDS Trigger Input
----------------------------------------------------------------------------------------------------
ibufds_trig : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => ext_trigger_p,
ib => ext_trigger_n,
o => ext_trigger
);
-----------------------------------------------------------------------------------
-- ADC triggering and burst control
-----------------------------------------------------------------------------------
process (rst, dac0_clk)
begin
if (rst = '1') then
ext_trigger_prev0 <= '0';
ext_trigger_prev1 <= '0';
ext_trigger_re <= '0';
ext_trigger_fe <= '0';
trigger <= '0';
armed <= '0';
unlim_bursts <= '0';
nb_bursts_cnt <= (others => '0');
burst_size_cnt <= (others => '0');
elsif (rising_edge(dac0_clk)) then
ext_trigger_prev0 <= ext_trigger;
ext_trigger_prev1 <= ext_trigger_prev0;
-- Generate pulse on rising edge external trigger
if (ext_trigger_prev0 = '1' and ext_trigger_prev1 = '0') then
ext_trigger_re <= '1';
else
ext_trigger_re <= '0';
end if;
-- Generate pulse on falling edge external trigger
if (ext_trigger_prev0 = '0' and ext_trigger_prev1 = '1') then
ext_trigger_fe <= '1';
else
ext_trigger_fe <= '0';
end if;
-- Select the trigger source
if (armed = '1' and sw_trigger = '1') then
trigger <= '1';
elsif (armed = '1' and ext_trigger_re = '1' and (trigger_sel_reg = EXT_TRIGGER_RISE or trigger_sel_reg = EXT_TRIGGER_BOTH) ) then
trigger <= '1';
elsif (armed = '1' and ext_trigger_fe = '1' and (trigger_sel_reg = EXT_TRIGGER_FALL or trigger_sel_reg = EXT_TRIGGER_BOTH) ) then
trigger <= '1';
else
trigger <= '0';
end if;
if (arm = '1' and armed = '0') then
armed <= '1';
elsif (disarm = '1' and armed = '1') then
armed <= '0';
elsif (unlim_bursts = '0' and nb_bursts_cnt = 0 and burst_size_cnt = 0) then
armed <= '0';
end if;
-- No of burst set to 0 means unlimited amount of bustst
if (armed = '0') then
unlim_bursts <= not or_reduce(nb_bursts_reg);
end if;
-- When not (yet) armed copy the register into the counter
if (armed = '0') then
nb_bursts_cnt <= nb_bursts_reg;
elsif (trigger = '1' and burst_size_cnt = 0 and nb_bursts_cnt /= 0) then
nb_bursts_cnt <= nb_bursts_cnt - '1';
end if;
-- Conversion start when the burst size counter is unequal to 0
-- Load the burst size counter on a trigger, when the previous burst is
-- finished and one or more channels are selected.
if (armed = '0') then
burst_size_cnt <= (others => '0');
elsif (trigger = '1' and burst_size_cnt = 0 and (nb_bursts_cnt /= 0 or unlim_bursts = '1')) then
burst_size_cnt <= burst_size_reg;
-- Decrease the burst size counter every conversion
elsif (burst_size_cnt /= 0) then
burst_size_cnt <= burst_size_cnt - 8;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
wfm0_load_size <= burst_size_reg(30 downto 0) & '0'; -- in bytes
wfm0_load_start <= wfm0_load and dac0_en;
wfm0_offload_size <= burst_size_reg(30 downto 0) & '0'; -- in bytes
wfm0_offload_start <= wfm0_arm and dac0_en;
wfm0_offload_stop <= wfm0_disarm;
wfm1_load_size <= burst_size_reg(30 downto 0) & '0'; -- in bytes
wfm1_load_start <= wfm1_load and dac1_en;
wfm1_offload_size <= burst_size_reg(30 downto 0) & '0'; -- in bytes
wfm1_offload_start <= wfm1_arm and dac1_en;
wfm1_offload_stop <= wfm1_disarm;
ext_trigger_buf <= ext_trigger_prev1;
clk_to_fpga_buf <= clk_to_fpga;
dac0_en <= dac0_en_reg;
dac1_en <= dac1_en_reg;
dac0_phy_en <= dac0_en;
dac1_phy_en <= dac1_en;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc230_ctrl_syn;
| mit | e0dca697f27a7793b7d9824a3bfd9e02 | 0.483421 | 3.756425 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/dualportRAM.vhd | 1 | 1,460 | -- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_tdp is
generic(
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 9
);
port(
-- Port A
a_clk : in std_logic;
a_we : in std_logic;
a_en : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
a_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Port B
b_clk : in std_logic;
b_we : in std_logic;
b_en : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
b_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end bram_tdp;
architecture rtl of bram_tdp is
-- Shared memory
type mem_type is array ((2 ** ADDR_WIDTH) - 1 downto 0) of std_logic_vector(DATA_WIDTH - 1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_clk)
begin
if (a_clk'event and a_clk = '1') then
if (a_we = '1' and a_en = '1') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if (b_clk'event and b_clk = '1') then
if (b_we = '1' and b_en = '1') then
mem(conv_integer(b_addr)) := b_din;
end if;
b_dout <= mem(conv_integer(b_addr));
end if;
end process;
end rtl;
| mit | 00b0c6355e1cf8fe8cdcee09ea7c9010 | 0.619178 | 2.491468 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/sim/blk_mem_gen_1.vhd | 1 | 12,112 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.528025 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
| mit | 0db1071bdb360e931846b225ff385dcf | 0.612616 | 3.212732 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_classic_multiplier.vhd | 1 | 5,211 | ----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Classic multiplication
-- Computes the polynomial multiplication mod F IN GF(2**m).
--
-- Ports:
-- a_i - First input value
-- b_i - Seccond input value
-- c_i - Output value
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) classical matrix multiplication
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_multiplier IS
PORT (
-- Input signals
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output SIGNAL
d_o: OUT std_logic_vector(2*M-2 DOWNTO 0)
);
END e_gf2m_multiplier;
ARCHITECTURE rtl OF e_gf2m_multiplier IS
-- Target matrix WITH double size of input
TYPE matrix_ands IS array (0 TO 2*M-2) OF STD_LOGIC_VECTOR(2*M-2 DOWNTO 0);
SIGNAL a_by_b: matrix_ands;
-- Temporary output SIGNAL
SIGNAL c: std_logic_vector(2*M-2 DOWNTO 0);
BEGIN
gen_ands: FOR k IN 0 TO M-1 GENERATE
l1: FOR i IN 0 TO k GENERATE
a_by_b(k)(i) <= a_i(i) and b_i(k-i);
END GENERATE;
END GENERATE;
gen_ands2: FOR k IN M TO 2*M-2 GENERATE
l2: FOR i IN k TO 2*M-2 GENERATE
a_by_b(k)(i) <= a_i(k-i+(M-1)) and b_i(i-(M-1));
END GENERATE;
END GENERATE;
d_o(0) <= a_by_b(0)(0);
gen_xors: FOR k IN 1 TO 2*M-2 GENERATE
l3: PROCESS(a_by_b(k),c(k))
VARIABLE aux: std_logic;
BEGIN
IF (k < M) THEN
aux := a_by_b(k)(0);
FOR i IN 1 TO k LOOP
aux := a_by_b(k)(i) xor aux;
END LOOP;
ELSE
aux := a_by_b(k)(k);
FOR i IN k+1 TO 2*M-2 LOOP
aux := a_by_b(k)(i) xor aux;
END LOOP;
END IF;
d_o(k) <= aux;
END PROCESS;
END GENERATE;
END rtl;
------------------------------------------------------------
-- GF(2^M) polynomial reduction
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_reducer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
-- Input SIGNAL
d_i: IN std_logic_vector(2*M-2 DOWNTO 0);
-- Output SIGNAL
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_reducer;
ARCHITECTURE rtl OF e_gf2m_reducer IS
-- Initial reduction matrix from polynomial F
CONSTANT R: matrix_reduction_return := reduction_matrix(MODULO);
BEGIN
-- GENERATE M-1 XORs FOR each redcutions matrix row
gen_xors: FOR j IN 0 TO M-1 GENERATE
l1: PROCESS(d_i)
VARIABLE aux: std_logic;
BEGIN
-- Store j-bit from input
aux := d_i(j);
-- Compute target bit FOR each reduction matrix column
FOR i IN 0 TO M-2 LOOP
aux := aux xor (d_i(M+i) and R(j)(i));
END LOOP;
c_o(j) <= aux;
END PROCESS;
END GENERATE;
END rtl;
------------------------------------------------------------
-- GF(2^M) classic multiplication tld
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_classic_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_classic_multiplier;
ARCHITECTURE rtl OF e_gf2m_classic_multiplier IS
-- Instantiate polynomial multiplier
COMPONENT e_gf2m_multiplier PORT (
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
d_o: OUT std_logic_vector(2*M-2 DOWNTO 0) );
END COMPONENT;
-- Import entity e_gf2m_reducer
COMPONENT e_gf2m_reducer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
d_i: IN std_logic_vector(2*M-2 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
SIGNAL d: std_logic_vector(2*M-2 DOWNTO 0);
BEGIN
-- Combine polynomial multiplier and reducer
instance_multiplier: e_gf2m_multiplier PORT MAP(
a_i => a_i,
b_i => b_i,
d_o => d
);
-- Instantiate polynomial reducer
reducer: e_gf2m_reducer GENERIC MAP (
MODULO => MODULO
) PORT MAP(
d_i => d,
c_o => c_o
);
END rtl; | gpl-3.0 | c47521894678a4cf58403dfd4508b3ab | 0.495107 | 3.552147 | false | false | false | false |
Naegolus/qam | src/qam_mapper.vhd | 1 | 3,244 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
entity qam_mapper is
generic
(
n : natural := 1
);
port
(
data : in std_ulogic_vector(4**n - 1 downto 0);
in_phase : out sfixed(1 downto -(4**(n - 1) - 2));
quadrature : out sfixed(1 downto -(4**(n - 1) - 2))
);
begin
assert n >= 1
report "QAM-Mapper: n must be at least 1"
severity error;
end entity qam_mapper;
architecture rtl of qam_mapper is
constant DATA_LEN : natural := 4**n;
constant OUT_LEN : natural := 4**(n - 1);
signal sig_in_phase : sfixed(1 downto -(OUT_LEN - 2));
signal sig_quadrature : sfixed(1 downto -(OUT_LEN - 2));
begin
sig_in_phase (1) <= data(DATA_LEN - 1);
sig_quadrature(1) <= data(DATA_LEN - 2);
comb: for i in 1 to OUT_LEN - 2 generate
sig_in_phase (1 - i) <= sig_in_phase (2 - i) xor data(DATA_LEN - 1 - 2*i);
sig_quadrature(1 - i) <= sig_quadrature(2 - i) xor data(DATA_LEN - 2 - 2*i);
end generate;
in_phase <= sig_in_phase;
quadrature <= sig_quadrature;
end architecture rtl;
| gpl-3.0 | 8e1c5c56e902d764439fa86406bea49a | 0.393033 | 4.634286 | false | false | false | false |
rkujawa/cr2amiga | sseg.vhd | 1 | 1,347 | -- Module implementing access to 7-segment 4-digit display present on
-- CoolRunner II started board by Digilent.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sseg is
Port (clock : in STD_LOGIC;
segA : in STD_LOGIC_VECTOR (7 downto 0);
segB : in STD_LOGIC_VECTOR (7 downto 0);
segC : in STD_LOGIC_VECTOR (7 downto 0);
segD : in STD_LOGIC_VECTOR (7 downto 0);
segout :out STD_LOGIC_VECTOR (7 downto 0);
segan : out STD_LOGIC_VECTOR (3 downto 0));
end sseg;
architecture Behavioral of sseg is
signal cycle_reg : STD_LOGIC_VECTOR (3 downto 0) := "1110";
begin
-- process (A1, B1, C1, D1)
-- begin
-- if (BTN0='1') then
-- A1 <= "10001000";
-- B1 <= "11111001";
-- C1 <= "11001000";
-- D1 <= "10001000";
-- else
-- A1 <= "10000110";
-- B1 <= "11000001";
-- C1 <= "11000000";
-- D1 <= "11000111";
-- end if;
-- end process;
cycle : process (clock, cycle_reg)
begin
if (rising_edge(clock)) then
cycle_reg <= cycle_reg(0) & cycle_reg(3 downto 1);
end if;
end process;
segan <= cycle_reg;
process (cycle_reg, segA, segB, segC, segD)
begin
case cycle_reg is
when "0111" => segout <= segA;
when "1011" => segout <= segB;
when "1101" => segout <= segC;
when "1110" => segout <= segD;
when others => segout <= "11111111";
end case;
end process;
end Behavioral;
| mit | 420aec3eecaa647df016fb9e7c9db84b | 0.613957 | 2.667327 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_funcsim.vhdl | 1 | 27,647 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:50:48 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_funcsim.vhdl
-- Design : blk_mem_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0blk_mem_gen_prim_wrapper_init is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end blk_mem_gen_0blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of blk_mem_gen_0blk_mem_gen_prim_wrapper_init is
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"4000DADADADADA122000DADADADADA111000DADADADADA104000DADADADADA0E",
INIT_04 => X"1000DADADADADA184000DADADADADA162000DADADADADA151000DADADADADA14",
INIT_05 => X"2000DADADADADA1D1000DADADADADA1C4000DADADADADA1A2000DADADADADA19",
INIT_06 => X"4000DADADADADA222000DADADADADA211000DADADADADA204000DADADADADA1E",
INIT_07 => X"1000DADADADADA284000DADADADADA262000DADADADADA251000DADADADADA24",
INIT_08 => X"2000DADADADADA2D1000DADADADADA2C4000DADADADADA2A2000DADADADADA29",
INIT_09 => X"4000DADADADADA322000DADADADADA311000DADADADADA304000DADADADADA2E",
INIT_0A => X"1000DADADADADA384000DADADADADA362000DADADADADA351000DADADADADA34",
INIT_0B => X"2000DADADADADA3D1000DADADADADA3C4000DADADADADA3A2000DADADADADA39",
INIT_0C => X"4000DADADADADA422000DADADADADA411000DADADADADA404000DADADADADA3E",
INIT_0D => X"1000DADADADADA484000DADADADADA462000DADADADADA451000DADADADADA44",
INIT_0E => X"2000DADADADADA4D1000DADADADADA4C4000DADADADADA4A2000DADADADADA49",
INIT_0F => X"4000DADADADADA522000DADADADADA511000DADADADADA504000DADADADADA4E",
INIT_10 => X"1000DADADADADA584000DADADADADA562000DADADADADA551000DADADADADA54",
INIT_11 => X"2000DADADADADA5D1000DADADADADA5C4000DADADADADA5A2000DADADADADA59",
INIT_12 => X"4000DADADADADA622000DADADADADA611000DADADADADA604000DADADADADA5E",
INIT_13 => X"1000DADADADADA684000DADADADADA662000DADADADADA651000DADADADADA64",
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INIT_19 => X"1000DADADADADA884000DADADADADA862000DADADADADA851000DADADADADA84",
INIT_1A => X"2000DADADADADA8D1000DADADADADA8C4000DADADADADA8A2000DADADADADA89",
INIT_1B => X"4000DADADADADA922000DADADADADA911000DADADADADA904000DADADADADA8E",
INIT_1C => X"1000DADADADADA984000DADADADADA962000DADADADADA951000DADADADADA94",
INIT_1D => X"2000DADADADADA9D1000DADADADADA9C4000DADADADADA9A2000DADADADADA99",
INIT_1E => X"4000DADADADADAA22000DADADADADAA11000DADADADADAA04000DADADADADA9E",
INIT_1F => X"1000DADADADADAA84000DADADADADAA62000DADADADADAA51000DADADADADAA4",
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INIT_23 => X"2000DADADADADABD1000DADADADADABC4000DADADADADABA2000DADADADADAB9",
INIT_24 => X"4000DADADADADAC22000DADADADADAC11000DADADADADAC04000DADADADADABE",
INIT_25 => X"1000DADADADADAC84000DADADADADAC62000DADADADADAC51000DADADADADAC4",
INIT_26 => X"2000DADADADADACD1000DADADADADACC4000DADADADADACA2000DADADADADAC9",
INIT_27 => X"4000DADADADADAD22000DADADADADAD11000DADADADADAD04000DADADADADACE",
INIT_28 => X"1000DADADADADAD84000DADADADADAD62000DADADADADAD51000DADADADADAD4",
INIT_29 => X"2000DADADADADADD1000DADADADADADC4000DADADADADADA2000DADADADADAD9",
INIT_2A => X"4000DADADADADAE22000DADADADADAE11000DADADADADAE04000DADADADADADE",
INIT_2B => X"1000DADADADADAE84000DADADADADAE62000DADADADADAE51000DADADADADAE4",
INIT_2C => X"2000DADADADADAED1000DADADADADAEC4000DADADADADAEA2000DADADADADAE9",
INIT_2D => X"4000DADADADADAF22000DADADADADAF11000DADADADADAF04000DADADADADAEE",
INIT_2E => X"1000DADADADADAF84000DADADADADAF62000DADADADADAF51000DADADADADAF4",
INIT_2F => X"2000DADADADADAFD1000DADADADADAFC4000DADADADADAFA2000DADADADADAF9",
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INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => addrb(8 downto 0),
ADDRARDADDR(5) => '1',
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => addra(8 downto 0),
ADDRBWRADDR(5) => '1',
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clkb,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => dina(31 downto 0),
DIBDI(31 downto 0) => dina(63 downto 32),
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => doutb(31 downto 0),
DOBDO(31 downto 0) => doutb(63 downto 32),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(3) => \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(2) => \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(1) => \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => enb,
ENBWREN => wea(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '1',
WEBWE(6) => '1',
WEBWE(5) => '1',
WEBWE(4) => '1',
WEBWE(3) => '1',
WEBWE(2) => '1',
WEBWE(1) => '1',
WEBWE(0) => '1'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_0blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_0blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.blk_mem_gen_0blk_mem_gen_prim_wrapper_init
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_0blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_0blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_0blk_mem_gen_prim_width
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_0blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_0blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_0blk_mem_gen_generic_cstr
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_0blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_0blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_0blk_mem_gen_top
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0blk_mem_gen_v8_2__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \blk_mem_gen_0blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_0blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.blk_mem_gen_0blk_mem_gen_v8_2_synth
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_0 : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=512,C_READ_DEPTH_A=512,C_ADDRA_WIDTH=9,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=512,C_READ_DEPTH_B=512,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.966099 mW}";
end blk_mem_gen_0;
architecture STRUCTURE of blk_mem_gen_0 is
begin
U0: entity work.\blk_mem_gen_0blk_mem_gen_v8_2__parameterized0\
port map (
addra(8 downto 0) => addra(8 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(63 downto 0) => dina(63 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
| mit | 0e76014efd4e824887cb8f6457b0aec8 | 0.720259 | 3.855927 | false | false | false | false |
titto-thomas/Pipeline_RISC | mux2to1bit.vhdl | 1 | 564 | --IITB RISC processor---
--Mux Module(2to1)---
-- author: Anakha
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1bit is
port (
input0 : in std_logic;
input1 : in std_logic;
output : out std_logic;
sel : in std_logic);
end mux2to1bit;
architecture behave of mux2to1bit is
begin -- mux2to1
process(input0,input1,sel)
variable sel_var: std_logic;
begin
sel_var:= sel;
case sel_var is
when '0' =>
output <= input0;
when '1' =>
output <= input1;
when others =>
output <= 'Z';
end case;
end process;
end behave;
| gpl-2.0 | 96bbad56c6bc829c00dca8c1a710d5e7 | 0.643617 | 2.672986 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_arbitration.vhd | 2 | 14,424 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_scheduling - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- The arbitration module decides which fifo to read from depending on the priority
-- access to the ports in the output_ports signal is requested
-- upon acknowledgement data are read from the memory and the corresponding singals (valid, last) are set
-- for multicast messages the ports_reg indicating the remaining output ports is updated
-- the overflow signal resets the state machine to idle state exept it is in send_frame state
--
-- more detailed information can found in file switch_port_rxpath_input_queue_arbitration.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity input_queue_arbitration is
Generic(
FABRIC_DATA_WIDTH : integer;
IQ_FIFO_DATA_WIDTH : integer;
NR_PORTS : integer;
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
NR_IQ_FIFOS : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface memory
iqarb_in_mem_enable : out std_logic;
iqarb_in_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqarb_in_mem_data : in std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
-- input interface fifo
iqarb_in_fifo_enable : out std_logic;
iqarb_in_fifo_prio : out std_logic;
iqarb_in_fifo_data : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
iqarb_in_fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
iqarb_in_fifo_overflow : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
-- output interface arbitration
iqarb_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iqarb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqarb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqarb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iqarb_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iqarb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iqarb_out_last : out std_logic;
iqarb_out_valid : out std_logic
);
end input_queue_arbitration;
architecture rtl of input_queue_arbitration is
type state is (
IDLE,
WAIT_GNT,
SEND_FRAME,
PORT_UPDATE
);
-- state signals
signal cur_state : state;
signal nxt_state : state;
signal empty_const : std_logic_vector(NR_IQ_FIFOS-1 downto 0) := (others => '1');
signal higher_prio : std_logic;
-- state machine signals
signal read_fifo_sig : std_logic;
signal req_fabric_sig : std_logic;
signal update_mem_cnt_sig : std_logic;
signal read_mem_sig : std_logic;
signal output_valid_sig : std_logic;
signal last_word_sig : std_logic;
signal update_ports_sig : std_logic;
signal update_fifo_sig : std_logic;
-- process registers
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal mem_ptr_reg : std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
signal length_reg : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal ports_reg : std_logic_vector(NR_PORTS-1 downto 0);
signal pending_low_prio_ports : std_logic_vector(NR_PORTS-1 downto 0);
signal fifo_reg : std_logic_vector(0 downto 0);
signal mem_cnt_reg : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
-- attribute mark_debug : string;
-- attribute mark_debug of cur_state : signal is "true";
-- attribute mark_debug of mem_ptr_reg : signal is "true";
-- attribute mark_debug of length_reg : signal is "true";
-- attribute mark_debug of ports_reg : signal is "true";
-- attribute mark_debug of mem_cnt_reg : signal is "true";
-- attribute mark_debug of read_fifo_sig : signal is "true";
-- attribute mark_debug of req_fabric_sig : signal is "true";
-- attribute mark_debug of output_valid_sig : signal is "true";
-- attribute mark_debug of last_word_sig : signal is "true";
-- attribute mark_debug of update_ports_sig : signal is "true";
-- attribute mark_debug of update_fifo_sig : signal is "true";
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, pending_low_prio_ports, iqarb_in_fifo_empty, ports_reg, iqarb_out_ports_gnt, mem_cnt_reg, length_reg, higher_prio, empty_const)
begin
-- default signal assignments
nxt_state <= IDLE;
read_fifo_sig <= '0';
req_fabric_sig <= '0';
update_mem_cnt_sig <= '0';
read_mem_sig <= '0';
output_valid_sig <= '0';
last_word_sig <= '0';
update_ports_sig <= '0';
update_fifo_sig <= '0';
case cur_state is
when IDLE => -- waiting for a header to appear in fifo and store data to internal registers
if iqarb_in_fifo_empty /= empty_const or pending_low_prio_ports /= 0 then
nxt_state <= WAIT_GNT;
read_fifo_sig <= '1'; -- read_fifo_p
end if;
when WAIT_GNT => -- request to send a frame and wait for grant
if ports_reg = 0 then
nxt_state <= IDLE;
elsif higher_prio = '1' then
nxt_state <= WAIT_GNT;
read_fifo_sig <= '1'; -- read_fifo_p
elsif (iqarb_out_ports_gnt and ports_reg) /= 0 then
nxt_state <= SEND_FRAME;
update_mem_cnt_sig <= '1'; -- mem_cnt_p
read_mem_sig <= '1'; -- mem_enable
else
nxt_state <= WAIT_GNT;
req_fabric_sig <= '1'; -- request_fabric_access_p
end if;
when SEND_FRAME => -- read the frame data from frame queue memory and forward to switch fabric
if mem_cnt_reg >= length_reg then
nxt_state <= PORT_UPDATE;
output_valid_sig <= '1'; -- output_valid
last_word_sig <= '1'; -- output_last
update_ports_sig <= '1'; -- read_fifo_p
elsif mem_cnt_reg < length_reg then
nxt_state <= SEND_FRAME;
update_mem_cnt_sig <= '1'; -- mem_cnt_p
read_mem_sig <= '1'; -- mem_enable
output_valid_sig <= '1'; -- output_valid
end if;
when PORT_UPDATE => -- update the remaining output ports for the current frame
if ports_reg = 0 then
nxt_state <= IDLE;
update_fifo_sig <= '1'; -- fifo_enable
else
nxt_state <= WAIT_GNT;
end if;
end case;
end process output_logic_p;
-- determine the fifo the be read from and store its contents to internal registers
read_fifo_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
mem_ptr_reg <= (others => '0');
length_reg <= (others => '0');
ports_reg <= (others => '0');
fifo_reg <= (others => '0');
pending_low_prio_ports <= (others => '0');
else
prio_reg <= prio_reg;
timestamp_reg <= timestamp_reg;
mem_ptr_reg <= mem_ptr_reg;
length_reg <= length_reg;
ports_reg <= ports_reg;
fifo_reg <= fifo_reg;
pending_low_prio_ports <= pending_low_prio_ports;
if iqarb_in_fifo_overflow(to_integer(unsigned(fifo_reg))) = '1' then
ports_reg <= (others => '0');
if fifo_reg = "0" then
pending_low_prio_ports <= (others => '0');
end if;
elsif update_ports_sig = '1' then
ports_reg <= ports_reg and (not iqarb_out_ports_gnt);
if NR_IQ_FIFOS = 2 and fifo_reg = "0" then -- a low priority multicast frame might be suppressed by a high priority message before transmitting to all output ports
pending_low_prio_ports <= ports_reg and (not iqarb_out_ports_gnt); -- store in this register and continue transmission later
end if;
elsif read_fifo_sig = '1' then
if NR_IQ_FIFOS = 2 and iqarb_in_fifo_empty(NR_IQ_FIFOS-1) = '0' then -- high priority fifo
prio_reg <= iqarb_in_fifo_data(IQ_FIFO_DATA_WIDTH+IQ_FIFO_PRIO_START+VLAN_PRIO_WIDTH-1 downto IQ_FIFO_DATA_WIDTH+IQ_FIFO_PRIO_START);
timestamp_reg <= iqarb_in_fifo_data(IQ_FIFO_DATA_WIDTH+IQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1 downto IQ_FIFO_DATA_WIDTH+IQ_FIFO_TIMESTAMP_START);
mem_ptr_reg <= iqarb_in_fifo_data(IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH_A-1 downto IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START);
length_reg <= iqarb_in_fifo_data(IQ_FIFO_DATA_WIDTH+IQ_FIFO_FRAME_LEN_START+FRAME_LENGTH_WIDTH-1 downto IQ_FIFO_DATA_WIDTH+IQ_FIFO_FRAME_LEN_START);
ports_reg <= iqarb_in_fifo_data(IQ_FIFO_DATA_WIDTH+IQ_FIFO_PORTS_START+NR_PORTS-1 downto IQ_FIFO_DATA_WIDTH+IQ_FIFO_PORTS_START);
fifo_reg <= "1";
else -- low priority fifo
prio_reg <= iqarb_in_fifo_data(IQ_FIFO_PRIO_START+VLAN_PRIO_WIDTH-1 downto IQ_FIFO_PRIO_START);
timestamp_reg <= iqarb_in_fifo_data(IQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1 downto IQ_FIFO_TIMESTAMP_START);
mem_ptr_reg <= iqarb_in_fifo_data(IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH_A-1 downto IQ_FIFO_MEM_PTR_START);
length_reg <= iqarb_in_fifo_data(IQ_FIFO_FRAME_LEN_START+FRAME_LENGTH_WIDTH-1 downto IQ_FIFO_FRAME_LEN_START);
if pending_low_prio_ports /= 0 then
ports_reg <= pending_low_prio_ports;
else
ports_reg <= iqarb_in_fifo_data(IQ_FIFO_PORTS_START+NR_PORTS-1 downto IQ_FIFO_PORTS_START);
end if;
fifo_reg <= "0";
end if;
end if;
end if;
end if;
end process;
-- set the switch fabric signals needed for output arbitration
request_fabric_access_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
iqarb_out_ports_req <= (others => '0');
iqarb_out_prio <= (others => '0');
iqarb_out_timestamp <= (others => '0');
iqarb_out_length <= (others => '0');
else
iqarb_out_ports_req <= (others => '0');
iqarb_out_prio <= prio_reg;
iqarb_out_timestamp <= timestamp_reg;
iqarb_out_length <= length_reg;
if req_fabric_sig = '1' then
iqarb_out_ports_req <= ports_reg;
end if;
end if;
end if;
end process;
-- count bytes read out of memory
mem_cnt_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mem_cnt_reg <= (others => '0');
else
mem_cnt_reg <= (others => '0');
if update_mem_cnt_sig = '1' then
mem_cnt_reg <= mem_cnt_reg + IQ_MEM_DATA_WIDTH_RATIO;
end if;
end if;
end if;
end process;
-- check if an a higher priority frame is available on a fifo different than the selected one
higher_prio_p : process(fifo_reg, iqarb_in_fifo_empty)
begin
higher_prio <= '0';
if NR_IQ_FIFOS = 2 and fifo_reg = "0" and iqarb_in_fifo_empty(NR_IQ_FIFOS-1) = '0' then
higher_prio <= '1';
end if;
end process;
-- singals to input queue memory
iqarb_in_mem_enable <= read_mem_sig;
iqarb_in_mem_addr <= mem_ptr_reg(IQ_MEM_ADDR_WIDTH_A-1 downto IQ_MEM_ADDR_WIDTH_A-IQ_MEM_ADDR_WIDTH_B)
+ mem_cnt_reg(FRAME_LENGTH_WIDTH-1 downto IQ_MEM_ADDR_WIDTH_A-IQ_MEM_ADDR_WIDTH_B);
-- output sigals to fabric
iqarb_out_data <= iqarb_in_mem_data;
iqarb_out_valid <= output_valid_sig;
iqarb_out_last <= last_word_sig;
-- signals to fifo
iqarb_in_fifo_enable <= update_fifo_sig;
iqarb_in_fifo_prio <= fifo_reg(0);
end rtl;
| mit | f1c1fc21c5768eb6a9321865964e9501 | 0.53508 | 3.834131 | false | false | false | false |
titto-thomas/Pipeline_RISC | FlagBlock.vhdl | 1 | 1,455 | ----------------------------------------
-- Flag Block Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FlagBlock is
port (
clock : in std_logic; -- clock signal
reset : in std_logic; -- reset signal
ALUc : in std_logic; -- conditional carry flag change
ALUz : in std_logic; -- conditional zero flag change
Cen : in std_logic; -- enable carry flag change
Zen : in std_logic; -- enable zero flag change
ALUop : in std_logic; -- unconditional ALU operation
ALUcout : in std_logic; -- the carry out from ALU
ALUzout : in std_logic; -- the zero out from ALU
ALUvalid : out std_logic; -- whether the ALU output is valid or not
FR : out std_logic_vector(1 downto 0) -- Flag register
);
end FlagBlock;
architecture behave of FlagBlock is
signal carry, zero : std_logic;
begin -- behave
ALUvalid <= ((carry and ALUc) or (zero and ALUz) or (ALUop));
FR(0) <= carry;
FR(1) <= zero;
process(clock,reset)
begin
if(rising_edge(clock)) then
if (reset = '1') then
carry <= '0'; -- reset the register
zero <= '0';
else
if (Cen = '1') then
carry <= ALUcout; -- Update the carry register
end if;
if (Zen = '1') then
zero <= ALUzout; -- Update the zero register
end if;
end if;
end if;
end process;
end behave;
| gpl-2.0 | 166ff38dc313c8f3918f832448dd6243 | 0.593814 | 3.306818 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/sync_blocks/aeg_design_sync_block.vhd | 2 | 5,632 | --------------------------------------------------------------------------------
-- Title : CDC Sync Block
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to another, this
-- is a multiple flip-flop pipeline, with all flops placed together
-- into the same slice. Thus the routing delay between the two is
-- minimum to safe-guard against metastability issues.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity aeg_design_0_sync_block is
generic (
INITIALISE : bit := '0';
DEPTH : integer := 5
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
attribute dont_touch : string;
attribute dont_touch of aeg_design_0_sync_block : entity is "yes";
end aeg_design_0_sync_block;
architecture structural of aeg_design_0_sync_block is
-- Internal Signals
signal data_sync0 : std_logic;
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
signal data_sync3 : std_logic;
signal data_sync4 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute async_reg : string;
attribute async_reg of data_sync_reg0 : label is "true";
attribute async_reg of data_sync_reg1 : label is "true";
attribute async_reg of data_sync_reg2 : label is "true";
attribute async_reg of data_sync_reg3 : label is "true";
attribute async_reg of data_sync_reg4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of data_sync_reg0 : label is "no";
attribute shreg_extract of data_sync_reg1 : label is "no";
attribute shreg_extract of data_sync_reg2 : label is "no";
attribute shreg_extract of data_sync_reg3 : label is "no";
attribute shreg_extract of data_sync_reg4 : label is "no";
begin
data_sync_reg0 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_in,
Q => data_sync0,
CE => '1',
R => '0'
);
data_sync_reg1 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync0,
Q => data_sync1,
CE => '1',
R => '0'
);
data_sync_reg2 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2,
CE => '1',
R => '0'
);
data_sync_reg3 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync2,
Q => data_sync3,
CE => '1',
R => '0'
);
data_sync_reg4 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync3,
Q => data_sync4,
CE => '1',
R => '0'
);
data_out <= data_sync4;
end structural;
| mit | 7787a5a2c812af4fd5c7575775c897c1 | 0.613281 | 4.054716 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_fabric/switch_fabric_arbitration.vhd | 2 | 11,469 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 20.12.2013 15:04:30
-- Design Name:
-- Module Name: output_port_arbitration - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: the switch fabric arbitration acts as a multiplexer between the input and output ports.
-- Each switch_fabric arbitration module is connected to one output port.
-- If one or multiple input ports are ready to send data to the output port connected to the
-- fabric_arbitration module, they request access at the arbitration module.
-- The arbitration module then decides in a round robin manner which of the input ports is allowed to
-- send its frame to the output port.
-- As soon as the output port is ready to store the frame, the arbitration module connects the input
-- data signals to the output data signals.
--
-- further information can be found in file switch_fabric_arbitration.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity switch_fabric_arbitration is
generic (
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port (
clk : in std_logic;
reset : in std_logic;
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- data from the RX data path
farb_in_data : in std_logic_vector(NR_PORTS*FABRIC_DATA_WIDTH-1 downto 0);
farb_in_valid : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_last : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_ports_req : in std_logic_vector(NR_PORTS-1 downto 0);
farb_in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
farb_in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
farb_in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
farb_in_ports_gnt : out std_logic_vector(NR_PORTS-1 downto 0);
-- data TO the TX data path
farb_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
farb_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
farb_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
farb_out_valid : out std_logic;
farb_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
farb_out_req : out std_logic;
farb_out_accept_frame : in std_logic
);
end switch_fabric_arbitration;
architecture rtl of switch_fabric_arbitration is
constant LD_NR_PORTS : integer := 2;
component arbitration_algorithm is
generic(
NR_PORTS : integer;
LD_NR_PORTS : integer;
ARBITRATION : integer;
FRAME_LENGTH_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
port(
clk : in std_logic;
reset : in std_logic;
in_start_arb : in std_logic;
in_req_ports : in std_logic_vector(NR_PORTS-1 downto 0);
in_prio : in std_logic_vector(NR_PORTS*VLAN_PRIO_WIDTH-1 downto 0);
in_timestamp : in std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
in_length : in std_logic_vector(NR_PORTS*FRAME_LENGTH_WIDTH-1 downto 0);
out_arb_finished : out std_logic;
out_winner_port : out std_logic_vector(LD_NR_PORTS-1 downto 0)
);
end component;
-- state machine
type state is (
IDLE,
ARBITRATE,
REQ_OUTPUT,
CONNECT,
WAIT1,
WAIT2,
WAIT3
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal start_arbitration_sig : std_logic;
signal winner_port_sig : std_logic_vector(LD_NR_PORTS-1 downto 0);
signal read_reg_sig : std_logic;
signal connect_sig : std_logic;
signal arbitration_finished_sig : std_logic;
-- process registers
signal gnt_port_id_reg : std_logic_vector(LD_NR_PORTS-1 downto 0);
signal length_reg : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal req_reg : std_logic_vector(NR_PORTS-1 downto 0);
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, farb_in_ports_req, req_reg, arbitration_finished_sig, farb_out_accept_frame, gnt_port_id_reg, farb_in_last)
begin
-- default signal assignments
nxt_state <= IDLE;
start_arbitration_sig <= '0';
read_reg_sig <= '0';
connect_sig <= '0';
-- default output values
farb_out_req <= '0';
farb_in_ports_gnt <= (others => '0');
case cur_state is
when IDLE => -- waiting for a input port to request access
if farb_in_ports_req /= 0 then
nxt_state <= ARBITRATE;
start_arbitration_sig <= '1'; -- arbitration_alg_p
end if;
when ARBITRATE => -- determine the winner input port
if arbitration_finished_sig = '1' then
nxt_state <= REQ_OUTPUT;
read_reg_sig <= '1'; -- read_reg_p
else
nxt_state <= ARBITRATE;
end if;
when REQ_OUTPUT => -- check if the output port is ready to accept the frame
if farb_out_accept_frame = '1' and farb_in_ports_req(to_integer(unsigned(gnt_port_id_reg))) = '1' then
nxt_state <= CONNECT;
farb_in_ports_gnt(to_integer(unsigned(gnt_port_id_reg))) <= '1';
--elsif
-- req_reg /= farb_in_ports_req then -- restart new port requesting --> would affect round robin
-- nxt_state <= IDLE;
elsif farb_in_ports_req(to_integer(unsigned(gnt_port_id_reg))) = '1' then
nxt_state <= REQ_OUTPUT;
farb_out_req <= '1';
end if;
when CONNECT => -- send the frame from the input port to the output port
connect_sig <= '1'; -- connect_p
if farb_in_last(to_integer(unsigned(gnt_port_id_reg))) = '1' then
nxt_state <= WAIT1;
farb_in_ports_gnt(to_integer(unsigned(gnt_port_id_reg))) <= '1';
else
nxt_state <= CONNECT;
farb_in_ports_gnt(to_integer(unsigned(gnt_port_id_reg))) <= '1';
end if;
when WAIT1 => -- wait three cycles for giving the current granted port time to join the next arbitration round
nxt_state <= WAIT2;
when WAIT2 =>
nxt_state <= WAIT3;
when WAIT3 =>
nxt_state <= IDLE;
end case;
end process;
-- buffer the arbitration winner input port id
round_robin_p : process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
gnt_port_id_reg <= (others => '0');
else
gnt_port_id_reg <= gnt_port_id_reg;
if arbitration_finished_sig = '1' then
gnt_port_id_reg <= winner_port_sig;
end if;
end if;
end if;
end process;
-- buffer requests
request_p : process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
req_reg <= (others => '0');
else
req_reg <= farb_in_ports_req;
end if;
end if;
end process;
-- buffer the frame length of the winner input port
read_reg_p : process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
length_reg <= (others => '0');
prio_reg <= (others => '0');
timestamp_reg <= (others => '0');
else
length_reg <= length_reg;
prio_reg <= prio_reg;
timestamp_reg <= timestamp_reg;
if read_reg_sig = '1' then
length_reg <= farb_in_length(((to_integer(unsigned(winner_port_sig)))+1)*FRAME_LENGTH_WIDTH-1 downto
(to_integer(unsigned(winner_port_sig)))*FRAME_LENGTH_WIDTH);
prio_reg <= farb_in_prio(((to_integer(unsigned(winner_port_sig)))+1)*VLAN_PRIO_WIDTH-1 downto
(to_integer(unsigned(winner_port_sig)))*VLAN_PRIO_WIDTH);
timestamp_reg <= farb_in_timestamp(((to_integer(unsigned(winner_port_sig)))+1)*TIMESTAMP_WIDTH-1 downto
(to_integer(unsigned(winner_port_sig)))*TIMESTAMP_WIDTH);
end if;
end if;
end if;
end process;
-- connect the arbitration winner input port to the output port
connect_p : process(farb_in_data, farb_in_valid, connect_sig, gnt_port_id_reg)
begin
farb_out_valid <= '0';
farb_out_data <= (others => '0');
if connect_sig = '1' then
farb_out_valid <= farb_in_valid(to_integer(unsigned(gnt_port_id_reg)));
farb_out_data <= farb_in_data(((to_integer(unsigned(gnt_port_id_reg)))+1)*FABRIC_DATA_WIDTH-1 downto
(to_integer(unsigned(gnt_port_id_reg)))*FABRIC_DATA_WIDTH);
end if;
end process;
arbitration_alg_p : arbitration_algorithm
generic map(
NR_PORTS => NR_PORTS,
LD_NR_PORTS => LD_NR_PORTS,
ARBITRATION => ARBITRATION,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map(
clk => clk,
reset => reset,
in_start_arb => start_arbitration_sig,
in_req_ports => farb_in_ports_req,
in_prio => farb_in_prio,
in_timestamp => farb_in_timestamp,
timestamp_cnt => timestamp_cnt,
in_length => farb_in_length,
out_arb_finished => arbitration_finished_sig,
out_winner_port => winner_port_sig
);
farb_out_length <= length_reg;
farb_out_prio <= prio_reg;
farb_out_timestamp <= timestamp_reg;
end rtl;
| mit | 4e96fe1a73990f048195752047f18e3f | 0.540588 | 3.883847 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/support/tri_mode_ethernet_mac_0_support.vhd | 1 | 16,243 | --------------------------------------------------------------------------------
-- Title : VHDL Support Level Module
-- File : tri_mode_ethernet_mac_0_support.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the support level for the Tri-Mode
-- Ethernet MAC IP. It contains potentially shareable FPGA
-- resources such as clocking, reset and IDELAYCTRL logic.
-- This can be used as-is in a single core design, or adapted
-- for use with multi-core implementations.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block support level
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_support is
port(
gtx_clk : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
rx_axis_filter_tuser : out std_logic_vector(4 downto 0);
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end tri_mode_ethernet_mac_0_support;
architecture wrapper of tri_mode_ethernet_mac_0_support is
------------------------------------------------------------------------------
-- Component declaration for the TEMAC core
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
rx_axis_filter_tuser : out std_logic_vector(4 downto 0);
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(12 -1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Shareable logic component declarations
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support_resets
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic );
end component;
-- Internal signals
signal idelayctrl_reset : std_logic;
signal idelayctrl_ready : std_logic;
begin
-----------------------------------------------------------------------------
-- Shareable logic
-----------------------------------------------------------------------------
-- Instantiate the sharable reset logic
tri_mode_ethernet_mac_support_resets_i : tri_mode_ethernet_mac_0_support_resets
port map(
glbl_rstn => glbl_rstn,
refclk => refclk,
idelayctrl_ready => idelayctrl_ready,
idelayctrl_reset_out => idelayctrl_reset );
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
tri_mode_ethernet_mac_idelayctrl_common_i : IDELAYCTRL
port map (
RDY => idelayctrl_ready,
REFCLK => refclk,
RST => idelayctrl_reset
);
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
tri_mode_ethernet_mac_i : tri_mode_ethernet_mac_0
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Receiver Interface
----------------------------
rx_enable => rx_enable,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_axis_filter_tuser => rx_axis_filter_tuser,
-- Transmitter Interface
-------------------------------
tx_enable => tx_enable,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- MAC Control Interface
------------------------
pause_req => pause_req,
pause_val => pause_val,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- GMII Interface
-----------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => mac_irq
);
end wrapper;
| mit | 6d03ef9b8d2c3511ff19ce073493ea1a | 0.464569 | 4.379348 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/DAQ_MEM/simulation/bmg_stim_gen.vhd | 1 | 12,286 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((10 <= 11),WR_RD_DEEP_COUNT,
((7/14)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((11 <= 10),WR_RD_DEEP_COUNT,
((14/7)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(9 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(10 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 2048 ,
RST_INC => 2 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 14,
DOUT_WIDTH => 14 ,
DATA_PART_CNT => 0,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
| gpl-3.0 | ad28bffb1e59a0af3cadfd36caaeb3ac | 0.542813 | 3.546767 | false | false | false | false |
Naegolus/qam | src/tb_qam.vhd | 1 | 3,141 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
entity tb_qam is
end entity tb_qam;
architecture bhv of tb_qam is
constant QAM_1_N : natural := 1;
constant QAM_1_DATA_LEN : natural := 4**QAM_1_N;
constant QAM_1_OUT_LEN : natural := QAM_1_DATA_LEN / 2;
signal qam_1_data : std_ulogic_vector(QAM_1_DATA_LEN - 1 downto 0) := (others => '0');
signal qam_1_in_phase : sfixed(QAM_1_OUT_LEN - 1 downto 0);
signal qam_1_quadrature : sfixed(QAM_1_OUT_LEN - 1 downto 0);
begin
qam_1: entity work.qam_mapper(rtl)
generic map
(
n => QAM_1_N
)
port map
(
data => qam_1_data,
in_phase => qam_1_in_phase,
quadrature => qam_1_quadrature
);
stimu: process
begin
-- TODO: Set input
wait for 2 ns;
-- TODO: Check output
assert false report "Simulation failed" severity error;
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
end architecture bhv;
| gpl-3.0 | 3bf85436a7292e4fe073b369bf5c1518 | 0.402101 | 4.824885 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/dependencies0/simpleSubunit3_arch.vhd | 1 | 1,929 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ARCHITECTURE rtl OF SimpleSubunit3 IS
SIGNAL sig_subunit0_a_data : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
SIGNAL sig_subunit0_a_last : STD_LOGIC;
SIGNAL sig_subunit0_a_ready : STD_LOGIC;
SIGNAL sig_subunit0_a_strb : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
SIGNAL sig_subunit0_a_valid : STD_LOGIC;
SIGNAL sig_subunit0_b_data : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
SIGNAL sig_subunit0_b_last : STD_LOGIC;
SIGNAL sig_subunit0_b_ready : STD_LOGIC;
SIGNAL sig_subunit0_b_strb : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
SIGNAL sig_subunit0_b_valid : STD_LOGIC;
COMPONENT subunit0 IS
GENERIC(
DATA_WIDTH : INTEGER
);
PORT(
a_data : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
a_last : IN STD_LOGIC;
a_ready : OUT STD_LOGIC;
a_strb : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
a_valid : IN STD_LOGIC;
b_data : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
b_last : OUT STD_LOGIC;
b_ready : IN STD_LOGIC;
b_strb : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
b_valid : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
subunit0_140508271342704 : COMPONENT subunit0
GENERIC MAP(
DATA_WIDTH => DATA_WIDTH
)
PORT MAP(
a_data => sig_subunit0_a_data,
a_last => sig_subunit0_a_last,
a_ready => sig_subunit0_a_ready,
a_strb => sig_subunit0_a_strb,
a_valid => sig_subunit0_a_valid,
b_data => sig_subunit0_b_data,
b_last => sig_subunit0_b_last,
b_ready => sig_subunit0_b_ready,
b_strb => sig_subunit0_b_strb,
b_valid => sig_subunit0_b_valid
);
a0_ready <= sig_subunit0_a_ready;
b0_data <= sig_subunit0_b_data;
b0_last <= sig_subunit0_b_last;
b0_strb <= sig_subunit0_b_strb;
b0_valid <= sig_subunit0_b_valid;
sig_subunit0_a_data <= a0_data;
sig_subunit0_a_last <= a0_last;
sig_subunit0_a_strb <= a0_strb;
sig_subunit0_a_valid <= a0_valid;
sig_subunit0_b_ready <= b0_ready;
END ARCHITECTURE rtl; | mit | 3bb6aac9d7e86475891c6611cfd80b73 | 0.660964 | 2.473077 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_2_funcsim.vhdl | 1 | 248,947 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:33:21 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_2_funcsim.vhdl
-- Design : fifo_generator_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2blk_mem_gen_prim_wrapper is
port (
DOUTB : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_2blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_2blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => ADDRA(9 downto 0),
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 4) => O3(9 downto 0),
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 8) => DOUTB(16 downto 9),
DOBDO(7 downto 0) => DOUTB(7 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => DOUTB(17),
DOPBDOP(0) => DOUTB(8),
ENARDEN => E(0),
ENBWREN => ENB,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 35 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => ADDRA(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => O3(9 downto 0),
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => DOUTB(34 downto 27),
DOBDO(23 downto 16) => DOUTB(25 downto 18),
DOBDO(15 downto 8) => DOUTB(16 downto 9),
DOBDO(7 downto 0) => DOUTB(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => DOUTB(35),
DOPBDOP(2) => DOUTB(26),
DOPBDOP(1) => DOUTB(17),
DOPBDOP(0) => DOUTB(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized1\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 34 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 34 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \fifo_generator_2blk_mem_gen_prim_wrapper__parameterized1\ is
signal \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => ADDRA(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => O3(9 downto 0),
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => DOUTB(34 downto 27),
DOBDO(23 downto 16) => DOUTB(25 downto 18),
DOBDO(15 downto 8) => DOUTB(16 downto 9),
DOBDO(7 downto 0) => DOUTB(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
DOPBDOP(2) => DOUTB(26),
DOPBDOP(1) => DOUTB(17),
DOPBDOP(0) => DOUTB(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2compare is
port (
comp0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2compare : entity is "compare";
end fifo_generator_2compare;
architecture STRUCTURE of fifo_generator_2compare is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2compare_0 : entity is "compare";
end fifo_generator_2compare_0;
architecture STRUCTURE of fifo_generator_2compare_0 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2compare_1 : entity is "compare";
end fifo_generator_2compare_1;
architecture STRUCTURE of fifo_generator_2compare_1 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2compare_2 : entity is "compare";
end fifo_generator_2compare_2;
architecture STRUCTURE of fifo_generator_2compare_2 is
signal \n_0_gmux.gm[3].gms.ms\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gmux.gm[3].gms.ms\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gmux.gm[3].gms.ms\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_2rd_bin_cntr;
architecture STRUCTURE of fifo_generator_2rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \n_0_gc0.count[9]_i_2\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair3";
attribute counter : integer;
attribute counter of \gc0.count_reg[0]\ : label is 2;
attribute counter of \gc0.count_reg[1]\ : label is 2;
attribute counter of \gc0.count_reg[2]\ : label is 2;
attribute counter of \gc0.count_reg[3]\ : label is 2;
attribute counter of \gc0.count_reg[4]\ : label is 2;
attribute counter of \gc0.count_reg[5]\ : label is 2;
attribute counter of \gc0.count_reg[6]\ : label is 2;
attribute counter of \gc0.count_reg[7]\ : label is 2;
attribute counter of \gc0.count_reg[8]\ : label is 2;
attribute counter of \gc0.count_reg[9]\ : label is 2;
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(4),
I3 => \^q\(3),
I4 => \^q\(2),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_gc0.count[9]_i_2\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(6),
I1 => \n_0_gc0.count[9]_i_2\,
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \n_0_gc0.count[9]_i_2\,
I1 => \^q\(6),
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \n_0_gc0.count[9]_i_2\,
I1 => \^q\(8),
I2 => \^q\(7),
I3 => \^q\(6),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(4),
I4 => \^q\(3),
I5 => \^q\(2),
O => \n_0_gc0.count[9]_i_2\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(0),
Q => O3(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(1),
Q => O3(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(2),
Q => O3(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(3),
Q => O3(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(4),
Q => O3(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(5),
Q => O3(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(6),
Q => O3(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(7),
Q => O3(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(8),
Q => O3(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => \^q\(9),
Q => O3(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => I1(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => I1(0),
D => plusOp(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ENB : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2rd_fwft : entity is "rd_fwft";
end fifo_generator_2rd_fwft;
architecture STRUCTURE of fifo_generator_2rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair1";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[9]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[88]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF5155"
)
port map (
I0 => I1,
I1 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I2 => rd_en,
I3 => curr_fwft_state(0),
I4 => Q(0),
O => ENB
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88EA"
)
port map (
I0 => empty_fwft_fb,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => I1,
O => O1(0)
);
\goreg_bm.dout_i[88]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => I1,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(1),
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2reset_blk_ramfifo is
port (
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
rst_d2 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_2reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_2reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2wr_bin_cntr is
port (
O1 : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
comp0 : in STD_LOGIC;
O2 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0_3 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
comp1_4 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_2wr_bin_cntr;
architecture STRUCTURE of fifo_generator_2wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \n_0_gcc0.gc0.count[9]_i_2\ : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair6";
attribute counter : integer;
attribute counter of \gcc0.gc0.count_reg[0]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[1]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[2]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[3]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[4]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[5]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[6]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[7]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[8]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[9]\ : label is 3;
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_8_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_8_out(0),
I1 => p_8_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_8_out(0),
I1 => p_8_out(1),
I2 => p_8_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(0),
I3 => p_8_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(2),
I3 => p_8_out(3),
I4 => p_8_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(4),
I3 => p_8_out(3),
I4 => p_8_out(2),
I5 => p_8_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_gcc0.gc0.count[9]_i_2\,
I1 => p_8_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_8_out(6),
I1 => \n_0_gcc0.gc0.count[9]_i_2\,
I2 => p_8_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \n_0_gcc0.gc0.count[9]_i_2\,
I1 => p_8_out(6),
I2 => p_8_out(7),
I3 => p_8_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \n_0_gcc0.gc0.count[9]_i_2\,
I1 => p_8_out(8),
I2 => p_8_out(7),
I3 => p_8_out(6),
I4 => p_8_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_8_out(5),
I1 => p_8_out(1),
I2 => p_8_out(0),
I3 => p_8_out(4),
I4 => p_8_out(3),
I5 => p_8_out(2),
O => \n_0_gcc0.gc0.count[9]_i_2\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(8),
Q => \^q\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(9),
Q => \^q\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_8_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_8_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_8_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_8_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_8_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_8_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => p_8_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => p_8_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => p_8_out(8)
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => p_8_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => O3(0),
I2 => \^q\(1),
I3 => O3(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => O3(0),
I2 => \^q\(1),
I3 => O3(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => I1(0),
I2 => \^q\(1),
I3 => I1(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(0),
I1 => O3(0),
I2 => p_8_out(1),
I3 => O3(1),
O => v1_reg_2(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
I2 => \^q\(3),
I3 => O3(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
I2 => \^q\(3),
I3 => O3(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => I1(2),
I2 => \^q\(3),
I3 => I1(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(2),
I1 => O3(2),
I2 => p_8_out(3),
I3 => O3(3),
O => v1_reg_2(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => O3(4),
I2 => \^q\(5),
I3 => O3(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => O3(4),
I2 => \^q\(5),
I3 => O3(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => I1(4),
I2 => \^q\(5),
I3 => I1(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(4),
I1 => O3(4),
I2 => p_8_out(5),
I3 => O3(5),
O => v1_reg_2(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => O3(6),
I2 => \^q\(7),
I3 => O3(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => O3(6),
I2 => \^q\(7),
I3 => O3(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => I1(6),
I2 => \^q\(7),
I3 => I1(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(6),
I1 => O3(6),
I2 => p_8_out(7),
I3 => O3(7),
O => v1_reg_2(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => O3(8),
I2 => \^q\(9),
I3 => O3(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => O3(8),
I2 => \^q\(9),
I3 => O3(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => I1(8),
I2 => \^q\(9),
I3 => I1(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_8_out(8),
I1 => O3(8),
I2 => p_8_out(9),
I3 => O3(9),
O => v1_reg_2(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFA22FAAAAA22AA"
)
port map (
I0 => p_18_out,
I1 => comp0,
I2 => O2(0),
I3 => wr_en,
I4 => p_1_out,
I5 => comp1,
O => O1
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"131313130F000000"
)
port map (
I0 => comp0_3,
I1 => rst_full_gen_i,
I2 => O2(0),
I3 => comp1_4,
I4 => wr_en,
I5 => p_1_out,
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2blk_mem_gen_prim_width is
port (
DOUTB : out STD_LOGIC_VECTOR ( 17 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 17 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_2blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_2blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_2blk_mem_gen_prim_wrapper
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(17 downto 0) => DOUTB(17 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(17 downto 0) => din(17 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2blk_mem_gen_prim_width__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 35 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_2blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \fifo_generator_2blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_2blk_mem_gen_prim_wrapper__parameterized0\
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(35 downto 0) => DOUTB(35 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(35 downto 0) => din(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2blk_mem_gen_prim_width__parameterized1\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 34 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 34 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_2blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \fifo_generator_2blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_2blk_mem_gen_prim_wrapper__parameterized1\
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(34 downto 0) => DOUTB(34 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(34 downto 0) => din(34 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2rd_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2rd_status_flags_ss : entity is "rd_status_flags_ss";
end fifo_generator_2rd_status_flags_ss;
architecture STRUCTURE of fifo_generator_2rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
c1: entity work.fifo_generator_2compare_1
port map (
comp0 => comp0,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.fifo_generator_2compare_2
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2wr_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2wr_status_flags_ss : entity is "wr_status_flags_ss";
end fifo_generator_2wr_status_flags_ss;
architecture STRUCTURE of fifo_generator_2wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
c0: entity work.fifo_generator_2compare
port map (
comp0 => comp0,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.fifo_generator_2compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2blk_mem_gen_generic_cstr is
port (
DOUTB : out STD_LOGIC_VECTOR ( 88 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 88 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_2blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_2blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_2blk_mem_gen_prim_width
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(17 downto 0) => DOUTB(17 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(17 downto 0) => din(17 downto 0)
);
\ramloop[1].ram.r\: entity work.\fifo_generator_2blk_mem_gen_prim_width__parameterized0\
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(35 downto 0) => DOUTB(53 downto 18),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(35 downto 0) => din(53 downto 18)
);
\ramloop[2].ram.r\: entity work.\fifo_generator_2blk_mem_gen_prim_width__parameterized1\
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(34 downto 0) => DOUTB(88 downto 54),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(34 downto 0) => din(88 downto 54)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2rd_logic is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
empty : out STD_LOGIC;
O1 : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ENB : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2rd_logic : entity is "rd_logic";
end fifo_generator_2rd_logic;
architecture STRUCTURE of fifo_generator_2rd_logic is
signal \^o2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_18_out\ : STD_LOGIC;
begin
O2(0) <= \^o2\(0);
p_18_out <= \^p_18_out\;
\gr1.rfwft\: entity work.fifo_generator_2rd_fwft
port map (
E(0) => E(0),
ENB => ENB,
I1 => \^p_18_out\,
O1(0) => \^o2\(0),
Q(1 downto 0) => Q(1 downto 0),
clk => clk,
empty => empty,
rd_en => rd_en
);
\grss.rsts\: entity work.fifo_generator_2rd_status_flags_ss
port map (
I1 => I1,
Q(0) => Q(1),
clk => clk,
comp0 => comp0,
comp1 => comp1,
p_18_out => \^p_18_out\,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.fifo_generator_2rd_bin_cntr
port map (
E(0) => \^o2\(0),
I1(0) => Q(1),
O3(9 downto 0) => O3(9 downto 0),
Q(9 downto 0) => O1(9 downto 0),
clk => clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2wr_logic is
port (
full : out STD_LOGIC;
O1 : out STD_LOGIC;
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
p_18_out : in STD_LOGIC;
comp0 : in STD_LOGIC;
O2 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2wr_logic : entity is "wr_logic";
end fifo_generator_2wr_logic;
architecture STRUCTURE of fifo_generator_2wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal comp0_1 : STD_LOGIC;
signal comp1_0 : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.fifo_generator_2wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
comp0 => comp0_1,
comp1 => comp1_0,
full => full,
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_d2 => rst_d2,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.fifo_generator_2wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
I1(9 downto 0) => I1(9 downto 0),
O1 => O1,
O2(0) => O2(0),
O3(9 downto 0) => O3(9 downto 0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
comp0 => comp0,
comp0_3 => comp0_1,
comp1 => comp1,
comp1_4 => comp1_0,
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
v1_reg_1(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_2(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2blk_mem_gen_top is
port (
DOUTB : out STD_LOGIC_VECTOR ( 88 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 88 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_2blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_2blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_2blk_mem_gen_generic_cstr
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(88 downto 0) => DOUTB(88 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(88 downto 0) => din(88 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2blk_mem_gen_v8_2_synth is
port (
DOUTB : out STD_LOGIC_VECTOR ( 88 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 88 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end fifo_generator_2blk_mem_gen_v8_2_synth;
architecture STRUCTURE of fifo_generator_2blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_2blk_mem_gen_top
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(88 downto 0) => DOUTB(88 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(88 downto 0) => din(88 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2blk_mem_gen_v8_2__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 88 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 88 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \fifo_generator_2blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \fifo_generator_2blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.fifo_generator_2blk_mem_gen_v8_2_synth
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(88 downto 0) => DOUTB(88 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(88 downto 0) => din(88 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2memory is
port (
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ENB : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRA : in STD_LOGIC_VECTOR ( 9 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2memory : entity is "memory";
end fifo_generator_2memory;
architecture STRUCTURE of fifo_generator_2memory is
signal doutb : STD_LOGIC_VECTOR ( 88 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\fifo_generator_2blk_mem_gen_v8_2__parameterized0\
port map (
ADDRA(9 downto 0) => ADDRA(9 downto 0),
DOUTB(88 downto 0) => doutb(88 downto 0),
E(0) => E(0),
ENB => ENB,
O3(9 downto 0) => O3(9 downto 0),
Q(0) => Q(0),
clk => clk,
din(88 downto 0) => din(88 downto 0)
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(24),
Q => dout(24),
R => Q(0)
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(25),
Q => dout(25),
R => Q(0)
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(26),
Q => dout(26),
R => Q(0)
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(27),
Q => dout(27),
R => Q(0)
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(28),
Q => dout(28),
R => Q(0)
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(29),
Q => dout(29),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(30),
Q => dout(30),
R => Q(0)
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(31),
Q => dout(31),
R => Q(0)
);
\goreg_bm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(32),
Q => dout(32),
R => Q(0)
);
\goreg_bm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(33),
Q => dout(33),
R => Q(0)
);
\goreg_bm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(34),
Q => dout(34),
R => Q(0)
);
\goreg_bm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(35),
Q => dout(35),
R => Q(0)
);
\goreg_bm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(36),
Q => dout(36),
R => Q(0)
);
\goreg_bm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(37),
Q => dout(37),
R => Q(0)
);
\goreg_bm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(38),
Q => dout(38),
R => Q(0)
);
\goreg_bm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(39),
Q => dout(39),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(40),
Q => dout(40),
R => Q(0)
);
\goreg_bm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(41),
Q => dout(41),
R => Q(0)
);
\goreg_bm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(42),
Q => dout(42),
R => Q(0)
);
\goreg_bm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(43),
Q => dout(43),
R => Q(0)
);
\goreg_bm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(44),
Q => dout(44),
R => Q(0)
);
\goreg_bm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(45),
Q => dout(45),
R => Q(0)
);
\goreg_bm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(46),
Q => dout(46),
R => Q(0)
);
\goreg_bm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(47),
Q => dout(47),
R => Q(0)
);
\goreg_bm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(48),
Q => dout(48),
R => Q(0)
);
\goreg_bm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(49),
Q => dout(49),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(50),
Q => dout(50),
R => Q(0)
);
\goreg_bm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(51),
Q => dout(51),
R => Q(0)
);
\goreg_bm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(52),
Q => dout(52),
R => Q(0)
);
\goreg_bm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(53),
Q => dout(53),
R => Q(0)
);
\goreg_bm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(54),
Q => dout(54),
R => Q(0)
);
\goreg_bm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(55),
Q => dout(55),
R => Q(0)
);
\goreg_bm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(56),
Q => dout(56),
R => Q(0)
);
\goreg_bm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(57),
Q => dout(57),
R => Q(0)
);
\goreg_bm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(58),
Q => dout(58),
R => Q(0)
);
\goreg_bm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(59),
Q => dout(59),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(60),
Q => dout(60),
R => Q(0)
);
\goreg_bm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(61),
Q => dout(61),
R => Q(0)
);
\goreg_bm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(62),
Q => dout(62),
R => Q(0)
);
\goreg_bm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(63),
Q => dout(63),
R => Q(0)
);
\goreg_bm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(64),
Q => dout(64),
R => Q(0)
);
\goreg_bm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(65),
Q => dout(65),
R => Q(0)
);
\goreg_bm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(66),
Q => dout(66),
R => Q(0)
);
\goreg_bm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(67),
Q => dout(67),
R => Q(0)
);
\goreg_bm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(68),
Q => dout(68),
R => Q(0)
);
\goreg_bm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(69),
Q => dout(69),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(70),
Q => dout(70),
R => Q(0)
);
\goreg_bm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(71),
Q => dout(71),
R => Q(0)
);
\goreg_bm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(72),
Q => dout(72),
R => Q(0)
);
\goreg_bm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(73),
Q => dout(73),
R => Q(0)
);
\goreg_bm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(74),
Q => dout(74),
R => Q(0)
);
\goreg_bm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(75),
Q => dout(75),
R => Q(0)
);
\goreg_bm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(76),
Q => dout(76),
R => Q(0)
);
\goreg_bm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(77),
Q => dout(77),
R => Q(0)
);
\goreg_bm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(78),
Q => dout(78),
R => Q(0)
);
\goreg_bm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(79),
Q => dout(79),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(80),
Q => dout(80),
R => Q(0)
);
\goreg_bm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(81),
Q => dout(81),
R => Q(0)
);
\goreg_bm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(82),
Q => dout(82),
R => Q(0)
);
\goreg_bm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(83),
Q => dout(83),
R => Q(0)
);
\goreg_bm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(84),
Q => dout(84),
R => Q(0)
);
\goreg_bm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(85),
Q => dout(85),
R => Q(0)
);
\goreg_bm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(86),
Q => dout(86),
R => Q(0)
);
\goreg_bm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(87),
Q => dout(87),
R => Q(0)
);
\goreg_bm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(88),
Q => dout(88),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_2fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_2fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \grss.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/comp0\ : STD_LOGIC;
signal \grss.rsts/comp1\ : STD_LOGIC;
signal \n_1_gntv_or_sync_fifo.gl0.wr\ : STD_LOGIC;
signal n_4_rstblk : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_2rd_logic
port map (
E(0) => p_15_out,
ENB => tmp_ram_rd_en,
I1 => \n_1_gntv_or_sync_fifo.gl0.wr\,
O1(9 downto 0) => rd_pntr_plus1(9 downto 0),
O2(0) => p_14_out,
O3(9 downto 0) => p_20_out(9 downto 0),
Q(1) => RD_RST,
Q(0) => n_4_rstblk,
clk => clk,
comp0 => \grss.rsts/comp0\,
comp1 => \grss.rsts/comp1\,
empty => empty,
p_18_out => p_18_out,
rd_en => rd_en,
v1_reg(4 downto 0) => \grss.rsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_2wr_logic
port map (
AR(0) => \^rst\,
E(0) => p_3_out,
I1(9 downto 0) => rd_pntr_plus1(9 downto 0),
O1 => \n_1_gntv_or_sync_fifo.gl0.wr\,
O2(0) => p_14_out,
O3(9 downto 0) => p_20_out(9 downto 0),
Q(9 downto 0) => p_9_out(9 downto 0),
clk => clk,
comp0 => \grss.rsts/comp0\,
comp1 => \grss.rsts/comp1\,
full => full,
p_18_out => p_18_out,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => \grss.rsts/c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_2memory
port map (
ADDRA(9 downto 0) => p_9_out(9 downto 0),
E(0) => p_3_out,
ENB => tmp_ram_rd_en,
I1(0) => p_15_out,
O3(9 downto 0) => p_20_out(9 downto 0),
Q(0) => n_4_rstblk,
clk => clk,
din(88 downto 0) => din(88 downto 0),
dout(88 downto 0) => dout(88 downto 0)
);
rstblk: entity work.fifo_generator_2reset_blk_ramfifo
port map (
AR(0) => \^rst\,
Q(1) => RD_RST,
Q(0) => n_4_rstblk,
clk => clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_2fifo_generator_top;
architecture STRUCTURE of fifo_generator_2fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_2fifo_generator_ramfifo
port map (
clk => clk,
din(88 downto 0) => din(88 downto 0),
dout(88 downto 0) => dout(88 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_2fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_generator_2fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_generator_2fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_2fifo_generator_top
port map (
clk => clk,
din(88 downto 0) => din(88 downto 0),
dout(88 downto 0) => dout(88 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_2fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 89;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 89;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
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attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
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attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
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attribute C_PROG_FULL_TYPE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_RD_DEPTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1024;
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attribute C_RD_FREQ of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_RD_PNTR_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_DOUT_RST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_USE_ECC of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_EMBEDDED_REG of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_FIFO16_FLAGS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_FWFT_DATA_COUNT of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_VALID_LOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_WR_ACK_LOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_WR_DEPTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1024;
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attribute C_HAS_SLAVE_CE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_MASTER_CE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_ADD_NGC_CONSTRAINT of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_COMMON_OVERFLOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_COMMON_UNDERFLOW of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_AXI_ID_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_ADDR_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 32;
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attribute C_AXI_DATA_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 64;
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attribute C_HAS_AXI_WUSER of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_AXI_BUSER of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_AXI_RUSER of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_AXI_ARUSER_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_AWUSER_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_WUSER_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_BUSER_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_RUSER_WIDTH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_HAS_AXIS_TDEST of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
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attribute C_HAS_AXIS_TSTRB : integer;
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attribute C_HAS_AXIS_TKEEP of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_AXIS_TSTRB_WIDTH : integer;
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attribute C_APPLICATION_TYPE_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_APPLICATION_TYPE_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_APPLICATION_TYPE_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_APPLICATION_TYPE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_APPLICATION_TYPE_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is "512x36";
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attribute C_USE_ECC_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_ECC_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_ECC_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_USE_ECC_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
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attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
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attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
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attribute C_DIN_WIDTH_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 32;
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attribute C_DIN_WIDTH_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
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attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 16;
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attribute C_WR_PNTR_WIDTH_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
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attribute C_WR_PNTR_WIDTH_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
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attribute C_HAS_DATA_COUNTS_WACH : integer;
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attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_generator_2fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_generator_2fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_generator_2fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_2fifo_generator_v12_0_synth
port map (
clk => clk,
din(88 downto 0) => din(88 downto 0),
dout(88 downto 0) => dout(88 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_2 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 88 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 88 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_2 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_2 : entity is "fifo_generator_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_2 : entity is "fifo_generator_2,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_generator_2 : entity is "fifo_generator_2,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=89,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=89,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_generator_2;
architecture STRUCTURE of fifo_generator_2 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 89;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 89;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 11;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_generator_2fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(10 downto 0) => NLW_U0_data_count_UNCONNECTED(10 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(88 downto 0) => din(88 downto 0),
dout(88 downto 0) => dout(88 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9) => '0',
prog_empty_thresh(8) => '0',
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(9) => '0',
prog_empty_thresh_assert(8) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(9) => '0',
prog_empty_thresh_negate(8) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9) => '0',
prog_full_thresh(8) => '0',
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(9) => '0',
prog_full_thresh_assert(8) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(9) => '0',
prog_full_thresh_negate(8) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(10 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(10 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(10 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(10 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit | f2282ebfe7610cb6758ca5260e33e2f9 | 0.625507 | 3.09624 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup_memory.vhd | 1 | 2,346 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 14:22:20
-- Design Name: rx_path_lookup_memory.vhd
-- Module Name: rx_path_lookup_memory - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module contains the lookup memory
-- for details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rx_path_lookup_memory is
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector;
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic;
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end rx_path_lookup_memory;
architecture structural of rx_path_lookup_memory is
component blk_mem_gen_0 is
Port (
--Port A -> Processor
wea : in std_logic_vector;
addra : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
dina : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clka : in std_logic;
--Port B -> Lookup module
enb : in std_logic; --opt port
addrb : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
doutb : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clkb : in std_logic
);
end component;
begin
lookup_mem_ip : blk_mem_gen_0
PORT MAP (
--Port A
wea => mem_in_wenable,
addra => mem_in_addr,
dina => mem_in_data,
clka => mem_in_clk,
--Port B
enb => mem_out_enable,
addrb => mem_out_addr,
doutb => mem_out_data,
clkb => mem_out_clk
);
end structural;
| mit | 486e4f38bcb4e4ebdc728daed1b75010 | 0.567775 | 3.419825 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | priority-updater/src/main_t.vhd | 1 | 955 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 24-04-2016
-- Module Name: main_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main_t is
end entity main_t;
architecture rtl of main_t is
component main
port (clk, free, reset : in std_logic;
address : in std_logic_vector(3 downto 0);
done : out std_logic;
memory : out std_logic_vector(3 downto 0));
end component;
for all:main use entity work.main;
signal clk, reset, free, done : std_logic := '0';
signal address, memory : std_logic_vector(3 downto 0);
begin
m : main port map (clk, free, reset, address, done, memory);
reset <= '1', '0' after 10 ns;
clk <= not clk after 50 ns;
free <= '1' after 500 ns;
-- free <= '0' when done = '1';
address <= "0101";
end architecture;
| gpl-3.0 | d23ccc0d00b4c486b922951a8e88ecc4 | 0.544503 | 3.472727 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sim_1/imports/simulation/demo_tb.vhd | 1 | 77,568 | --------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : demo_tb.vhd
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This testbench will exercise the ports of the MAC core
-- to demonstrate the functionality.
--------------------------------------------------------------------------------
--
-- This testbench performs the following operations on the MAC core
-- and its design example:
-- - The MDIO interface will respond to a read request with data to prevent the
-- example design thinking it is real hardware
-- - Five frames are then pushed into the receiver from the PHY
-- interface (GMII or RGMII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- The address of fifth frame does not match with the value the address
-- filter is set to therefore gets dropped.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
-- The last frame gets dropped by the address filter due to
-- address mismatch.
-- - The five frames are then re-sent at 100Mb/s, 10Mb/s and finally 1Gb/s again.
------------------------------------------------------------------------
-- DEMONSTRATION TESTBENCH |
-- |
-- |
-- ---------------------------------------------- |
-- | TOP LEVEL WRAPPER (DUT) | |
-- | ------------------- ---------------- | |
-- | | USER LOOPBACK | | TRI-MODE | | |
-- | | DESIGN EXAMPLE | | ETHERNET MAC | | |
-- | | | | CORE | | |
-- | | | | | | Monitor |
-- | | ------->|--->| Tx |--------> Frames |
-- | | | | | PHY | | |
-- | | | | | I/F | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | Rx | | |
-- | | | | | PHY | | |
-- | | --------|<---| I/F |<-------- Generate |
-- | | | | | | Frames |
-- | ------------------- ---------------- | |
-- --------------------------------^------------- |
-- | |
-- | |
-- Stimulate |
-- Management I/F |
-- (if present) |
-- |
------------------------------------------------------------------------
entity demo_tb is
end demo_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of demo_tb is
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
config_board : in std_logic;
--serial_command : in std_logic;
serial_response : out std_logic;
gen_tx_data : in std_logic;
chk_tx_data : in std_logic;
reset_error : in std_logic;
frame_error : out std_logic;
frame_errorn : out std_logic;
activity_flash : out std_logic;
activity_flashn : out std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type tri_mode_ethernet_mac_0_frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of tri_mode_ethernet_mac_0_frame_typ;
-----------------------------------
-- testbench mode selection
-----------------------------------
-- the testbench has two modes of operation:
-- - DEMO := In this mode frames are generated and checked by the testbench
-- and looped back at the user side of the MAC.
-- - BIST := In this mode the built in pattern generators and patttern
-- checkers are used with the data looped back in the PHY domain.
constant TB_MODE : string := "BIST";
-- The following parameter does not control the value the address filter is set to
-- it is only used in the testbench
constant address_filter_value : std_logic_vector(95 downto 0) := X"06050403025A_0605040302DA"; --SA and DA
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core transmit interface by the testbench.
------------------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-------------
0 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-------------
1 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"80", VALID => '1', ERROR => '0'), -- Length/Type = Type = 8000
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'),
60 => ( DATA => X"2F", VALID => '1', ERROR => '0'), -- 47th Data byte
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-------------
2 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'),
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '1'), -- Error asserted
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => true),
-------------
-- Frame 3
-------------
3 => (
columns => (
0 => ( DATA => X"DA", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4
-------------
4 => (
columns => (
0 => ( DATA => X"DB", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"02", VALID => '1', ERROR => '0'),
2 => ( DATA => X"03", VALID => '1', ERROR => '0'),
3 => ( DATA => X"04", VALID => '1', ERROR => '0'),
4 => ( DATA => X"05", VALID => '1', ERROR => '0'),
5 => ( DATA => X"06", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"03", VALID => '1', ERROR => '0'), -- Length/Type = Length = 03
14 => ( DATA => X"01", VALID => '1', ERROR => '0'), -- Therefore padding is required
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Padding starts here
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"00", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"00", VALID => '1', ERROR => '0'),
23 => ( DATA => X"00", VALID => '1', ERROR => '0'),
24 => ( DATA => X"00", VALID => '1', ERROR => '0'),
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"00", VALID => '1', ERROR => '0'),
27 => ( DATA => X"00", VALID => '1', ERROR => '0'),
28 => ( DATA => X"00", VALID => '1', ERROR => '0'),
29 => ( DATA => X"00", VALID => '1', ERROR => '0'),
30 => ( DATA => X"00", VALID => '1', ERROR => '0'),
31 => ( DATA => X"00", VALID => '1', ERROR => '0'),
32 => ( DATA => X"00", VALID => '1', ERROR => '0'),
33 => ( DATA => X"00", VALID => '1', ERROR => '0'),
34 => ( DATA => X"00", VALID => '1', ERROR => '0'),
35 => ( DATA => X"00", VALID => '1', ERROR => '0'),
36 => ( DATA => X"00", VALID => '1', ERROR => '0'),
37 => ( DATA => X"00", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'),
39 => ( DATA => X"00", VALID => '1', ERROR => '0'),
40 => ( DATA => X"00", VALID => '1', ERROR => '0'),
41 => ( DATA => X"00", VALID => '1', ERROR => '0'),
42 => ( DATA => X"00", VALID => '1', ERROR => '0'),
43 => ( DATA => X"00", VALID => '1', ERROR => '0'),
44 => ( DATA => X"00", VALID => '1', ERROR => '0'),
45 => ( DATA => X"00", VALID => '1', ERROR => '0'),
46 => ( DATA => X"00", VALID => '1', ERROR => '0'),
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'),
49 => ( DATA => X"00", VALID => '1', ERROR => '0'),
50 => ( DATA => X"00", VALID => '1', ERROR => '0'),
51 => ( DATA => X"00", VALID => '1', ERROR => '0'),
52 => ( DATA => X"00", VALID => '1', ERROR => '0'),
53 => ( DATA => X"00", VALID => '1', ERROR => '0'),
54 => ( DATA => X"00", VALID => '1', ERROR => '0'),
55 => ( DATA => X"00", VALID => '1', ERROR => '0'),
56 => ( DATA => X"00", VALID => '1', ERROR => '0'),
57 => ( DATA => X"00", VALID => '1', ERROR => '0'),
58 => ( DATA => X"00", VALID => '1', ERROR => '0'),
59 => ( DATA => X"00", VALID => '1', ERROR => '0'),
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal tx_monitor_finished_10M : boolean := false;
signal tx_monitor_finished_100M : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal test_half_duplex : std_logic := '0';
signal gmii_rxd_dut : std_logic_vector(7 downto 0);
signal gmii_rx_dv_dut : std_logic;
signal gmii_rx_er_dut : std_logic;
signal gen_tx_data : std_logic;
signal check_tx_data : std_logic;
signal config_bist : std_logic;
signal frame_error : std_logic;
signal bist_mode_error : std_logic;
signal serial_response : std_logic;
begin
-- select between loopback or local data
gmii_rxd_dut <= gmii_txd when (TB_MODE = "BIST") else gmii_rxd;
gmii_rx_dv_dut <= gmii_tx_en when (TB_MODE = "BIST") else gmii_rx_dv;
gmii_rx_er_dut <= gmii_tx_er when (TB_MODE = "BIST") else gmii_rx_er;
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: tri_mode_ethernet_mac_0_example_design
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd_dut,
gmii_rx_dv => gmii_rx_dv_dut,
gmii_rx_er => gmii_rx_er_dut,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
config_board => config_bist,
serial_response => serial_response,
gen_tx_data => gen_tx_data,
chk_tx_data => check_tx_data,
reset_error => '0',
frame_error => frame_error,
frame_errorn => open,
activity_flash => open,
activity_flashn => open
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 680 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Simulate the MDIO
------------------------------------------------------------------------------
-- respond with sensible data to mdio reads and accept writes.
-- expect mdio to try and read from reg addr 1 - return all 1's if we don't
-- want any other mdio accesses
-- if any other response then mdio will write to reg_addr 9 then 4 then 0
-- (may check for expected write data?)
-- finally mdio read from reg addr 1 until bit 5 is seen high
-- NOTE - do not check any other bits so could drive all high again..
p_mdio_count : process (mdc, reset)
begin
if (reset = '1') then
mdio_count <= (others => '0');
last_mdio <= '0';
elsif mdc'event and mdc = '1' then
last_mdio <= mdio;
if mdio_count >= "100000" then
mdio_count <= (others => '0');
elsif (mdio_count /= "000000") then
mdio_count <= mdio_count + "000001";
else -- only get here if mdio state is 0 - now look for a start
if mdio = '1' and last_mdio = '0' then
mdio_count <= "000001";
end if;
end if;
end if;
end process p_mdio_count;
mdio <= '1' when (mdio_read = '1' and (mdio_count >= "001110") and (mdio_count <= "011111")) else 'Z';
-- only respond to phy and reg address == 1 (PHY_STATUS)
p_mdio_check : process (mdc, reset)
begin
if (reset = '1') then
mdio_read <= '0';
mdio_addr <= '1'; -- this will go low if the address doesn't match required
mdio_fail <= '0';
elsif mdc'event and mdc = '1' then
if (mdio_count = "000010") then
mdio_addr <= '1'; -- reset at the start of a new access to enable the address to be revalidated
if last_mdio = '1' and mdio = '0' then
mdio_read <= '1';
else -- take a write as a default as won't drive at the wrong time
mdio_read <= '0';
end if;
elsif mdio_count <= "001100" then
-- check the phy_addr is 7 and the reg_addr is 0
if mdio_count <= "000111" and mdio_count >= "000101" then
if (mdio /= '1') then
mdio_addr <= '0';
end if;
else
if (mdio /= '0') then
mdio_addr <= '0';
end if;
end if;
elsif mdio_count = "001110" then
if mdio_read = '0' and (mdio = '1' or last_mdio = '0') then
assert false
report "ERROR - Write TA phase is incorrect" & cr
severity failure;
end if;
elsif (mdio_count >= "001111") and (mdio_count <= "011110") and mdio_addr = '1' then
if (mdio_read = '0') then
if (mdio_count = "010100") then
if (mdio = '1') then
mdio_fail <= '1';
assert false
report "ERROR - Expected bit 10 of mdio write data to be 0" & cr
severity failure;
end if;
else
if (mdio = '0') then
mdio_fail <= '1';
assert false
report "ERROR - Expected all except bit 10 of mdio write data to be 1" & cr
severity failure;
end if;
end if;
end if;
end if;
end if;
end process p_mdio_check;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
-- drives mii_tx_clk100 at 25 MHz
p_mii_tx_clk100 : process
begin
mii_tx_clk100 <= '0';
wait for 20 ns;
loop
wait for 20 ns;
mii_tx_clk100 <= '1';
wait for 20 ns;
mii_tx_clk100 <= '0';
end loop;
end process p_mii_tx_clk100;
-- drives mii_tx_clk10 at 2.5 MHz
p_mii_tx_clk10 : process
begin
mii_tx_clk10 <= '0';
wait for 10 ns;
loop
wait for 200 ns;
mii_tx_clk10 <= '1';
wait for 200 ns;
mii_tx_clk10 <= '0';
end loop;
end process p_mii_tx_clk10;
-- Select between 10Mb/s and 100Mb/s MII Tx clock frequencies
p_mii_tx_clk : process(phy_speed, mii_tx_clk100, mii_tx_clk10)
begin
if phy_speed = "11" then
mii_tx_clk <= '0';
elsif phy_speed = "01" then
mii_tx_clk <= mii_tx_clk100;
else
mii_tx_clk <= mii_tx_clk10;
end if;
end process p_mii_tx_clk;
-- Receiver and transmitter clocks are the same in this simulation: connect
-- the appropriate Tx clock source (based on operating speed) to the receiver
-- clock
gmii_rx_clk <= gmii_tx_clk when phy_speed = "10" else mii_tx_clk;
-- monitor frame error and output error when asserted
bist_mode_error_p : process (gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if reset = '1' then
bist_mode_error <= '0';
elsif frame_error = '1' and bist_mode_error = '0' then
bist_mode_error <= '1';
assert false
report "Error: Frame mismatch seen" & cr
severity error;
end if;
end if;
end process bist_mode_error_p;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, and checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
p_management : process
-- Procedure to reset the MAC
------------------------------
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 400 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin -- process p_management
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
gen_tx_data <= '0';
check_tx_data <= '0';
config_bist <= '0';
-- reset the core
mac_reset;
wait until mdio_count = "100000";
wait until mdio_count = "000000";
if TB_MODE = "BIST" then
gen_tx_data <= '1';
check_tx_data <= '1';
-- run for a set time and then stop
wait for 100 us;
-- Our work here is done
if frame_error = '1' then
assert false
report "ERROR: Frame mismatch seen" & cr
severity failure;
elsif serial_response = '1' then
assert false
report "ERROR: AXI4 Lite state Machine error. Incorrect or non-existant PTP frame." & cr
severity failure;
else
assert false
report "Test completed successfully" & cr
severity note;
assert false
report "Simulation Stopped" & cr
severity failure;
end if;
else
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- The stimulus process will now send 5 frames at 1Gb/s.
--------------------------------------------------------------------
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
management_config_finished <= false;
-- Change the speed to 100Mb/s and send the 5 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "01";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
phy_speed <= "01";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_100M;
management_config_finished <= false;
-- Change the speed to 10Mb/s and send the 5 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "00";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
phy_speed <= "00";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_10M;
management_config_finished <= false;
-- Change the speed back to 1Gb/s and send the 4 frames
--------------------------------------------------------------------
wait until gtx_clk'event and gtx_clk = '1';
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
wait until gtx_clk'event and gtx_clk = '1';
update_speed <= '0';
wait until mdio_count = "001000";
wait until mdio_count = "100000";
wait until mdio_count = "000000";
-- Signal that configuration is complete. Other processes will now
-- be allowed to run.
management_config_finished <= true;
wait;
end if;
end process p_management;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
---------------------------------------------------------------
-- Procedure to inject a frame into the receiver at 10/100Mb/s
---------------------------------------------------------------
procedure send_frame_10_100m (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 15 loop
gmii_rxd <= "00000101" after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "00001101" after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
gmii_rxd <= "0000" & to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) after 30 ns;
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after 30 ns;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after 30 ns;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= "0000" & fcs(((8*j)+3) downto (8*j)) after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
gmii_rxd <= "0000" & fcs(((8*j)+7) downto ((8*j)+4)) after 30 ns;
gmii_rx_dv <= '1' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
wait until gmii_rx_clk'event and gmii_rx_clk = '1'; -- wait for next clock tick
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after 30 ns;
gmii_rx_dv <= '0' after 30 ns;
gmii_rx_er <= '0' after 30 ns;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_10_100m;
begin
-- Send four frames through the MAC and Design Exampled
-- at each state Ethernet speed
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-------------------------------------------------------
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
wait for 10 ns;
-- 100 Mb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 100Mb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_10_100m(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_100M;
wait for 10 ns;
-- 10 Mb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 10Mb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_10_100m(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 100M monitor process to complete.
wait until tx_monitor_finished_10M;
wait for 10 ns;
-- 1 Gb/s speed
-------------------------------------------------------
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
assert false
report "Sending five frames at 1Gb/s..." & cr
severity note;
for current_frame in frame_data'low to frame_data'high loop
send_frame_1g(current_frame);
if current_frame = 4 then
send_complete <= '1';
else
send_complete <= '0';
end if;
end loop;
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0' and bist_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
---------------------------------------------------
-- Procedure to check a transmitted frame at 1Gb/s
---------------------------------------------------
procedure check_frame_1g (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_type : string(1 to 4) := (others => ' ');
variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
if (addr_comp_reg /= address_filter_value) then
frame_filtered := 1;
else
frame_filtered := 0;
end if;
if (frame_filtered = 1) then
report "FRAME DROPPED by Address Filter" & cr ;
else
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
if TB_MODE = "DEMO" then
-- Start comparing transmitted data to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
else
frame_type := (others => ' ');
while (gmii_tx_en='1') loop
if current_col = 12 and gmii_txd = X"81" then
frame_type := "VLAN";
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
assert false
report frame_type & " Frame tramsmitted : Size " & integer'image(current_col) & cr
severity note;
end if;
end if;
end check_frame_1g;
--------------------------------------------------------
-- Procedure to check a transmitted frame at 10/100Mb/s
--------------------------------------------------------
procedure check_frame_10_100m (current_frame : in natural) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frame_filtered : integer := 0;
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := to_stdlogicvector(frame_data(current_frame).columns(current_col).data);
current_col := current_col + 1;
end loop;
current_col := 0;
if (addr_comp_reg /= address_filter_value) then
frame_filtered := 1;
else
frame_filtered := 0;
end if;
if (frame_filtered = 1) then
report "FRAME DROPPED by Address Filter" & cr ;
else
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "00000101" loop
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop;
-- Start comparing transmitted dat to received data
assert false
report "Comparing Transmitted Data Frames to Received Data Frames" & cr
severity note;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "00001101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
if gmii_tx_en /= to_stdulogic(frame_data(current_frame).columns(current_col).valid) then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Destination Address field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Destination Address field" & cr
severity error;
end if;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Source Address field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during the Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(3 downto 0)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_txd(3 downto 0) /=
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd(3 downto 0) /= fcs(((8*j)+3) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd(3 downto 0) /= fcs(((8*j)+7) downto ((8*j)+4)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until mii_tx_clk'event and mii_tx_clk = '1';
end loop;
end if;
end check_frame_10_100m;
variable f : tri_mode_ethernet_mac_0_frame_typ; -- temporary frame variable
variable current_frame : natural := 0; -- current frame pointer
begin -- process p_monitor
-- Compare the transmitted frame to the received frames
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
-- Repeated for all stated speeds.
-------------------------------------------------------
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset'event and reset = '0';
wait until management_config_finished;
wait for 300 ns;
if TB_MODE = "DEMO" then
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
-- 100 Mb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 100Mb/s frames.
-- loop over all the frames in the stimulus vector
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_10_100m(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_100M <= true;
tx_monitor_finished_1G <= false;
-- 10 Mb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 10Mb/s frames.
-- loop over all the frames in the stimulus vector
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_10_100m(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_10M <= true;
-- 1 Gb/s speed
-------------------------------------------------------
current_frame := 0;
-- Look for 1Gb/s frames.
-- loop over all the frames in the stimulus record
loop
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move immediately
-- on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Check the current frame
check_frame_1g(current_frame);
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
else
loop
check_frame_1g(current_frame);
end loop;
end if;
end process p_monitor;
end behav;
| mit | 58303ddde9a490239a4b46c9eb163d60 | 0.459223 | 3.909283 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | priority-updater/src/controller.vhd | 1 | 2,457 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 18-04-2016
-- Module Name: controller.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (g, e, l : in std_logic;
clk, reset : in std_logic;
sel_1 : out std_logic;
sel_2 : out std_logic_vector(1 downto 0);
counter_reset, counter_enable : out std_logic;
load : out std_logic;
counter_done : in std_logic;
free: in std_logic;
done: out std_logic;
rwbar : out std_logic);
end entity;
architecture rtl of controller is
type state is (RESET0, RESET1, WAITING, S1, S2, S3, S4, S5);
signal current_state : state;
signal next_state : state;
begin
-- next
process (clk, reset)
begin
if reset = '1' then
current_state <= RESET0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
-- next state + outputs :D
process (current_state, counter_done, g, e, l, reset, free)
begin
if current_state = S1 then
sel_1 <= '0';
rwbar <= '1';
counter_reset <= '1';
next_state <= S2;
elsif current_state = S2 then
load <= '1';
counter_reset <= '0';
sel_1 <= '1';
next_state <= S3;
elsif current_state = S3 then
load <= '0';
next_state <= S4;
elsif current_state = S4 then
if e = '1' and g = '0' and l = '0' then
sel_2 <= "10";
rwbar <= '0';
elsif e = '0' and g = '1' and l = '0' then
rwbar <= '1';
elsif e = '0' and g = '0' and l = '1' then
sel_2 <= "00";
rwbar <= '0';
end if;
next_state <= S5;
elsif current_state = S5 then
rwbar <= '1';
if counter_done = '1' then
done <= '1';
next_state <= WAITING;
else
counter_enable <= '1';
next_state <= S3;
end if;
elsif current_state = WAITING then
if free = '1' then
done <= '0';
next_state <= S1;
else
done <= '0';
next_state <= WAITING;
end if;
elsif current_state = RESET0 then
counter_reset <= '1';
next_state <= RESET1;
sel_1 <= '1';
sel_2 <= "11";
elsif current_state = RESET1 then
counter_enable <= '1';
counter_reset <= '0';
if counter_done = '1' then
rwbar <= '1';
counter_enable <= '0';
next_state <= WAITING;
else
rwbar <= '0';
next_state <= RESET1;
end if;
end if;
end process;
end architecture rtl;
| gpl-3.0 | cc064ffc909de58f3a66a71ebc2811d6 | 0.542939 | 2.880422 | false | false | false | false |
titto-thomas/Pipeline_RISC | regfile.vhdl | 1 | 2,784 | --IITB RISC processor---
--Regfile Module(2to1)---
-- author: Anakha
-----------------------description of entity---------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity regfile is
port (
clock : in std_logic;
reset : in std_logic;
InA : in std_logic_vector(2 downto 0); --address for selecting A
InB : in std_logic_vector(2 downto 0); --address for selecting B
dataA : out std_logic_vector(15 downto 0); --read the data into reg A
dataB : out std_logic_vector(15 downto 0);--read the data into reg B
dataIn : in std_logic_vector(15 downto 0);---data to be written into the register
WritEn : in std_logic; ---enable for writing
WriteAdr : in std_logic_vector(2 downto 0) --to select the destination register
);
end regfile;
----------------------end entity----------------------------
-----------------------description of architecture----------
architecture behave of regfile is
type regarray is array (6 downto 0) of std_logic_vector(15 downto 0);
signal reg: regarray;
begin
---separate process for write and read----------------------
write: process(clock)
begin
if clock'event and clock='1' then
if reset ='1' then
reg(0)<= X"0000";
reg(1)<= X"0000";
reg(2)<= X"0000";
reg(3)<= X"0000";
reg(4)<= X"0000";
reg(5)<= X"0000";
reg(6)<= X"0000";
else
if WritEn = '1' then
case WriteAdr is
when "000" =>
reg(0)<= dataIn;
when "001" =>
reg(1) <= dataIn;
when "010" =>
reg(2) <= dataIn;
when "011" =>
reg(3) <= dataIn;
when "100" =>
reg(4) <= dataIn;
when "101" =>
reg(5) <= dataIn;
when "110" =>
reg(6) <= dataIn;
when others =>
reg(0)<= reg(0);
end case;
end if;
end if;
end if;
end process write;
---------------------------------------------------------------
---------------------process for read-------------------------
read: process(InA,InB)
begin
case InA is
when "000" =>
dataA <= reg(0);
when "001" =>
dataA <= reg(1);
when "010" =>
dataA <= reg(2);
when "011" =>
dataA <= reg(3);
when "100" =>
dataA <= reg(4);
when "101" =>
dataA <= reg(5);
when "110" =>
dataA <= reg(6);
when others =>
dataB <= X"0000";
end case;
case InB is
when "000" =>
dataB <= reg(0);
when "001" =>
dataB <= reg(1);
when "010" =>
dataB <= reg(2);
when "011" =>
dataB <= reg(3);
when "100" =>
dataB <= reg(4);
when "101" =>
dataB <= reg(5);
when "110" =>
dataB <= reg(6);
when others =>
dataB <= X"0000";
end case;
end process read;
---------------------------------------------------
end behave;
| gpl-2.0 | 741654cc1572aebbbf69b663d9b7007b | 0.493894 | 3.362319 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/synth/blk_mem_gen_1.vhd | 1 | 14,001 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.528025 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 5.528025 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
| mit | 31e9826adafb6daf761373dd89c49035 | 0.630098 | 3.021364 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_address_swap.vhd | 1 | 19,134 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_address_swap.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This address swap block will accept the first 12 byte of a packet before
-- starting to loop it out. At this point both the source and destination fields have
-- been completely captured and can therefore be swapped.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_address_swap is
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
-- address swap enable control
enable_address_swap : in std_logic;
-- data from the RX FIFO
rx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : in std_logic;
rx_axis_fifo_tlast : in std_logic;
rx_axis_fifo_tready : out std_logic;
-- data TO the tx fifo
tx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
tx_axis_fifo_tvalid : out std_logic;
tx_axis_fifo_tlast : out std_logic;
tx_axis_fifo_tready : in std_logic
);
end tri_mode_ethernet_mac_0_address_swap;
architecture rtl of tri_mode_ethernet_mac_0_address_swap is
-- State machine
type rd_state_typ is (IDLE,
WAIT_S,
READ_DEST,
READ_SRC,
READ_DEST2,
READ_SRC2,
READ);
type wr_state_typ is (IDLE_W,
WRITE_SLOT1,
WRITE_SLOT2,
WRITE);
signal next_rd_state : rd_state_typ;
signal rd_state : rd_state_typ;
signal next_wr_state : wr_state_typ;
signal wr_state : wr_state_typ;
signal rx_axis_fifo_tvalid_reg : std_logic;
signal rx_axis_fifo_tlast_reg : std_logic;
signal wr_count : unsigned(3 downto 0) := (others => '0');
signal fifo_full : std_logic;
signal wr_slot : unsigned(2 downto 0) := (others => '0');
signal wr_addr : unsigned(2 downto 0) := (others => '0');
signal dia : std_logic_vector(8 downto 0);
signal doa : std_logic_vector(8 downto 0);
signal wea : std_logic;
signal rd_count : unsigned(3 downto 0) := (others => '0');
signal fifo_empty : std_logic;
signal rd_slot : unsigned(2 downto 0) := (others => '0');
signal rd_addr : unsigned(2 downto 0) := (others => '0');
signal dob : std_logic_vector(8 downto 0);
signal tx_axis_fifo_tvalid_int : std_logic;
signal tx_axis_fifo_tlast_int : std_logic;
signal rx_axis_fifo_tready_int : std_logic;
signal axi_treset : std_logic;
signal new_packet_start : std_logic;
signal rd_count_6 : std_logic;
signal rd_count_12 : std_logic;
signal slot_diff : unsigned(2 downto 0) := (others => '0');
signal packet_waiting : std_logic;
begin
rx_axis_fifo_tready <= rx_axis_fifo_tready_int;
axi_treset <= not axi_tresetn;
-- capture a new packet starting as we only want to start taking it once the read side is idle
new_pkt_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
new_packet_start <= '0';
elsif wr_state = IDLE_W and packet_waiting = '0' and rx_axis_fifo_tvalid = '1' and
(rx_axis_fifo_tvalid_reg = '0' or rx_axis_fifo_tlast_reg = '1') then
new_packet_start <= '1';
elsif wr_state /= IDLE_W then
new_packet_start <= '0';
end if;
end if;
end process new_pkt_p;
-- need to monitor the RX FIFO AXI interface and when a new transaction starts capture the first
-- 6 bytes of the frame. Use a LUT6 to capture the data - allows some backoff to take place
-- need to maintain a read an write interface..
-- Write interface
reg_axi_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
rx_axis_fifo_tvalid_reg <= rx_axis_fifo_tvalid;
rx_axis_fifo_tlast_reg <= rx_axis_fifo_tlast;
end if;
end process reg_axi_p;
-- simple write state machine
next_wr_s : process(wr_state, rx_axis_fifo_tvalid, wr_count, rx_axis_fifo_tlast,
new_packet_start, rd_state)
begin
next_wr_state <= wr_state;
case wr_state is
-- detect a rising edge on TVALID OR TLAST on previous cycle AND TVALID
when IDLE_W =>
if rd_state = IDLE and new_packet_start = '1' then
next_wr_state <= WRITE_SLOT1;
end if;
-- finish writing when tlast is high
when WRITE_SLOT1 =>
if wr_count = X"6" and rx_axis_fifo_tvalid = '1' then
next_wr_state <= WRITE_SLOT2;
elsif rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
when WRITE_SLOT2 =>
if wr_count = X"c" and rx_axis_fifo_tvalid = '1' then
next_wr_state <= WRITE;
elsif rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
when WRITE =>
if rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
end case;
end process;
wr_state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_state <= IDLE_W;
elsif fifo_full = '0' then
wr_state <= next_wr_state;
end if;
end if;
end process wr_state_p;
packet_wait_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
packet_waiting <= '0';
elsif wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
packet_waiting <= '1';
elsif rd_state /= IDLE then
packet_waiting <= '0';
end if;
end if;
end process packet_wait_p;
-- generate a write count to control where the data is written
wr_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_count <= (others => '0');
else
if wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
wr_count <= X"1";
elsif wr_state /= IDLE_W and rx_axis_fifo_tvalid = '1' and fifo_full = '0' and wr_count /= x"f" then
wr_count <= wr_count + X"1";
end if;
end if;
end if;
end process wr_count_p;
-- we have a 64 deep lut - to simplify storing/fetching of data this is split into 8 address slots. When
-- a new packet starts the first byte of the address is stored in the next available address slot, with the next address being
-- stored in the next slot (i.e after a gap of two locations). Once the addresses have been stored the data starts
-- at the next slot and then continues until completion.
wr_slot_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_slot <= (others => '0');
wr_addr <= (others => '0');
elsif wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
wr_slot <= "000";
wr_addr <= (others => '0');
elsif wr_state = WRITE_SLOT1 and next_wr_state = WRITE_SLOT2 then
wr_slot <= "001";
wr_addr <= (others => '0');
elsif wr_state = WRITE_SLOT2 and next_wr_state = WRITE then
wr_slot <= "010";
wr_addr <= (others => '0');
elsif rx_axis_fifo_tready_int = '1' and rx_axis_fifo_tvalid = '1' and fifo_full = '0' then
wr_addr <= wr_addr + "001";
if wr_addr = "111" then
wr_slot <= wr_slot + "001";
end if;
end if;
end if;
end process wr_slot_p;
slot_diff <= rd_slot - wr_slot;
-- need to generate full logic to generate the ready - simplified by there only being
-- one clock domain..
-- to allow for reaction time generate as full when we are only one slot away
fifo_full_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if (slot_diff = "010" or slot_diff = "001") and wr_state = WRITE then
fifo_full <= '1';
else
fifo_full <= '0';
end if;
end if;
end process fifo_full_p;
rx_axis_fifo_tready_int <= '1' when fifo_full = '0' and wr_state /= IDLE_W else '0';
dia <= rx_axis_fifo_tlast & rx_axis_fifo_tdata;
wea <= '1' when rx_axis_fifo_tready_int = '1' else '0';
LUT6_gen : for I in 0 to 8 generate
begin
RAM64X1D_inst : RAM64X1D
port map (
DPO => dob(I),
SPO => doa(I),
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_slot(0),
A4 => wr_slot(1),
A5 => wr_slot(2),
D => dia(I),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_slot(0),
DPRA4 => rd_slot(1),
DPRA5 => rd_slot(2),
WCLK => axi_tclk,
WE => wea
);
end generate;
-- read logic - this is kicked into action when the wr_state moves from IDLE but will not start to read until
-- the wr_state moves to WRITE as the two addresses are then in situ
-- can then choose if we wish to addess swap or not - if a small packet is rxd which is less than the required 12 bytes
-- the read logic will revert to non address swap and just output what is there..
next_rd_s : process(rd_state, enable_address_swap, rd_count_6, rd_count_12, tx_axis_fifo_tready, dob,
wr_state, tx_axis_fifo_tvalid_int)
begin
next_rd_state <= rd_state;
case rd_state is
when IDLE =>
if wr_state /= IDLE_W then
next_rd_state <= WAIT_S;
end if;
when WAIT_S =>
if wr_state = IDLE_W then
next_rd_state <= READ_DEST2;
elsif wr_state = WRITE then
if enable_address_swap = '1' then
next_rd_state <= READ_SRC;
else
next_rd_state <= READ_DEST2;
end if;
end if;
when READ_SRC =>
if rd_count_6 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ_DEST;
end if;
when READ_DEST =>
if rd_count_12 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ;
end if;
when READ_DEST2 =>
if rd_count_6 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ_SRC2;
end if;
when READ_SRC2 =>
if rd_count_12 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ;
end if;
when READ =>
if dob(8) = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= IDLE;
end if;
when others =>
next_rd_state <= IDLE;
end case;
end process;
rd_state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_state <= IDLE;
else
rd_state <= next_rd_state;
end if;
end if;
end process rd_state_p;
-- generate a read count to control where the data is read
rd_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_count <= (others => '0');
rd_count_6 <= '0';
rd_count_12 <= '0';
else
if rd_state = WAIT_S then
rd_count <= X"1";
elsif rd_state /= IDLE and tx_axis_fifo_tvalid_int = '1' and
tx_axis_fifo_tready = '1' and rd_count /= X"f" then
rd_count <= rd_count + X"1";
if rd_count = X"5" then
rd_count_6 <= '1';
else
rd_count_6 <= '0';
end if;
if rd_count = X"b" then
rd_count_12 <= '1';
else
rd_count_12 <= '0';
end if;
end if;
end if;
end if;
end process rd_count_p;
-- we have a 64 deep lut - to simplify storing/fetching of data this is split into 8 address slots. When
-- a new packet starts the first byte of the address is stored in the next available address slot, with the next address being
-- stored in the next slot (i.e after a gap of two locations). Once the addresses have been stored the data starts
-- at the next slot and then continues until completion.
rd_slot_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_slot <= (others => '0');
rd_addr <= (others => '0');
elsif rd_state = WAIT_S and next_rd_state = READ_DEST2 then
rd_slot <= "000";
rd_addr <= (others => '0');
elsif rd_state = WAIT_S and next_rd_state = READ_SRC then
rd_slot <= "001";
rd_addr <= (others => '0');
elsif rd_state = READ_DEST2 and next_rd_state = READ_SRC2 then
rd_slot <= "001";
rd_addr <= (others => '0');
elsif rd_state = READ_SRC and next_rd_state = READ_DEST then
rd_slot <= "000";
rd_addr <= (others => '0');
elsif rd_state = READ_DEST and next_rd_state = READ then
rd_slot <= "010";
rd_addr <= (others => '0');
elsif rd_state = READ_SRC2 and next_rd_state = READ then
rd_slot <= "010";
rd_addr <= (others => '0');
elsif tx_axis_fifo_tvalid_int = '1' and tx_axis_fifo_tready = '1' then
rd_addr <= rd_addr + "001";
if rd_addr = "111" then
rd_slot <= rd_slot + "001";
end if;
end if;
end if;
end process rd_slot_p;
-- need to generate empty to generate the tvalid for the tx_fifo interface - the empty is purely a compare of the
-- rd/wr access point - if the same and TLAST (dob[8]) is low then must still be in packet so drop tvalid - and stall read
empty_p : process (wr_slot, wr_addr, rd_slot, rd_addr)
begin
if wr_slot = rd_slot and wr_addr = rd_addr then
fifo_empty <= '1';
else
fifo_empty <= '0';
end if;
end process;
-- generate the tvalid
valid_p : process (rd_state, fifo_empty, tx_axis_fifo_tready, dob)
begin
if rd_state = IDLE then
tx_axis_fifo_tvalid_int <= '0';
elsif rd_state /= WAIT_S then
if fifo_empty = '1' and tx_axis_fifo_tready = '1' and dob(8) = '0' then
tx_axis_fifo_tvalid_int <= '0';
else
tx_axis_fifo_tvalid_int <= '1';
end if;
else
tx_axis_fifo_tvalid_int <= '0';
end if;
end process;
-- and the output data/tlast
rd_data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if tx_axis_fifo_tready = '1' then
if fifo_empty = '0' then
tx_axis_fifo_tdata <= dob(7 downto 0);
end if;
tx_axis_fifo_tvalid <= tx_axis_fifo_tvalid_int;
tx_axis_fifo_tlast_int <= dob(8);
end if;
end if;
end process rd_data_p;
tx_axis_fifo_tlast <= tx_axis_fifo_tlast_int;
end rtl;
| mit | 05b6baa923b8a451d6eb61083b2f708a | 0.535905 | 3.785163 | false | false | false | false |
Caian/Minesweeper | Projeto/stack.vhd | 1 | 8,047 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: stack.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY stack IS
PORT(
enable, rstn, clock : in std_logic;
mode : in std_logic_vector(1 downto 0);
data : in std_logic_vector(13 downto 0);
empty : out std_logic;
q : out std_logic_vector(13 downto 0)
);
END stack;
ARCHITECTURE SYN OF stack IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (13 DOWNTO 0);
signal la, wa, pa, eff : std_logic_vector(9 downto 0);
signal wren : std_logic;
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(13 DOWNTO 0);
wren <= '1' when mode = "01" or
mode = "11" else '0';
process(clock, rstn)
begin
if rstn = '0' then
wa <= (wa'range => '1') + 1;
la <= (la'range => '1');
pa <= (pa'range => '1') - 1;
elsif enable = '1' then
if rising_edge(clock) then
if mode = "01" then
wa <= wa + 1;
la <= la + 1;
pa <= pa + 1;
elsif mode = "10" then
wa <= wa - 1;
la <= la - 1;
pa <= pa - 1;
end if;
end if;
end if;
end process;
with mode select
eff <= wa when "01", -- Write address
pa when "10", -- Pop address
la when others; -- Lookup address
empty <= '1' when la = (la'range => '1') else '0';
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./stack.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 10,
width_a => 14,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => eff,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Stack/stack.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "12"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Stack/stack.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL data[11..0]
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL stack_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 6205e486b8f7e27c04e89611008afd91 | 0.640611 | 3.424255 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_point_doubling.vhd | 1 | 8,453 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Doubling
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- x1_i - X part of input point
-- y1_i - Y part of input point
-- x2_io - X part of output point
-- y2_o - Y part of putput point
-- ready_o - Ready flag
--
-- Math:
-- s = x1 + y1/x1
-- x2 = s^2 + s + a
-- y2 = x1^2 + s*x2 + x2
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 27.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- K163 elliptic curve point doubling
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_doubling IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT(
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
x2_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y2_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_doubling;
ARCHITECTURE rtl of e_gf2m_point_doubling IS
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Temporary signals for divider and multiplier
SIGNAL div_xy, mult_lx2, lambda, lambda_square, x1_square: std_logic_vector(M-1 DOWNTO 0);
SIGNAL x2_tmp, y2_tmp, next_xq, next_yq: std_logic_vector(M-1 DOWNTO 0);
-- Signals to switch between multiplier and divider
SIGNAL start_div, div_done, start_mult, mult_done, sel, load, ch_q: std_logic;
-- Define all available states
subtype states IS natural RANGE 0 TO 9;
SIGNAL current_state: states;
BEGIN
-- Output register
register_q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
x2_io <= (OTHERS=>'1');
y2_o <= (OTHERS=>'1');
ELSIF ch_q = '1' THEN
x2_io <= next_xq;
y2_o <= next_yq;
END IF;
END IF;
END PROCESS;
-- Instantiate divider entity
-- Calculate div_xy = y1 / x1
divider: e_gf2m_divider GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_div,
g_i => y1_i,
h_i => x1_i,
z_o => div_xy,
ready_o => div_done
);
-- Compute lambda
-- Calculate lambda = x1 + y1/x1
multiplier_inputs: FOR i IN 0 TO M-1 GENERATE
lambda(i) <= x1_i(i) xor div_xy(i);
END GENERATE;
-- Instantiate squarer
-- Calculate lambda^2 and x1^2
lambda_square_computation: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => lambda,
c_o => lambda_square
);
x1_square_computation: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => x1_i,
c_o => x1_square
);
-- Compute x2_tmp
-- Calculate x2 = lambda^2 + lambda + a
x2_output: FOR i IN 0 TO M-1 GENERATE
x2_tmp(i) <= lambda_square(i) xor lambda(i) xor A(i);
END GENERATE;
-- Instantiate multiplier entity
-- Calculate mult_lx2 = lambda * x2_tmp
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_mult,
a_i => lambda,
b_i => x2_tmp,
z_o => mult_lx2,
ready_o => mult_done
);
-- Compute y2_tmp
-- Calculate y2 = x1^2 + lambda*x2 + x2
y2_output: FOR i IN 0 TO M-1 GENERATE
y2_tmp(i) <= x1_square(i) xor mult_lx2(i) xor x2_tmp(i);
END GENERATE;
WITH sel SELECT next_yq <= y2_tmp WHEN '0', ONES WHEN OTHERS;
WITH sel SELECT next_xq <= x2_tmp WHEN '0', ONES WHEN OTHERS;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate s = (py-qy)/(px-qx), s^2
-- 4,5,6 : Calculate rx/ry
CASE current_state IS
WHEN 0 TO 1 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '1';
WHEN 2 => load <= '1'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 3 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 4 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '1'; start_mult <= '0'; ready_o <= '0';
WHEN 5 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 6 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '1'; ready_o <= '0';
WHEN 7 => load <= '0'; sel <= '0'; ch_q <= '0'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 8 => load <= '0'; sel <= '0'; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 9 => load <= '0'; sel <= '1'; ch_q <= '1'; start_div <= '0'; start_mult <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (x1_i = ONES) OR (y1_i = ONES) THEN
current_state <= 9;
ELSE
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF div_done = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF mult_done = '1' THEN
current_state <= 8;
END IF;
WHEN 8 =>
current_state <= 0;
WHEN 9 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS;
END rtl; | gpl-3.0 | 410cc2b97804eeeb86f2cc338080f49e | 0.457116 | 3.510382 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | priority-updater/src/datapath.vhd | 1 | 2,719 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 11-04-2016
-- Module Name: datapath.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity datapath is
port (g, e, l : out std_logic;
clk : in std_logic;
sel_1 : in std_logic;
sel_2 : in std_logic_vector(1 downto 0);
counter_reset, counter_enable : in std_logic;
rwbar : in std_logic;
load : in std_logic;
counter_done : out std_logic;
input_address : in std_logic_vector(3 downto 0));
end entity;
architecture rtl of datapath is
component memory
port (address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector;
clk, rwbar : in std_logic);
end component;
component n_register
generic (N : integer := 4);
port (d : in std_logic_vector(N - 1 downto 0);
clk, load : in std_logic;
q : out std_logic_vector(N - 1 downto 0));
end component;
component compare
port (n1, n2 : in std_logic_vector(3 downto 0);
g, e, l : out std_logic);
end component;
component fulladdr
port (a, b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
c_out : out std_logic;
sum : out std_logic_vector(3 downto 0));
end component;
component counter
generic (N : integer := 4);
port (number : out std_logic_vector (N - 1 downto 0) := (others => '0');
clk, r, en : in std_logic);
end component;
for all:memory use entity work.memory;
for all:n_register use entity work.n_register;
for all:compare use entity work.compare;
for all:fulladdr use entity work.fulladdr;
for all:counter use entity work.counter;
signal value : std_logic_vector(3 downto 0);
signal p_v : std_logic_vector(3 downto 0);
signal fulladdr_data_in : std_logic_vector(3 downto 0);
signal data_in : std_logic_vector(3 downto 0);
signal c_out : std_logic;
signal address : std_logic_vector(3 downto 0);
signal counter_address : std_logic_vector(4 downto 0);
begin
mem : memory port map(address, data_in, value, clk, rwbar);
priority_register : n_register generic map(4) port map(value, clk, load, p_v);
cmp : compare port map(value, p_v, g, e, l);
fa : fulladdr port map (value, "0001", '0', c_out, fulladdr_data_in);
cn : counter generic map(5) port map(counter_address, clk, counter_reset, counter_enable);
data_in <= counter_address(3 downto 0) when sel_2 = "11"
else fulladdr_data_in when sel_2 = "00" else (others => '0') ;
address <= counter_address(3 downto 0) when sel_1 = '1' else input_address;
counter_done <= '1' when counter_address(4) = '1' else '0';
end architecture rtl;
| gpl-3.0 | 915ed5c9819d6b1b550a8b29175c4aaf | 0.632953 | 3.103881 | false | false | false | false |
lennartbublies/ecdsa | src/e_nm_piso_register.vhd | 1 | 1,374 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Parallel In Serial Out Register
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz ([email protected])
-- Date: 29.06.2017
-- Last change: 22.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_nm_piso_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
load_i : IN std_logic;
data_i : IN std_logic_vector(M-1 DOWNTO 0);
data_o : OUT std_logic_vector(U-1 DOWNTO 0)
);
END e_nm_piso_register;
ARCHITECTURE rtl OF e_nm_piso_register IS
SIGNAL temp : std_logic_vector(M-1 DOWNTO 0);
BEGIN
PROCESS (clk_i, rst_i, load_i, data_i) IS
BEGIN
IF (rst_i='1') THEN
temp <= (OTHERS=>'0');
ELSIF rising_edge(clk_i) THEN
IF load_i = '1' THEN
temp <= data_i ;
END IF;
IF enable_i='1' THEN
temp(M-U-1 DOWNTO 0) <= temp(M-1 DOWNTO U);
END IF;
END IF;
END PROCESS;
data_o(U-1 DOWNTO 0) <= temp(U-1 DOWNTO 0);
END rtl; | gpl-3.0 | 006266c496afd32ea848a1e03e9900ce | 0.483261 | 3.578125 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/sim/fifo_generator_2.vhd | 1 | 33,397 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_2 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(88 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(88 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_2;
ARCHITECTURE fifo_generator_2_arch OF fifo_generator_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_2_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(88 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(88 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 89,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 89,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_2_arch;
| mit | bb213453f1102c0f87896061e0d88668 | 0.60727 | 3.074947 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_final.vhd | 1 | 5,907 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_final is
port
( clock : in std_logic;
Uofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vactcapofk_mux_sel : in std_logic;
Vactcapofk_sel : in std_logic;
Vactcapofk_reset : in std_logic;
Pofk_mux_sel : in std_logic;
Pofk_sel : in std_logic;
Pofk_reset : in std_logic;
Vactcapofkplusone_sel : in std_logic;
Vactcapofkplusone_reset : in std_logic;
Pofkplusone_sel : in std_logic;
Pofkplusone_reset : in std_logic;
Pofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0);
Vactcapofkplusone_enable : out std_logic;
Pofkplusone_enable : out std_logic
);
end kn_kalman_final;
architecture struct of kn_kalman_final is
component kn_kalman_Vactcapdashofkplusone is
port
( clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pdashofkplusone is
port
( clock : in std_logic;
Pofk : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Kofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
R : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Pofkplusone is
port
( clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component mux is
port
( clock : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
Z : in std_logic;
prod : out std_logic_vector(31 downto 0));
end component;
component kr_regbuf is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0) );
end component;
component kr_regbuf_enable is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0);
enable : out std_logic );
end component;
signal Vactcapdashofkplusone,Pdashofkplusone,Kofkplusone : std_logic_vector(31 downto 0);
signal Vactcapofk_initial : std_logic_vector (31 downto 0) := "00111111111011001100110011001101";
signal Pofk_initial : std_logic_vector (31 downto 0) := "00111111011111010111000010100100";
signal M : std_logic_vector (31 downto 0) := "00111100001000111101011100001010";
signal Q : std_logic_vector (31 downto 0) := "00111100001000111101011100001010";
signal R : std_logic_vector (31 downto 0) := "00111000110100011011011100010111";
signal V1,V2,V3,J1,J2,J3,K1,K2,K3,N1,N2 : std_logic_vector (31 downto 0);
begin
M1 : mux port map
( clock => clock,
a => Vactcapofk_initial,
b => K1,
z => Vactcapofk_mux_sel,
prod => V1);
M2 : kr_regbuf port map
( clock => clock,
reset => Vactcapofk_reset,
load => Vactcapofk_sel,
I => V1,
Y => J1);
M3 : mux port map
( clock => clock,
a => Pofk_initial,
b => K2,
z => Pofk_mux_sel,
prod => V2);
M4 : kr_regbuf port map
( clock => clock,
reset => Pofk_reset,
load => Pofk_sel,
I => V2,
Y => J2);
M5 : kn_kalman_Vactcapdashofkplusone
port map
( clock => clock,
Vactcapofk => J1,
M => M,
Uofk => Uofk,
Vactcapdashofkplusone => Vactcapdashofkplusone );
M6 : kn_kalman_Pdashofkplusone
port map
( clock => clock,
Pofk => J2,
Q => Q,
Pdashofkplusone => Pdashofkplusone );
M7 : kn_kalman_Kofkplusone
port map
( clock => clock,
Pdashofkplusone => Pdashofkplusone,
R => R,
Kofkplusone => Kofkplusone );
M8 : kn_kalman_Pofkplusone
port map
( clock => clock,
Pdashofkplusone => Pdashofkplusone,
Kofkplusone => Kofkplusone,
Pofkplusone => N2 );
M9 : kr_regbuf_enable
port map
( clock => clock,
reset => Pofkplusone_reset,
load => Pofkplusone_sel,
I => N2,
Y => K2,
enable => Pofkplusone_enable);
M10 : kn_kalman_Vactcapofkplusone
port map
( clock => clock,
Vactcapdashofkplusone => Vactcapdashofkplusone,
Vrefofkplusone => Vrefofkplusone,
Kofkplusone => Kofkplusone,
Vactcapofkplusone => N1 );
M11 : kr_regbuf_enable
port map
( clock => clock,
reset => Vactcapofkplusone_reset,
load => Vactcapofkplusone_sel,
I => N1,
Y => K1,
enable => Vactcapofkplusone_enable);
Pofkplusone <= K2;
Vactcapofkplusone <= K1;
end struct;
| gpl-2.0 | a34148c921fc91d44244c65a588f3a2b | 0.582868 | 4.004746 | false | false | false | false |
titto-thomas/Pipeline_RISC | mux8to1.vhdl | 1 | 1,221 | --IITB RISC processor---
--Mux Module(8to1)---
-- author: Anakha
library ieee;
use ieee.std_logic_1164.all;
entity mux8to1 is
generic (
nbits : integer);
port (
input0, input1, input2, input3, input4, input5, input6, input7 : in std_logic_vector(nbits-1 downto 0);
output : out std_logic_vector(nbits-1 downto 0);
sel0, sel1, sel2 : in std_logic);
end mux8to1;
architecture behave of mux8to1 is
begin -- behave
process(input0,input1,input2,input3,input4,input5,input6,input7,sel0,sel1,sel2)
variable sel_var : std_logic_vector(2 downto 0);
begin
sel_var(0) := sel0;
sel_var(1) := sel1;
sel_var(2) := sel2;
case sel_var is
when "000" =>
output <= input0 ;
when "001" =>
output <= input1;
when "010" =>
output <= input2;
when "011" =>
output <= input3;
when "100" =>
output <= input4;
when "101" =>
output <= input5;
when "110" =>
output <= input6;
when "111" =>
output <= input7;
when others =>
output <="Z";
end case;
end process;
end behave ;
| gpl-2.0 | f202c2159da8b8996f55bef9f0c4dcea | 0.529075 | 3.317935 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/sync_blocks/aeg_design_reset_sync.vhd | 2 | 5,702 | --------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity aeg_design_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of aeg_design_0_reset_sync : entity is "yes";
end aeg_design_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of aeg_design_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
| mit | fb22ee06c86838c58ca057f3ab5d5b7c | 0.608208 | 4.137881 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/rx_path_header_extraction.vhd | 2 | 10,786 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 19.11.2013 09:52:09
-- Design Name:
-- Module Name: rx_path_header_extraction - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
-- Description:
-- Incoming frames are analyzed and the ethernet header is analyzed
-- the output consists of the source address of the incoming frame,
-- a signal for vlan frame indication and the vlan priority
-- a state machine handles the header extraction and the forwarding of the outputs
--
-- more details in switch_port_rxpath_header_extraction.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity rx_path_header_extraction is
Generic (
RECEIVER_DATA_WIDTH : integer;
DEST_ADDR_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
hext_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
hext_in_valid : in std_logic;
hext_in_last : in std_logic;
hext_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface
hext_out_dest : out std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
hext_out_vlan_enable : out std_logic;
hext_out_vlan_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
hext_out_valid : out std_logic;
hext_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
hext_out_ready : in std_logic
);
end rx_path_header_extraction;
architecture rtl of rx_path_header_extraction is
constant DEST_ADDR_WIDTH_BYTE : integer := DEST_ADDR_WIDTH/8;
constant SOURCE_ADDR_WIDTH : integer := 6;
constant UPPER_DEST_ADDRESS : integer := SOURCE_ADDR_WIDTH;
constant UPPER_SOURCE_ADDRESS : integer := UPPER_DEST_ADDRESS + SOURCE_ADDR_WIDTH;
constant CNT_WIDTH : integer := 5; -- ld ethernet_header size = ld 18
constant VLAN_TPID1 : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0) := x"81";
constant VLAN_TPID2 : std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0) := x"00";
constant TPID_UPPER : integer := 7;
constant TPID_LOWER : integer := 5;
-- extraction header state machine
type state is (
IDLE,
DEST_ADDR,
SOURCE_ADDR,
TYPE_LENGTH1,
TYPE_LENGTH2,
VLAN_PRIO,
HANDSHAKE,
WAIT_EOF
);
signal cur_state : state;
signal nxt_state : state;
-- state machine signals
signal update_cnt_sig : std_logic := '0';
signal reset_cnt_sig : std_logic := '0';
signal read_dest_sig : std_logic := '0';
signal vlan_frame_sig : std_logic := '0';
signal no_vlan_frame_sig : std_logic := '0';
signal read_vlan_prio_sig : std_logic := '0';
signal valid_out_sig : std_logic := '0';
signal read_timestamp_sig : std_logic := '0';
-- process registers
signal dest_reg : std_logic_vector(DEST_ADDR_WIDTH-1 downto 0) := (others => '0'); -- contains mac destination address
signal vlan_frame_reg : std_logic := '0'; -- indicates whether the current frame is a vlan frame
signal vlan_prio_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := (others => '0'); -- contains the vlan priority
signal valid_reg : std_logic := '0'; -- indicates whether output is valid or not
signal timestamp_reg : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal cnt : std_logic_vector(CNT_WIDTH-1 downto 0) := (others => '0'); -- frame byte counter
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_state <= IDLE;
else
cur_state <= nxt_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next state, combinitorial logic
output_logic_p : process(cur_state, hext_in_valid, cnt, hext_out_ready, hext_in_data, hext_in_last)
begin
nxt_state <= IDLE;
update_cnt_sig <= '0';
reset_cnt_sig <= '0';
read_dest_sig <= '0';
vlan_frame_sig <= '0';
no_vlan_frame_sig <= '0';
read_vlan_prio_sig <= '0';
valid_out_sig <= '0';
read_timestamp_sig <= '0';
case cur_state is
when IDLE => -- waiting for a frame
if hext_in_valid = '1' and hext_in_last = '0' then
nxt_state <= DEST_ADDR;
update_cnt_sig <= '1'; -- cnt_p
read_dest_sig <= '1'; -- dest_mac_p
read_timestamp_sig <= '1'; -- read_timestamp_p
end if;
when DEST_ADDR => -- extracting the destination mac address
if cnt = UPPER_DEST_ADDRESS-1 and hext_in_valid = '1' then
nxt_state <= SOURCE_ADDR;
else
nxt_state <= DEST_ADDR;
end if;
if hext_in_valid = '1' then
read_dest_sig <= '1'; -- dest_mac_p
update_cnt_sig <= '1'; -- cnt_p
end if;
when SOURCE_ADDR => -- 6 bytes of source mac address
if cnt = UPPER_SOURCE_ADDRESS-1 and hext_in_valid = '1' then
nxt_state <= TYPE_LENGTH1;
else
nxt_state <= SOURCE_ADDR;
end if;
if hext_in_valid = '1' then
update_cnt_sig <= '1'; -- cnt_p
end if;
when TYPE_LENGTH1 => -- first length/type byte, check for vlan frame
if hext_in_valid = '1' then
if hext_in_data = VLAN_TPID1 then
nxt_state <= TYPE_LENGTH2;
else
no_vlan_frame_sig <= '1'; -- vlan_frame_p
valid_out_sig <= '1'; -- output_handshake_p
nxt_state <= HANDSHAKE;
end if;
else
nxt_state <= TYPE_LENGTH1;
end if;
when TYPE_LENGTH2 => -- second length/type byte, check for vlan frame
if hext_in_valid = '1' then
if hext_in_data = VLAN_TPID2 then
nxt_state <= VLAN_PRIO;
vlan_frame_sig <= '1'; -- vlan_frame_p
else
no_vlan_frame_sig <= '1'; -- vlan_frame_p
valid_out_sig <= '1'; -- output_handshake_p
nxt_state <= HANDSHAKE;
end if;
else
nxt_state <= TYPE_LENGTH2;
end if;
when VLAN_PRIO => -- extract vlan priority field
if hext_in_valid = '1' then
nxt_state <= HANDSHAKE;
valid_out_sig <= '1'; -- output_handshake_p
read_vlan_prio_sig <= '1'; -- vlan_prio_p
else
nxt_state <= VLAN_PRIO;
end if;
when HANDSHAKE => -- send output data to next layer
if hext_out_ready = '1' then
nxt_state <= WAIT_EOF;
reset_cnt_sig <= '1'; -- cnt_p
else
nxt_state <= HANDSHAKE;
valid_out_sig <= '1'; -- output_handshake_p
end if;
when WAIT_EOF => -- wait for last byte of current frame
if hext_in_last = '1' then
nxt_state <= IDLE;
else
nxt_state <= WAIT_EOF;
end if;
end case;
end process;
-- header bytes counter
cnt_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' or reset_cnt_sig = '1' then
cnt <= (others => '0');
else
cnt <= cnt;
if update_cnt_sig = '1' then
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
-- write the destination address of the current frame to an internal register
dest_mac_p : process (clk)
variable remaining_dest_bytes : integer;
begin
if clk'event and clk = '1' then
if reset = '1' then
dest_reg <= (others => '0');
else
dest_reg <= dest_reg;
if read_dest_sig = '1' then
remaining_dest_bytes := DEST_ADDR_WIDTH_BYTE - to_integer(unsigned(cnt));
dest_reg(remaining_dest_bytes*8-1 downto remaining_dest_bytes*8-RECEIVER_DATA_WIDTH) <= hext_in_data;
end if;
end if;
end if;
end process;
-- store the timestamp for incoming messages
read_timestamp_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
timestamp_reg <= (others => '0');
else
timestamp_reg <= timestamp_reg;
if read_timestamp_sig = '1' then
timestamp_reg <= hext_in_timestamp_cnt;
end if;
end if;
end if;
end process;
-- write to an internal register if the current frame is a vlan frame
vlan_frame_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
vlan_frame_reg <= '0';
else
vlan_frame_reg <= vlan_frame_reg;
if no_vlan_frame_sig = '1' then
vlan_frame_reg <= '0';
elsif vlan_frame_sig = '1' then
vlan_frame_reg <= '1';
end if;
end if;
end if;
end process;
-- write the vlan priority to an internal register
vlan_prio_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
vlan_prio_reg <= (others => '0');
else
vlan_prio_reg <= vlan_prio_reg;
if read_vlan_prio_sig = '1' then
vlan_prio_reg <= hext_in_data(TPID_UPPER downto TPID_LOWER);
end if;
end if;
end if;
end process;
-- handshake protocol to send header to next layer
output_handshake_p : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
valid_reg <= '0';
else
valid_reg <= '0';
if valid_out_sig = '1' then
valid_reg <= '1';
end if;
end if;
end if;
end process;
hext_out_dest <= dest_reg;
hext_out_vlan_enable <= vlan_frame_reg;
hext_out_vlan_prio <= vlan_prio_reg;
hext_out_valid <= valid_reg;
hext_out_timestamp <= timestamp_reg;
end rtl;
| mit | 9030c2d6732a0dfc8648233275fa1275 | 0.525774 | 3.693836 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/sim/blk_mem_gen_2.vhd | 1 | 12,117 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_2 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_2;
ARCHITECTURE blk_mem_gen_2_arch OF blk_mem_gen_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.9418 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_2_arch;
| mit | 54c60f4c1348ac13c904d3f2fa36430e | 0.612775 | 3.214911 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | s4/mealy/mealy_t.vhd | 1 | 960 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: mealy_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mealy_t is
end entity;
architecture arch_mealy_t of mealy_t is
component mealy is
port (d, clk, reset: in std_logic;
z: out std_logic);
end component mealy;
signal data: std_logic_vector(0 to 9) := "1100010110";
signal clk, r, d, z: std_logic := '0';
signal clk_t: std_logic := '0';
for all:mealy use entity work.mealy(arch_mealy);
begin
m : mealy port map (d, clk, r, z);
clk <= not clk after 50 ns;
clk_t <= not clk_t after 40 ns;
process (clk_t)
variable i : natural := 0;
begin
if clk_t = '1' and clk_t'event then
d <= data(i);
i := i + 1;
end if;
end process;
end architecture arch_mealy_t;
| gpl-3.0 | 2327620715b80970be561aa064181ac3 | 0.535417 | 3.189369 | false | false | false | false |
titto-thomas/Pipeline_RISC | reg.vhdl | 1 | 905 | ----------------------------------------
-- Register Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 8/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg is
generic (
nbits : integer);
port (
reg_in : in std_logic_vector(nbits-1 downto 0); -- register input
reg_out : out std_logic_vector(nbits-1 downto 0); -- register output
clock : in std_logic; -- clock signal
write : in std_logic; -- write enable signal
reset : in std_logic -- reset signal
);
end reg;
architecture behave of reg is
begin -- behave
process(clock,reset)
begin
if(rising_edge(clock)) then
if(reset = '1') then
reg_out <= (others => '0'); -- reset the register
elsif write = '1' then
reg_out <= reg_in; -- store the input
end if;
end if;
end process;
end behave;
| gpl-2.0 | 208744e1828ac3ed89c7476352ce97d4 | 0.564641 | 3.376866 | false | false | false | false |
lennartbublies/ecdsa | src/e_uart_receiver.vhd | 1 | 13,635 | ----------------------------------------------------------------------------------------------------
-- Entity - UART Receiver
-- Receives data from RX of UART interface. Can be toggled between SIG and VALID mode.
--
-- The key has to be right aligned if it is not byte-aligned:
-- i.e. M=9 => 9 Bits => rx_i will get 2 Bytes: "0000_0001" and "1111_1111"
-- with 0 being ignored and 1 being the key.
--
--
-- Generic:
-- baud_rate : baud rate of UART
-- N
-- M - Key length in Bits
-- Ports:
-- clk_i - global clock signal
-- rst_i - global reset signal
-- rx_i - uart rx input (receive data)
-- mode_i - Mode of ECDSA: 0 = Sign (receive message), 1 = Verify (receive R, S and message)
-- data_o - byte wise output of data
-- ena_r_o - enable write to R register
-- ena_s_o - enable write to S register
-- ena_m_o - enable write to R register
-- rdy_o - ready at end of incoming data
--
-- Author: Leander Schulz ([email protected])
-- Date: 10.07.2017
-- Last change: 25.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY e_uart_receiver IS
GENERIC (
baud_rate : IN NATURAL RANGE 1200 TO 500000;
N : IN NATURAL RANGE 1 TO 256;
M : IN NATURAL RANGE 1 TO 256);
PORT (
clk_i : IN std_logic;
rst_i : IN std_logic;
rx_i : IN std_logic;
mode_o : OUT std_logic;
data_o : OUT std_logic_vector (7 DOWNTO 0);
ena_r_o : OUT std_logic;
ena_s_o : OUT std_logic;
ena_m_o : OUT std_logic;
rdy_o : OUT std_logic);
END ENTITY e_uart_receiver;
ARCHITECTURE e_uart_receiver_arch OF e_uart_receiver IS
-- signal declaration
--TYPE uart_state_type IS (idle, start, data0, data1, data2, data3, data4, data5, data6, data7, parity, stop);
TYPE uart_state_type IS (idle, start, data, stop);
SIGNAL s_uart_state, s_uart_next : uart_state_type;
--SIGNAL scan_cnt, wait_cnt, symbol_cycles, wait_rate, bit_cnt : INTEGER;
-- #################
-- p_scan_clk:
CONSTANT clk_period : INTEGER := 20; -- 1G/50M ns
SUBTYPE t_scan IS NATURAL RANGE 0 TO 50000000;
SIGNAL scan_clk : std_logic := '0';
SIGNAL scan_cnt : t_scan := 0;
-- symbol_length in ns (104.166ns bei 9600 Baud)
CONSTANT symbol_length : INTEGER := 1000000000 / baud_rate; -- 1G
-- symbol_cycles = Anzahl taktperioden eines Symbols (5208 Zyklen bei 9600 Baud)
CONSTANT symbol_cycles : INTEGER := symbol_length / clk_period;
CONSTANT wait_rate : t_scan := (symbol_cycles/2)*3;
SIGNAL wait_cnt : INTEGER RANGE 0 TO wait_rate := 0;
-- p_scan_clk:
SIGNAL rst_internal : std_logic := '1';
-- p_scan_symbol:
SUBTYPE t_byte IS NATURAL RANGE 0 TO 9;
SIGNAL bit_cnt : t_byte := 0;
-- #################
-- p_calc_bytes
CONSTANT param_bytes_a : NATURAL RANGE 1 TO 128 := M / 8;
CONSTANT param_bytes_b : NATURAL RANGE 0 TO 7 := M MOD 8; -- for check if M is byte aligned
SIGNAL param_bytes : NATURAL RANGE 1 TO 128;
-- p_cnt_bytes
-- dmode = detect mode ("00000000" for sign or "11111111" for verify)
-- smode = set mode ('0' or '1')
-- phase1 = read point r
-- phase2 = read point s
-- phase3 = read message
TYPE phase_state_type IS (idle, dmode, smode, phase1, phase2, phase3, stop);
SIGNAL s_phase, s_phase_next : phase_state_type;
SIGNAL s_cnt_phas1 : NATURAL RANGE 0 TO 128;
SIGNAL s_cnt_phas2 : NATURAL RANGE 0 TO 128;
SIGNAL s_cnt_phas3 : NATURAL RANGE 0 TO 256 := N;
SIGNAL s_phas1_tmp : NATURAL RANGE 0 TO 128;
SIGNAL s_phas2_tmp : NATURAL RANGE 0 TO 128;
SIGNAL s_phas3_tmp : NATURAL RANGE 0 TO 128;
SIGNAL s_rdy : std_logic;
SIGNAL s_data : std_logic_vector (0 TO 7);
SIGNAL s_data_o : std_logic_vector (0 TO 7);
-- detect mode
CONSTANT c_mode_sign : std_logic_vector (7 DOWNTO 0) := "00000000";
CONSTANT c_mode_verify : std_logic_vector (7 DOWNTO 0) := "11111111";
SIGNAL s_mode, s_mode_tmp : std_logic;
SIGNAL s_mode_start, s_mode_start_tmp : std_logic;
SIGNAL s_rx_ff, s_rx : std_logic;
BEGIN
-- synchronize rx signal
PROCESS BEGIN
WAIT UNTIL rising_edge(clk_i);
s_rx_ff <= rx_i;
s_rx <= s_rx_ff;
END PROCESS;
-- UART Receive State Machine
p_byte_fsm : PROCESS(s_uart_state,s_uart_next,rst_internal,s_rx,scan_clk,bit_cnt,s_rdy)
BEGIN
s_uart_next <= s_uart_state;
rst_internal <= '1';
CASE s_uart_state IS
WHEN idle =>
IF s_rx = '0' THEN
s_uart_next <= start;
rst_internal <= '0';
END IF;
WHEN start =>
rst_internal <= '1';
IF scan_clk = '1' THEN
s_uart_next <= data;
END IF;
WHEN data =>
IF bit_cnt = 9 THEN
s_uart_next <= stop;
END IF;
WHEN stop =>
IF s_rx = '0' OR s_rdy = '1' THEN
s_uart_next <= idle;
END IF;
END CASE;
END PROCESS p_byte_fsm;
--- save the rx signal via shifting into s_data:
p_shift : PROCESS(clk_i,rst_i,rst_internal,s_rx,s_data,scan_clk,bit_cnt,s_uart_state) --ALL)
BEGIN
IF rst_i = '1' THEN
s_data <= (others => '0');
ELSIF rising_edge(clk_i) AND scan_clk = '1' THEN
IF bit_cnt < 8 AND NOT (s_uart_state = idle) THEN
s_data(0) <= s_rx;
FOR i IN 1 TO 7 LOOP
s_data(i) <= s_data(i-1);
END LOOP;
END IF;
END IF;
END PROCESS p_shift;
p_scan_symbol : PROCESS(clk_i,s_rx,scan_clk,rst_i,bit_cnt,rst_internal)
BEGIN
IF rst_i = '1' THEN
bit_cnt <= 0;
ELSIF rst_internal = '0' THEN
bit_cnt <= 0;
ELSIF rising_edge(clk_i) AND scan_clk = '1' THEN
IF bit_cnt < 9 AND NOT (s_uart_state = idle) THEN
bit_cnt <= bit_cnt + 1;
END IF;
END IF;
END PROCESS p_scan_symbol;
--- process to generate the clock signal 'scan_clk' to determine when to read s_rx
-- p_scan_clk : PROCESS(ALL)
p_scan_clk : PROCESS(clk_i,rst_i,s_rx,rst_internal,wait_cnt,bit_cnt,scan_cnt)
BEGIN
IF rst_i = '1' THEN
scan_clk <= '0';
scan_cnt <= 0;
wait_cnt <= 0;
ELSIF rising_edge(clk_i) THEN
IF rst_internal = '0' THEN
scan_clk <= '0';
scan_cnt <= 0;
wait_cnt <= 0;
ELSIF wait_cnt < wait_rate THEN
wait_cnt <= wait_cnt + 1;
ELSE
IF bit_cnt = 9 AND NOT (s_uart_state = idle) THEN
scan_clk <= '0';
scan_cnt <= 0;
wait_cnt <= 0;
ELSIF scan_cnt = 0 THEN
scan_clk <= '1';
scan_cnt <= scan_cnt + 1;
ELSE
scan_clk <= '0';
IF scan_cnt < symbol_cycles THEN
scan_cnt <= scan_cnt + 1;
ELSIF scan_cnt = symbol_cycles THEN
scan_cnt <= 0;
END IF;
END IF;
END IF;
END IF;
END PROCESS p_scan_clk;
p_byte_store : PROCESS(rst_i,clk_i,param_bytes) --ALL)
BEGIN
IF rst_i = '1' THEN
s_uart_state <= idle;
s_phase <= idle;
s_phas1_tmp <= param_bytes;
s_phas2_tmp <= param_bytes;
s_phas3_tmp <= N;
s_mode <= '0';
s_mode_start <= '0';
ELSIF rising_edge(clk_i) THEN
s_uart_state <= s_uart_next;
s_phase <= s_phase_next;
s_phas1_tmp <= s_cnt_phas1;
s_phas2_tmp <= s_cnt_phas2;
s_phas3_tmp <= s_cnt_phas3;
s_mode <= s_mode_tmp;
s_mode_start <= s_mode_start_tmp;
END IF;
END PROCESS p_byte_store;
-- push to output
p_scan_out : PROCESS(clk_i,rst_i,s_uart_state,s_uart_next)
BEGIN
IF rst_i = '1' THEN
s_data_o <= "00000000";
s_rdy <= '0';
s_mode_start_tmp <= '0';
ELSIF rising_edge(clk_i) THEN
IF s_uart_state = data AND s_uart_next = stop THEN
-- detect mode
IF s_phase = dmode THEN
IF s_data = c_mode_sign THEN
-- sign
s_mode_tmp <= '0';
s_mode_start_tmp <= '1';
ELSIF s_data = c_mode_verify THEN
-- verify
s_mode_tmp <= '1';
s_mode_start_tmp <= '1';
s_rdy <= '1';
ELSE
-- mode detection failed
-- raise huge error
ASSERT FALSE REPORT "Mode Detection Failed!" SEVERITY FAILURE;
END IF;
ELSE
s_data_o <= s_data;
s_rdy <= '1';
s_mode_start_tmp <= '0';
END IF;
ELSE
s_mode_start_tmp <= '0';
s_rdy <= '0';
END IF;
END IF;
END PROCESS p_scan_out;
-- calculate bytes to read
p_calc_bytes : PROCESS(param_bytes)
BEGIN
IF (param_bytes_b = 0) THEN
param_bytes <= param_bytes_a;
ELSE
param_bytes <= param_bytes_a+1;
END IF;
END PROCESS p_calc_bytes;
-- state machine
p_cnt_bytes : PROCESS(rst_i,rst_internal,s_mode,s_phase,s_rdy,s_mode_start,s_phas1_tmp,s_phas2_tmp,s_phas3_tmp,param_bytes)
BEGIN
s_phase_next <= s_phase;
s_cnt_phas1 <= s_phas1_tmp;
s_cnt_phas2 <= s_phas2_tmp;
s_cnt_phas3 <= s_phas3_tmp;
CASE s_phase IS
WHEN idle =>
s_cnt_phas1 <= param_bytes;
s_cnt_phas2 <= param_bytes;
s_cnt_phas3 <= N;
IF rst_internal = '0' THEN
s_phase_next <= dmode;
END IF;
WHEN dmode =>
IF s_mode_start = '1' THEN
s_phase_next <= smode;
END IF;
WHEN smode =>
IF s_mode = '1' THEN
-- verify
s_phase_next <= phase1;
ELSIF s_mode = '0' THEN
-- sign
s_phase_next <= phase3;
END IF;
WHEN phase1 =>
IF s_rdy = '1' THEN
s_cnt_phas1 <= s_phas1_tmp - 1;
END IF;
IF s_phas1_tmp = 0 THEN
s_phase_next <= phase2;
END IF;
WHEN phase2 =>
IF s_rdy = '1' THEN
s_cnt_phas2 <= s_phas2_tmp - 1;
END IF;
IF s_phas2_tmp = 0 THEN
s_phase_next <= phase3;
END IF;
WHEN phase3 =>
IF s_rdy = '1' THEN
s_cnt_phas3 <= s_phas3_tmp - 1;
END IF;
IF s_phas3_tmp = 0 THEN
s_phase_next <= stop;
END IF;
WHEN stop =>
s_phase_next <= idle;
END CASE;
END PROCESS p_cnt_bytes;
-- push to output
p_bytes_out : PROCESS(clk_i,rst_i,s_phase,s_phase_next,s_mode)
BEGIN
IF rst_i = '1' THEN
mode_o <= '0';
data_o <= "00000000";
rdy_o <= '0';
ena_r_o <= '0';
ena_s_o <= '0';
ena_m_o <= '0';
ELSIF rising_edge(clk_i) THEN
IF s_mode_start = '1' THEN
mode_o <= s_mode;
END IF;
IF s_rdy = '1' THEN
IF s_phase = idle OR s_phase = dmode or s_phase = smode THEN
data_o <= "00000000";
ena_r_o <= '0';
ena_s_o <= '0';
ena_m_o <= '0';
ELSIF s_phase = phase1 THEN
data_o <= s_data_o;
ena_r_o <= '1';
ena_s_o <= '0';
ena_m_o <= '0';
ELSIF s_phase = phase2 THEN
data_o <= s_data_o;
ena_r_o <= '0';
ena_s_o <= '1';
ena_m_o <= '0';
ELSIF s_phase = phase3 THEN
data_o <= s_data_o;
ena_r_o <= '0';
ena_s_o <= '0';
ena_m_o <= '1';
ELSIF s_phase = stop THEN
ena_r_o <= '0';
ena_s_o <= '0';
ena_m_o <= '0';
END IF;
ELSE
data_o <= "00000000";
ena_r_o <= '0';
ena_s_o <= '0';
ena_m_o <= '0';
END IF;
IF s_phase_next = stop THEN
rdy_o <= '1';
ELSE
rdy_o <= '0';
END IF;
END IF;
END PROCESS p_bytes_out;
END ARCHITECTURE e_uart_receiver_arch;
| gpl-3.0 | ce3e249acc12a12d4df9fd369b0ec726 | 0.448845 | 3.58062 | false | false | false | false |
EclipseSpark/unipa-exercises | c/vhdl/dec24.vhdl | 1 | 524 | library IEEE;
use IEEE.std_logic_1164.ALL;
--use IEEE.std_logic_arith.ALL;
entity DEC24 is
port(A, B, E: in std_logic;
O: out std_logic_vector (3 to 0));
end DEC24;
architecture Behavioral of DEC24 is
function
string(A, B, E);
begin
signal(An, Bn: std_logic);
An <= NOT A;
Bn <= NOT B;
if (E=1) then
A: = '0' & B: = '0' => O <= "0001";
A: = '0' & B: = '1' => O <= "0010";
A: = '1' & B: = '0' => O <= "0100";
A: = '1' & B: = '1' => O <= "1000";
else
O = "0000";
end if;
end architecture;
| gpl-3.0 | bda26233aa05888c8428ba81cd5f5eae | 0.519084 | 2.258621 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/tx/output_queue_memory.vhd | 2 | 4,356 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 14:15:52
-- Design Name:
-- Module Name: output_queue_memory - rtl
-- Project Name: automotive ehternet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: wrapper for the output queue memory
-- the output queue memory stores frames received from the switching fabric temporarily
-- until they can be tranismitted via the mac
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity output_queue_memory is
Generic (
NR_OQ_MEM : integer;
VLAN_PRIO_WIDTH : integer;
OQ_MEM_ADDR_WIDTH_A : integer;
OQ_MEM_ADDR_WIDTH_B : integer;
OQ_MEM_DATA_WIDTH_IN : integer;
OQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
--Port A -> control module
oqmem_in_wr_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
oqmem_in_wenable : in std_logic_vector;
oqmem_in_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
oqmem_in_data : in std_logic_vector(OQ_MEM_DATA_WIDTH_IN-1 downto 0);
oqmem_in_clk : in std_logic;
--Port B -> arbitration module -> mac
oqmem_out_rd_prio : in std_logic;
oqmem_out_enable : in std_logic;
oqmem_out_addr : in std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
oqmem_out_data : out std_logic_vector(NR_OQ_MEM*OQ_MEM_DATA_WIDTH_OUT-1 downto 0);
oqmem_out_clk : in std_logic
);
end output_queue_memory;
architecture rtl of output_queue_memory is
component blk_mem_gen_2 is
Port (
--Port A -> control module
wea : in std_logic_vector;
addra : in std_logic_vector(OQ_MEM_ADDR_WIDTH_A-1 downto 0);
dina : in std_logic_vector(OQ_MEM_DATA_WIDTH_IN-1 downto 0);
clka : in std_logic;
--Port B -> arbitration module -> mac
enb : in std_logic; --opt port
addrb : in std_logic_vector(OQ_MEM_ADDR_WIDTH_B-1 downto 0);
doutb : out std_logic_vector(OQ_MEM_DATA_WIDTH_OUT-1 downto 0);
clkb : in std_logic
);
end component;
signal rd_en_sig : std_logic_vector(NR_OQ_MEM-1 downto 0) := (others => '0');
signal wr_en_sig : std_logic_vector(NR_OQ_MEM-1 downto 0) := (others => '0');
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
begin
init_p : process(oqmem_out_enable, oqmem_in_wenable, oqmem_in_wr_prio, oqmem_out_rd_prio, high_priority_border_value_reg)
begin
if NR_OQ_MEM = 1 then
wr_en_sig(0) <= oqmem_in_wenable(0);
rd_en_sig(0) <= oqmem_out_enable;
elsif NR_OQ_MEM = 2 then
if oqmem_in_wr_prio >= high_priority_border_value_reg then
wr_en_sig(0) <= '0';
wr_en_sig(NR_OQ_MEM-1) <= oqmem_in_wenable(0);
else
wr_en_sig(0) <= oqmem_in_wenable(0);
wr_en_sig(NR_OQ_MEM-1) <= '0';
end if;
if oqmem_out_rd_prio = '1' then
rd_en_sig(0) <= '0';
rd_en_sig(NR_OQ_MEM-1) <= oqmem_out_enable;
else
rd_en_sig(0) <= oqmem_out_enable;
rd_en_sig(NR_OQ_MEM-1) <= '0';
end if;
end if;
end process;
Xmem : for i in 0 to NR_OQ_MEM-1 generate
output_queue_mem_ip : blk_mem_gen_2
PORT MAP (
--Port A
wea => wr_en_sig(i downto i),
addra => oqmem_in_addr,
dina => oqmem_in_data,
clka => oqmem_in_clk,
--Port B
enb => rd_en_sig(i),
addrb => oqmem_out_addr,
doutb => oqmem_out_data((i+1)*OQ_MEM_DATA_WIDTH_OUT-1 downto i*OQ_MEM_DATA_WIDTH_OUT),
clkb => oqmem_out_clk
);
end generate Xmem;
end rtl;
| mit | b86a9e10287f34cb57648a632de93a74 | 0.527319 | 3.389883 | false | false | false | false |
caiopo/mips-multiciclo | src/operacaoULA.vhd | 1 | 1,029 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity operacaoULA is
port(
ULAOp: in std_logic_vector(1 downto 0);
funct: in std_logic_vector(5 downto 0);
Operacao: out std_logic_vector(2 downto 0)
);
end entity;
architecture comportamental of operacaoULA is
begin
Operacao <= "010" when ULAOp="00" else -- sum
"110" when ULAOp="01" else -- sub
"111" when funct(3)='1' else -- slt
"001" when funct(0)='1' else -- or
"000" when funct(2)='1' else -- and
"010" when funct(1)='0' else -- sum
"110"; -- sub
end architecture; | mit | 5b8c2c691fe6133c68a6987967289fe0 | 0.524781 | 3.714801 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/common/tri_mode_ethernet_mac_0_reset_sync.vhd | 5 | 5,746 | --------------------------------------------------------------------------------
-- Title : Reset synchroniser
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_reset_sync is
generic (
INITIALISE : bit := '1';
DEPTH : integer := 5
);
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_reset_sync : entity is "yes";
end tri_mode_ethernet_mac_0_reset_sync;
--------------------------------------------------------------------------------
architecture rtl of tri_mode_ethernet_mac_0_reset_sync is
signal reset_sync_reg0 : std_logic;
signal reset_sync_reg1 : std_logic;
signal reset_sync_reg2 : std_logic;
signal reset_sync_reg3 : std_logic;
signal reset_sync_reg4 : std_logic;
attribute async_reg : string;
attribute async_reg of reset_sync0 : label is "true";
attribute async_reg of reset_sync1 : label is "true";
attribute async_reg of reset_sync2 : label is "true";
attribute async_reg of reset_sync3 : label is "true";
attribute async_reg of reset_sync4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of reset_sync0 : label is "no";
attribute shreg_extract of reset_sync1 : label is "no";
attribute shreg_extract of reset_sync2 : label is "no";
attribute shreg_extract of reset_sync3 : label is "no";
attribute shreg_extract of reset_sync4 : label is "no";
begin
reset_sync0 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => '0',
Q => reset_sync_reg0
);
reset_sync1 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg0,
Q => reset_sync_reg1
);
reset_sync2 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg1,
Q => reset_sync_reg2
);
reset_sync3 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg2,
Q => reset_sync_reg3
);
reset_sync4 : FDPE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
CE => enable,
PRE => reset_in,
D => reset_sync_reg3,
Q => reset_sync_reg4
);
reset_out <= reset_sync_reg4;
end rtl;
| mit | be41891e5b68765ea7e7ddcda487a679 | 0.609816 | 4.121951 | false | false | false | false |
diecaptain/kalman_mppt | demux.vhd | 1 | 807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity demux is
port ( clock : in std_logic;
prod : in std_logic_vector (31 downto 0);
Z0 : in std_logic;
Z1 : in std_logic;
Z2 : in std_logic;
Z3 : in std_logic;
a : out std_logic_vector (7 downto 0));
end demux;
architecture dataf of demux is
signal S0 : std_logic;
signal S1 : std_logic;
begin
process (prod,S0,S1,Z0,Z1,Z2,Z3)
begin
if S0 = '0' then
if S1 = '0' then
if Z0 = '0' then
a <= prod(31 downto 24);
end if;
else
if Z1 = '0' then
a <= prod(23 downto 16);
end if;
end if;
else
if S1 = '0' then
if Z2 = '0' then
a <= prod(15 downto 8);
end if;
else
if Z3 = '0' then
a <= prod(7 downto 0);
end if;
end if;
end if;
end process;
end dataf; | gpl-2.0 | 1bc799d4b5862f3a97a88bdf95407fa7 | 0.584882 | 2.681063 | false | false | false | false |
gihankarunarathne/vhdl-learn | DataFlow/ConditionBasedOn1Matching.vhd | 1 | 1,307 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:20:40 08/27/2013
-- Design Name:
-- Module Name: ConditionBasedOn1Matching - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ConditionBasedOn1Matching is
port(s0,s1: in STD_LOGIC;
input: in STD_LOGIC_VECTOR (3 downto 0);
z: out STD_LOGIC);
end ConditionBasedOn1Matching;
architecture Behavioral of ConditionBasedOn1Matching is
begin
z <= input(0) when s0='0' else -- if stop after first matching condition
-- So, here it out put input(0) when (s0=0 and s1=0) or (s0=0 and s1=1)
input(1) when s0='1' and s1='0' else
input(2) when s0='0' and s1='1' else
input(3);
end Behavioral;
| mit | c1e4fa6549f96c5975d3e7d5012afcfb | 0.612089 | 3.532432 | false | false | false | false |
rkujawa/cr2amiga | main.vhd | 1 | 4,839 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port( LEDS : out STD_LOGIC_VECTOR (3 downto 0);
D_AN : out STD_LOGIC_VECTOR (3 downto 0);
D_C : out STD_LOGIC_VECTOR (7 downto 0);
BTN0 : in STD_LOGIC;
BTN1 : in STD_LOGIC;
SW0 : in STD_LOGIC;
SW1 : in STD_LOGIC;
MCLK : in STD_LOGIC;
USB_D : inout STD_LOGIC_VECTOR (7 downto 0);
USB_WAIT : out STD_LOGIC;
USB_WRITE : in STD_LOGIC;
USB_ASTB : in STD_LOGIC;
USB_DSTB : in STD_LOGIC;
-- clockport
CP_CS : in STD_LOGIC;
CP_A : in STD_LOGIC_VECTOR (3 downto 0);
CP_D : inout STD_LOGIC_VECTOR (7 downto 0);
CP_IORD : in STD_LOGIC;
CP_IOWR : in STD_LOGIC);
end main;
architecture Behavioral of main is
component clk_gen
Port( clk : in STD_LOGIC;
clkmod : out STD_LOGIC;
divval : in integer
);
end component;
component eppmodule
Port ( astb : in STD_LOGIC;
dstb : in STD_LOGIC;
wr : in STD_LOGIC;
wt : out STD_LOGIC;
databus :inout STD_LOGIC_VECTOR (7 downto 0);
ssegReg :out STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg: in STD_LOGIC_VECTOR(7 downto 0));
end component;
component sseg
Port ( clock : in STD_LOGIC;
segA : in STD_LOGIC_VECTOR (7 downto 0);
segB : in STD_LOGIC_VECTOR (7 downto 0);
segC : in STD_LOGIC_VECTOR (7 downto 0);
segD : in STD_LOGIC_VECTOR (7 downto 0);
segout :out STD_LOGIC_VECTOR (7 downto 0);
segan : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component hextoseg
Port ( hex : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component clockport
Port( -- clockport signals
data : inout STD_LOGIC_VECTOR (7 downto 0);
addressIn : in STD_LOGIC_VECTOR (3 downto 0);
iord : in STD_LOGIC;
iowr : in STD_LOGIC;
cs : in STD_LOGIC;
--addressOut : out STD_LOGIC_VECTOR (3 downto 0);
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
testOut : out STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg: in STD_LOGIC_VECTOR(7 downto 0));
end component;
signal sA, sB, sC, sD : STD_LOGIC_VECTOR (7 downto 0);
signal sHex : STD_LOGIC_VECTOR (7 downto 0);
signal sHexLo : STD_LOGIC_VECTOR (3 downto 0);
signal sHexHi : STD_LOGIC_VECTOR (3 downto 0);
signal sHex2 : STD_LOGIC_VECTOR (7 downto 0);
signal sHex2Lo : STD_LOGIC_VECTOR (3 downto 0);
signal sHex2Hi : STD_LOGIC_VECTOR (3 downto 0);
signal slowclk : STD_LOGIC;
signal pushableReg : STD_LOGIC_VECTOR(7 downto 0);
signal ledReg : STD_LOGIC_VECTOR(3 downto 0);
signal commDataAtoU : STD_LOGIC_VECTOR (7 downto 0);
signal commDataUtoA : STD_LOGIC_VECTOR (7 downto 0);
-- only for debugging
--signal cpAddress : STD_LOGIC_VECTOR (3 downto 0);
begin
-- CLK_DIV16_inst1 : CLK_DIV16
-- port map (
-- CLKDV => fullclk1,
-- CLKIN => CLK
-- );
clk_gen_inst1 : clk_gen
port map (
clk => MCLK,
clkmod => slowclk,
divval => 500 -- 8MHz / 500 = circa 16kHz
);
deppusb : eppmodule
port map (
astb => USB_ASTB,
dstb => USB_DSTB,
wr => USB_WRITE,
wt => USB_WAIT,
dataBus => USB_D,
ssegReg => sHex,
-- ledReg => ledReg,
btnReg => pushableReg,
commDataInReg => commDataAtoU,
commDataOutReg => commDataUtoA
);
sseg1 : sseg
port map (
clock => slowclk,
segA => sA,
segB => sB,
segC => sC,
segD => sD,
segout => D_C,
segan => D_AN
);
hextoseglo : hextoseg
port map (
hex => sHexLo,
seg => sA
);
hextoseghi : hextoseg
port map (
hex => sHexHi,
seg => sB
);
hextoseglo2 : hextoseg
port map (
hex => sHex2Lo,
seg => sC
);
hextoseghi2 : hextoseg
port map (
hex => sHex2Hi,
seg => sD
);
amigacp : clockport
port map (
data => CP_D,
addressIn => CP_A,
iord => CP_IORD,
iowr => CP_IOWR,
cs => CP_CS,
btnReg => pushableReg,
ledReg => ledReg,
testOut => sHex2,
commDataInReg => commDataUtoA,
commDataOutReg => commDataAtoU
);
LEDS <= NOT ledReg;
--LEDS <= NOT cpAddress;
sHexLo <= sHex(0) & sHex(1) & sHex(2) & sHex(3);
sHexHi <= sHex(4) & sHex(5) & sHex(6) & sHex(7);
sHex2Lo <= sHex2(0) & sHex2(1) & sHex2(2) & sHex2(3);
sHex2Hi <= sHex2(4) & sHex2(5) & sHex2(6) & sHex2(7);
pushableReg(0) <= NOT BTN0;
pushableReg(1) <= NOT BTN1;
pushableReg(2) <= NOT SW0;
pushableReg(3) <= NOT SW1;
end Behavioral;
| mit | edd47addadc3ebb0698870365fbeddf3 | 0.647448 | 2.760411 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_funcsim.vhdl | 1 | 118,209 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:06 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_funcsim.vhdl
-- Design : blk_mem_gen_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_2blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_2blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_2blk_mem_gen_prim_wrapper
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
port (
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_2blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_2blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_2blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(25 downto 24),
dina(5 downto 4) => dina(17 downto 16),
dina(3 downto 2) => dina(9 downto 8),
dina(1 downto 0) => dina(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
enb => enb,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(27 downto 26),
dina(5 downto 4) => dina(19 downto 18),
dina(3 downto 2) => dina(11 downto 10),
dina(1 downto 0) => dina(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
enb => enb,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(29 downto 28),
dina(5 downto 4) => dina(21 downto 20),
dina(3 downto 2) => dina(13 downto 12),
dina(1 downto 0) => dina(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
enb => enb,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\blk_mem_gen_2blk_mem_gen_prim_width__parameterized2\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 6) => dina(31 downto 30),
dina(5 downto 4) => dina(23 downto 22),
dina(3 downto 2) => dina(15 downto 14),
dina(1 downto 0) => dina(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_2blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_2blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_2blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_2blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_2blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_2blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_2.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 12;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 16384;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 14;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "4";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 10.9418 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(31) <= \<const0>\;
douta(30) <= \<const0>\;
douta(29) <= \<const0>\;
douta(28) <= \<const0>\;
douta(27) <= \<const0>\;
douta(26) <= \<const0>\;
douta(25) <= \<const0>\;
douta(24) <= \<const0>\;
douta(23) <= \<const0>\;
douta(22) <= \<const0>\;
douta(21) <= \<const0>\;
douta(20) <= \<const0>\;
douta(19) <= \<const0>\;
douta(18) <= \<const0>\;
douta(17) <= \<const0>\;
douta(16) <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_2blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_2 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_2 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_2 : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_2 : entity is "blk_mem_gen_2,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.9418 mW}";
end blk_mem_gen_2;
architecture STRUCTURE of blk_mem_gen_2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 1;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.9418 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\blk_mem_gen_2blk_mem_gen_v8_2__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(31 downto 0) => dina(31 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(31 downto 0) => NLW_U0_douta_UNCONNECTED(31 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| mit | 2d15973112339c9244b5c0fccb653104 | 0.698678 | 4.085612 | false | false | false | false |
caiopo/mips-multiciclo | src/extensaoSinal.vhd | 1 | 992 | ----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity extensaoSinal is
generic(
larguraOriginal: natural := 8;
larguraExtendida: natural := 8);
port(
entrada: in std_logic_vector(larguraOriginal-1 downto 0);
saida: out std_logic_vector(larguraExtendida-1 downto 0)
);
end entity;
architecture comportamental of extensaoSinal is
begin
saida(larguraOriginal-1 downto 0) <= entrada;
saida(larguraExtendida-1 downto larguraOriginal) <= (others => entrada(larguraOriginal-1));
end architecture;
| mit | c1b88c506650aa40f25bbe264b209862 | 0.571573 | 4.257511 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup_memory.vhd | 1 | 2,413 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 14:22:20
-- Design Name: rx_path_lookup_memory.vhd
-- Module Name: rx_path_lookup_memory - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module contains the lookup memory
-- for details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rx_path_lookup_memory is
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector;
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic;
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end rx_path_lookup_memory;
architecture structural of rx_path_lookup_memory is
component blk_mem_gen_0 is
Port (
--Port A -> Processor
wea : in std_logic_vector;
addra : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
dina : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clka : in std_logic;
--Port B -> Lookup module
enb : in std_logic; --opt port
addrb : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
doutb : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clkb : in std_logic
);
end component;
signal neg_clk : std_logic;
begin
neg_clk <= not mem_out_clk;
lookup_mem_ip : blk_mem_gen_0
PORT MAP (
--Port A
wea => mem_in_wenable,
addra => mem_in_addr,
dina => mem_in_data,
clka => mem_in_clk,
--Port B
enb => mem_out_enable,
addrb => mem_out_addr,
doutb => mem_out_data,
clkb => mem_out_clk
);
end structural;
| mit | 5490f098463362b4a77944ce34ece92c | 0.567758 | 3.413013 | false | false | false | false |
lfmunoz/4dsp_sip_interface | sip_pci_cmd.vhd | 1 | 22,405 | --------------------------------------------------------------------------------
-- file name : sip_pci_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -sip_pci_cmd
-- arch_itecture - arch_sip_pci_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- specify libraries.
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------------------------
-- entity declaration
--------------------------------------------------------------------------------
entity sip_pci_cmd is
port
(
pci_clk :in std_logic; --modle is synchronous to this clock
reset :in std_logic;
--command if
cmd_clk_in :in std_logic;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
fw_cmd_clk : in std_logic;
fw_cmd :out std_logic_vector(31 downto 0);
fw_cmd_val :out std_logic;
fw_incmd :in std_logic_vector(31 downto 0);
fw_incmd_val :in std_logic;
--dma control signals
dma_loop_back_en :out std_logic;
dma_isim_en :out std_logic;
dma_osim_en :out std_logic;
dma_blackhole_en :out std_logic;
dma_data_gen_en :out std_logic;
dma_wr_error :in std_logic;
dma_rd_error :in std_logic;
--register interface
pci_in_data :in std_logic_vector(31 downto 0);--caries the input register data
pci_in_dval :in std_logic; --the input data is valid
pci_wr_addr :in std_logic_vector(8 downto 0); --address for the PCI write
pci_rd_addr :in std_logic_vector(8 downto 0); --address for the PCI read
pci_out_data :out std_logic_vector(31 downto 0);--requested register data is placed on this bus
pci_out_req :in std_logic; --pulse to requested data
pci_mbx_int :out std_logic; --int is asserted upon receipt of an mailbox 2 host
cmd_mbx_int :out std_logic --int is asserted upon receipt of an read ack
);
end entity sip_pci_cmd ;
--------------------------------------------------------------------------------
-- arch_itecture declaration
--------------------------------------------------------------------------------
architecture arch_sip_pci_cmd of sip_pci_cmd is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0";
constant cmd_rd :std_logic_vector(3 downto 0) :=x"2";
constant cmd_wr :std_logic_vector(3 downto 0) :=x"1";
constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4";
--register addresses
constant addr_cmd2pci_lsb :std_logic_vector(8 downto 0) :='0' & x"41"; --register address for the lsb of the command to PCI register
constant addr_cmd2pci_msb :std_logic_vector(8 downto 0) :='0' & x"43"; --register address for the lsb of the command to PCI register
constant addr_pci2cmd_lsb :std_logic_vector(8 downto 0) :='0' & x"40"; --register address for the lsb of the command to PCI register
constant addr_pci2cmd_msb :std_logic_vector(8 downto 0) :='0' & x"42"; --register address for the lsb of the command to PCI register
constant addr_pci_mbx :std_logic_vector(8 downto 0) :='0' & x"0D"; --register address for the PCi mailbox
constant addr_boarddiag1 :std_logic_vector(8 downto 0) :='0' & x"14"; --register address for the lsb of the command to PCI register
constant addr_boarddiag2 :std_logic_vector(8 downto 0) :='0' & x"1E"; --register address for the lsb of the command to PCI register
constant addr_boarddiag3 :std_logic_vector(8 downto 0) :='0' & x"44"; --register address for the lsb of the command to PCI register
constant addr_sourcedest :std_logic_vector(8 downto 0) :='0' & x"0F"; --register address for the lsb of the command to PCI register
constant addr_fwsize :std_logic_vector(8 downto 0) :='0' & x"09"; --register address for the lsb of the command to PCI register
constant addr_userrom :std_logic_vector(8 downto 0) :='0' & x"15"; --register address for the lsb of the command to PCI register
constant addr_ublaze_status :std_logic_vector(8 downto 0) :='0' & x"50"; --register address for the lsb of the command to PCI register
constant addr_ublaze_id :std_logic_vector(8 downto 0) :='0' & x"51"; --register address for the lsb of the command to PCI register
type std2d_32b is array(natural range<>) of std_logic_vector(31 downto 0);
constant nb_regs :integer :=8;
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal registers :std2d_32b(nb_regs-1 downto 0);
signal out_reg :std_logic_vector(31 downto 0):=(others=>'0');
signal out_reg_val :std_logic;
signal out_reg_addr :std_logic_vector(27 downto 0):=(others=>'0');
signal in_reg :std_logic_vector(31 downto 0):=(others=>'0');
signal in_reg_val :std_logic;
signal in_reg_req :std_logic;
signal in_reg_addr :std_logic_vector(27 downto 0):=(others=>'0');
signal out_reg_val_ack :std_logic;
signal wr_ack :std_logic;
signal cmd2pci_reg_lsb :std_logic_vector(31 downto 0):=(others=>'0');
signal cmd2pci_reg_msb :std_logic_vector(63 downto 32):=(others=>'0');
signal pci2cmd_reg_lsb :std_logic_vector(31 downto 0):=(others=>'0');
signal pci2cmd_reg_msb :std_logic_vector(63 downto 32):=(others=>'0');
signal pci_mbx_out_data :std_logic_vector(31 downto 0):=(others=>'0');
signal out_cmd_sig :std_logic_vector(63 downto 0):=(others=>'0');
signal in_cmd_reg :std_logic_vector(63 downto 0):=(others=>'0');
signal out_cmd_val_sig :std_logic;
signal int_out_cmd :std_logic_vector(63 downto 0):=(others=>'0');
--signal fw_cmd_sig :std_logic_vector(63 downto 0);
--signal fw_cmd_val_sig :std_logic;
signal int_out_cmd_val :std_logic;
signal in_reg_addr_sig :std_logic_vector(27 downto 0):=(others=>'0');
signal cmd_always_ack : std_logic;
signal in_cmd_val_pciclk :std_logic;
--signal fw_cmd_val_sig_pipe :std_logic_vector(15 downto 0);
--signal fw_cmd_select :std_logic;
signal board_diagnostics1 :std_logic_vector(31 downto 0);
signal board_diagnostics2 :std_logic_vector(31 downto 0);
signal board_diagnostics3 :std_logic_vector(31 downto 0);
signal userrom :std_logic_vector(31 downto 0);
signal ublaze_status :std_logic_vector(31 downto 0);
signal ublaze_id :std_logic_vector(31 downto 0);
signal cmd_addr :std_logic_vector(27 downto 0);
signal cmd_cmd :std_logic_vector(3 downto 0);
--signal fw_cmd_val_pci_clk :std_logic;
--signal fw_incmd_val_pciclk :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end component;
--********************************************************************************
begin
--********************************************************************************
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map
(
in_clk =>cmd_clk_in ,
out_clk =>pci_clk,
rst =>reset,
pulsein =>in_cmd_val ,
inbusy =>open,
pulseout =>in_cmd_val_pciclk
);
p2p1: pulse2pulse
port map
(
in_clk =>pci_clk,
out_clk =>cmd_clk_in,
rst =>reset,
pulsein =>out_cmd_val_sig ,
inbusy =>open,
pulseout =>out_cmd_val
);
--p2p2: pulse2pulse
--port map
-- (
-- in_clk =>pci_clk,
-- out_clk =>fw_cmd_clk,
-- rst =>reset,
-- pulsein =>fw_cmd_val_pci_clk ,
-- inbusy =>open,
-- pulseout =>fw_cmd_val
-- );
--p2p3: pulse2pulse
--port map
-- (
-- in_clk =>fw_cmd_clk ,
-- out_clk =>pci_clk,
-- rst =>reset,
-- pulsein =>fw_incmd_val ,
-- inbusy =>open,
-- pulseout =>fw_incmd_val_pciclk
-- );
--
i_stellar_cmd: entity work.stellar_cmd
generic map (
start_addr =>x"0000000",
stop_addr =>x"0000007"
)
port map (
reset =>reset,
--command if
clk_cmd =>pci_clk,
out_cmd =>int_out_cmd,
out_cmd_val =>int_out_cmd_val,
in_cmd =>out_cmd_sig,
in_cmd_val =>out_cmd_val_sig,
cmd_always_ack =>cmd_always_ack,
--register interface
clk_reg =>pci_clk,
out_reg =>out_reg,
out_reg_val_ack =>out_reg_val_ack,
out_reg_val =>out_reg_val,
out_reg_addr =>out_reg_addr,
in_reg =>in_reg,
wr_ack =>wr_ack,
in_reg_val =>in_reg_val,
in_reg_req =>in_reg_req,
in_reg_addr =>in_reg_addr,
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
pci_in_proc: process(pci_clk )
begin
if(pci_clk'event and pci_clk='1') then
--register lsb of the command packet
if (pci_in_dval = '1' and pci_wr_addr =addr_pci2cmd_lsb ) then
pci2cmd_reg_lsb <= pci_in_data;
end if;
--register msb of the command packet
if (pci_in_dval = '1' and pci_wr_addr =addr_pci2cmd_msb ) then
pci2cmd_reg_msb <= pci_in_data;
out_cmd_sig <= pci_in_data & pci2cmd_reg_lsb;
end if;
------if(pci_in_dval='1' and pci_wr_addr=addr_boarddiag1) then --board info 1
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(0, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(pci_in_dval='1' and pci_wr_addr=addr_boarddiag2) then --board info 2
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(1, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(pci_in_dval='1' and pci_wr_addr=addr_boarddiag3) then --board info 3
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(2, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(pci_in_dval='1' and pci_wr_addr=addr_sourcedest) then --source destination updated
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(3, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(pci_in_dval='1' and pci_wr_addr=addr_fwsize) then --FW update size
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(4, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(pci_in_dval='1' and pci_wr_addr=addr_userrom) then --user rom
------ fw_cmd_sig <= cmd_wr & conv_std_logic_vector(5, 28) & pci_in_data;
------ fw_cmd_val_sig <= '1';
------elsif(fw_cmd_val_sig_pipe(14)='1') then --the seccond part of the cmd packet
------ fw_cmd_sig <= fw_cmd_sig(31 downto 0) & fw_cmd_sig(63 downto 32);
------else
------ fw_cmd_val_sig <= '0';
------end if;
------
------fw_cmd_val_sig_pipe <= fw_cmd_val_sig_pipe(14 downto 0) & fw_cmd_val_sig;
------
------
--transmit the command upon receipt of the msb
if (pci_in_dval = '1' and pci_wr_addr =addr_pci2cmd_msb ) then
out_cmd_val_sig <= '1';
else
out_cmd_val_sig <= '0';
end if;
end if;
end process;
int_proc: process(pci_clk, reset )
begin
if(pci_clk'event and pci_clk='1') then
if (reset='1') then
pci_mbx_out_data <=(others=>'0');
pci_mbx_int <='0';
cmd2pci_reg_lsb <=(others=>'0');
cmd2pci_reg_msb <=(others=>'0');
cmd_mbx_int <= '0';
--fw_cmd_select <= '0';
--ublaze_status <=(others=>'0');
--ublaze_id <=(others=>'0');
--board_diagnostics3 <=(others=>'0');
--userrom <=(others=>'0');
cmd_addr <=(others=>'0');
cmd_cmd <=(others=>'0');
else
--when we receive a mailbox command packet we need to write to the FPGA to PCI mailbox register
--this will cause a mailbox interrupt to the host.
if (in_cmd_val_pciclk = '1' and in_cmd_reg(63 downto 60) = cmd_mbx ) then
pci_mbx_out_data <= in_cmd_reg(31 downto 0);
elsif (int_out_cmd_val = '1' and int_out_cmd(63 downto 60) = cmd_mbx ) then
pci_mbx_out_data <= int_out_cmd(31 downto 0);
end if;
if (in_cmd_val_pciclk = '1' and in_cmd_reg(63 downto 60) = cmd_mbx ) then
pci_mbx_int <='1';
elsif (int_out_cmd_val = '1' and int_out_cmd(63 downto 60) = cmd_mbx ) then
pci_mbx_int <='1';
elsif (pci_out_req = '1' and pci_rd_addr =addr_pci_mbx ) then
pci_mbx_int <='0';
end if;
--when we receive another packet we will interrupt the host to come and read the packet
if (in_cmd_val_pciclk = '1' and in_cmd_reg(63 downto 60) /= cmd_mbx ) then
cmd_mbx_int <= '1';
elsif (int_out_cmd_val = '1' and int_out_cmd(63 downto 60) /= cmd_mbx ) then
cmd_mbx_int <= '1';
elsif (pci_out_req = '1' and pci_rd_addr =addr_cmd2pci_lsb ) then
cmd_mbx_int <= '0';
end if;
if (in_cmd_val_pciclk = '1' and in_cmd_reg(63 downto 60) /= cmd_mbx ) then
cmd2pci_reg_msb <= in_cmd_reg(63 downto 32);
cmd2pci_reg_lsb <= in_cmd_reg(31 downto 0);
elsif (int_out_cmd_val = '1' and int_out_cmd(63 downto 60) /= cmd_mbx ) then
cmd2pci_reg_msb <= int_out_cmd(63 downto 32);
cmd2pci_reg_lsb <= int_out_cmd(31 downto 0);
end if;
-- --receive the flash status registers
-- if (fw_incmd_val_pciclk='1')then
-- fw_cmd_select <= not fw_cmd_select;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 0 and cmd_cmd= cmd_wr)then
-- board_diagnostics1 <= fw_incmd;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 1 and cmd_cmd= cmd_wr)then
-- board_diagnostics2 <= fw_incmd;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 2 and cmd_cmd= cmd_wr)then
-- board_diagnostics3 <= fw_incmd;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 5 and cmd_cmd= cmd_wr)then
-- userrom <= fw_incmd;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 6 and cmd_cmd= cmd_wr)then
-- ublaze_status <= fw_incmd;
-- end if;
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='1' and cmd_addr = 7 and cmd_cmd= cmd_wr)then
-- ublaze_id <= fw_incmd;
-- end if;
--
--
-- if (fw_incmd_val_pciclk='1' and fw_cmd_select ='0' )then
-- cmd_addr <= fw_incmd(27 downto 0);
-- cmd_cmd <= fw_incmd(31 downto 28);
-- end if;
end if;
end if;
end process;
in_reg_proc: process(pci_clk, reset )
begin
if(pci_clk'event and pci_clk='1') then
if (reset = '1') then
for i in 0 to nb_regs-1 loop
registers(i) <= (others=>'0');
wr_ack <= '0';
end loop;
else
-- Write acknowledge
if (out_reg_val_ack = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
for i in 0 to nb_regs-1 loop
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = i) then
registers(i) <= out_reg;
end if;
end loop;
--assign default values
registers(0) <=x"BEEFDEAF";
registers(1) <=x"DEADBEEF";
registers(2) <=x"01234567";
--acknoledge the requested register
in_reg_val <= in_reg_req;
registers(3)(5) <= dma_wr_error;
registers(3)(6) <= dma_rd_error;
end if;
end if;
end process;
cmd_reg_proc: process(cmd_clk_in )
begin
if(cmd_clk_in'event and cmd_clk_in='1') then
if(in_cmd_val = '1') then
in_cmd_reg <= in_cmd;
end if;
end if;
end process;
cmd_reg2_proc: process(pci_clk )
begin
if(pci_clk'event and pci_clk='1') then
if(out_cmd_val_sig = '1') then
out_cmd <= out_cmd_sig;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
outmux_proc: process(cmd2pci_reg_lsb, pci_rd_addr)
begin
case pci_rd_addr is
when addr_cmd2pci_lsb => pci_out_data <= cmd2pci_reg_lsb;
when addr_cmd2pci_msb => pci_out_data <= cmd2pci_reg_msb;
when addr_pci2cmd_lsb => pci_out_data <= pci2cmd_reg_lsb;
when addr_pci2cmd_msb => pci_out_data <= pci2cmd_reg_msb;
when addr_pci_mbx => pci_out_data <= pci_mbx_out_data;
--when addr_boarddiag1 => pci_out_data <= board_diagnostics1(31 downto 8) & x"10" ;--hard code CPLD version to 1.0
--when addr_boarddiag2 => pci_out_data <= board_diagnostics2;
--when addr_boarddiag3 => pci_out_data <= board_diagnostics3;
--when addr_userrom => pci_out_data <= userrom;
--when addr_ublaze_status => pci_out_data <= ublaze_status;
--when addr_ublaze_id => pci_out_data <= ublaze_id;
when others => pci_out_data <= pci2cmd_reg_msb;
end case;
end process;
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
--map the requested register register
in_reg <= registers(conv_integer(in_reg_addr));
--fw_cmd <= fw_cmd_sig(31 downto 0);
--fw_cmd_val_pci_clk <= fw_cmd_val_sig or fw_cmd_val_sig_pipe(15);
dma_loop_back_en <= registers(3)(0);
dma_isim_en <= registers(3)(1);
dma_osim_en <= registers(3)(2);
dma_blackhole_en <= registers(3)(3);
dma_data_gen_en <= registers(3)(4);
cmd_always_ack <= registers(3)(7);
end architecture arch_sip_pci_cmd ; -- of sip_pci_cmd
| mit | d20d5c29954e8a6f0f96f54eaa0ccf3b | 0.489712 | 3.53224 | false | false | false | false |
lennartbublies/ecdsa | src/tld_ecdsa_package.vhd | 1 | 5,351 | ----------------------------------------------------------------------------------------------------
-- TOP LEVEL ENTITY - ECDSA
-- FPGA implementation of ECDSA algorithm
--
-- Constants:
-- M - Galois field base GF(p=2^M)
-- P - Number of element in GF(p=2^M)
-- logM - Helper for M
-- N - N part of ECC curve
-- A - A part of ECC curve
-- U - Length of UART input/output
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 02.07.2017
-- Last Change: 17.11.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) ecdsa package
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
PACKAGE tld_ecdsa_package IS
-- Elliptic curve parameter of sect163k1 and generated private and public key
-- See http://www.secg.org/SEC2-Ver-1.0.pdf for more information
-- 163 Bit sect163k1
CONSTANT M: natural := 163;
CONSTANT logM: integer := 9;--logM IS the number of bits of m plus an additional sign bit
CONSTANT N: std_logic_vector(M DOWNTO 0) := x"800000000000000000000000000000000000000C9";
--CONSTANT N: std_logic_vector(M DOWNTO 0) := x"4000000000000000000020108A2E0CC0D99F8A5EF";
CONSTANT P: std_logic_vector(M DOWNTO 0) := x"800000000000000000000000000000000000000C9";
CONSTANT A: std_logic_vector(M-1 downto 0) := (0 => '1', OTHERS=>'0');
-- Set parameter of sect163k1
CONSTANT xG: std_logic_vector(M-1 DOWNTO 0) := "010" & x"FE13C0537BBC11ACAA07D793DE4E6D5E5C94EEE8";
CONSTANT yG: std_logic_vector(M-1 DOWNTO 0) := "010" & x"89070FB05D38FF58321F2E800536D538CCDAA3D9";
CONSTANT k: std_logic_vector(M-1 DOWNTO 0) := "000" & x"CD06203260EEE9549351BD29733E7D1E2ED49D88";
-- VDHL point multiplication version 1 - original from C
--CONSTANT dA: std_logic_vector(M-1 DOWNTO 0) := "101" & x"4E78BA70719678AFC09BA25E822B81FCF23B87CA";
--CONSTANT xQB: std_logic_vector(M-1 DOWNTO 0) := "110" & x"D4845314B7851DA63B9569E812A6602A22493216";
--CONSTANT yQB: std_logic_vector(M-1 DOWNTO 0) := "000" & x"0D5B712A2981DD2FB1AFA15FE4079C79A3724BB0";
-- VDHL point multiplication version 2
CONSTANT dA: std_logic_vector(M-1 DOWNTO 0) := "000" & x"CD06203260EEE9549351BD29733E7D1E2ED49D88";
CONSTANT xQB: std_logic_vector(M-1 DOWNTO 0) := "000" & x"06E24E8B2B34F45098730E20100D52121AE91873";
CONSTANT yQB: std_logic_vector(M-1 DOWNTO 0) := "001" & x"5B1340F838650657125A796EBB6B67CDBE442048";
--CONSTANT dA: std_logic_vector(M-1 DOWNTO 0) := "101" & x"4E78BA70719678AFC09BA25E822B81FCF23B87CA";
--CONSTANT xQB: std_logic_vector(M-1 DOWNTO 0) := "010" & x"97677AE929EE458EB7D1945E964194E9152A69D5";
--CONSTANT yQB: std_logic_vector(M-1 DOWNTO 0) := "110" & x"9A4C4A2DB7725B9DE1485B8C5EF89E4BD540AE6F";
-- 9 Bit testcurve
--CONSTANT M: natural := 9;
--CONSTANT logM: integer := 5;
--CONSTANT N: std_logic_vector(M downto 0) := "1000000011";
--CONSTANT P: std_logic_vector(M downto 0) := "1000000011";
--CONSTANT A: std_logic_vector(M-1 downto 0) := (0 => '1', OTHERS=>'0');
--CONSTANT xG: std_logic_vector(M-1 DOWNTO 0) := "011101110";
--CONSTANT yG: std_logic_vector(M-1 DOWNTO 0) := "010101111";
--CONSTANT P: std_logic_vector(M-1 DOWNTO 0) := "000000000";
--CONSTANT dA: std_logic_vector(M-1 DOWNTO 0) := "000111110";
--CONSTANT xQB: std_logic_vector(M-1 DOWNTO 0) := "011000101";
--CONSTANT yQB: std_logic_vector(M-1 DOWNTO 0) := "111011010";
--CONSTANT k: std_logic_vector(M-1 DOWNTO 0) := "001101001";
-- UART
CONSTANT U: natural := 8;
CONSTANT BAUD_RATE: INTEGER RANGE 1200 TO 500000 := 9600;
-- Other
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ONES: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'1');
CONSTANT ONE: std_logic_vector(M downto 0) := (0 => '1', OTHERS=>'0');
-- Types for reduction matrix
TYPE matrix_reduction_return IS ARRAY (0 TO M-1) OF STD_LOGIC_VECTOR(M-2 DOWNTO 0);
SUBTYPE matrix_reduction_arg IS STD_LOGIC_VECTOR(M-1 DOWNTO 0);
-- Functions
FUNCTION reduction_matrix(MODULO: matrix_reduction_arg) RETURN matrix_reduction_return;
END tld_ecdsa_package;
PACKAGE BODY tld_ecdsa_package IS
FUNCTION reduction_matrix(MODULO: matrix_reduction_arg) RETURN matrix_reduction_return IS
VARIABLE R: matrix_reduction_return;
BEGIN
-- Initialise matrix
FOR j IN 0 TO M-1 LOOP
FOR i IN 0 TO M-2 LOOP
R(j)(i) := '0';
END LOOP;
END LOOP;
-- Copy polynomial
FOR j IN 0 TO M-1 LOOP
R(j)(0) := MODULO(j);
END LOOP;
-- Compute lookup table
FOR i IN 1 TO M-2 LOOP
FOR j IN 0 TO M-1 LOOP
IF j = 0 THEN
R(j)(i) := R(M-1)(i-1) and R(j)(0);
ELSE
R(j)(i) := R(j-1)(i-1) xor (R(M-1)(i-1) and R(j)(0));
END IF;
END LOOP;
END LOOP;
RETURN R;
END reduction_matrix;
END tld_ecdsa_package;
| gpl-3.0 | 586448b3f6332872c1ec4b2327fab483 | 0.59858 | 3.250911 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/LUTROM/simulation/LUTROM_tb.vhd | 1 | 4,343 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: LUTROM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUTROM_tb IS
END ENTITY;
ARCHITECTURE LUTROM_tb_ARCH OF LUTROM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
LUTROM_synth_inst:ENTITY work.LUTROM_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | d1fae669c55811aba48f13098a74f63e | 0.619388 | 4.664876 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/sim/fifo_generator_3.vhd | 1 | 33,444 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_3 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_3;
ARCHITECTURE fifo_generator_3_arch OF fifo_generator_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_3_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 31,
C_PROG_FULL_THRESH_NEGATE_VAL => 30,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_3_arch;
| mit | e61856cbaad43a809f927da1dad98774 | 0.607045 | 3.070792 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_interleaved_mult.vhd | 1 | 7,820 | ----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Interleaved Multiplier
-- Computes the polynomial multiplication a*b mod F IN GF(2**M) (LSB first)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- a_i - First input value
-- b_i - Seccond input value
-- z_o - Output value
-- ready_o - Ready flag after computation
--
-- Example:
-- (x^2+x+1)*(x^2+1) = x^4+x^3+x+1
-- 1 1 1 * 1 0 1 = 11011 (bit-shift and XOR, shifts 2*M-2 bits)
--
-- BIT-SHIFT and XOR:
-- 11100 <- [1] 0 1 shift 2 bits
-- 111 <- 1 0 [1] shift 0 bits
-- 11011 <- XOR result
--
-- -> Result has more then M bits, so we've to reduce it by irreducible polynomial like 1011
-- 11011
-- 1011 <- shift 1 bits (degree 4 - degree 3)
-- 1101 <- shift 0 bits (degree 3 - degree 3)
-- 1011
-- 110
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/interleaved_mult.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
-----------------------------------
-- GF(2^M) interleaved MSB-first multipication data path
-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_interleaved_data_path IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
-- Clock and reset signals
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Input signals
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Load input, shift right and ???
inic_i: IN std_logic;
shiftr_i: IN std_logic;
cec_i: IN std_logic;
-- Output signals
z_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END e_gf2m_interleaved_data_path;
ARCHITECTURE rtl OF e_gf2m_interleaved_data_path IS
-- Internal signals
SIGNAL aa, bb, cc: std_logic_vector(M-1 DOWNTO 0);
SIGNAL new_a, new_c: std_logic_vector(M-1 DOWNTO 0);
BEGIN
-- Register and multiplexer
register_a: PROCESS(clk_i, rst_i)
BEGIN
IF rst_i = '1' THEN
aa <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF inic_i = '1' THEN
-- Load register a
aa <= a_i;
ELSE
-- Override register a with ???
aa <= new_a;
END IF;
END IF;
END PROCESS register_a;
shift_register_b: PROCESS(clk_i, rst_i)
BEGIN
IF rst_i = '1' THEN
bb <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF inic_i = '1' THEN
-- Load register b
bb <= b_i;
END IF;
IF shiftr_i = '1' THEN
-- Shift input of register b
bb <= '0' & bb(M-1 DOWNTO 1);
END IF;
END IF;
END PROCESS shift_register_b;
register_c: PROCESS(inic_i, clk_i, rst_i)
BEGIN
IF inic_i = '1' or rst_i = '1' THEN
cc <= (OTHERS => '0');
ELSIF clk_i'event and clk_i = '1' THEN
IF cec_i = '1' THEN
-- Set output register
cc <= new_c;
END IF;
END IF;
END PROCESS register_c;
-- Calculate next value for register a and c
new_a(0) <= aa(M-1) and MODULO(0);
new_a_calc: FOR i IN 1 TO M-1 GENERATE
new_a(i) <= aa(i-1) xor (aa(M-1) and MODULO(i));
END GENERATE;
new_c_calc: FOR i IN 0 TO M-1 GENERATE
new_c(i) <= cc(i) xor (aa(i) and bb(0));
END GENERATE;
-- Set output
z_o <= cc;
END rtl;
-----------------------------------
-- GF(2^M) interleaved multiplication
-----------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0) := ONE(M-1 DOWNTO 0)
);
PORT (
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_interleaved_multiplier;
ARCHITECTURE rtl OF e_gf2m_interleaved_multiplier IS
-- Import entity e_gf2m_interleaved_data_path
COMPONENT e_gf2m_interleaved_data_path IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
inic_i: IN std_logic;
shiftr_i: IN std_logic;
cec_i: IN std_logic;
z_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL inic, shiftr, cec: std_logic;
SIGNAL count: natural RANGE 0 TO M;
-- Define all available states
type states IS RANGE 0 TO 3;
SIGNAL current_state: states;
BEGIN
-- Instantiate interleaved data path
-- Used to computes the polynomial multiplication mod F in one step
data_path: e_gf2m_interleaved_data_path GENERIC MAP (
MODULO => MODULO
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
a_i => a_i,
b_i => b_i,
inic_i => inic,
shiftr_i => shiftr,
cec_i => cec,
z_o => z_o
);
-- Clock signals
counter: PROCESS(rst_i, clk_i)
BEGIN
IF rst_i = '1' THEN
count <= 0;
ELSIF clk_i' event and clk_i = '1' THEN
-- Shift until all input bits are proceeds
IF inic = '1' THEN
count <= 0;
ELSIF shiftr = '1' THEN
count <= count+1;
END IF;
END IF;
END PROCESS counter;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2 : Load input arguments (initialize registers)
-- 3 : Shift and add
CASE current_state IS
WHEN 0 TO 1 => inic <= '0'; shiftr <= '0'; cec <= '0'; ready_o <= '1';
WHEN 2 => inic <= '1'; shiftr <= '0'; cec <= '0'; ready_o <= '0';
WHEN 3 => inic <= '0'; shiftr <= '1'; cec <= '1'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF count = M-1 THEN
current_state <= 0;
END IF;
END CASE;
END IF;
END PROCESS control_unit;
END rtl; | gpl-3.0 | 02c5880818c8e5d811fac56c6978f95b | 0.478005 | 3.632141 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/DAQ_MEM/simulation/DAQ_MEM_tb.vhd | 1 | 4,511 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: DAQ_MEM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY DAQ_MEM_tb IS
END ENTITY;
ARCHITECTURE DAQ_MEM_tb_ARCH OF DAQ_MEM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
DAQ_MEM_synth_inst:ENTITY work.DAQ_MEM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | ebc2a8f68057c81b9c547498e3f5784e | 0.61472 | 4.575051 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/fifo.vhd | 1 | 2,062 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity Fifo is
Generic (
constant DATA_WIDTH : positive := 64;
constant DEPTH : positive := 200
);
Port (
clk : in STD_LOGIC;
rst_n : in STD_LOGIC;
data_in_en : in STD_LOGIC;
data_in_data : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
data_in_wait : out STD_LOGIC;
data_out_en : in STD_LOGIC;
data_out_data : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
data_out_wait : out STD_LOGIC
);
end Fifo;
architecture Behavioral of Fifo is
begin
-- Memory Pointer Process
fifo_proc : process (clk)
type FIFO_Memory is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
variable Memory : FIFO_Memory;
variable Head : natural range 0 to DEPTH - 1;
variable Tail : natural range 0 to DEPTH - 1;
variable Looped : boolean;
begin
if rising_edge(clk) then
if rst_n = '0' then
Head := 0;
Tail := 0;
Looped := false;
data_in_wait <= '0';
data_out_wait <= '1';
else
if (data_out_en = '1') then
if ((Looped = true) or (Head /= Tail)) then
-- Update data output
data_out_data <= Memory(Tail);
-- Update Tail pointer as needed
if (Tail = DEPTH - 1) then
Tail := 0;
Looped := false;
else
Tail := Tail + 1;
end if;
end if;
end if;
if (data_in_en = '1') then
if ((Looped = false) or (Head /= Tail)) then
-- Write Data to Memory
Memory(Head) := data_in_data;
-- Increment Head pointer as needed
if (Head = DEPTH - 1) then
Head := 0;
Looped := true;
else
Head := Head + 1;
end if;
end if;
end if;
-- Update Empty and Full flags
if (Head = Tail) then
if Looped then
data_in_wait <= '1';
else
data_out_wait <= '1';
end if;
else
data_out_wait <= '0';
data_in_wait <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 4e5db731597269aec041f30c1b56bdc0 | 0.550436 | 3.019034 | false | false | false | false |
titto-thomas/Pipeline_RISC | alu16.vhdl | 1 | 2,213 | ----------------------------------------
-- ALU : IITB-RISC
-- Author : Sainath
-- Date : 18/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu16 is
port (
operand1 : in std_logic_vector(15 downto 0); -- 16 std_logic input1
operand2 : in std_logic_vector(15 downto 0); -- 16 std_logic input2
op_code : in std_logic; -- 1 std_logic opcode
result : out std_logic_vector(15 downto 0); -- 16 std_logic ALU result
carry : out std_logic; -- carry flag
zero : out std_logic; -- zero flag
alu_equ : out std_logic -- comparator output
);
end alu16;
--------------------------------Architecture-----------------------------------------------
architecture code of alu16 is
signal result_dummy : std_logic_vector(16 downto 0) := X"0000" & '0';
begin -- behave
result <= result_dummy(15 downto 0);
carry <= result_dummy(16);
ALU : process (operand1, operand2, op_code)
begin
---------- OPCODE for ADDITION operation ---------------------
if(op_code='0') then
result_dummy <= std_logic_vector(unsigned('0' & operand1) + unsigned('0' & operand2));
---------- OPCODE for NAND operation ---------------------
elsif(op_code='1') then
for i in 0 to 15 loop
result_dummy(i) <= operand1(i) nand operand2(i);
end loop;
result_dummy(16) <= '0';
end if;
--------------------------------------------------------------------
end process ALU;
Equality_Check : process(operand1, operand2)
begin
if( operand1 = operand2 ) then -- to set comparator output
alu_equ <= '1';
else
alu_equ <= '0';
end if;
end process Equality_Check;
Zero_Check : process(result_dummy, op_code)
begin
if( result_dummy(15 downto 0) = X"0000" and op_code = '0' ) then -- to set comparator output
zero <= '1';
else
zero <= '0';
end if;
end process Zero_Check;
end code;
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
| gpl-2.0 | e98cb8d11c4bf1e1e676fee27e075e5b | 0.473565 | 3.706868 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/synth/fifo_generator_2.vhd | 1 | 38,505 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_2 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(88 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(88 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_2;
ARCHITECTURE fifo_generator_2_arch OF fifo_generator_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_2_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(88 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(88 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_2_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_2_arch : ARCHITECTURE IS "fifo_generator_2,fifo_generator_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_2_arch: ARCHITECTURE IS "fifo_generator_2,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=89,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=89,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 89,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 89,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_2_arch;
| mit | 371945291fd70279c86538e32209928a | 0.628256 | 2.920143 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/DAQ_MEM/simulation/DAQ_MEM_synth.vhd | 1 | 8,879 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DAQ_MEM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY DAQ_MEM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE DAQ_MEM_synth_ARCH OF DAQ_MEM_synth IS
COMPONENT DAQ_MEM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 14,
READ_WIDTH => 7 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: DAQ_MEM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| gpl-3.0 | 805e7bffcdf5ce140c7daf025aa0f4ce | 0.567969 | 3.586026 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_axi_pat_check.vhd | 1 | 17,110 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_pat_check.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: A simple pattern checker - expects the same data pattern as generated by the pat_gen
-- with the same DA/SA order (it is expected that the frames will pass through
-- two address swap blocks). the checker will first sync to the data and then
-- identify any errors (this is a sticky output but the internal signal is
-- per byte)
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_axi_pat_check is
generic (
DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405";
SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405";
MAX_SIZE : unsigned(11 downto 0) := X"1f4";
MIN_SIZE : unsigned(11 downto 0) := X"040";
ENABLE_VLAN : boolean := false;
VLAN_ID : bit_vector(11 downto 0) := X"002";
VLAN_PRIORITY : bit_vector(2 downto 0) := "010"
);
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
enable_pat_chk : in std_logic;
speed : in std_logic_vector(1 downto 0);
tdata : in std_logic_vector(7 downto 0);
tvalid : in std_logic;
tlast : in std_logic;
tready : in std_logic;
tuser : in std_logic;
frame_error : out std_logic;
activity_flash : out std_logic
);
end tri_mode_ethernet_mac_0_axi_pat_check;
architecture rtl of tri_mode_ethernet_mac_0_axi_pat_check is
-- State machine
type state_typ is (IDLE,
INFO,
LOOK,
PKT);
function Sel (Cond : boolean; A,B : integer) return integer is
begin
if Cond then
return A;
else
return B;
end if;
end function Sel;
-- work out the adjustment required to get the right packet size.
constant PKT_ADJUST : integer := Sel(ENABLE_VLAN,22,18);
-- generate the vlan fields
constant VLAN_HEADER : bit_vector(31 downto 0) := X"8100" & VLAN_PRIORITY & '0' & VLAN_ID;
-- generate the require header count compare
constant HEADER_LENGTH : integer := Sel(ENABLE_VLAN,15,11);
signal errored_data : std_logic;
signal errored_addr_data : std_logic;
signal errored_swap_data : std_logic;
signal lut_data : std_logic_vector(7 downto 0);
signal lut_swap_data : std_logic_vector(7 downto 0);
signal expected_data : unsigned(7 downto 0) := (others => '0');
signal packet_size : unsigned(15 downto 0) := (others => '0');
signal packet_count : unsigned(4 downto 0) := (others => '0');
signal next_rx_state : state_typ;
signal rx_state : state_typ;
signal maybe_frame_error : std_logic;
signal frame_error_int : std_logic;
signal frame_activity_count: unsigned(15 downto 0) := (others => '0');
signal sm_active : std_logic;
constant dummy : bit_vector(47 downto 0) := (others => '0');
begin
-- link flasher to a bit of the counter depending upon the speed to give a good flash rate
activity_flash <= frame_activity_count(15) when speed(1) = '1' else
frame_activity_count(13) when speed(0) = '1' else frame_activity_count(11);
frame_error <= frame_error_int when sm_active = '1' else '0';
-- we need a way to confirm data has been received to ensure that if no data is received it is
-- flagged as an error
active_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
sm_active <= '0';
elsif rx_state = PKT then
sm_active <= '1';
end if;
end if;
end process active_p;
-- the pattern checker is a slave in all respects so has to look for ackowledged data
-- the first and 6 bytes of data are compared against the first byte of DEST_ADDR and SCR_ADDR
-- to allow for address swaps being removed
-- a simple state machine will keep track of the packet position
next_s : process(rx_state, tlast, tvalid, tready, tuser, enable_pat_chk, maybe_frame_error)
begin
next_rx_state <= rx_state;
case rx_state is
-- cannot simply look for a rise on valid have to see a last first so
-- we know the next asserted valid is new data
when IDLE =>
if tlast = '1' and tvalid = '1' and tready = '1' and enable_pat_chk = '1' then
next_rx_state <= INFO;
end if;
-- since we don't know where the packet gen will be rx a frame to enable
-- packet size to be initialised
when INFO =>
if tlast = '1' and tvalid = '1' and tready = '1' and tuser = '0' then
next_rx_state <= LOOK;
end if;
-- have seen a last so now look for a start
when LOOK =>
if tlast = '0' and tvalid = '1' and tready = '1' then
next_rx_state <= PKT;
end if;
-- rxd first byte of packet - now stay in this state until we see a last
when PKT =>
if enable_pat_chk = '0' then
next_rx_state <= IDLE;
elsif tlast = '1' and tvalid = '1' and tready = '1' then
if tuser = '0' and maybe_frame_error = '1' then
next_rx_state <= IDLE;
else
next_rx_state <= LOOK;
end if;
end if;
end case;
end process;
state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
rx_state <= IDLE;
else
rx_state <= next_rx_state;
end if;
end if;
end process state_p;
result_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if rx_state = PKT and next_rx_state = LOOK then
if tuser = '0' then
if ENABLE_VLAN then
if errored_addr_data = '1' then
assert false
report "VLAN Frame PASSED. DA/SA swapped" & cr
severity note;
else
assert false
report "VLAN Frame PASSED." & cr
severity note;
end if;
else
if errored_addr_data = '1' then
assert false
report "Frame PASSED. DA/SA swapped" & cr
severity note;
else
assert false
report "Frame PASSED." & cr
severity note;
end if;
end if;
end if;
end if;
end if;
end process result_p;
-- now need a counter for packet size and packet position AND data
pkt_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
packet_count <= (others => '0');
else
if tlast = '1' then
packet_count <= (others => '0');
elsif (next_rx_state = PKT or rx_state = PKT or rx_state = INFO) and tvalid = '1' and
tready = '1' and packet_count(4 downto 3) /= "11" then
packet_count <= packet_count + "00001";
end if;
end if;
end if;
end process pkt_count_p;
-- need to get packet size info
-- this is first initialised during the info state (the assumption being that
-- the generate sends incrementing packet sizes (wrapping at MAX_SIZE)
pkt_size_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if rx_state = INFO and packet_count = (HEADER_LENGTH+1) and tvalid = '1' and tready = '1' then
packet_size(15 downto 8) <= unsigned(tdata);
elsif rx_state = INFO and packet_count = (HEADER_LENGTH+2) and tvalid = '1' and tready = '1' then
packet_size(7 downto 0) <= unsigned(tdata);
-- when in the LOOK state we want to update the packet size to the next expected
elsif rx_state /= LOOK and next_rx_state = LOOK and tuser = '0' then
if packet_size(11 downto 0) = MAX_SIZE - PKT_ADJUST then
packet_size <= X"0" & (MIN_SIZE - PKT_ADJUST);
else
packet_size <= packet_size + X"0001";
end if;
end if;
end if;
end process pkt_size_p;
exp_data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if rx_state = LOOK and next_rx_state = PKT then
expected_data <= packet_size(7 downto 0);
elsif rx_state = PKT and packet_count >= (HEADER_LENGTH+3) and tvalid = '1' and tready = '1' then
expected_data <= expected_data - X"01";
end if;
end if;
end process exp_data_p;
-- store the parametised values in a lut (64 deep)
-- this should mean the values could be adjusted in fpga_editor etc..
LUT6_gen : for I in 0 to 7 generate
begin
LUT6_inst : LUT6
generic map (
INIT => dummy &
VLAN_HEADER(i) &
VLAN_HEADER(i+8) &
VLAN_HEADER(i+16) &
VLAN_HEADER(i+24) &
SRC_ADDR(I) &
SRC_ADDR(I+8) &
SRC_ADDR(I+16) &
SRC_ADDR(I+24) &
SRC_ADDR(I+32) &
SRC_ADDR(I+40) &
DEST_ADDR(I) &
DEST_ADDR(I+8) &
DEST_ADDR(I+16) &
DEST_ADDR(I+24) &
DEST_ADDR(I+32) &
DEST_ADDR(I+40)
)
port map (
O => lut_data(I),
I0 => packet_count(0),
I1 => packet_count(1),
I2 => packet_count(2),
I3 => packet_count(3),
I4 => '0',
I5 => '0'
);
LUT6_swap_inst : LUT6
generic map (
INIT => dummy &
VLAN_HEADER(i) &
VLAN_HEADER(i+8) &
VLAN_HEADER(i+16) &
VLAN_HEADER(i+24) &
DEST_ADDR(I) &
DEST_ADDR(I+8) &
DEST_ADDR(I+16) &
DEST_ADDR(I+24) &
DEST_ADDR(I+32) &
DEST_ADDR(I+40) &
SRC_ADDR(I) &
SRC_ADDR(I+8) &
SRC_ADDR(I+16) &
SRC_ADDR(I+24) &
SRC_ADDR(I+32) &
SRC_ADDR(I+40)
)
port map (
O => lut_swap_data(I),
I0 => packet_count(0),
I1 => packet_count(1),
I2 => packet_count(2),
I3 => packet_count(3),
I4 => '0',
I5 => '0'
);
end generate;
-- we do not know if the address will be swapped or not so check for both - if either pass
-- then this field is ok (assumption being that an address swap cannot be performed by mistake.)
-- errored_data is high on the cycle after a mismatch and stays high until the end of frame
error_addr_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
errored_addr_data <= '0';
elsif tlast = '1' and tvalid = '1' and tready = '1' then
errored_addr_data <= '0';
elsif packet_count <= HEADER_LENGTH and tvalid = '1' and tready = '1' and tuser = '0' then
if lut_data /= tdata then
errored_addr_data <= '1';
end if;
end if;
end if;
end process error_addr_p;
-- errored_data is high on the cycle after a mismatch and stays high until the end of frame
error_addr_swap_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
errored_swap_data <= '0';
elsif tlast = '1' and tvalid = '1' and tready = '1' then
errored_swap_data <= '0';
elsif packet_count <= HEADER_LENGTH and tvalid = '1' and tready = '1' and tuser = '0' then
if lut_swap_data /= tdata then
errored_swap_data <= '1';
end if;
end if;
end if;
end process error_addr_swap_p;
-- finally the check states - errored_data is only high on the cycle after a mismatch
chk_data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
errored_data <= '0';
if packet_count = (HEADER_LENGTH+1) and tvalid = '1' and tready = '1' and tuser = '0' then
if packet_size(15 downto 8) /= unsigned(tdata) then
errored_data <= '1';
end if;
elsif packet_count = (HEADER_LENGTH+2) and tvalid = '1' and tready = '1' and tuser = '0' then
if packet_size(7 downto 0) /= unsigned(tdata) then
errored_data <= '1';
end if;
elsif packet_count >= (HEADER_LENGTH+3) and tvalid = '1' and tready = '1' and tuser = '0' and rx_state = PKT then
if expected_data /= unsigned(tdata) then
errored_data <= '1';
end if;
end if;
end if;
end process chk_data_p;
maybe_error_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
maybe_frame_error <= '0';
elsif (tlast = '1' and tvalid = '1' and tready = '1' and tuser = '1') or rx_state = IDLE then
maybe_frame_error <= '0';
elsif rx_state /= IDLE and rx_state /= INFO and (errored_data = '1' or (errored_addr_data = '1' and errored_swap_data = '1')) then
maybe_frame_error <= '1';
end if;
end if;
end process maybe_error_p;
-- capture the error and hold until reset
error_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
frame_error_int <= '0';
elsif maybe_frame_error = '1' and tlast = '1' and tready = '1' and tvalid = '1' and tuser = '0' then
frame_error_int <= '1';
end if;
end if;
end process error_p;
-- need a counter for frame activity to provide some feedback that frames are being received
-- a 16 bit counter is used as this should give a slow flash rate at 10M and a very fast rate at 1G
flash_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_tresetn = '0' then
frame_activity_count <= (others => '0');
elsif tlast = '1' then
frame_activity_count <= frame_activity_count + X"0001";
end if;
end if;
end process flash_p;
end rtl;
| mit | bd2ece97667251e79d6c70a1ae3046ee | 0.560257 | 3.832027 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_divider_inv.vhd | 1 | 5,202 | ----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Polynom Division with Inversion+Multiplication
-- Computes the g/h mod f IN GF(2**m)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- g_i - First input value
-- h_i - Seccond input value
-- z_o - Output value
-- ready_o - Ready flag after computation
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) divider with inversion
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_divider_inv IS
PORT(
-- Clock, reset and enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_divider_inv;
ARCHITECTURE rtl of e_gf2m_divider_inv IS
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_eea_inversion
COMPONENT e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
SIGNAL invh: std_logic_vector(M-1 DOWNTO 0);
SIGNAL enable_inversion, done_inversion, enable_multiplication, done_multiplication: std_logic;
-- Define all available states
subtype states IS natural RANGE 0 TO 6;
SIGNAL current_state: states;
BEGIN
-- Instantiate inversion entity to compute h^-1
inversion: e_gf2m_eea_inversion GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_inversion,
a_i => h_i,
z_o => invh,
ready_o => done_inversion
);
-- Instantiate multiplier entity to g * h^-1
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => enable_multiplication,
a_i => g_i,
b_i => invh,
z_o => z_o,
ready_o => done_multiplication
);
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate inversion
-- 4,5 : Calculate multiplication
CASE current_state IS
WHEN 0 TO 1 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '1';
WHEN 2 => enable_inversion <='1'; enable_multiplication <= '0'; ready_o <= '0';
WHEN 3 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '0';
WHEN 4 => enable_inversion <='0'; enable_multiplication <= '1'; ready_o <= '0';
WHEN 5 TO 6 => enable_inversion <='0'; enable_multiplication <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF done_inversion = '1' THEN
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF done_multiplication = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS control_unit;
END rtl;
| gpl-3.0 | d0fd2637dc86006bfd3920fbbfb14a52 | 0.471357 | 3.977064 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.vhd | 1 | 33,503 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_generator_0 IS
PORT (
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 10,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 10,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 13,
C_PROG_FULL_THRESH_NEGATE_VAL => 12,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => 16,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 4,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 4,
C_WR_DEPTH => 16,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 4,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 16,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 2,
C_AXIS_TKEEP_WIDTH => 2,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_0_arch;
| mit | 0cb05a2d66856b97301f408fcdc1bae4 | 0.60705 | 3.072542 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/pat_gen/tri_mode_ethernet_mac_0_axi_mux.vhd | 1 | 4,263 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_mux.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: A simple AXI-Streaming MUX
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_axi_mux is
port (
mux_select : in std_logic;
-- mux inputs
tdata0 : in std_logic_vector(7 downto 0);
tvalid0 : in std_logic;
tlast0 : in std_logic;
tready0 : out std_logic;
tdata1 : in std_logic_vector(7 downto 0);
tvalid1 : in std_logic;
tlast1 : in std_logic;
tready1 : out std_logic;
-- mux outputs
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end tri_mode_ethernet_mac_0_axi_mux;
architecture rtl of tri_mode_ethernet_mac_0_axi_mux is
begin
main_mux : process(mux_select, tdata0, tvalid0, tlast0, tdata1,
tvalid1, tlast1)
begin
if mux_select = '1' then
tdata <= tdata1;
tvalid <= tvalid1;
tlast <= tlast1;
else
tdata <= tdata0;
tvalid <= tvalid0;
tlast <= tlast0;
end if;
end process;
split : process (mux_select, tready)
begin
if mux_select = '1' then
tready0 <= '1';
else
tready0 <= tready;
end if;
tready1 <= tready;
end process;
end rtl;
| mit | 2e07d90457e9c05ec2d5f91d95037c89 | 0.587849 | 4.569132 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/tri_mode_ethernet_mac_0_example_design_resets.vhd | 1 | 9,013 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates fully synchronous resets for each clock domain
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end tri_mode_ethernet_mac_0_example_design_resets;
architecture RTL of tri_mode_ethernet_mac_0_example_design_resets is
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- define internal signals
signal s_axi_pre_resetn : std_logic := '0';
signal s_axi_reset_int : std_logic;
signal combined_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal gtx_clk_reset_int : std_logic;
signal clear_checker : std_logic;
signal chk_pre_resetn : std_logic := '0';
signal chk_reset_int : std_logic;
signal dcm_locked_sync : std_logic;
signal glbl_rst_int : std_logic;
signal phy_resetn_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Synchronise the async dcm_locked into the gtx_clk clock domain
------------------------------------------------------------------------------
dcm_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => gtx_clk,
data_in => dcm_locked,
data_out => dcm_locked_sync
);
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
-- in each case the async reset is first captured and then synchronised
-----------------
-- global reset
glbl_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => glbl_rst,
reset_out => glbl_rst_int
);
glbl_rst_intn <= not glbl_rst_int;
-----------------
-- AXI-Lite reset
axi_lite_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => s_axi_aclk,
enable => phy_resetn_int,
reset_in => glbl_rst,
reset_out => s_axi_reset_int
);
-- Create fully synchronous reset in the s_axi clock domain.
axi_lite_reset_p : process(s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset_int = '1' then
s_axi_pre_resetn <= '0';
s_axi_resetn <= '0';
else
s_axi_pre_resetn <= '1';
s_axi_resetn <= s_axi_pre_resetn;
end if;
end if;
end process axi_lite_reset_p;
-----------------
-- gtx_clk reset
combined_reset <= glbl_rst or rx_reset or tx_reset;
gtx_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => combined_reset,
reset_out => gtx_clk_reset_int
);
-- Create fully synchronous reset in the gtx_clk domain.
gtx_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gtx_reset_p;
-----------------
-- data check reset
clear_checker <= glbl_rst or reset_error;
chk_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => clear_checker,
reset_out => chk_reset_int
);
-- Create fully synchronous reset in the gtx_clk domain.
chk_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if chk_reset_int = '1' then
chk_pre_resetn <= '0';
chk_resetn <= '0';
else
chk_pre_resetn <= '1';
chk_resetn <= chk_pre_resetn;
end if;
end if;
end process chk_reset_p;
-----------------
-- PHY reset
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
-- this is derived using the 125MHz available and a 6 bit counter
phy_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if glbl_rst_int = '1' then
phy_resetn_int <= '0';
phy_reset_count <= (others => '0');
else
if phy_reset_count /= "111111" then
phy_reset_count <= phy_reset_count + "000001";
else
phy_resetn_int <= '1';
end if;
end if;
end if;
end process phy_reset_p;
phy_resetn <= phy_resetn_int;
end RTL;
| mit | c94fda18a17f8dea70b2d9dd14ec7945 | 0.53911 | 4.223524 | false | false | false | false |
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