enceth.inc
fachat_csa_ultracpu/tests/enceth.inc
; ENC28J60 Control Registers
; Control register definitions are a combination of address,
; bank number, and Ethernet/MAC/PHY indicator bits.
; - Register address	(bits 0-4)
; - Bank number		(bits 5-6)
; - MAC/PHY indicator	(bit 7)

ADDR_MASK	=	$1F
BANK_MASK	=	$60
SPRD_MASK	=	$80

BANK0		=	$00
BANK1		=	$20
BANK2		=	$40
BANK3		=	$60
DSPRD		=	$80		; dummy SPI read required

; All-bank registers
EIE		=	$1B
EIR		=	$1C
ESTAT		=	$1D
ECON2		=	$1E
ECON1		=	$1F

; Bank 0 registers
ERDPTL	=	$00 + BANK0
ERDPTH	=	$01 + BANK0
EWRPTL	=	$02 + BANK0
EWRPTH	=	$03 + BANK0
ETXSTL	=	$04 + BANK0
ETXSTH	=	$05 + BANK0
ETXNDL	=	$06 + BANK0
ETXNDH	=	$07 + BANK0
ERXSTL	=	$08 + BANK0
ERXSTH	=	$09 + BANK0
ERXNDL	=	$0A + BANK0
ERXNDH	=	$0B + BANK0
ERXRDPTL	=	$0C + BANK0
ERXRDPTH	=	$0D + BANK0
ERXWRPTL	=	$0E + BANK0
ERXWRPTH	=	$0F + BANK0
EDMASTL	=	$10 + BANK0
EDMASTH	=	$11 + BANK0
EDMANDL	=	$12 + BANK0
EDMANDH	=	$13 + BANK0
EDMADSTL	=	$14 + BANK0
EDMADSTH	=	$15 + BANK0
EDMACSL	=	$16 + BANK0
EDMACSH	=	$17 + BANK0

; Bank 1 registers
EHT0		=	$00 + BANK1
EHT1		=	$01 + BANK1
EHT2		=	$02 + BANK1
EHT3		=	$03 + BANK1
EHT4		=	$04 + BANK1
EHT5		=	$05 + BANK1
EHT6		=	$06 + BANK1
EHT7		=	$07 + BANK1
EPMM0		=	$08 + BANK1
EPMM1		=	$09 + BANK1
EPMM2		=	$0A + BANK1
EPMM3		=	$0B + BANK1
EPMM4		=	$0C + BANK1
EPMM5		=	$0D + BANK1
EPMM6		=	$0E + BANK1
EPMM7		=	$0F + BANK1
EPMCSL	=	$10 + BANK1
EPMCSH	=	$11 + BANK1
EPMOL		=	$14 + BANK1
EPMOH		=	$15 + BANK1
EWOLIE	=	$16 + BANK1
EWOLIR	=	$17 + BANK1
ERXFCON	=	$18 + BANK1
EPKTCNT	=	$19 + BANK1

; Bank 2 registers
MACON1	=	$00 + BANK2 + DSPRD
MACON2	=	$01 + BANK2 + DSPRD
MACON3	=	$02 + BANK2 + DSPRD
MACON4	=	$03 + BANK2 + DSPRD
MABBIPG	=	$04 + BANK2 + DSPRD
MAIPGL	=	$06 + BANK2 + DSPRD
MAIPGH	=	$07 + BANK2 + DSPRD
MACLCON1	=	$08 + BANK2 + DSPRD
MACLCON2	=	$09 + BANK2 + DSPRD
MAMXFLL	=	$0A + BANK2 + DSPRD
MAMXFLH	=	$0B + BANK2 + DSPRD
MAPHSUP	=	$0D + BANK2 + DSPRD
MICON		=	$11 + BANK2 + DSPRD
MICMD		=	$12 + BANK2 + DSPRD
MIREGADR	=	$14 + BANK2 + DSPRD
MIWRL		=	$16 + BANK2 + DSPRD
MIWRH		=	$17 + BANK2 + DSPRD
MIRDL		=	$18 + BANK2 + DSPRD
MIRDH		=	$19 + BANK2 + DSPRD

; Bank 3 registers
MAADR1	=	$00 + BANK3 + DSPRD
MAADR0	=	$01 + BANK3 + DSPRD
MAADR3	=	$02 + BANK3 + DSPRD
MAADR2	=	$03 + BANK3 + DSPRD
MAADR5	=	$04 + BANK3 + DSPRD
MAADR4	=	$05 + BANK3 + DSPRD
EBSTSD	=	$06 + BANK3
EBSTCON	=	$07 + BANK3
EBSTCSL	=	$08 + BANK3
EBSTCSH	=	$09 + BANK3
MISTAT	=	$0A + BANK3 + DSPRD
EREVID	=	$12 + BANK3
ECOCON	=	$15 + BANK3
EFLOCON	=	$17 + BANK3
EPAUSL	=	$18 + BANK3
EPAUSH	=	$19 + BANK3

; PHY registers
PHCON1	=	$00
PHSTAT1	=	$01
PHHID1	=	$02
PHHID2	=	$03
PHCON2	=	$10
PHSTAT2	=	$11
PHIE		=	$12
PHIR		=	$13
PHLCON	=	$14

; ENC28J60 EIE Register Bit Definitions
EIE_INTIE		=	$80
EIE_PKTIE		=	$40
EIE_DMAIE		=	$20
EIE_LINKIE		=	$10
EIE_TXIE		=	$08
EIE_WOLIE		=	$04
EIE_TXERIE		=	$02
EIE_RXERIE		=	$01

; ENC28J60 EIR Register Bit Definitions
EIR_PKTIF		=	$40
EIR_DMAIF		=	$20
EIR_LINKIF		=	$10
EIR_TXIF		=	$08
EIR_WOLIF		=	$04
EIR_TXERIF		=	$02
EIR_RXERIF		=	$01

; ENC28J60 ESTAT Register Bit Definitions
ESTAT_INT		=	$80
ESTAT_LATECOL		=	$10
ESTAT_RXBUSY		=	$04
ESTAT_TXABRT		=	$02
ESTAT_CLKRDY		=	$01

; ENC28J60 ECON2 Register Bit Definitions
ECON2_AUTOINC		=	$80
ECON2_PKTDEC		=	$40
ECON2_PWRSV		=	$20
ECON2_VRPS		=	$08

; ENC28J60 ECON1 Register Bit Definitions
ECON1_TXRST		=	$80
ECON1_RXRST		=	$40
ECON1_DMAST		=	$20
ECON1_CSUMEN		=	$10
ECON1_TXRTS		=	$08
ECON1_RXEN		=	$04
ECON1_BSEL1		=	$02
ECON1_BSEL0		=	$01

; ENC28J60 MACON1 Register Bit Definitions
MACON1_LOOPBK	=	$10
MACON1_TXPAUS	=	$08
MACON1_RXPAUS	=	$04
MACON1_PASSALL	=	$02
MACON1_MARXEN	=	$01

; ENC28J60 MACON2 Register Bit Definitions
MACON2_MARST	=	$80
MACON2_RNDRST	=	$40
MACON2_MARXRST	=	$08
MACON2_RFUNRST	=	$04
MACON2_MATXRST	=	$02
MACON2_TFUNRST	=	$01

; ENC28J60 MACON3 Register Bit Definitions
MACON3_PADCFG2	=	$80
MACON3_PADCFG1	=	$40
MACON3_PADCFG0	=	$20
MACON3_TXCRCEN	=	$10
MACON3_PHDRLEN	=	$08
MACON3_HFRMLEN	=	$04
MACON3_FRMLNEN	=	$02
MACON3_FULDPX	=	$01

; ENC28J60 MICMD Register Bit Definitions
MICMD_MIISCAN	=	$02
MICMD_MIIRD	=	$01

; ENC28J60 MISTAT Register Bit Definitions
MISTAT_NVALID		=	$04
MISTAT_SCAN		=	$02
MISTAT_BUSY		=	$01

; ENC28J60 PHY PHCON1 Register Bit Definitions
PHCON1_PRST		=	$8000
PHCON1_PLOOPBK	=	$4000
PHCON1_PPWRSV	=	$0800
PHCON1_PDPXMD	=	$0100

; ENC28J60 PHY PHSTAT1 Register Bit Definitions
PHSTAT1_PFDPX	=	$1000
PHSTAT1_PHDPX	=	$0800
PHSTAT1_LLSTAT	=	$0004
PHSTAT1_JBSTAT	=	$0002

; ENC28J60 PHY PHCON2 Register Bit Definitions
PHCON2_FRCLINK	=	$4000
PHCON2_TXDIS	=	$2000
PHCON2_JABBER	=	$0400
PHCON2_HDLDIS	=	$0100

; ENC28J60 Packet Control Byte Bit Definitions
PKTCTRL_PHUGEEN	=	$08
PKTCTRL_PPADEN	=	$04
PKTCTRL_PCRCEN	=	$02
PKTCTRL_POVERRIDE	=	$01

; SPI operation codes
ENC_READ_CTRL_REG	=	$00
ENC_READ_BUF_MEM	=	$3A
ENC_WRITE_CTRL_REG =	$40
ENC_WRITE_BUF_MEM	=	$7A
ENC_BIT_FIELD_SET	=	$80
ENC_BIT_FIELD_CLR	=	$A0
ENC_SOFT_RESET	=	$FF


; buffer boundaries applied to internal 8K ram
; entire available packet buffer space is allocated
TXSTART_INIT   	=	$0000	; start TX buffer at 0
RXSTART_INIT   	=	$0600	; give TX buffer space for one full ethernet frame ~1500 bytes)
RXSTOP_INIT    	=	$1FFF	; receive buffer gets the rest
MAX_FRAMELEN	=	1518		; maximum ethernet frame length


; Ethernet constants
ETHERNET_MIN_PACKET_LENGTH	=	$3C
ETHERNET_HEADER_LENGTH		=	$0E

