
â
Command: %s
53*	vivadotcl2X
Dsynth_design -top sd_mem -part xc7a100tcsg324-1 -mode out_of_context2default:defaultZ4-113hpxê
:
Starting synth_design
149*	vivadotclZ4-321hpxê
ü
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2
	Synthesis2default:default2
xc7a100t2default:defaultZ17-347hpxê
è
0Got license for feature '%s' and/or device '%s'
310*common2
	Synthesis2default:default2
xc7a100t2default:defaultZ17-349hpxê
§
%s*synth2ã
wStarting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 385.184 ; gain = 98.664
2default:defaulthpxê
õ
synthesizing module '%s'638*oasys2
sd_mem2default:default2¶
èd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/synth/sd_mem.vhd2default:default2
692default:default8@Z8-638hpxê
a
%s
*synth2I
5	Parameter C_FAMILY bound to: artix7 - type: string 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_ADDR_WIDTH bound to: 12 - type: integer 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_DEFAULT_DATA bound to: 0 - type: string 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_DEPTH bound to: 2560 - type: integer 
2default:defaulthp
x
ê
^
%s
*synth2F
2	Parameter C_HAS_CLK bound to: 1 - type: integer 
2default:defaulthp
x
ê
\
%s
*synth2D
0	Parameter C_HAS_D bound to: 1 - type: integer 
2default:defaulthp
x
ê
^
%s
*synth2F
2	Parameter C_HAS_DPO bound to: 0 - type: integer 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_HAS_DPRA bound to: 0 - type: integer 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_HAS_I_CE bound to: 0 - type: integer 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_HAS_QDPO bound to: 0 - type: integer 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_HAS_QDPO_CE bound to: 0 - type: integer 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter C_HAS_QDPO_CLK bound to: 0 - type: integer 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter C_HAS_QDPO_RST bound to: 0 - type: integer 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter C_HAS_QDPO_SRST bound to: 0 - type: integer 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_HAS_QSPO bound to: 0 - type: integer 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_HAS_QSPO_CE bound to: 0 - type: integer 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter C_HAS_QSPO_RST bound to: 0 - type: integer 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter C_HAS_QSPO_SRST bound to: 0 - type: integer 
2default:defaulthp
x
ê
^
%s
*synth2F
2	Parameter C_HAS_SPO bound to: 1 - type: integer 
2default:defaulthp
x
ê
]
%s
*synth2E
1	Parameter C_HAS_WE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter C_MEM_INIT_FILE bound to: sd_mem.mif - type: string 
2default:defaulthp
x
ê
f
%s
*synth2N
:	Parameter C_ELABORATION_DIR bound to: ./ - type: string 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_MEM_TYPE bound to: 1 - type: integer 
2default:defaulthp
x
ê
f
%s
*synth2N
:	Parameter C_PIPELINE_STAGES bound to: 0 - type: integer 
2default:defaulthp
x
ê
a
%s
*synth2I
5	Parameter C_QCE_JOINED bound to: 0 - type: integer 
2default:defaulthp
x
ê
a
%s
*synth2I
5	Parameter C_QUALIFY_WE bound to: 0 - type: integer 
2default:defaulthp
x
ê
_
%s
*synth2G
3	Parameter C_READ_MIF bound to: 1 - type: integer 
2default:defaulthp
x
ê
e
%s
*synth2M
9	Parameter C_REG_A_D_INPUTS bound to: 0 - type: integer 
2default:defaulthp
x
ê
e
%s
*synth2M
9	Parameter C_REG_DPRA_INPUT bound to: 0 - type: integer 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_SYNC_ENABLE bound to: 1 - type: integer 
2default:defaulthp
x
ê
]
%s
*synth2E
1	Parameter C_WIDTH bound to: 32 - type: integer 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter C_PARSER_TYPE bound to: 1 - type: integer 
2default:defaulthp
x
ê
Ú
Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2(
dist_mem_gen_v8_0_122default:default2∑
¢d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd2default:default2
32372default:default2
U02default:default2(
dist_mem_gen_v8_0_122default:default2¶
èd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/synth/sd_mem.vhd2default:default2
1352default:default8@Z8-3491hpxê
÷
%done synthesizing module '%s' (%s#%s)256*oasys2
sd_mem2default:default2
42default:default2
12default:default2¶
èd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/synth/sd_mem.vhd2default:default2
692default:default8@Z8-256hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[31]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[30]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[29]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[28]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[27]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[26]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[25]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[24]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[23]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[22]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[21]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[20]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[19]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[18]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[17]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[16]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[15]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[14]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[13]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[12]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[11]2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[10]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[9]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[8]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[7]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[6]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[5]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[4]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[3]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[2]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[1]2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo[0]2default:defaultZ8-3331hpxê
x
!design %s has unconnected port %s3331*oasys2
spram2default:default2
i_ce2default:defaultZ8-3331hpxê
{
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo_ce2default:defaultZ8-3331hpxê
|
!design %s has unconnected port %s3331*oasys2
spram2default:default2
qspo_rst2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
spram2default:default2
	qspo_srst2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[31]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[30]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[29]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[28]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[27]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[26]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[25]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[24]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[23]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[22]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[21]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[20]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[19]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[18]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[17]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[16]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[15]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[14]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[13]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[12]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[11]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[10]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[9]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[8]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[7]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[6]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[5]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[4]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[3]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[2]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[1]2default:defaultZ8-3331hpxê
è
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
dpo[0]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[31]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[30]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[29]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[28]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[27]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[26]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[25]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[24]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[23]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[22]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[21]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[20]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[19]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[18]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[17]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[16]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[15]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[14]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[13]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[12]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[11]2default:defaultZ8-3331hpxê
ë
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[10]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[9]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[8]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[7]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[6]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[5]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[4]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[3]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[2]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[1]2default:defaultZ8-3331hpxê
ê
!design %s has unconnected port %s3331*oasys2.
dist_mem_gen_v8_0_12_synth2default:default2
qdpo[0]2default:defaultZ8-3331hpxê
›
ÅMessage '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33312default:default2
1002default:defaultZ17-14hpxê
¶
%s*synth2ç
yFinished RTL Elaboration : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
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%s
*synth2,

Report Check Netlist: 
2default:defaulthp
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
x
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u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
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%s
*synth2]
I|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
2default:defaulthp
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ô
ÑFinished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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∞
%s*synth2ó
ÇFinished RTL Optimization Phase 1 : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Loading part %s157*device2$
xc7a100tcsg324-12default:defaultZ21-403hpxê
K
)Preparing netlist for logic optimization
349*projectZ1-570hpxê
>

Processing XDC Constraints
244*projectZ1-262hpxê
=
Initializing timing engine
348*projectZ1-569hpxê
é
$Parsing XDC File [%s] for cell '%s'
848*designutils2§
çd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/sd_mem_ooc.xdc2default:default2
U0	2default:default8Z20-848hpxê
ó
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2§
çd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/sd_mem_ooc.xdc2default:default2
U0	2default:default8Z20-847hpxê
·
Parsing XDC File [%s]
179*designutils2ü
àD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/sd_mem_synth_1/dont_touch.xdc2default:default8Z20-179hpxê
Í
Finished Parsing XDC File [%s]
178*designutils2ü
àD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/sd_mem_synth_1/dont_touch.xdc2default:default8Z20-178hpxê
H
&Completed Processing XDC Constraints

245*projectZ1-263hpxê
~
!Unisim Transformation Summary:
%s111*project29
%No Unisim elements were transformed.
2default:defaultZ1-111hpxê
ö
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common24
 Constraint Validation Runtime : 2default:default2
00:00:002default:default2 
00:00:00.0312default:default2
1132.9922default:default2
0.0002default:defaultZ17-268hpxê
~
%s
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2default:defaulthp
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Finished Constraint Validation : Time (s): cpu = 00:01:33 ; elapsed = 00:01:37 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2f
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2default:defaulthp
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*Start Loading Part and Timing Information
2default:defaulthp
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth23
Loading part: xc7a100tcsg324-1
2default:defaulthp
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%s
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2default:defaulthp
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%s*synth2¢
çFinished Loading Part and Timing Information : Time (s): cpu = 00:01:33 ; elapsed = 00:01:37 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Z
%s
*synth2B
.Start Applying 'set_property' XDC Constraints
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2¶
ëFinished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:33 ; elapsed = 00:01:37 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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∞
%s*synth2ó
ÇFinished RTL Optimization Phase 2 : Time (s): cpu = 00:01:33 ; elapsed = 00:01:37 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth24
 Start RTL Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 1     
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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O
%s
*synth27
#Finished RTL Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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Y
%s
*synth2A
-Start RTL Hierarchical Component Statistics 
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth27
#Hierarchical RTL Component report 
2default:defaulthp
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%s
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Module spram 
2default:defaulthp
x
ê
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%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
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%s
*synth2%
+---Registers : 
2default:defaulthp
x
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Z
%s
*synth2B
.	               32 Bit    Registers := 1     
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2C
/Finished RTL Hierarchical Component Statistics
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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H
%s
*synth20
Start Part Resource Summary
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2k
WPart Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
2default:defaulthp
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~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth23
Finished Part Resource Summary
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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W
%s
*synth2?
+Start Cross Boundary and Area Optimization
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2E
1Warning: Parallel synthesis criteria is not met 
2default:defaulthp
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%s
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2default:defaulthp
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%s*synth2£
éFinished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:35 ; elapsed = 00:01:39 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ò
É---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
2default:defaulthpxê
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%s*synth2f
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2default:defaulthpxê
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%s*synth2S
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Distributed RAM: Preliminary Mapping  Report (see note below)
2default:defaulthpxê
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%s*synth2ú
á+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+
2default:defaulthpxê
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%s*synth2ù
à|Module Name | RTL Object                                                | Inference      | Size (Depth x Width) | Primitives        | 
2default:defaulthpxê
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á+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+
2default:defaulthpxê
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à|U0          | synth_options.dist_mem_inst/gen_sp_ram.spram_inst/ram_reg | User Attribute | 4 K x 32             | RAM256X1S x 320   | 
2default:defaulthpxê
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à+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+

2default:defaulthpxê
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óNote: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
2default:defaulthpxê
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%s*synth2õ
Ü---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
2default:defaulthpxê
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%s*synth2f
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2default:defaulthpxê
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
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%s
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++-+--------------+------------+----------+
2default:defaulthp
x
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%s
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+| |RTL Partition |Replication |Instances |
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2:
&Start Applying XDC Timing Constraints
2default:defaulthp
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
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2default:defaulthp
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∑
%s*synth2û
âFinished Applying XDC Timing Constraints : Time (s): cpu = 00:01:46 ; elapsed = 00:01:51 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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F
%s
*synth2.
Start Timing Optimization
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ë
}Finished Timing Optimization : Time (s): cpu = 00:01:46 ; elapsed = 00:01:51 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2ò
É---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2<
(
Distributed RAM: Final Mapping  Report
2default:defaulthp
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%s
*synth2ú
á+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+
2default:defaulthp
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%s
*synth2ù
à|Module Name | RTL Object                                                | Inference      | Size (Depth x Width) | Primitives        | 
2default:defaulthp
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µ
%s
*synth2ú
á+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+
2default:defaulthp
x
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∂
%s
*synth2ù
à|U0          | synth_options.dist_mem_inst/gen_sp_ram.spram_inst/ram_reg | User Attribute | 4 K x 32             | RAM256X1S x 320   | 
2default:defaulthp
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%s
*synth2ù
à+------------+-----------------------------------------------------------+----------------+----------------------+-------------------+

2default:defaulthp
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%s
*synth2õ
Ü---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
x
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~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
x
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E
%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2-
Start Technology Mapping
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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©
%s*synth2ê
|Finished Technology Mapping : Time (s): cpu = 00:01:46 ; elapsed = 00:01:52 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2'
Start IO Insertion
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Q
%s
*synth29
%Start Flattening Before IO Insertion
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2<
(Finished Flattening Before IO Insertion
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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H
%s
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Start Final Netlist Cleanup
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Finished Final Netlist Cleanup
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s*synth2ä
vFinished IO Insertion : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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D
%s
*synth2,

Report Check Netlist: 
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
2default:defaulthp
x
ê
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
O
%s
*synth27
#Start Renaming Generated Instances
2default:defaulthp
x
ê
~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2õ
ÜFinished Renaming Generated Instances : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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%s
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++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
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+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth24
 Start Rebuilding User Hierarchy
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s*synth2ò
ÉFinished Rebuilding User Hierarchy : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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K
%s
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Start Renaming Generated Ports
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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∞
%s*synth2ó
ÇFinished Renaming Generated Ports : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
M
%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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≤
%s*synth2ô
ÑFinished Handling Custom Attributes : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
J
%s
*synth22
Start Renaming Generated Nets
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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Ø
%s*synth2ñ
ÅFinished Renaming Generated Nets : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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K
%s
*synth23
Start Writing Synthesis Report
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
A
%s
*synth2)

Report BlackBoxes: 
2default:defaulthp
x
ê
J
%s
*synth22
+-+--------------+----------+
2default:defaulthp
x
ê
J
%s
*synth22
| |BlackBox name |Instances |
2default:defaulthp
x
ê
J
%s
*synth22
+-+--------------+----------+
2default:defaulthp
x
ê
J
%s
*synth22
+-+--------------+----------+
2default:defaulthp
x
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A
%s*synth2)

Report Cell Usage: 
2default:defaulthpxê
G
%s*synth2/
+------+----------+------+
2default:defaulthpxê
G
%s*synth2/
|      |Cell      |Count |
2default:defaulthpxê
G
%s*synth2/
+------+----------+------+
2default:defaulthpxê
G
%s*synth2/
|1     |LUT5      |    74|
2default:defaulthpxê
G
%s*synth2/
|2     |LUT6      |    64|
2default:defaulthpxê
G
%s*synth2/
|3     |RAM256X1S |   320|
2default:defaulthpxê
G
%s*synth2/
|4     |FDRE      |    32|
2default:defaulthpxê
G
%s*synth2/
+------+----------+------+
2default:defaulthpxê
E
%s
*synth2-

Report Instance Areas: 
2default:defaulthp
x
ê
{
%s
*synth2c
O+------+----------------------------------+---------------------------+------+
2default:defaulthp
x
ê
{
%s
*synth2c
O|      |Instance                          |Module                     |Cells |
2default:defaulthp
x
ê
{
%s
*synth2c
O+------+----------------------------------+---------------------------+------+
2default:defaulthp
x
ê
{
%s
*synth2c
O|1     |top                               |                           |   490|
2default:defaulthp
x
ê
{
%s
*synth2c
O|2     |  U0                              |dist_mem_gen_v8_0_12       |   490|
2default:defaulthp
x
ê
{
%s
*synth2c
O|3     |    \synth_options.dist_mem_inst  |dist_mem_gen_v8_0_12_synth |   490|
2default:defaulthp
x
ê
{
%s
*synth2c
O|4     |      \gen_sp_ram.spram_inst      |spram                      |   490|
2default:defaulthp
x
ê
{
%s
*synth2c
O+------+----------------------------------+---------------------------+------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
∞
%s*synth2ó
ÇFinished Writing Synthesis Report : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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t
%s
*synth2\
HSynthesis finished with 0 errors, 0 critical warnings and 116 warnings.
2default:defaulthp
x
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¨
%s
*synth2ì
Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:01:38 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthp
x
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Æ
%s
*synth2ï
ÄSynthesis Optimization Complete : Time (s): cpu = 00:01:48 ; elapsed = 00:01:53 . Memory (MB): peak = 1132.992 ; gain = 846.473
2default:defaulthp
x
ê
B
 Translating synthesized netlist
350*projectZ1-571hpxê
g
-Analyzing %s Unisim elements for replacement
17*netlist2
3202default:defaultZ29-17hpxê
j
2Unisim Transformation completed in %s CPU seconds
28*netlist2
02default:defaultZ29-28hpxê
K
)Preparing netlist for logic optimization
349*projectZ1-570hpxê
u
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138hpxê
Í
!Unisim Transformation Summary:
%s111*project2§
è  A total of 320 instances were transformed.
  RAM256X1S => RAM256X1S (MUXF7, MUXF7, MUXF8, RAMS64E, RAMS64E, RAMS64E, RAMS64E): 320 instances
2default:defaultZ1-111hpxê
U
Releasing license: %s
83*common2
	Synthesis2default:defaultZ17-83hpxê
»
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
152default:default2
1002default:default2
02default:default2
02default:defaultZ4-41hpxê
^
%s completed successfully
29*	vivadotcl2 
synth_design2default:defaultZ4-42hpxê
Ü
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
synth_design: 2default:default2
00:01:512default:default2
00:01:572default:default2
1132.9922default:default2
857.9412default:defaultZ17-268hpxê
K
"No constraint will be written out.1103*constraintsZ18-5210hpxê
ˇ
 The %s '%s' has been generated.
621*common2

checkpoint2default:default2ô
ÑD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/sd_mem_synth_1/sd_mem.dcp2default:defaultZ17-1381hpxê

,Added synthesis output to IP cache for IP %s415*coretcl2û
âd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/sd_mem/sd_mem.xci2default:defaultZ2-1482hpxê
P
Renamed %s cell refs.
330*coretcl2
32default:defaultZ2-1174hpxê
K
"No constraint will be written out.1103*constraintsZ18-5210hpxê
ˇ
 The %s '%s' has been generated.
621*common2

checkpoint2default:default2ô
ÑD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/sd_mem_synth_1/sd_mem.dcp2default:defaultZ17-1381hpxê
í
%s4*runtcl2v
bExecuting : report_utilization -file sd_mem_utilization_synth.rpt -pb sd_mem_utilization_synth.pb
2default:defaulthpxê
â
treport_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1132.992 ; gain = 0.000
*commonhpxê
Ä
Exiting %s at %s...
206*common2
Vivado2default:default2,
Mon Dec 24 19:09:21 20182default:defaultZ17-206hpxê


End Record