// -*- mode: verilog -*-
// Generated by cuttlec from a KÃ´ika module
module uart(input wire CLK, input wire RST_N, output wire write_bit_arg, input wire write_bit_out, output wire read_byte_arg, input wire[8:0] read_byte_out);
	reg[1:0] state = 2'b0;
	reg[7:0] in_byte = 8'b0;
	reg[2:0] in_byte_offset = 3'b0;
	reg out_bit = 1'b1;
	reg[7:0] delay = 8'b0;
	reg last_write_ack = 1'b0;

	wire _cond0 = delay == 8'b0;
	wire _cond1 = state == 2'b01;
	wire _cond2 = state == 2'b10;
	wire _cond3 = state == 2'b11;
	wire[1:0] _mux_ccontext0 = _cond0 ? (_cond1 ? 2'b10 : (_cond2 ? (in_byte_offset == 3'b111 ? 2'b11 : state) : (_cond3 ? 2'b0 : state))) : state;
	wire _0 = _mux_ccontext0 == 2'b0;
	assign read_byte_arg = _0;
	wire _cond4 = _0 && read_byte_out[8 +: 1];
	wire _mux_ccontext1 = _cond0 ? (_cond1 ? 1'b0 : (_cond2 ? in_byte[3'b0] : _cond3 || out_bit)) : out_bit;
	assign write_bit_arg = _mux_ccontext1;

	always @(posedge CLK) begin
		if (!RST_N) begin
			state <= 2'b0;
			in_byte <= 8'b0;
			in_byte_offset <= 3'b0;
			out_bit <= 1'b1;
			delay <= 8'b0;
			last_write_ack <= 1'b0;
		end else begin
			state <= _cond4 ? 2'b01 : _mux_ccontext0;
			in_byte <= _cond4 ? read_byte_out[0 +: 8] : (_cond0 && ~(_cond1 || ~_cond2) ? in_byte >> 1'b1 : in_byte);
			in_byte_offset <= _cond0 && ~(_cond1 || ~_cond2) ? in_byte_offset + 3'b001 : in_byte_offset;
			out_bit <= _mux_ccontext1;
			delay <= _cond0 ? 8'b11011000 : delay - 8'b0000001;
			last_write_ack <= write_bit_out;
		end
	end
endmodule
