//
// Generated by Bluespec Compiler (build 7d0b6cf)
//
// On Thu Feb 27 23:21:31 EST 2020
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module top_bsv(CLK,
	       RST_N);
  input  CLK;
  input  RST_N;

  // inlined wires
  wire [68 : 0] rv_core_toDmem_rv$port0__write_1,
		rv_core_toDmem_rv$port1__read,
		rv_core_toDmem_rv$port2__read,
		rv_core_toImem_rv$port0__write_1,
		rv_core_toImem_rv$port1__read,
		rv_core_toImem_rv$port2__read;
  wire [31 : 0] rv_core_pc_port_0$wget,
		rv_core_pc_port_1$wget,
		rv_core_rf_rf_10_port_0$wget,
		rv_core_rf_rf_11_port_0$wget,
		rv_core_rf_rf_12_port_0$wget,
		rv_core_rf_rf_13_port_0$wget,
		rv_core_rf_rf_14_port_0$wget,
		rv_core_rf_rf_15_port_0$wget,
		rv_core_rf_rf_16_port_0$wget,
		rv_core_rf_rf_17_port_0$wget,
		rv_core_rf_rf_18_port_0$wget,
		rv_core_rf_rf_19_port_0$wget,
		rv_core_rf_rf_1_port_0$wget,
		rv_core_rf_rf_20_port_0$wget,
		rv_core_rf_rf_21_port_0$wget,
		rv_core_rf_rf_22_port_0$wget,
		rv_core_rf_rf_23_port_0$wget,
		rv_core_rf_rf_24_port_0$wget,
		rv_core_rf_rf_25_port_0$wget,
		rv_core_rf_rf_26_port_0$wget,
		rv_core_rf_rf_27_port_0$wget,
		rv_core_rf_rf_28_port_0$wget,
		rv_core_rf_rf_29_port_0$wget,
		rv_core_rf_rf_2_port_0$wget,
		rv_core_rf_rf_30_port_0$wget,
		rv_core_rf_rf_31_port_0$wget,
		rv_core_rf_rf_3_port_0$wget,
		rv_core_rf_rf_4_port_0$wget,
		rv_core_rf_rf_5_port_0$wget,
		rv_core_rf_rf_6_port_0$wget,
		rv_core_rf_rf_7_port_0$wget,
		rv_core_rf_rf_8_port_0$wget,
		rv_core_rf_rf_9_port_0$wget;
  wire [1 : 0] bram_serverAdapterA_s1_1$wget,
	       bram_serverAdapterA_writeWithResp$wget,
	       bram_serverAdapterB_s1_1$wget,
	       bram_serverAdapterB_writeWithResp$wget,
	       rv_core_scoreboard_scores_0_port_0$wget,
	       rv_core_scoreboard_scores_0_port_1$wget,
	       rv_core_scoreboard_scores_10_port_0$wget,
	       rv_core_scoreboard_scores_10_port_1$wget,
	       rv_core_scoreboard_scores_11_port_0$wget,
	       rv_core_scoreboard_scores_11_port_1$wget,
	       rv_core_scoreboard_scores_12_port_0$wget,
	       rv_core_scoreboard_scores_12_port_1$wget,
	       rv_core_scoreboard_scores_13_port_0$wget,
	       rv_core_scoreboard_scores_13_port_1$wget,
	       rv_core_scoreboard_scores_14_port_0$wget,
	       rv_core_scoreboard_scores_14_port_1$wget,
	       rv_core_scoreboard_scores_15_port_0$wget,
	       rv_core_scoreboard_scores_15_port_1$wget,
	       rv_core_scoreboard_scores_16_port_0$wget,
	       rv_core_scoreboard_scores_16_port_1$wget,
	       rv_core_scoreboard_scores_17_port_0$wget,
	       rv_core_scoreboard_scores_17_port_1$wget,
	       rv_core_scoreboard_scores_18_port_0$wget,
	       rv_core_scoreboard_scores_18_port_1$wget,
	       rv_core_scoreboard_scores_19_port_0$wget,
	       rv_core_scoreboard_scores_19_port_1$wget,
	       rv_core_scoreboard_scores_1_port_0$wget,
	       rv_core_scoreboard_scores_1_port_1$wget,
	       rv_core_scoreboard_scores_20_port_0$wget,
	       rv_core_scoreboard_scores_20_port_1$wget,
	       rv_core_scoreboard_scores_21_port_0$wget,
	       rv_core_scoreboard_scores_21_port_1$wget,
	       rv_core_scoreboard_scores_22_port_0$wget,
	       rv_core_scoreboard_scores_22_port_1$wget,
	       rv_core_scoreboard_scores_23_port_0$wget,
	       rv_core_scoreboard_scores_23_port_1$wget,
	       rv_core_scoreboard_scores_24_port_0$wget,
	       rv_core_scoreboard_scores_24_port_1$wget,
	       rv_core_scoreboard_scores_25_port_0$wget,
	       rv_core_scoreboard_scores_25_port_1$wget,
	       rv_core_scoreboard_scores_26_port_0$wget,
	       rv_core_scoreboard_scores_26_port_1$wget,
	       rv_core_scoreboard_scores_27_port_0$wget,
	       rv_core_scoreboard_scores_27_port_1$wget,
	       rv_core_scoreboard_scores_28_port_0$wget,
	       rv_core_scoreboard_scores_28_port_1$wget,
	       rv_core_scoreboard_scores_29_port_0$wget,
	       rv_core_scoreboard_scores_29_port_1$wget,
	       rv_core_scoreboard_scores_2_port_0$wget,
	       rv_core_scoreboard_scores_2_port_1$wget,
	       rv_core_scoreboard_scores_30_port_0$wget,
	       rv_core_scoreboard_scores_30_port_1$wget,
	       rv_core_scoreboard_scores_31_port_0$wget,
	       rv_core_scoreboard_scores_31_port_1$wget,
	       rv_core_scoreboard_scores_3_port_0$wget,
	       rv_core_scoreboard_scores_3_port_1$wget,
	       rv_core_scoreboard_scores_4_port_0$wget,
	       rv_core_scoreboard_scores_4_port_1$wget,
	       rv_core_scoreboard_scores_5_port_0$wget,
	       rv_core_scoreboard_scores_5_port_1$wget,
	       rv_core_scoreboard_scores_6_port_0$wget,
	       rv_core_scoreboard_scores_6_port_1$wget,
	       rv_core_scoreboard_scores_7_port_0$wget,
	       rv_core_scoreboard_scores_7_port_1$wget,
	       rv_core_scoreboard_scores_8_port_0$wget,
	       rv_core_scoreboard_scores_8_port_1$wget,
	       rv_core_scoreboard_scores_9_port_0$wget,
	       rv_core_scoreboard_scores_9_port_1$wget;
  wire bram_serverAdapterA_cnt_1$whas,
       bram_serverAdapterA_outData_deqCalled$whas,
       bram_serverAdapterA_outData_enqData$whas,
       bram_serverAdapterA_outData_outData$whas,
       bram_serverAdapterB_cnt_1$whas,
       bram_serverAdapterB_outData_deqCalled$whas,
       bram_serverAdapterB_outData_enqData$whas,
       bram_serverAdapterB_outData_outData$whas,
       bram_serverAdapterB_writeWithResp$whas,
       rv_core_epoch_port_0$wget,
       rv_core_pc_port_0$whas,
       rv_core_pc_port_1$whas,
       rv_core_rf_rf_10_port_0$whas,
       rv_core_rf_rf_11_port_0$whas,
       rv_core_rf_rf_12_port_0$whas,
       rv_core_rf_rf_13_port_0$whas,
       rv_core_rf_rf_14_port_0$whas,
       rv_core_rf_rf_15_port_0$whas,
       rv_core_rf_rf_16_port_0$whas,
       rv_core_rf_rf_17_port_0$whas,
       rv_core_rf_rf_18_port_0$whas,
       rv_core_rf_rf_19_port_0$whas,
       rv_core_rf_rf_1_port_0$whas,
       rv_core_rf_rf_20_port_0$whas,
       rv_core_rf_rf_21_port_0$whas,
       rv_core_rf_rf_22_port_0$whas,
       rv_core_rf_rf_23_port_0$whas,
       rv_core_rf_rf_24_port_0$whas,
       rv_core_rf_rf_25_port_0$whas,
       rv_core_rf_rf_26_port_0$whas,
       rv_core_rf_rf_27_port_0$whas,
       rv_core_rf_rf_28_port_0$whas,
       rv_core_rf_rf_29_port_0$whas,
       rv_core_rf_rf_2_port_0$whas,
       rv_core_rf_rf_30_port_0$whas,
       rv_core_rf_rf_31_port_0$whas,
       rv_core_rf_rf_3_port_0$whas,
       rv_core_rf_rf_4_port_0$whas,
       rv_core_rf_rf_5_port_0$whas,
       rv_core_rf_rf_6_port_0$whas,
       rv_core_rf_rf_7_port_0$whas,
       rv_core_rf_rf_8_port_0$whas,
       rv_core_rf_rf_9_port_0$whas,
       rv_core_scoreboard_scores_0_port_0$whas,
       rv_core_scoreboard_scores_0_port_1$whas,
       rv_core_scoreboard_scores_10_port_1$whas,
       rv_core_scoreboard_scores_11_port_1$whas,
       rv_core_scoreboard_scores_12_port_1$whas,
       rv_core_scoreboard_scores_13_port_1$whas,
       rv_core_scoreboard_scores_14_port_1$whas,
       rv_core_scoreboard_scores_15_port_1$whas,
       rv_core_scoreboard_scores_16_port_1$whas,
       rv_core_scoreboard_scores_17_port_1$whas,
       rv_core_scoreboard_scores_18_port_1$whas,
       rv_core_scoreboard_scores_19_port_1$whas,
       rv_core_scoreboard_scores_1_port_1$whas,
       rv_core_scoreboard_scores_20_port_1$whas,
       rv_core_scoreboard_scores_21_port_1$whas,
       rv_core_scoreboard_scores_22_port_1$whas,
       rv_core_scoreboard_scores_23_port_1$whas,
       rv_core_scoreboard_scores_24_port_1$whas,
       rv_core_scoreboard_scores_25_port_1$whas,
       rv_core_scoreboard_scores_26_port_1$whas,
       rv_core_scoreboard_scores_27_port_1$whas,
       rv_core_scoreboard_scores_28_port_1$whas,
       rv_core_scoreboard_scores_29_port_1$whas,
       rv_core_scoreboard_scores_2_port_1$whas,
       rv_core_scoreboard_scores_30_port_1$whas,
       rv_core_scoreboard_scores_31_port_1$whas,
       rv_core_scoreboard_scores_3_port_1$whas,
       rv_core_scoreboard_scores_4_port_1$whas,
       rv_core_scoreboard_scores_5_port_1$whas,
       rv_core_scoreboard_scores_6_port_1$whas,
       rv_core_scoreboard_scores_7_port_1$whas,
       rv_core_scoreboard_scores_8_port_1$whas,
       rv_core_scoreboard_scores_9_port_1$whas,
       rv_core_toDmem_rv$EN_port0__write,
       rv_core_toImem_rv$EN_port0__write,
       rv_core_toImem_rv$EN_port1__write;

  // register bram_serverAdapterA_cnt
  reg [2 : 0] bram_serverAdapterA_cnt;
  wire [2 : 0] bram_serverAdapterA_cnt$D_IN;
  wire bram_serverAdapterA_cnt$EN;

  // register bram_serverAdapterA_s1
  reg [1 : 0] bram_serverAdapterA_s1;
  wire [1 : 0] bram_serverAdapterA_s1$D_IN;
  wire bram_serverAdapterA_s1$EN;

  // register bram_serverAdapterB_cnt
  reg [2 : 0] bram_serverAdapterB_cnt;
  wire [2 : 0] bram_serverAdapterB_cnt$D_IN;
  wire bram_serverAdapterB_cnt$EN;

  // register bram_serverAdapterB_s1
  reg [1 : 0] bram_serverAdapterB_s1;
  wire [1 : 0] bram_serverAdapterB_s1$D_IN;
  wire bram_serverAdapterB_s1$EN;

  // register cycle_count
  reg [31 : 0] cycle_count;
  wire [31 : 0] cycle_count$D_IN;
  wire cycle_count$EN;

  // register dreq
  reg [67 : 0] dreq;
  wire [67 : 0] dreq$D_IN;
  wire dreq$EN;

  // register ireq
  reg [67 : 0] ireq;
  wire [67 : 0] ireq$D_IN;
  wire ireq$EN;

  // register rv_core_epoch_register
  reg rv_core_epoch_register;
  wire rv_core_epoch_register$D_IN, rv_core_epoch_register$EN;

  // register rv_core_instr_count
  reg [31 : 0] rv_core_instr_count;
  wire [31 : 0] rv_core_instr_count$D_IN;
  wire rv_core_instr_count$EN;

  // register rv_core_pc_register
  reg [31 : 0] rv_core_pc_register;
  wire [31 : 0] rv_core_pc_register$D_IN;
  wire rv_core_pc_register$EN;

  // register rv_core_rf_rf_0_register
  reg [31 : 0] rv_core_rf_rf_0_register;
  wire [31 : 0] rv_core_rf_rf_0_register$D_IN;
  wire rv_core_rf_rf_0_register$EN;

  // register rv_core_rf_rf_10_register
  reg [31 : 0] rv_core_rf_rf_10_register;
  wire [31 : 0] rv_core_rf_rf_10_register$D_IN;
  wire rv_core_rf_rf_10_register$EN;

  // register rv_core_rf_rf_11_register
  reg [31 : 0] rv_core_rf_rf_11_register;
  wire [31 : 0] rv_core_rf_rf_11_register$D_IN;
  wire rv_core_rf_rf_11_register$EN;

  // register rv_core_rf_rf_12_register
  reg [31 : 0] rv_core_rf_rf_12_register;
  wire [31 : 0] rv_core_rf_rf_12_register$D_IN;
  wire rv_core_rf_rf_12_register$EN;

  // register rv_core_rf_rf_13_register
  reg [31 : 0] rv_core_rf_rf_13_register;
  wire [31 : 0] rv_core_rf_rf_13_register$D_IN;
  wire rv_core_rf_rf_13_register$EN;

  // register rv_core_rf_rf_14_register
  reg [31 : 0] rv_core_rf_rf_14_register;
  wire [31 : 0] rv_core_rf_rf_14_register$D_IN;
  wire rv_core_rf_rf_14_register$EN;

  // register rv_core_rf_rf_15_register
  reg [31 : 0] rv_core_rf_rf_15_register;
  wire [31 : 0] rv_core_rf_rf_15_register$D_IN;
  wire rv_core_rf_rf_15_register$EN;

  // register rv_core_rf_rf_16_register
  reg [31 : 0] rv_core_rf_rf_16_register;
  wire [31 : 0] rv_core_rf_rf_16_register$D_IN;
  wire rv_core_rf_rf_16_register$EN;

  // register rv_core_rf_rf_17_register
  reg [31 : 0] rv_core_rf_rf_17_register;
  wire [31 : 0] rv_core_rf_rf_17_register$D_IN;
  wire rv_core_rf_rf_17_register$EN;

  // register rv_core_rf_rf_18_register
  reg [31 : 0] rv_core_rf_rf_18_register;
  wire [31 : 0] rv_core_rf_rf_18_register$D_IN;
  wire rv_core_rf_rf_18_register$EN;

  // register rv_core_rf_rf_19_register
  reg [31 : 0] rv_core_rf_rf_19_register;
  wire [31 : 0] rv_core_rf_rf_19_register$D_IN;
  wire rv_core_rf_rf_19_register$EN;

  // register rv_core_rf_rf_1_register
  reg [31 : 0] rv_core_rf_rf_1_register;
  wire [31 : 0] rv_core_rf_rf_1_register$D_IN;
  wire rv_core_rf_rf_1_register$EN;

  // register rv_core_rf_rf_20_register
  reg [31 : 0] rv_core_rf_rf_20_register;
  wire [31 : 0] rv_core_rf_rf_20_register$D_IN;
  wire rv_core_rf_rf_20_register$EN;

  // register rv_core_rf_rf_21_register
  reg [31 : 0] rv_core_rf_rf_21_register;
  wire [31 : 0] rv_core_rf_rf_21_register$D_IN;
  wire rv_core_rf_rf_21_register$EN;

  // register rv_core_rf_rf_22_register
  reg [31 : 0] rv_core_rf_rf_22_register;
  wire [31 : 0] rv_core_rf_rf_22_register$D_IN;
  wire rv_core_rf_rf_22_register$EN;

  // register rv_core_rf_rf_23_register
  reg [31 : 0] rv_core_rf_rf_23_register;
  wire [31 : 0] rv_core_rf_rf_23_register$D_IN;
  wire rv_core_rf_rf_23_register$EN;

  // register rv_core_rf_rf_24_register
  reg [31 : 0] rv_core_rf_rf_24_register;
  wire [31 : 0] rv_core_rf_rf_24_register$D_IN;
  wire rv_core_rf_rf_24_register$EN;

  // register rv_core_rf_rf_25_register
  reg [31 : 0] rv_core_rf_rf_25_register;
  wire [31 : 0] rv_core_rf_rf_25_register$D_IN;
  wire rv_core_rf_rf_25_register$EN;

  // register rv_core_rf_rf_26_register
  reg [31 : 0] rv_core_rf_rf_26_register;
  wire [31 : 0] rv_core_rf_rf_26_register$D_IN;
  wire rv_core_rf_rf_26_register$EN;

  // register rv_core_rf_rf_27_register
  reg [31 : 0] rv_core_rf_rf_27_register;
  wire [31 : 0] rv_core_rf_rf_27_register$D_IN;
  wire rv_core_rf_rf_27_register$EN;

  // register rv_core_rf_rf_28_register
  reg [31 : 0] rv_core_rf_rf_28_register;
  wire [31 : 0] rv_core_rf_rf_28_register$D_IN;
  wire rv_core_rf_rf_28_register$EN;

  // register rv_core_rf_rf_29_register
  reg [31 : 0] rv_core_rf_rf_29_register;
  wire [31 : 0] rv_core_rf_rf_29_register$D_IN;
  wire rv_core_rf_rf_29_register$EN;

  // register rv_core_rf_rf_2_register
  reg [31 : 0] rv_core_rf_rf_2_register;
  wire [31 : 0] rv_core_rf_rf_2_register$D_IN;
  wire rv_core_rf_rf_2_register$EN;

  // register rv_core_rf_rf_30_register
  reg [31 : 0] rv_core_rf_rf_30_register;
  wire [31 : 0] rv_core_rf_rf_30_register$D_IN;
  wire rv_core_rf_rf_30_register$EN;

  // register rv_core_rf_rf_31_register
  reg [31 : 0] rv_core_rf_rf_31_register;
  wire [31 : 0] rv_core_rf_rf_31_register$D_IN;
  wire rv_core_rf_rf_31_register$EN;

  // register rv_core_rf_rf_3_register
  reg [31 : 0] rv_core_rf_rf_3_register;
  wire [31 : 0] rv_core_rf_rf_3_register$D_IN;
  wire rv_core_rf_rf_3_register$EN;

  // register rv_core_rf_rf_4_register
  reg [31 : 0] rv_core_rf_rf_4_register;
  wire [31 : 0] rv_core_rf_rf_4_register$D_IN;
  wire rv_core_rf_rf_4_register$EN;

  // register rv_core_rf_rf_5_register
  reg [31 : 0] rv_core_rf_rf_5_register;
  wire [31 : 0] rv_core_rf_rf_5_register$D_IN;
  wire rv_core_rf_rf_5_register$EN;

  // register rv_core_rf_rf_6_register
  reg [31 : 0] rv_core_rf_rf_6_register;
  wire [31 : 0] rv_core_rf_rf_6_register$D_IN;
  wire rv_core_rf_rf_6_register$EN;

  // register rv_core_rf_rf_7_register
  reg [31 : 0] rv_core_rf_rf_7_register;
  wire [31 : 0] rv_core_rf_rf_7_register$D_IN;
  wire rv_core_rf_rf_7_register$EN;

  // register rv_core_rf_rf_8_register
  reg [31 : 0] rv_core_rf_rf_8_register;
  wire [31 : 0] rv_core_rf_rf_8_register$D_IN;
  wire rv_core_rf_rf_8_register$EN;

  // register rv_core_rf_rf_9_register
  reg [31 : 0] rv_core_rf_rf_9_register;
  wire [31 : 0] rv_core_rf_rf_9_register$D_IN;
  wire rv_core_rf_rf_9_register$EN;

  // register rv_core_scoreboard_scores_0_register
  reg [1 : 0] rv_core_scoreboard_scores_0_register;
  wire [1 : 0] rv_core_scoreboard_scores_0_register$D_IN;
  wire rv_core_scoreboard_scores_0_register$EN;

  // register rv_core_scoreboard_scores_10_register
  reg [1 : 0] rv_core_scoreboard_scores_10_register;
  wire [1 : 0] rv_core_scoreboard_scores_10_register$D_IN;
  wire rv_core_scoreboard_scores_10_register$EN;

  // register rv_core_scoreboard_scores_11_register
  reg [1 : 0] rv_core_scoreboard_scores_11_register;
  wire [1 : 0] rv_core_scoreboard_scores_11_register$D_IN;
  wire rv_core_scoreboard_scores_11_register$EN;

  // register rv_core_scoreboard_scores_12_register
  reg [1 : 0] rv_core_scoreboard_scores_12_register;
  wire [1 : 0] rv_core_scoreboard_scores_12_register$D_IN;
  wire rv_core_scoreboard_scores_12_register$EN;

  // register rv_core_scoreboard_scores_13_register
  reg [1 : 0] rv_core_scoreboard_scores_13_register;
  wire [1 : 0] rv_core_scoreboard_scores_13_register$D_IN;
  wire rv_core_scoreboard_scores_13_register$EN;

  // register rv_core_scoreboard_scores_14_register
  reg [1 : 0] rv_core_scoreboard_scores_14_register;
  wire [1 : 0] rv_core_scoreboard_scores_14_register$D_IN;
  wire rv_core_scoreboard_scores_14_register$EN;

  // register rv_core_scoreboard_scores_15_register
  reg [1 : 0] rv_core_scoreboard_scores_15_register;
  wire [1 : 0] rv_core_scoreboard_scores_15_register$D_IN;
  wire rv_core_scoreboard_scores_15_register$EN;

  // register rv_core_scoreboard_scores_16_register
  reg [1 : 0] rv_core_scoreboard_scores_16_register;
  wire [1 : 0] rv_core_scoreboard_scores_16_register$D_IN;
  wire rv_core_scoreboard_scores_16_register$EN;

  // register rv_core_scoreboard_scores_17_register
  reg [1 : 0] rv_core_scoreboard_scores_17_register;
  wire [1 : 0] rv_core_scoreboard_scores_17_register$D_IN;
  wire rv_core_scoreboard_scores_17_register$EN;

  // register rv_core_scoreboard_scores_18_register
  reg [1 : 0] rv_core_scoreboard_scores_18_register;
  wire [1 : 0] rv_core_scoreboard_scores_18_register$D_IN;
  wire rv_core_scoreboard_scores_18_register$EN;

  // register rv_core_scoreboard_scores_19_register
  reg [1 : 0] rv_core_scoreboard_scores_19_register;
  wire [1 : 0] rv_core_scoreboard_scores_19_register$D_IN;
  wire rv_core_scoreboard_scores_19_register$EN;

  // register rv_core_scoreboard_scores_1_register
  reg [1 : 0] rv_core_scoreboard_scores_1_register;
  wire [1 : 0] rv_core_scoreboard_scores_1_register$D_IN;
  wire rv_core_scoreboard_scores_1_register$EN;

  // register rv_core_scoreboard_scores_20_register
  reg [1 : 0] rv_core_scoreboard_scores_20_register;
  wire [1 : 0] rv_core_scoreboard_scores_20_register$D_IN;
  wire rv_core_scoreboard_scores_20_register$EN;

  // register rv_core_scoreboard_scores_21_register
  reg [1 : 0] rv_core_scoreboard_scores_21_register;
  wire [1 : 0] rv_core_scoreboard_scores_21_register$D_IN;
  wire rv_core_scoreboard_scores_21_register$EN;

  // register rv_core_scoreboard_scores_22_register
  reg [1 : 0] rv_core_scoreboard_scores_22_register;
  wire [1 : 0] rv_core_scoreboard_scores_22_register$D_IN;
  wire rv_core_scoreboard_scores_22_register$EN;

  // register rv_core_scoreboard_scores_23_register
  reg [1 : 0] rv_core_scoreboard_scores_23_register;
  wire [1 : 0] rv_core_scoreboard_scores_23_register$D_IN;
  wire rv_core_scoreboard_scores_23_register$EN;

  // register rv_core_scoreboard_scores_24_register
  reg [1 : 0] rv_core_scoreboard_scores_24_register;
  wire [1 : 0] rv_core_scoreboard_scores_24_register$D_IN;
  wire rv_core_scoreboard_scores_24_register$EN;

  // register rv_core_scoreboard_scores_25_register
  reg [1 : 0] rv_core_scoreboard_scores_25_register;
  wire [1 : 0] rv_core_scoreboard_scores_25_register$D_IN;
  wire rv_core_scoreboard_scores_25_register$EN;

  // register rv_core_scoreboard_scores_26_register
  reg [1 : 0] rv_core_scoreboard_scores_26_register;
  wire [1 : 0] rv_core_scoreboard_scores_26_register$D_IN;
  wire rv_core_scoreboard_scores_26_register$EN;

  // register rv_core_scoreboard_scores_27_register
  reg [1 : 0] rv_core_scoreboard_scores_27_register;
  wire [1 : 0] rv_core_scoreboard_scores_27_register$D_IN;
  wire rv_core_scoreboard_scores_27_register$EN;

  // register rv_core_scoreboard_scores_28_register
  reg [1 : 0] rv_core_scoreboard_scores_28_register;
  wire [1 : 0] rv_core_scoreboard_scores_28_register$D_IN;
  wire rv_core_scoreboard_scores_28_register$EN;

  // register rv_core_scoreboard_scores_29_register
  reg [1 : 0] rv_core_scoreboard_scores_29_register;
  wire [1 : 0] rv_core_scoreboard_scores_29_register$D_IN;
  wire rv_core_scoreboard_scores_29_register$EN;

  // register rv_core_scoreboard_scores_2_register
  reg [1 : 0] rv_core_scoreboard_scores_2_register;
  wire [1 : 0] rv_core_scoreboard_scores_2_register$D_IN;
  wire rv_core_scoreboard_scores_2_register$EN;

  // register rv_core_scoreboard_scores_30_register
  reg [1 : 0] rv_core_scoreboard_scores_30_register;
  wire [1 : 0] rv_core_scoreboard_scores_30_register$D_IN;
  wire rv_core_scoreboard_scores_30_register$EN;

  // register rv_core_scoreboard_scores_31_register
  reg [1 : 0] rv_core_scoreboard_scores_31_register;
  wire [1 : 0] rv_core_scoreboard_scores_31_register$D_IN;
  wire rv_core_scoreboard_scores_31_register$EN;

  // register rv_core_scoreboard_scores_3_register
  reg [1 : 0] rv_core_scoreboard_scores_3_register;
  wire [1 : 0] rv_core_scoreboard_scores_3_register$D_IN;
  wire rv_core_scoreboard_scores_3_register$EN;

  // register rv_core_scoreboard_scores_4_register
  reg [1 : 0] rv_core_scoreboard_scores_4_register;
  wire [1 : 0] rv_core_scoreboard_scores_4_register$D_IN;
  wire rv_core_scoreboard_scores_4_register$EN;

  // register rv_core_scoreboard_scores_5_register
  reg [1 : 0] rv_core_scoreboard_scores_5_register;
  wire [1 : 0] rv_core_scoreboard_scores_5_register$D_IN;
  wire rv_core_scoreboard_scores_5_register$EN;

  // register rv_core_scoreboard_scores_6_register
  reg [1 : 0] rv_core_scoreboard_scores_6_register;
  wire [1 : 0] rv_core_scoreboard_scores_6_register$D_IN;
  wire rv_core_scoreboard_scores_6_register$EN;

  // register rv_core_scoreboard_scores_7_register
  reg [1 : 0] rv_core_scoreboard_scores_7_register;
  wire [1 : 0] rv_core_scoreboard_scores_7_register$D_IN;
  wire rv_core_scoreboard_scores_7_register$EN;

  // register rv_core_scoreboard_scores_8_register
  reg [1 : 0] rv_core_scoreboard_scores_8_register;
  wire [1 : 0] rv_core_scoreboard_scores_8_register$D_IN;
  wire rv_core_scoreboard_scores_8_register$EN;

  // register rv_core_scoreboard_scores_9_register
  reg [1 : 0] rv_core_scoreboard_scores_9_register;
  wire [1 : 0] rv_core_scoreboard_scores_9_register$D_IN;
  wire rv_core_scoreboard_scores_9_register$EN;

  // register rv_core_toDmem_rv
  reg [68 : 0] rv_core_toDmem_rv;
  wire [68 : 0] rv_core_toDmem_rv$D_IN;
  wire rv_core_toDmem_rv$EN;

  // register rv_core_toImem_rv
  reg [68 : 0] rv_core_toImem_rv;
  wire [68 : 0] rv_core_toImem_rv$D_IN;
  wire rv_core_toImem_rv$EN;

  // ports of submodule bram_memory
  wire [31 : 0] bram_memory$DIA,
		bram_memory$DIB,
		bram_memory$DOA,
		bram_memory$DOB;
  wire [13 : 0] bram_memory$ADDRA, bram_memory$ADDRB;
  wire [3 : 0] bram_memory$WEA, bram_memory$WEB;
  wire bram_memory$ENA, bram_memory$ENB;

  // ports of submodule bram_serverAdapterA_outDataCore
  wire [31 : 0] bram_serverAdapterA_outDataCore$D_IN,
		bram_serverAdapterA_outDataCore$D_OUT;
  wire bram_serverAdapterA_outDataCore$CLR,
       bram_serverAdapterA_outDataCore$DEQ,
       bram_serverAdapterA_outDataCore$EMPTY_N,
       bram_serverAdapterA_outDataCore$ENQ,
       bram_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule bram_serverAdapterB_outDataCore
  wire [31 : 0] bram_serverAdapterB_outDataCore$D_IN,
		bram_serverAdapterB_outDataCore$D_OUT;
  wire bram_serverAdapterB_outDataCore$CLR,
       bram_serverAdapterB_outDataCore$DEQ,
       bram_serverAdapterB_outDataCore$EMPTY_N,
       bram_serverAdapterB_outDataCore$ENQ,
       bram_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule rv_core_epoch_readBeforeLaterWrites_0
  wire rv_core_epoch_readBeforeLaterWrites_0$D_IN,
       rv_core_epoch_readBeforeLaterWrites_0$EN,
       rv_core_epoch_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_epoch_readBeforeLaterWrites_1
  wire rv_core_epoch_readBeforeLaterWrites_1$D_IN,
       rv_core_epoch_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_fromDecode
  wire [168 : 0] rv_core_fromDecode$D_IN, rv_core_fromDecode$D_OUT;
  wire rv_core_fromDecode$CLR,
       rv_core_fromDecode$DEQ,
       rv_core_fromDecode$EMPTY_N,
       rv_core_fromDecode$ENQ,
       rv_core_fromDecode$FULL_N;

  // ports of submodule rv_core_fromDmem
  wire [67 : 0] rv_core_fromDmem$D_IN, rv_core_fromDmem$D_OUT;
  wire rv_core_fromDmem$CLR,
       rv_core_fromDmem$DEQ,
       rv_core_fromDmem$EMPTY_N,
       rv_core_fromDmem$ENQ,
       rv_core_fromDmem$FULL_N;

  // ports of submodule rv_core_fromExecute
  wire [76 : 0] rv_core_fromExecute$D_IN, rv_core_fromExecute$D_OUT;
  wire rv_core_fromExecute$CLR,
       rv_core_fromExecute$DEQ,
       rv_core_fromExecute$EMPTY_N,
       rv_core_fromExecute$ENQ,
       rv_core_fromExecute$FULL_N;

  // ports of submodule rv_core_fromFetch
  wire [64 : 0] rv_core_fromFetch$D_IN, rv_core_fromFetch$D_OUT;
  wire rv_core_fromFetch$CLR,
       rv_core_fromFetch$DEQ,
       rv_core_fromFetch$EMPTY_N,
       rv_core_fromFetch$ENQ,
       rv_core_fromFetch$FULL_N;

  // ports of submodule rv_core_fromFetchprim
  wire [64 : 0] rv_core_fromFetchprim$D_IN, rv_core_fromFetchprim$D_OUT;
  wire rv_core_fromFetchprim$CLR,
       rv_core_fromFetchprim$DEQ,
       rv_core_fromFetchprim$EMPTY_N,
       rv_core_fromFetchprim$ENQ,
       rv_core_fromFetchprim$FULL_N;

  // ports of submodule rv_core_fromImem
  wire [67 : 0] rv_core_fromImem$D_IN, rv_core_fromImem$D_OUT;
  wire rv_core_fromImem$CLR,
       rv_core_fromImem$DEQ,
       rv_core_fromImem$EMPTY_N,
       rv_core_fromImem$ENQ,
       rv_core_fromImem$FULL_N;

  // ports of submodule rv_core_pc_readBeforeLaterWrites_0
  wire rv_core_pc_readBeforeLaterWrites_0$D_IN,
       rv_core_pc_readBeforeLaterWrites_0$EN,
       rv_core_pc_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_pc_readBeforeLaterWrites_1
  wire rv_core_pc_readBeforeLaterWrites_1$D_IN,
       rv_core_pc_readBeforeLaterWrites_1$EN,
       rv_core_pc_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_rf_rf_0_readBeforeLaterWrites_0
  wire rv_core_rf_rf_0_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_0_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_0_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_0_readBeforeLaterWrites_1
  wire rv_core_rf_rf_0_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_0_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_10_readBeforeLaterWrites_0
  wire rv_core_rf_rf_10_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_10_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_10_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_10_readBeforeLaterWrites_1
  wire rv_core_rf_rf_10_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_10_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_11_readBeforeLaterWrites_0
  wire rv_core_rf_rf_11_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_11_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_11_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_11_readBeforeLaterWrites_1
  wire rv_core_rf_rf_11_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_11_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_12_readBeforeLaterWrites_0
  wire rv_core_rf_rf_12_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_12_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_12_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_12_readBeforeLaterWrites_1
  wire rv_core_rf_rf_12_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_12_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_13_readBeforeLaterWrites_0
  wire rv_core_rf_rf_13_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_13_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_13_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_13_readBeforeLaterWrites_1
  wire rv_core_rf_rf_13_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_13_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_14_readBeforeLaterWrites_0
  wire rv_core_rf_rf_14_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_14_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_14_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_14_readBeforeLaterWrites_1
  wire rv_core_rf_rf_14_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_14_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_15_readBeforeLaterWrites_0
  wire rv_core_rf_rf_15_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_15_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_15_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_15_readBeforeLaterWrites_1
  wire rv_core_rf_rf_15_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_15_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_16_readBeforeLaterWrites_0
  wire rv_core_rf_rf_16_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_16_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_16_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_16_readBeforeLaterWrites_1
  wire rv_core_rf_rf_16_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_16_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_17_readBeforeLaterWrites_0
  wire rv_core_rf_rf_17_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_17_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_17_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_17_readBeforeLaterWrites_1
  wire rv_core_rf_rf_17_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_17_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_18_readBeforeLaterWrites_0
  wire rv_core_rf_rf_18_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_18_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_18_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_18_readBeforeLaterWrites_1
  wire rv_core_rf_rf_18_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_18_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_19_readBeforeLaterWrites_0
  wire rv_core_rf_rf_19_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_19_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_19_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_19_readBeforeLaterWrites_1
  wire rv_core_rf_rf_19_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_19_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_1_readBeforeLaterWrites_0
  wire rv_core_rf_rf_1_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_1_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_1_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_1_readBeforeLaterWrites_1
  wire rv_core_rf_rf_1_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_1_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_20_readBeforeLaterWrites_0
  wire rv_core_rf_rf_20_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_20_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_20_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_20_readBeforeLaterWrites_1
  wire rv_core_rf_rf_20_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_20_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_21_readBeforeLaterWrites_0
  wire rv_core_rf_rf_21_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_21_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_21_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_21_readBeforeLaterWrites_1
  wire rv_core_rf_rf_21_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_21_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_22_readBeforeLaterWrites_0
  wire rv_core_rf_rf_22_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_22_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_22_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_22_readBeforeLaterWrites_1
  wire rv_core_rf_rf_22_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_22_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_23_readBeforeLaterWrites_0
  wire rv_core_rf_rf_23_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_23_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_23_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_23_readBeforeLaterWrites_1
  wire rv_core_rf_rf_23_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_23_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_24_readBeforeLaterWrites_0
  wire rv_core_rf_rf_24_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_24_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_24_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_24_readBeforeLaterWrites_1
  wire rv_core_rf_rf_24_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_24_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_25_readBeforeLaterWrites_0
  wire rv_core_rf_rf_25_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_25_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_25_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_25_readBeforeLaterWrites_1
  wire rv_core_rf_rf_25_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_25_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_26_readBeforeLaterWrites_0
  wire rv_core_rf_rf_26_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_26_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_26_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_26_readBeforeLaterWrites_1
  wire rv_core_rf_rf_26_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_26_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_27_readBeforeLaterWrites_0
  wire rv_core_rf_rf_27_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_27_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_27_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_27_readBeforeLaterWrites_1
  wire rv_core_rf_rf_27_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_27_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_28_readBeforeLaterWrites_0
  wire rv_core_rf_rf_28_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_28_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_28_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_28_readBeforeLaterWrites_1
  wire rv_core_rf_rf_28_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_28_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_29_readBeforeLaterWrites_0
  wire rv_core_rf_rf_29_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_29_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_29_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_29_readBeforeLaterWrites_1
  wire rv_core_rf_rf_29_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_29_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_2_readBeforeLaterWrites_0
  wire rv_core_rf_rf_2_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_2_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_2_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_2_readBeforeLaterWrites_1
  wire rv_core_rf_rf_2_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_2_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_30_readBeforeLaterWrites_0
  wire rv_core_rf_rf_30_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_30_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_30_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_30_readBeforeLaterWrites_1
  wire rv_core_rf_rf_30_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_30_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_31_readBeforeLaterWrites_0
  wire rv_core_rf_rf_31_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_31_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_31_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_31_readBeforeLaterWrites_1
  wire rv_core_rf_rf_31_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_31_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_3_readBeforeLaterWrites_0
  wire rv_core_rf_rf_3_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_3_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_3_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_3_readBeforeLaterWrites_1
  wire rv_core_rf_rf_3_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_3_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_4_readBeforeLaterWrites_0
  wire rv_core_rf_rf_4_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_4_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_4_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_4_readBeforeLaterWrites_1
  wire rv_core_rf_rf_4_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_4_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_5_readBeforeLaterWrites_0
  wire rv_core_rf_rf_5_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_5_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_5_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_5_readBeforeLaterWrites_1
  wire rv_core_rf_rf_5_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_5_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_6_readBeforeLaterWrites_0
  wire rv_core_rf_rf_6_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_6_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_6_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_6_readBeforeLaterWrites_1
  wire rv_core_rf_rf_6_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_6_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_7_readBeforeLaterWrites_0
  wire rv_core_rf_rf_7_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_7_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_7_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_7_readBeforeLaterWrites_1
  wire rv_core_rf_rf_7_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_7_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_8_readBeforeLaterWrites_0
  wire rv_core_rf_rf_8_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_8_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_8_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_8_readBeforeLaterWrites_1
  wire rv_core_rf_rf_8_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_8_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_rf_rf_9_readBeforeLaterWrites_0
  wire rv_core_rf_rf_9_readBeforeLaterWrites_0$D_IN,
       rv_core_rf_rf_9_readBeforeLaterWrites_0$EN,
       rv_core_rf_rf_9_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_rf_rf_9_readBeforeLaterWrites_1
  wire rv_core_rf_rf_9_readBeforeLaterWrites_1$D_IN,
       rv_core_rf_rf_9_readBeforeLaterWrites_1$EN;

  // ports of submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_0
  wire rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$D_IN,
       rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$EN,
       rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$Q_OUT;

  // ports of submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_1
  wire rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$D_IN,
       rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$EN,
       rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$Q_OUT;

  // rule scheduling signals
  wire WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq,
       WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_requestD,
       WILL_FIRE_RL_rv_core_decode,
       WILL_FIRE_RL_rv_core_execute,
       WILL_FIRE_RL_rv_core_writeback;

  // remaining internal signals
  reg [31 : 0] rd_val__h60521, v__h60948, x__h51819, x__h58382;
  reg [3 : 0] CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5;
  reg [2 : 0] CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12;
  reg [1 : 0] old_score__h47292,
	      old_score__h61195,
	      score1__h40258,
	      score2__h40259;
  reg CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6,
      CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302,
      CASE_rv_core_fromImemD_OUT_BITS_14_TO_12_0b0__ETC__q9,
      CASE_rv_core_fromImemD_OUT_BITS_31_TO_20_0b0__ETC__q7,
      CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10,
      CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8,
      CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b11_r_ETC__q11,
      IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093;
  wire [31 : 0] IF_rv_core_fromDecode_first__002_BIT_99_031_AN_ETC___d1066,
		_theResult___fst__h59888,
		_theResult___fst__h59954,
		_theResult___fst__h59974,
		alu_src2__h60518,
		data__h58906,
		execute_bookkeeping_newrd__h60339,
		imm__h58901,
		incPC__h59791,
		mem_data__h60980,
		n__read__h53808,
		n__read__h53810,
		n__read__h53812,
		n__read__h53814,
		n__read__h53816,
		n__read__h53818,
		n__read__h53820,
		n__read__h53822,
		n__read__h53824,
		n__read__h53826,
		n__read__h53828,
		n__read__h53830,
		n__read__h53832,
		n__read__h53834,
		n__read__h53836,
		n__read__h53838,
		n__read__h53840,
		n__read__h53842,
		n__read__h53844,
		n__read__h53846,
		n__read__h53848,
		n__read__h53850,
		n__read__h53852,
		n__read__h53854,
		n__read__h53856,
		n__read__h53858,
		n__read__h53860,
		n__read__h53862,
		n__read__h53864,
		n__read__h53866,
		n__read__h53868,
		newpc__h39535,
		nextPC__h59891,
		nextPC__h59957,
		nextPc__h59778,
		rv_core_fromDecodeD_OUT_BITS_63_TO_32__q4,
		rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073,
		v__h60853,
		x__h39845,
		x__h58876,
		x__h59703,
		x__h59724,
		x__h60263,
		x__h68821,
		x__h69742;
  wire [20 : 0] x__h59538;
  wire [15 : 0] mem_data0980_BITS_15_TO_0__q2;
  wire [12 : 0] x__h59375;
  wire [11 : 0] rv_core_fromDecodeD_OUT_BITS_95_TO_84__q3, x__h59305;
  wire [7 : 0] mem_data0980_BITS_7_TO_0__q1;
  wire [4 : 0] shift_amount__h58981, x__h61031;
  wire [3 : 0] req_byte_en__h59077;
  wire [2 : 0] bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32,
	       bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91;
  wire [1 : 0] n__read__h42281,
	       n__read__h42283,
	       n__read__h42285,
	       n__read__h42287,
	       n__read__h42289,
	       n__read__h42291,
	       n__read__h42293,
	       n__read__h42295,
	       n__read__h42297,
	       n__read__h42299,
	       n__read__h42301,
	       n__read__h42303,
	       n__read__h42305,
	       n__read__h42307,
	       n__read__h42309,
	       n__read__h42311,
	       n__read__h42313,
	       n__read__h42315,
	       n__read__h42317,
	       n__read__h42319,
	       n__read__h42321,
	       n__read__h42323,
	       n__read__h42325,
	       n__read__h42327,
	       n__read__h42329,
	       n__read__h42331,
	       n__read__h42333,
	       n__read__h42335,
	       n__read__h42337,
	       n__read__h42339,
	       n__read__h42341,
	       n__read__h42343,
	       new_score__h47293,
	       new_score__h61196;
  wire NOT_rv_core_rf_rf_0_readBeforeLaterWrites_0_re_ETC___d1208,
       NOT_rv_core_rf_rf_10_readBeforeLaterWrites_0_r_ETC___d1238,
       NOT_rv_core_rf_rf_11_readBeforeLaterWrites_0_r_ETC___d1241,
       NOT_rv_core_rf_rf_12_readBeforeLaterWrites_0_r_ETC___d1244,
       NOT_rv_core_rf_rf_13_readBeforeLaterWrites_0_r_ETC___d1247,
       NOT_rv_core_rf_rf_14_readBeforeLaterWrites_0_r_ETC___d1250,
       NOT_rv_core_rf_rf_15_readBeforeLaterWrites_0_r_ETC___d1253,
       NOT_rv_core_rf_rf_16_readBeforeLaterWrites_0_r_ETC___d1256,
       NOT_rv_core_rf_rf_17_readBeforeLaterWrites_0_r_ETC___d1259,
       NOT_rv_core_rf_rf_18_readBeforeLaterWrites_0_r_ETC___d1262,
       NOT_rv_core_rf_rf_19_readBeforeLaterWrites_0_r_ETC___d1265,
       NOT_rv_core_rf_rf_1_readBeforeLaterWrites_0_re_ETC___d1211,
       NOT_rv_core_rf_rf_20_readBeforeLaterWrites_0_r_ETC___d1268,
       NOT_rv_core_rf_rf_21_readBeforeLaterWrites_0_r_ETC___d1271,
       NOT_rv_core_rf_rf_22_readBeforeLaterWrites_0_r_ETC___d1274,
       NOT_rv_core_rf_rf_23_readBeforeLaterWrites_0_r_ETC___d1277,
       NOT_rv_core_rf_rf_24_readBeforeLaterWrites_0_r_ETC___d1280,
       NOT_rv_core_rf_rf_25_readBeforeLaterWrites_0_r_ETC___d1283,
       NOT_rv_core_rf_rf_26_readBeforeLaterWrites_0_r_ETC___d1286,
       NOT_rv_core_rf_rf_27_readBeforeLaterWrites_0_r_ETC___d1289,
       NOT_rv_core_rf_rf_28_readBeforeLaterWrites_0_r_ETC___d1292,
       NOT_rv_core_rf_rf_29_readBeforeLaterWrites_0_r_ETC___d1295,
       NOT_rv_core_rf_rf_2_readBeforeLaterWrites_0_re_ETC___d1214,
       NOT_rv_core_rf_rf_30_readBeforeLaterWrites_0_r_ETC___d1298,
       NOT_rv_core_rf_rf_31_readBeforeLaterWrites_0_r_ETC___d1301,
       NOT_rv_core_rf_rf_3_readBeforeLaterWrites_0_re_ETC___d1217,
       NOT_rv_core_rf_rf_4_readBeforeLaterWrites_0_re_ETC___d1220,
       NOT_rv_core_rf_rf_5_readBeforeLaterWrites_0_re_ETC___d1223,
       NOT_rv_core_rf_rf_6_readBeforeLaterWrites_0_re_ETC___d1226,
       NOT_rv_core_rf_rf_7_readBeforeLaterWrites_0_re_ETC___d1229,
       NOT_rv_core_rf_rf_8_readBeforeLaterWrites_0_re_ETC___d1232,
       NOT_rv_core_rf_rf_9_readBeforeLaterWrites_0_re_ETC___d1235,
       SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702,
       execute_bookkeeping_isUnsigned__h60338,
       fetch_bookkeeping_epoch__h39977,
       rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1079,
       rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1083,
       rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1087,
       rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007,
       rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602,
       x__h58718,
       x__h60674,
       x__h60681;

  // submodule bram_memory
  BRAM2BELoad #(
		.PIPELINED(1'd0),
		.ADDR_WIDTH(32'd14),
		.DATA_WIDTH(32'd32),
		.CHUNKSIZE(32'd8),
		.WE_WIDTH(32'd4),
		.MEMSIZE(15'd16384)) bram_memory(.CLKA(CLK),
					   .CLKB(CLK),
					   .ADDRA(bram_memory$ADDRA),
					   .ADDRB(bram_memory$ADDRB),
					   .DIA(bram_memory$DIA),
					   .DIB(bram_memory$DIB),
					   .WEA(bram_memory$WEA),
					   .WEB(bram_memory$WEB),
					   .ENA(bram_memory$ENA),
					   .ENB(bram_memory$ENB),
					   .DOA(bram_memory$DOA),
					   .DOB(bram_memory$DOB));

  // submodule bram_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterA_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterA_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterA_outDataCore$DEQ),
							       .CLR(bram_serverAdapterA_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterA_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterA_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterA_outDataCore$EMPTY_N));

  // submodule bram_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterB_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterB_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterB_outDataCore$DEQ),
							       .CLR(bram_serverAdapterB_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterB_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterB_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N));

  // submodule rv_core_epoch_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_epoch_readBeforeLaterWrites_0(.CLK(CLK),
								 .D_IN(rv_core_epoch_readBeforeLaterWrites_0$D_IN),
								 .EN(rv_core_epoch_readBeforeLaterWrites_0$EN),
								 .Q_OUT(rv_core_epoch_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_epoch_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_epoch_readBeforeLaterWrites_1(.CLK(CLK),
								 .D_IN(rv_core_epoch_readBeforeLaterWrites_1$D_IN),
								 .EN(rv_core_epoch_readBeforeLaterWrites_1$EN),
								 .Q_OUT());

  // submodule rv_core_fromDecode
  FIFOL1 #(.width(32'd169)) rv_core_fromDecode(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(rv_core_fromDecode$D_IN),
					       .ENQ(rv_core_fromDecode$ENQ),
					       .DEQ(rv_core_fromDecode$DEQ),
					       .CLR(rv_core_fromDecode$CLR),
					       .D_OUT(rv_core_fromDecode$D_OUT),
					       .FULL_N(rv_core_fromDecode$FULL_N),
					       .EMPTY_N(rv_core_fromDecode$EMPTY_N));

  // submodule rv_core_fromDmem
  FIFOL1 #(.width(32'd68)) rv_core_fromDmem(.RST(RST_N),
					    .CLK(CLK),
					    .D_IN(rv_core_fromDmem$D_IN),
					    .ENQ(rv_core_fromDmem$ENQ),
					    .DEQ(rv_core_fromDmem$DEQ),
					    .CLR(rv_core_fromDmem$CLR),
					    .D_OUT(rv_core_fromDmem$D_OUT),
					    .FULL_N(rv_core_fromDmem$FULL_N),
					    .EMPTY_N(rv_core_fromDmem$EMPTY_N));

  // submodule rv_core_fromExecute
  FIFOL1 #(.width(32'd77)) rv_core_fromExecute(.RST(RST_N),
					       .CLK(CLK),
					       .D_IN(rv_core_fromExecute$D_IN),
					       .ENQ(rv_core_fromExecute$ENQ),
					       .DEQ(rv_core_fromExecute$DEQ),
					       .CLR(rv_core_fromExecute$CLR),
					       .D_OUT(rv_core_fromExecute$D_OUT),
					       .FULL_N(rv_core_fromExecute$FULL_N),
					       .EMPTY_N(rv_core_fromExecute$EMPTY_N));

  // submodule rv_core_fromFetch
  FIFOL1 #(.width(32'd65)) rv_core_fromFetch(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(rv_core_fromFetch$D_IN),
					     .ENQ(rv_core_fromFetch$ENQ),
					     .DEQ(rv_core_fromFetch$DEQ),
					     .CLR(rv_core_fromFetch$CLR),
					     .D_OUT(rv_core_fromFetch$D_OUT),
					     .FULL_N(rv_core_fromFetch$FULL_N),
					     .EMPTY_N(rv_core_fromFetch$EMPTY_N));

  // submodule rv_core_fromFetchprim
  FIFOL1 #(.width(32'd65)) rv_core_fromFetchprim(.RST(RST_N),
						 .CLK(CLK),
						 .D_IN(rv_core_fromFetchprim$D_IN),
						 .ENQ(rv_core_fromFetchprim$ENQ),
						 .DEQ(rv_core_fromFetchprim$DEQ),
						 .CLR(rv_core_fromFetchprim$CLR),
						 .D_OUT(rv_core_fromFetchprim$D_OUT),
						 .FULL_N(rv_core_fromFetchprim$FULL_N),
						 .EMPTY_N(rv_core_fromFetchprim$EMPTY_N));

  // submodule rv_core_fromImem
  FIFOL1 #(.width(32'd68)) rv_core_fromImem(.RST(RST_N),
					    .CLK(CLK),
					    .D_IN(rv_core_fromImem$D_IN),
					    .ENQ(rv_core_fromImem$ENQ),
					    .DEQ(rv_core_fromImem$DEQ),
					    .CLR(rv_core_fromImem$CLR),
					    .D_OUT(rv_core_fromImem$D_OUT),
					    .FULL_N(rv_core_fromImem$FULL_N),
					    .EMPTY_N(rv_core_fromImem$EMPTY_N));

  // submodule rv_core_pc_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_pc_readBeforeLaterWrites_0(.CLK(CLK),
							      .D_IN(rv_core_pc_readBeforeLaterWrites_0$D_IN),
							      .EN(rv_core_pc_readBeforeLaterWrites_0$EN),
							      .Q_OUT(rv_core_pc_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_pc_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_pc_readBeforeLaterWrites_1(.CLK(CLK),
							      .D_IN(rv_core_pc_readBeforeLaterWrites_1$D_IN),
							      .EN(rv_core_pc_readBeforeLaterWrites_1$EN),
							      .Q_OUT(rv_core_pc_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_rf_rf_0_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_0_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_0_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_0_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_0_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_0_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_0_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_0_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_0_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_10_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_10_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_10_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_10_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_10_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_10_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_10_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_10_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_10_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_11_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_11_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_11_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_11_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_11_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_11_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_11_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_11_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_11_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_12_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_12_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_12_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_12_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_12_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_12_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_12_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_12_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_12_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_13_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_13_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_13_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_13_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_13_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_13_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_13_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_13_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_13_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_14_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_14_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_14_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_14_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_14_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_14_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_14_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_14_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_14_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_15_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_15_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_15_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_15_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_15_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_15_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_15_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_15_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_15_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_16_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_16_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_16_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_16_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_16_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_16_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_16_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_16_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_16_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_17_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_17_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_17_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_17_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_17_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_17_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_17_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_17_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_17_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_18_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_18_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_18_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_18_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_18_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_18_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_18_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_18_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_18_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_19_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_19_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_19_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_19_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_19_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_19_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_19_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_19_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_19_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_1_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_1_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_1_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_1_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_1_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_1_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_1_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_1_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_1_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_20_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_20_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_20_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_20_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_20_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_20_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_20_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_20_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_20_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_21_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_21_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_21_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_21_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_21_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_21_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_21_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_21_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_21_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_22_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_22_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_22_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_22_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_22_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_22_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_22_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_22_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_22_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_23_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_23_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_23_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_23_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_23_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_23_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_23_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_23_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_23_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_24_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_24_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_24_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_24_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_24_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_24_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_24_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_24_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_24_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_25_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_25_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_25_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_25_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_25_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_25_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_25_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_25_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_25_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_26_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_26_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_26_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_26_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_26_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_26_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_26_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_26_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_26_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_27_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_27_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_27_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_27_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_27_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_27_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_27_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_27_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_27_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_28_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_28_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_28_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_28_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_28_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_28_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_28_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_28_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_28_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_29_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_29_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_29_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_29_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_29_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_29_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_29_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_29_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_29_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_2_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_2_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_2_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_2_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_2_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_2_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_2_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_2_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_2_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_30_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_30_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_30_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_30_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_30_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_30_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_30_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_30_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_30_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_31_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_31_readBeforeLaterWrites_0(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_31_readBeforeLaterWrites_0$D_IN),
								    .EN(rv_core_rf_rf_31_readBeforeLaterWrites_0$EN),
								    .Q_OUT(rv_core_rf_rf_31_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_31_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_31_readBeforeLaterWrites_1(.CLK(CLK),
								    .D_IN(rv_core_rf_rf_31_readBeforeLaterWrites_1$D_IN),
								    .EN(rv_core_rf_rf_31_readBeforeLaterWrites_1$EN),
								    .Q_OUT());

  // submodule rv_core_rf_rf_3_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_3_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_3_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_3_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_3_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_3_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_3_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_3_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_3_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_4_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_4_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_4_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_4_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_4_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_4_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_4_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_4_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_4_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_5_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_5_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_5_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_5_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_5_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_5_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_5_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_5_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_5_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_6_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_6_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_6_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_6_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_6_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_6_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_6_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_6_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_6_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_7_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_7_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_7_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_7_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_7_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_7_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_7_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_7_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_7_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_8_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_8_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_8_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_8_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_8_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_8_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_8_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_8_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_8_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_rf_rf_9_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_9_readBeforeLaterWrites_0(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_9_readBeforeLaterWrites_0$D_IN),
								   .EN(rv_core_rf_rf_9_readBeforeLaterWrites_0$EN),
								   .Q_OUT(rv_core_rf_rf_9_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_rf_rf_9_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_rf_rf_9_readBeforeLaterWrites_1(.CLK(CLK),
								   .D_IN(rv_core_rf_rf_9_readBeforeLaterWrites_1$D_IN),
								   .EN(rv_core_rf_rf_9_readBeforeLaterWrites_1$EN),
								   .Q_OUT());

  // submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_0_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_0_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_10_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_10_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_11_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_11_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_12_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_12_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_13_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_13_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_14_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_14_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_15_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_15_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_16_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_16_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_17_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_17_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_18_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_18_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_19_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_19_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_1_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_1_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_20_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_20_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_21_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_21_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_22_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_22_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_23_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_23_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_24_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_24_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_25_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_25_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_26_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_26_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_27_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_27_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_28_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_28_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_29_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_29_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_2_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_2_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_30_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_30_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_31_readBeforeLaterWrites_0(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$D_IN),
										.EN(rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$EN),
										.Q_OUT(rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_31_readBeforeLaterWrites_1(.CLK(CLK),
										.D_IN(rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$D_IN),
										.EN(rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$EN),
										.Q_OUT(rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_3_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_3_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_4_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_4_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_5_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_5_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_6_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_6_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_7_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_7_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_8_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_8_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$Q_OUT));

  // submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_9_readBeforeLaterWrites_0(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$D_IN),
									       .EN(rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$EN),
									       .Q_OUT(rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$Q_OUT));

  // submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) rv_core_scoreboard_scores_9_readBeforeLaterWrites_1(.CLK(CLK),
									       .D_IN(rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$D_IN),
									       .EN(rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$EN),
									       .Q_OUT(rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$Q_OUT));

  // rule RL_rv_core_writeback
  assign WILL_FIRE_RL_rv_core_writeback =
	     rv_core_fromExecute$EMPTY_N &&
	     (rv_core_fromExecute$D_OUT[6] ||
	      rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	      rv_core_fromDmem$EMPTY_N) &&
	     (!rv_core_fromExecute$D_OUT[36] ||
	      rv_core_fromExecute$D_OUT[11:7] == 5'd0 ||
	      CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302) ;

  // rule RL_bram_serverAdapterA_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq =
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;

  // rule RL_rv_core_execute
  assign WILL_FIRE_RL_rv_core_execute =
	     rv_core_fromDecode$EMPTY_N &&
	     (!rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007 ||
	      !rv_core_fromDecode$D_OUT[103] ||
	      rv_core_fromExecute$FULL_N &&
	      (rv_core_fromDecode$D_OUT[70] ||
	       rv_core_fromDecode$D_OUT[68:67] != 2'b0 ||
	       !rv_core_toDmem_rv[68])) ;

  // rule RL_requestD
  assign WILL_FIRE_RL_requestD =
	     rv_core_toDmem_rv$port1__read[68] &&
	     (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;

  // rule RL_rv_core_decode
  assign WILL_FIRE_RL_rv_core_decode =
	     rv_core_fromFetchprim$EMPTY_N && rv_core_fromImem$EMPTY_N &&
	     (!rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 ||
	      score1__h40258 != 2'd0 ||
	      score2__h40259 != 2'd0 ||
	      rv_core_fromDecode$FULL_N) ;

  // rule RL_bram_serverAdapterB_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq =
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;

  // inlined wires
  assign bram_serverAdapterA_outData_enqData$whas =
	     (!bram_serverAdapterA_s1[0] ||
	      bram_serverAdapterA_outDataCore$FULL_N) &&
	     bram_serverAdapterA_s1[1] &&
	     bram_serverAdapterA_s1[0] ;
  assign bram_serverAdapterA_outData_outData$whas =
	     bram_serverAdapterA_outDataCore$EMPTY_N ||
	     !bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_cnt_1$whas =
	     rv_core_toDmem_rv$port1__read[68] &&
	     (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
	     (!bram_serverAdapterA_writeWithResp$wget[1] ||
	      bram_serverAdapterA_writeWithResp$wget[0]) ;
  assign bram_serverAdapterA_writeWithResp$wget =
	     { rv_core_toDmem_rv$port1__read[67:64] != 4'd0, 1'd1 } ;
  assign bram_serverAdapterA_s1_1$wget =
	     { 1'd1,
	       !bram_serverAdapterA_writeWithResp$wget[1] ||
	       bram_serverAdapterA_writeWithResp$wget[0] } ;
  assign bram_serverAdapterB_outData_enqData$whas =
	     (!bram_serverAdapterB_s1[0] ||
	      bram_serverAdapterB_outDataCore$FULL_N) &&
	     bram_serverAdapterB_s1[1] &&
	     bram_serverAdapterB_s1[0] ;
  assign bram_serverAdapterB_outData_outData$whas =
	     bram_serverAdapterB_outDataCore$EMPTY_N ||
	     !bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_cnt_1$whas =
	     rv_core_toImem_rv$port1__read[68] &&
	     (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 &&
	     (!bram_serverAdapterB_writeWithResp$wget[1] ||
	      bram_serverAdapterB_writeWithResp$wget[0]) ;
  assign bram_serverAdapterB_writeWithResp$wget =
	     { rv_core_toImem_rv$port1__read[67:64] != 4'd0, 1'd1 } ;
  assign bram_serverAdapterB_writeWithResp$whas =
	     rv_core_toImem_rv$port1__read[68] &&
	     (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
  assign bram_serverAdapterB_s1_1$wget =
	     { 1'd1,
	       !bram_serverAdapterB_writeWithResp$wget[1] ||
	       bram_serverAdapterB_writeWithResp$wget[0] } ;
  assign rv_core_rf_rf_1_port_0$wget =
	     rv_core_rf_rf_1_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_1_register ;
  assign rv_core_rf_rf_1_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd1 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_2_port_0$wget =
	     rv_core_rf_rf_2_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_2_register ;
  assign rv_core_rf_rf_2_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd2 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_3_port_0$wget =
	     rv_core_rf_rf_3_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_3_register ;
  assign rv_core_rf_rf_3_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd3 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_4_port_0$wget =
	     rv_core_rf_rf_4_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_4_register ;
  assign rv_core_rf_rf_4_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd4 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_5_port_0$wget =
	     rv_core_rf_rf_5_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_5_register ;
  assign rv_core_rf_rf_5_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd5 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_6_port_0$wget =
	     rv_core_rf_rf_6_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_6_register ;
  assign rv_core_rf_rf_6_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd6 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_7_port_0$wget =
	     rv_core_rf_rf_7_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_7_register ;
  assign rv_core_rf_rf_7_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd7 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_8_port_0$wget =
	     rv_core_rf_rf_8_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_8_register ;
  assign rv_core_rf_rf_8_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd8 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_9_port_0$wget =
	     rv_core_rf_rf_9_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_9_register ;
  assign rv_core_rf_rf_9_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd9 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_10_port_0$wget =
	     rv_core_rf_rf_10_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_10_register ;
  assign rv_core_rf_rf_10_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd10 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_11_port_0$wget =
	     rv_core_rf_rf_11_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_11_register ;
  assign rv_core_rf_rf_11_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd11 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_12_port_0$wget =
	     rv_core_rf_rf_12_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_12_register ;
  assign rv_core_rf_rf_12_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd12 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_13_port_0$wget =
	     rv_core_rf_rf_13_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_13_register ;
  assign rv_core_rf_rf_13_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd13 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_14_port_0$wget =
	     rv_core_rf_rf_14_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_14_register ;
  assign rv_core_rf_rf_14_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd14 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_15_port_0$wget =
	     rv_core_rf_rf_15_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_15_register ;
  assign rv_core_rf_rf_15_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd15 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_16_port_0$wget =
	     rv_core_rf_rf_16_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_16_register ;
  assign rv_core_rf_rf_16_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd16 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_17_port_0$wget =
	     rv_core_rf_rf_17_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_17_register ;
  assign rv_core_rf_rf_17_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd17 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_18_port_0$wget =
	     rv_core_rf_rf_18_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_18_register ;
  assign rv_core_rf_rf_18_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd18 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_19_port_0$wget =
	     rv_core_rf_rf_19_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_19_register ;
  assign rv_core_rf_rf_19_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd19 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_20_port_0$wget =
	     rv_core_rf_rf_20_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_20_register ;
  assign rv_core_rf_rf_20_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd20 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_21_port_0$wget =
	     rv_core_rf_rf_21_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_21_register ;
  assign rv_core_rf_rf_21_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd21 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_22_port_0$wget =
	     rv_core_rf_rf_22_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_22_register ;
  assign rv_core_rf_rf_22_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd22 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_23_port_0$wget =
	     rv_core_rf_rf_23_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_23_register ;
  assign rv_core_rf_rf_23_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd23 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_24_port_0$wget =
	     rv_core_rf_rf_24_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_24_register ;
  assign rv_core_rf_rf_24_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd24 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_25_port_0$wget =
	     rv_core_rf_rf_25_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_25_register ;
  assign rv_core_rf_rf_25_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd25 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_26_port_0$wget =
	     rv_core_rf_rf_26_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_26_register ;
  assign rv_core_rf_rf_26_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd26 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_27_port_0$wget =
	     rv_core_rf_rf_27_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_27_register ;
  assign rv_core_rf_rf_27_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd27 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_28_port_0$wget =
	     rv_core_rf_rf_28_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_28_register ;
  assign rv_core_rf_rf_28_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd28 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_29_port_0$wget =
	     rv_core_rf_rf_29_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_29_register ;
  assign rv_core_rf_rf_29_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd29 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_30_port_0$wget =
	     rv_core_rf_rf_30_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_30_register ;
  assign rv_core_rf_rf_30_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd30 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_rf_rf_31_port_0$wget =
	     rv_core_rf_rf_31_readBeforeLaterWrites_0$Q_OUT ?
	       v__h60853 :
	       rv_core_rf_rf_31_register ;
  assign rv_core_rf_rf_31_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd31 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_pc_port_0$wget =
	     rv_core_fromDecode$D_OUT[103] ? x__h60263 : x__h58876 ;
  assign rv_core_pc_port_0$whas =
	     WILL_FIRE_RL_rv_core_execute &&
	     rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007 &&
	     (nextPc__h59778 != rv_core_fromDecode$D_OUT[136:105] ||
	      !rv_core_fromDecode$D_OUT[103]) ;
  assign rv_core_pc_port_1$wget =
	     rv_core_pc_readBeforeLaterWrites_1$Q_OUT ?
	       x__h39845 :
	       newpc__h39535 ;
  assign rv_core_pc_port_1$whas =
	     !rv_core_toImem_rv[68] && rv_core_fromFetch$FULL_N ;
  assign rv_core_epoch_port_0$wget =
	     rv_core_epoch_readBeforeLaterWrites_0$Q_OUT ?
	       x__h58718 :
	       rv_core_epoch_register ;
  assign rv_core_scoreboard_scores_0_port_0$wget =
	     rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_0_register ;
  assign rv_core_scoreboard_scores_0_port_0$whas =
	     WILL_FIRE_RL_rv_core_writeback &&
	     rv_core_fromExecute$D_OUT[11:7] == 5'd0 &&
	     rv_core_fromExecute$D_OUT[36] ;
  assign rv_core_scoreboard_scores_0_port_1$wget =
	     rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42281 ;
  assign rv_core_scoreboard_scores_0_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd0 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_1_port_0$wget =
	     rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_1_register ;
  assign rv_core_scoreboard_scores_1_port_1$wget =
	     rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42283 ;
  assign rv_core_scoreboard_scores_1_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd1 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_2_port_0$wget =
	     rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_2_register ;
  assign rv_core_scoreboard_scores_2_port_1$wget =
	     rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42285 ;
  assign rv_core_scoreboard_scores_2_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd2 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_3_port_0$wget =
	     rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_3_register ;
  assign rv_core_scoreboard_scores_3_port_1$wget =
	     rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42287 ;
  assign rv_core_scoreboard_scores_3_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd3 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_4_port_0$wget =
	     rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_4_register ;
  assign rv_core_scoreboard_scores_4_port_1$wget =
	     rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42289 ;
  assign rv_core_scoreboard_scores_4_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd4 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_5_port_0$wget =
	     rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_5_register ;
  assign rv_core_scoreboard_scores_5_port_1$wget =
	     rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42291 ;
  assign rv_core_scoreboard_scores_5_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd5 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_6_port_0$wget =
	     rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_6_register ;
  assign rv_core_scoreboard_scores_6_port_1$wget =
	     rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42293 ;
  assign rv_core_scoreboard_scores_6_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd6 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_7_port_0$wget =
	     rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_7_register ;
  assign rv_core_scoreboard_scores_7_port_1$wget =
	     rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42295 ;
  assign rv_core_scoreboard_scores_7_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd7 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_8_port_0$wget =
	     rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_8_register ;
  assign rv_core_scoreboard_scores_8_port_1$wget =
	     rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42297 ;
  assign rv_core_scoreboard_scores_8_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd8 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_9_port_0$wget =
	     rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_9_register ;
  assign rv_core_scoreboard_scores_9_port_1$wget =
	     rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42299 ;
  assign rv_core_scoreboard_scores_9_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd9 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_10_port_0$wget =
	     rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_10_register ;
  assign rv_core_scoreboard_scores_10_port_1$wget =
	     rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42301 ;
  assign rv_core_scoreboard_scores_10_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd10 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_11_port_0$wget =
	     rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_11_register ;
  assign rv_core_scoreboard_scores_11_port_1$wget =
	     rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42303 ;
  assign rv_core_scoreboard_scores_11_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd11 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_12_port_0$wget =
	     rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_12_register ;
  assign rv_core_scoreboard_scores_12_port_1$wget =
	     rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42305 ;
  assign rv_core_scoreboard_scores_12_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd12 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_13_port_0$wget =
	     rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_13_register ;
  assign rv_core_scoreboard_scores_13_port_1$wget =
	     rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42307 ;
  assign rv_core_scoreboard_scores_13_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd13 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_14_port_0$wget =
	     rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_14_register ;
  assign rv_core_scoreboard_scores_14_port_1$wget =
	     rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42309 ;
  assign rv_core_scoreboard_scores_14_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd14 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_15_port_0$wget =
	     rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_15_register ;
  assign rv_core_scoreboard_scores_15_port_1$wget =
	     rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42311 ;
  assign rv_core_scoreboard_scores_15_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd15 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_16_port_0$wget =
	     rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_16_register ;
  assign rv_core_scoreboard_scores_16_port_1$wget =
	     rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42313 ;
  assign rv_core_scoreboard_scores_16_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd16 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_17_port_0$wget =
	     rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_17_register ;
  assign rv_core_scoreboard_scores_17_port_1$wget =
	     rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42315 ;
  assign rv_core_scoreboard_scores_17_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd17 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_18_port_0$wget =
	     rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_18_register ;
  assign rv_core_scoreboard_scores_18_port_1$wget =
	     rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42317 ;
  assign rv_core_scoreboard_scores_18_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd18 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_19_port_0$wget =
	     rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_19_register ;
  assign rv_core_scoreboard_scores_19_port_1$wget =
	     rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42319 ;
  assign rv_core_scoreboard_scores_19_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd19 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_20_port_0$wget =
	     rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_20_register ;
  assign rv_core_scoreboard_scores_20_port_1$wget =
	     rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42321 ;
  assign rv_core_scoreboard_scores_20_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd20 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_21_port_0$wget =
	     rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_21_register ;
  assign rv_core_scoreboard_scores_21_port_1$wget =
	     rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42323 ;
  assign rv_core_scoreboard_scores_21_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd21 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_22_port_0$wget =
	     rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_22_register ;
  assign rv_core_scoreboard_scores_22_port_1$wget =
	     rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42325 ;
  assign rv_core_scoreboard_scores_22_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd22 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_23_port_0$wget =
	     rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_23_register ;
  assign rv_core_scoreboard_scores_23_port_1$wget =
	     rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42327 ;
  assign rv_core_scoreboard_scores_23_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd23 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_24_port_0$wget =
	     rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_24_register ;
  assign rv_core_scoreboard_scores_24_port_1$wget =
	     rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42329 ;
  assign rv_core_scoreboard_scores_24_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd24 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_25_port_0$wget =
	     rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_25_register ;
  assign rv_core_scoreboard_scores_25_port_1$wget =
	     rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42331 ;
  assign rv_core_scoreboard_scores_25_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd25 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_26_port_0$wget =
	     rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_26_register ;
  assign rv_core_scoreboard_scores_26_port_1$wget =
	     rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42333 ;
  assign rv_core_scoreboard_scores_26_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd26 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_27_port_0$wget =
	     rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_27_register ;
  assign rv_core_scoreboard_scores_27_port_1$wget =
	     rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42335 ;
  assign rv_core_scoreboard_scores_27_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd27 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_28_port_0$wget =
	     rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_28_register ;
  assign rv_core_scoreboard_scores_28_port_1$wget =
	     rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42337 ;
  assign rv_core_scoreboard_scores_28_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd28 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_29_port_0$wget =
	     rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_29_register ;
  assign rv_core_scoreboard_scores_29_port_1$wget =
	     rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42339 ;
  assign rv_core_scoreboard_scores_29_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd29 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_30_port_0$wget =
	     rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_30_register ;
  assign rv_core_scoreboard_scores_30_port_1$wget =
	     rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42341 ;
  assign rv_core_scoreboard_scores_30_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd30 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign rv_core_scoreboard_scores_31_port_0$wget =
	     rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$Q_OUT ?
	       new_score__h61196 :
	       rv_core_scoreboard_scores_31_register ;
  assign rv_core_scoreboard_scores_31_port_1$wget =
	     rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$Q_OUT ?
	       new_score__h47293 :
	       n__read__h42343 ;
  assign rv_core_scoreboard_scores_31_port_1$whas =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromImem$D_OUT[11:7] == 5'd31 &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 ;
  assign bram_serverAdapterA_outData_deqCalled$whas =
	     (bram_serverAdapterA_outDataCore$EMPTY_N ||
	      bram_serverAdapterA_outData_enqData$whas) &&
	     bram_serverAdapterA_outData_outData$whas &&
	     rv_core_fromDmem$FULL_N ;
  assign bram_serverAdapterB_outData_deqCalled$whas =
	     (bram_serverAdapterB_outDataCore$EMPTY_N ||
	      bram_serverAdapterB_outData_enqData$whas) &&
	     bram_serverAdapterB_outData_outData$whas &&
	     rv_core_fromImem$FULL_N ;
  assign rv_core_toImem_rv$EN_port0__write =
	     !rv_core_toImem_rv[68] && rv_core_fromFetch$FULL_N ;
  assign rv_core_toImem_rv$port0__write_1 = { 5'd16, newpc__h39535, 32'd0 } ;
  assign rv_core_toImem_rv$port1__read =
	     rv_core_toImem_rv$EN_port0__write ?
	       rv_core_toImem_rv$port0__write_1 :
	       rv_core_toImem_rv ;
  assign rv_core_toImem_rv$EN_port1__write =
	     rv_core_toImem_rv$port1__read[68] &&
	     (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
  assign rv_core_toImem_rv$port2__read =
	     rv_core_toImem_rv$EN_port1__write ?
	       69'h0AAAAAAAAAAAAAAAAA :
	       rv_core_toImem_rv$port1__read ;
  assign rv_core_toDmem_rv$EN_port0__write =
	     WILL_FIRE_RL_rv_core_execute &&
	     rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007 &&
	     rv_core_fromDecode$D_OUT[103] &&
	     !rv_core_fromDecode$D_OUT[70] &&
	     rv_core_fromDecode$D_OUT[68:67] == 2'b0 ;
  assign rv_core_toDmem_rv$port0__write_1 =
	     { 1'd1, req_byte_en__h59077, x__h59703, x__h59724 } ;
  assign rv_core_toDmem_rv$port1__read =
	     rv_core_toDmem_rv$EN_port0__write ?
	       rv_core_toDmem_rv$port0__write_1 :
	       rv_core_toDmem_rv ;
  assign rv_core_toDmem_rv$port2__read =
	     WILL_FIRE_RL_requestD ?
	       69'h0AAAAAAAAAAAAAAAAA :
	       rv_core_toDmem_rv$port1__read ;

  // register bram_serverAdapterA_cnt
  assign bram_serverAdapterA_cnt$D_IN =
	     bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 ;
  assign bram_serverAdapterA_cnt$EN =
	     bram_serverAdapterA_cnt_1$whas ||
	     bram_serverAdapterA_outData_deqCalled$whas ;

  // register bram_serverAdapterA_s1
  assign bram_serverAdapterA_s1$D_IN =
	     { WILL_FIRE_RL_requestD && bram_serverAdapterA_s1_1$wget[1],
	       bram_serverAdapterA_s1_1$wget[0] } ;
  assign bram_serverAdapterA_s1$EN = 1'd1 ;

  // register bram_serverAdapterB_cnt
  assign bram_serverAdapterB_cnt$D_IN =
	     bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 ;
  assign bram_serverAdapterB_cnt$EN =
	     bram_serverAdapterB_cnt_1$whas ||
	     bram_serverAdapterB_outData_deqCalled$whas ;

  // register bram_serverAdapterB_s1
  assign bram_serverAdapterB_s1$D_IN =
	     { bram_serverAdapterB_writeWithResp$whas &&
	       bram_serverAdapterB_s1_1$wget[1],
	       bram_serverAdapterB_s1_1$wget[0] } ;
  assign bram_serverAdapterB_s1$EN = 1'd1 ;

  // register cycle_count
  assign cycle_count$D_IN = cycle_count + 32'd1 ;
  assign cycle_count$EN = 1'd1 ;

  // register dreq
  assign dreq$D_IN = rv_core_toDmem_rv$port1__read[67:0] ;
  assign dreq$EN = WILL_FIRE_RL_requestD ;

  // register ireq
  assign ireq$D_IN = rv_core_toImem_rv$port1__read[67:0] ;
  assign ireq$EN = bram_serverAdapterB_writeWithResp$whas ;

  // register rv_core_epoch_register
  assign rv_core_epoch_register$D_IN = fetch_bookkeeping_epoch__h39977 ;
  assign rv_core_epoch_register$EN = 1'd1 ;

  // register rv_core_instr_count
  assign rv_core_instr_count$D_IN = rv_core_instr_count + 32'd1 ;
  assign rv_core_instr_count$EN = WILL_FIRE_RL_rv_core_writeback ;

  // register rv_core_pc_register
  assign rv_core_pc_register$D_IN =
	     rv_core_pc_port_1$whas ? rv_core_pc_port_1$wget : newpc__h39535 ;
  assign rv_core_pc_register$EN = 1'd1 ;

  // register rv_core_rf_rf_0_register
  assign rv_core_rf_rf_0_register$D_IN = rv_core_rf_rf_0_register ;
  assign rv_core_rf_rf_0_register$EN = 1'd1 ;

  // register rv_core_rf_rf_10_register
  assign rv_core_rf_rf_10_register$D_IN = n__read__h53826 ;
  assign rv_core_rf_rf_10_register$EN = 1'd1 ;

  // register rv_core_rf_rf_11_register
  assign rv_core_rf_rf_11_register$D_IN = n__read__h53828 ;
  assign rv_core_rf_rf_11_register$EN = 1'd1 ;

  // register rv_core_rf_rf_12_register
  assign rv_core_rf_rf_12_register$D_IN = n__read__h53830 ;
  assign rv_core_rf_rf_12_register$EN = 1'd1 ;

  // register rv_core_rf_rf_13_register
  assign rv_core_rf_rf_13_register$D_IN = n__read__h53832 ;
  assign rv_core_rf_rf_13_register$EN = 1'd1 ;

  // register rv_core_rf_rf_14_register
  assign rv_core_rf_rf_14_register$D_IN = n__read__h53834 ;
  assign rv_core_rf_rf_14_register$EN = 1'd1 ;

  // register rv_core_rf_rf_15_register
  assign rv_core_rf_rf_15_register$D_IN = n__read__h53836 ;
  assign rv_core_rf_rf_15_register$EN = 1'd1 ;

  // register rv_core_rf_rf_16_register
  assign rv_core_rf_rf_16_register$D_IN = n__read__h53838 ;
  assign rv_core_rf_rf_16_register$EN = 1'd1 ;

  // register rv_core_rf_rf_17_register
  assign rv_core_rf_rf_17_register$D_IN = n__read__h53840 ;
  assign rv_core_rf_rf_17_register$EN = 1'd1 ;

  // register rv_core_rf_rf_18_register
  assign rv_core_rf_rf_18_register$D_IN = n__read__h53842 ;
  assign rv_core_rf_rf_18_register$EN = 1'd1 ;

  // register rv_core_rf_rf_19_register
  assign rv_core_rf_rf_19_register$D_IN = n__read__h53844 ;
  assign rv_core_rf_rf_19_register$EN = 1'd1 ;

  // register rv_core_rf_rf_1_register
  assign rv_core_rf_rf_1_register$D_IN = n__read__h53808 ;
  assign rv_core_rf_rf_1_register$EN = 1'd1 ;

  // register rv_core_rf_rf_20_register
  assign rv_core_rf_rf_20_register$D_IN = n__read__h53846 ;
  assign rv_core_rf_rf_20_register$EN = 1'd1 ;

  // register rv_core_rf_rf_21_register
  assign rv_core_rf_rf_21_register$D_IN = n__read__h53848 ;
  assign rv_core_rf_rf_21_register$EN = 1'd1 ;

  // register rv_core_rf_rf_22_register
  assign rv_core_rf_rf_22_register$D_IN = n__read__h53850 ;
  assign rv_core_rf_rf_22_register$EN = 1'd1 ;

  // register rv_core_rf_rf_23_register
  assign rv_core_rf_rf_23_register$D_IN = n__read__h53852 ;
  assign rv_core_rf_rf_23_register$EN = 1'd1 ;

  // register rv_core_rf_rf_24_register
  assign rv_core_rf_rf_24_register$D_IN = n__read__h53854 ;
  assign rv_core_rf_rf_24_register$EN = 1'd1 ;

  // register rv_core_rf_rf_25_register
  assign rv_core_rf_rf_25_register$D_IN = n__read__h53856 ;
  assign rv_core_rf_rf_25_register$EN = 1'd1 ;

  // register rv_core_rf_rf_26_register
  assign rv_core_rf_rf_26_register$D_IN = n__read__h53858 ;
  assign rv_core_rf_rf_26_register$EN = 1'd1 ;

  // register rv_core_rf_rf_27_register
  assign rv_core_rf_rf_27_register$D_IN = n__read__h53860 ;
  assign rv_core_rf_rf_27_register$EN = 1'd1 ;

  // register rv_core_rf_rf_28_register
  assign rv_core_rf_rf_28_register$D_IN = n__read__h53862 ;
  assign rv_core_rf_rf_28_register$EN = 1'd1 ;

  // register rv_core_rf_rf_29_register
  assign rv_core_rf_rf_29_register$D_IN = n__read__h53864 ;
  assign rv_core_rf_rf_29_register$EN = 1'd1 ;

  // register rv_core_rf_rf_2_register
  assign rv_core_rf_rf_2_register$D_IN = n__read__h53810 ;
  assign rv_core_rf_rf_2_register$EN = 1'd1 ;

  // register rv_core_rf_rf_30_register
  assign rv_core_rf_rf_30_register$D_IN = n__read__h53866 ;
  assign rv_core_rf_rf_30_register$EN = 1'd1 ;

  // register rv_core_rf_rf_31_register
  assign rv_core_rf_rf_31_register$D_IN = n__read__h53868 ;
  assign rv_core_rf_rf_31_register$EN = 1'd1 ;

  // register rv_core_rf_rf_3_register
  assign rv_core_rf_rf_3_register$D_IN = n__read__h53812 ;
  assign rv_core_rf_rf_3_register$EN = 1'd1 ;

  // register rv_core_rf_rf_4_register
  assign rv_core_rf_rf_4_register$D_IN = n__read__h53814 ;
  assign rv_core_rf_rf_4_register$EN = 1'd1 ;

  // register rv_core_rf_rf_5_register
  assign rv_core_rf_rf_5_register$D_IN = n__read__h53816 ;
  assign rv_core_rf_rf_5_register$EN = 1'd1 ;

  // register rv_core_rf_rf_6_register
  assign rv_core_rf_rf_6_register$D_IN = n__read__h53818 ;
  assign rv_core_rf_rf_6_register$EN = 1'd1 ;

  // register rv_core_rf_rf_7_register
  assign rv_core_rf_rf_7_register$D_IN = n__read__h53820 ;
  assign rv_core_rf_rf_7_register$EN = 1'd1 ;

  // register rv_core_rf_rf_8_register
  assign rv_core_rf_rf_8_register$D_IN = n__read__h53822 ;
  assign rv_core_rf_rf_8_register$EN = 1'd1 ;

  // register rv_core_rf_rf_9_register
  assign rv_core_rf_rf_9_register$D_IN = n__read__h53824 ;
  assign rv_core_rf_rf_9_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_0_register
  assign rv_core_scoreboard_scores_0_register$D_IN =
	     rv_core_scoreboard_scores_0_port_1$whas ?
	       rv_core_scoreboard_scores_0_port_1$wget :
	       n__read__h42281 ;
  assign rv_core_scoreboard_scores_0_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_10_register
  assign rv_core_scoreboard_scores_10_register$D_IN =
	     rv_core_scoreboard_scores_10_port_1$whas ?
	       rv_core_scoreboard_scores_10_port_1$wget :
	       n__read__h42301 ;
  assign rv_core_scoreboard_scores_10_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_11_register
  assign rv_core_scoreboard_scores_11_register$D_IN =
	     rv_core_scoreboard_scores_11_port_1$whas ?
	       rv_core_scoreboard_scores_11_port_1$wget :
	       n__read__h42303 ;
  assign rv_core_scoreboard_scores_11_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_12_register
  assign rv_core_scoreboard_scores_12_register$D_IN =
	     rv_core_scoreboard_scores_12_port_1$whas ?
	       rv_core_scoreboard_scores_12_port_1$wget :
	       n__read__h42305 ;
  assign rv_core_scoreboard_scores_12_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_13_register
  assign rv_core_scoreboard_scores_13_register$D_IN =
	     rv_core_scoreboard_scores_13_port_1$whas ?
	       rv_core_scoreboard_scores_13_port_1$wget :
	       n__read__h42307 ;
  assign rv_core_scoreboard_scores_13_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_14_register
  assign rv_core_scoreboard_scores_14_register$D_IN =
	     rv_core_scoreboard_scores_14_port_1$whas ?
	       rv_core_scoreboard_scores_14_port_1$wget :
	       n__read__h42309 ;
  assign rv_core_scoreboard_scores_14_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_15_register
  assign rv_core_scoreboard_scores_15_register$D_IN =
	     rv_core_scoreboard_scores_15_port_1$whas ?
	       rv_core_scoreboard_scores_15_port_1$wget :
	       n__read__h42311 ;
  assign rv_core_scoreboard_scores_15_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_16_register
  assign rv_core_scoreboard_scores_16_register$D_IN =
	     rv_core_scoreboard_scores_16_port_1$whas ?
	       rv_core_scoreboard_scores_16_port_1$wget :
	       n__read__h42313 ;
  assign rv_core_scoreboard_scores_16_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_17_register
  assign rv_core_scoreboard_scores_17_register$D_IN =
	     rv_core_scoreboard_scores_17_port_1$whas ?
	       rv_core_scoreboard_scores_17_port_1$wget :
	       n__read__h42315 ;
  assign rv_core_scoreboard_scores_17_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_18_register
  assign rv_core_scoreboard_scores_18_register$D_IN =
	     rv_core_scoreboard_scores_18_port_1$whas ?
	       rv_core_scoreboard_scores_18_port_1$wget :
	       n__read__h42317 ;
  assign rv_core_scoreboard_scores_18_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_19_register
  assign rv_core_scoreboard_scores_19_register$D_IN =
	     rv_core_scoreboard_scores_19_port_1$whas ?
	       rv_core_scoreboard_scores_19_port_1$wget :
	       n__read__h42319 ;
  assign rv_core_scoreboard_scores_19_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_1_register
  assign rv_core_scoreboard_scores_1_register$D_IN =
	     rv_core_scoreboard_scores_1_port_1$whas ?
	       rv_core_scoreboard_scores_1_port_1$wget :
	       n__read__h42283 ;
  assign rv_core_scoreboard_scores_1_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_20_register
  assign rv_core_scoreboard_scores_20_register$D_IN =
	     rv_core_scoreboard_scores_20_port_1$whas ?
	       rv_core_scoreboard_scores_20_port_1$wget :
	       n__read__h42321 ;
  assign rv_core_scoreboard_scores_20_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_21_register
  assign rv_core_scoreboard_scores_21_register$D_IN =
	     rv_core_scoreboard_scores_21_port_1$whas ?
	       rv_core_scoreboard_scores_21_port_1$wget :
	       n__read__h42323 ;
  assign rv_core_scoreboard_scores_21_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_22_register
  assign rv_core_scoreboard_scores_22_register$D_IN =
	     rv_core_scoreboard_scores_22_port_1$whas ?
	       rv_core_scoreboard_scores_22_port_1$wget :
	       n__read__h42325 ;
  assign rv_core_scoreboard_scores_22_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_23_register
  assign rv_core_scoreboard_scores_23_register$D_IN =
	     rv_core_scoreboard_scores_23_port_1$whas ?
	       rv_core_scoreboard_scores_23_port_1$wget :
	       n__read__h42327 ;
  assign rv_core_scoreboard_scores_23_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_24_register
  assign rv_core_scoreboard_scores_24_register$D_IN =
	     rv_core_scoreboard_scores_24_port_1$whas ?
	       rv_core_scoreboard_scores_24_port_1$wget :
	       n__read__h42329 ;
  assign rv_core_scoreboard_scores_24_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_25_register
  assign rv_core_scoreboard_scores_25_register$D_IN =
	     rv_core_scoreboard_scores_25_port_1$whas ?
	       rv_core_scoreboard_scores_25_port_1$wget :
	       n__read__h42331 ;
  assign rv_core_scoreboard_scores_25_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_26_register
  assign rv_core_scoreboard_scores_26_register$D_IN =
	     rv_core_scoreboard_scores_26_port_1$whas ?
	       rv_core_scoreboard_scores_26_port_1$wget :
	       n__read__h42333 ;
  assign rv_core_scoreboard_scores_26_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_27_register
  assign rv_core_scoreboard_scores_27_register$D_IN =
	     rv_core_scoreboard_scores_27_port_1$whas ?
	       rv_core_scoreboard_scores_27_port_1$wget :
	       n__read__h42335 ;
  assign rv_core_scoreboard_scores_27_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_28_register
  assign rv_core_scoreboard_scores_28_register$D_IN =
	     rv_core_scoreboard_scores_28_port_1$whas ?
	       rv_core_scoreboard_scores_28_port_1$wget :
	       n__read__h42337 ;
  assign rv_core_scoreboard_scores_28_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_29_register
  assign rv_core_scoreboard_scores_29_register$D_IN =
	     rv_core_scoreboard_scores_29_port_1$whas ?
	       rv_core_scoreboard_scores_29_port_1$wget :
	       n__read__h42339 ;
  assign rv_core_scoreboard_scores_29_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_2_register
  assign rv_core_scoreboard_scores_2_register$D_IN =
	     rv_core_scoreboard_scores_2_port_1$whas ?
	       rv_core_scoreboard_scores_2_port_1$wget :
	       n__read__h42285 ;
  assign rv_core_scoreboard_scores_2_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_30_register
  assign rv_core_scoreboard_scores_30_register$D_IN =
	     rv_core_scoreboard_scores_30_port_1$whas ?
	       rv_core_scoreboard_scores_30_port_1$wget :
	       n__read__h42341 ;
  assign rv_core_scoreboard_scores_30_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_31_register
  assign rv_core_scoreboard_scores_31_register$D_IN =
	     rv_core_scoreboard_scores_31_port_1$whas ?
	       rv_core_scoreboard_scores_31_port_1$wget :
	       n__read__h42343 ;
  assign rv_core_scoreboard_scores_31_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_3_register
  assign rv_core_scoreboard_scores_3_register$D_IN =
	     rv_core_scoreboard_scores_3_port_1$whas ?
	       rv_core_scoreboard_scores_3_port_1$wget :
	       n__read__h42287 ;
  assign rv_core_scoreboard_scores_3_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_4_register
  assign rv_core_scoreboard_scores_4_register$D_IN =
	     rv_core_scoreboard_scores_4_port_1$whas ?
	       rv_core_scoreboard_scores_4_port_1$wget :
	       n__read__h42289 ;
  assign rv_core_scoreboard_scores_4_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_5_register
  assign rv_core_scoreboard_scores_5_register$D_IN =
	     rv_core_scoreboard_scores_5_port_1$whas ?
	       rv_core_scoreboard_scores_5_port_1$wget :
	       n__read__h42291 ;
  assign rv_core_scoreboard_scores_5_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_6_register
  assign rv_core_scoreboard_scores_6_register$D_IN =
	     rv_core_scoreboard_scores_6_port_1$whas ?
	       rv_core_scoreboard_scores_6_port_1$wget :
	       n__read__h42293 ;
  assign rv_core_scoreboard_scores_6_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_7_register
  assign rv_core_scoreboard_scores_7_register$D_IN =
	     rv_core_scoreboard_scores_7_port_1$whas ?
	       rv_core_scoreboard_scores_7_port_1$wget :
	       n__read__h42295 ;
  assign rv_core_scoreboard_scores_7_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_8_register
  assign rv_core_scoreboard_scores_8_register$D_IN =
	     rv_core_scoreboard_scores_8_port_1$whas ?
	       rv_core_scoreboard_scores_8_port_1$wget :
	       n__read__h42297 ;
  assign rv_core_scoreboard_scores_8_register$EN = 1'd1 ;

  // register rv_core_scoreboard_scores_9_register
  assign rv_core_scoreboard_scores_9_register$D_IN =
	     rv_core_scoreboard_scores_9_port_1$whas ?
	       rv_core_scoreboard_scores_9_port_1$wget :
	       n__read__h42299 ;
  assign rv_core_scoreboard_scores_9_register$EN = 1'd1 ;

  // register rv_core_toDmem_rv
  assign rv_core_toDmem_rv$D_IN = rv_core_toDmem_rv$port2__read ;
  assign rv_core_toDmem_rv$EN = 1'b1 ;

  // register rv_core_toImem_rv
  assign rv_core_toImem_rv$D_IN = rv_core_toImem_rv$port2__read ;
  assign rv_core_toImem_rv$EN = 1'b1 ;

  // submodule bram_memory
  assign bram_memory$ADDRA = rv_core_toDmem_rv$port1__read[47:34] ;
  assign bram_memory$ADDRB = rv_core_toImem_rv$port1__read[47:34] ;
  assign bram_memory$DIA = rv_core_toDmem_rv$port1__read[31:0] ;
  assign bram_memory$DIB = rv_core_toImem_rv$port1__read[31:0] ;
  assign bram_memory$WEA = rv_core_toDmem_rv$port1__read[67:64] ;
  assign bram_memory$WEB = rv_core_toImem_rv$port1__read[67:64] ;
  assign bram_memory$ENA = WILL_FIRE_RL_requestD ;
  assign bram_memory$ENB = bram_serverAdapterB_writeWithResp$whas ;

  // submodule bram_serverAdapterA_outDataCore
  assign bram_serverAdapterA_outDataCore$D_IN = bram_memory$DOA ;
  assign bram_serverAdapterA_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     !bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     !bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$CLR = 1'b0 ;

  // submodule bram_serverAdapterB_outDataCore
  assign bram_serverAdapterB_outDataCore$D_IN = bram_memory$DOB ;
  assign bram_serverAdapterB_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     !bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     !bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$CLR = 1'b0 ;

  // submodule rv_core_epoch_readBeforeLaterWrites_0
  assign rv_core_epoch_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_epoch_readBeforeLaterWrites_0$EN = rv_core_pc_port_0$whas ;

  // submodule rv_core_epoch_readBeforeLaterWrites_1
  assign rv_core_epoch_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_epoch_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_fromDecode
  assign rv_core_fromDecode$D_IN =
	     { rv_core_fromFetchprim$D_OUT,
	       CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b11_r_ETC__q11,
	       rv_core_fromImem$D_OUT[6:2] == 5'b11000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b0 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01100 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11001 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00100,
	       rv_core_fromImem$D_OUT[6:2] == 5'b11000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01100,
	       rv_core_fromImem$D_OUT[6:2] == 5'b01101 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11011 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b0 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01100 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11001 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00100 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00101,
	       rv_core_fromImem$D_OUT[6:2] == 5'b0 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00001 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00100 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00110 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11001 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b00101 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01101 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b01001 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11000 ||
	       rv_core_fromImem$D_OUT[6:2] == 5'b11011,
	       CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12,
	       rv_core_fromImem$D_OUT[31:0],
	       x__h51819,
	       x__h58382 } ;
  assign rv_core_fromDecode$ENQ =
	     WILL_FIRE_RL_rv_core_decode &&
	     rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 &&
	     score1__h40258 == 2'd0 &&
	     score2__h40259 == 2'd0 ;
  assign rv_core_fromDecode$DEQ = WILL_FIRE_RL_rv_core_execute ;
  assign rv_core_fromDecode$CLR = 1'b0 ;

  // submodule rv_core_fromDmem
  assign rv_core_fromDmem$D_IN = { dreq[67:32], x__h69742 } ;
  assign rv_core_fromDmem$ENQ = bram_serverAdapterA_outData_deqCalled$whas ;
  assign rv_core_fromDmem$DEQ =
	     WILL_FIRE_RL_rv_core_writeback &&
	     !rv_core_fromExecute$D_OUT[6] &&
	     rv_core_fromExecute$D_OUT[4:3] == 2'b0 ;
  assign rv_core_fromDmem$CLR = 1'b0 ;

  // submodule rv_core_fromExecute
  assign rv_core_fromExecute$D_IN =
	     { execute_bookkeeping_isUnsigned__h60338,
	       rv_core_fromDecode$D_OUT[77:76],
	       rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[1:0],
	       execute_bookkeeping_newrd__h60339,
	       rv_core_fromDecode$D_OUT[103:64] } ;
  assign rv_core_fromExecute$ENQ =
	     WILL_FIRE_RL_rv_core_execute &&
	     rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007 &&
	     rv_core_fromDecode$D_OUT[103] ;
  assign rv_core_fromExecute$DEQ = WILL_FIRE_RL_rv_core_writeback ;
  assign rv_core_fromExecute$CLR = 1'b0 ;

  // submodule rv_core_fromFetch
  assign rv_core_fromFetch$D_IN =
	     { newpc__h39535, x__h39845, fetch_bookkeeping_epoch__h39977 } ;
  assign rv_core_fromFetch$ENQ = rv_core_pc_port_1$whas ;
  assign rv_core_fromFetch$DEQ =
	     rv_core_fromFetch$EMPTY_N && rv_core_fromFetchprim$FULL_N ;
  assign rv_core_fromFetch$CLR = 1'b0 ;

  // submodule rv_core_fromFetchprim
  assign rv_core_fromFetchprim$D_IN = rv_core_fromFetch$D_OUT ;
  assign rv_core_fromFetchprim$ENQ =
	     rv_core_fromFetch$EMPTY_N && rv_core_fromFetchprim$FULL_N ;
  assign rv_core_fromFetchprim$DEQ =
	     WILL_FIRE_RL_rv_core_decode &&
	     (score1__h40258 == 2'd0 && score2__h40259 == 2'd0 ||
	      !rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602) ;
  assign rv_core_fromFetchprim$CLR = 1'b0 ;

  // submodule rv_core_fromImem
  assign rv_core_fromImem$D_IN = { ireq[67:32], x__h68821 } ;
  assign rv_core_fromImem$ENQ = bram_serverAdapterB_outData_deqCalled$whas ;
  assign rv_core_fromImem$DEQ =
	     WILL_FIRE_RL_rv_core_decode &&
	     (score1__h40258 == 2'd0 && score2__h40259 == 2'd0 ||
	      !rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602) ;
  assign rv_core_fromImem$CLR = 1'b0 ;

  // submodule rv_core_pc_readBeforeLaterWrites_0
  assign rv_core_pc_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_pc_readBeforeLaterWrites_0$EN = rv_core_pc_port_0$whas ;

  // submodule rv_core_pc_readBeforeLaterWrites_1
  assign rv_core_pc_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_pc_readBeforeLaterWrites_1$EN = rv_core_pc_port_1$whas ;

  // submodule rv_core_rf_rf_0_readBeforeLaterWrites_0
  assign rv_core_rf_rf_0_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_0_readBeforeLaterWrites_0$EN = 1'b0 ;

  // submodule rv_core_rf_rf_0_readBeforeLaterWrites_1
  assign rv_core_rf_rf_0_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_0_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_10_readBeforeLaterWrites_0
  assign rv_core_rf_rf_10_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_10_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_10_port_0$whas ;

  // submodule rv_core_rf_rf_10_readBeforeLaterWrites_1
  assign rv_core_rf_rf_10_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_10_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_11_readBeforeLaterWrites_0
  assign rv_core_rf_rf_11_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_11_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_11_port_0$whas ;

  // submodule rv_core_rf_rf_11_readBeforeLaterWrites_1
  assign rv_core_rf_rf_11_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_11_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_12_readBeforeLaterWrites_0
  assign rv_core_rf_rf_12_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_12_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_12_port_0$whas ;

  // submodule rv_core_rf_rf_12_readBeforeLaterWrites_1
  assign rv_core_rf_rf_12_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_12_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_13_readBeforeLaterWrites_0
  assign rv_core_rf_rf_13_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_13_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_13_port_0$whas ;

  // submodule rv_core_rf_rf_13_readBeforeLaterWrites_1
  assign rv_core_rf_rf_13_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_13_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_14_readBeforeLaterWrites_0
  assign rv_core_rf_rf_14_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_14_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_14_port_0$whas ;

  // submodule rv_core_rf_rf_14_readBeforeLaterWrites_1
  assign rv_core_rf_rf_14_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_14_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_15_readBeforeLaterWrites_0
  assign rv_core_rf_rf_15_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_15_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_15_port_0$whas ;

  // submodule rv_core_rf_rf_15_readBeforeLaterWrites_1
  assign rv_core_rf_rf_15_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_15_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_16_readBeforeLaterWrites_0
  assign rv_core_rf_rf_16_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_16_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_16_port_0$whas ;

  // submodule rv_core_rf_rf_16_readBeforeLaterWrites_1
  assign rv_core_rf_rf_16_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_16_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_17_readBeforeLaterWrites_0
  assign rv_core_rf_rf_17_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_17_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_17_port_0$whas ;

  // submodule rv_core_rf_rf_17_readBeforeLaterWrites_1
  assign rv_core_rf_rf_17_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_17_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_18_readBeforeLaterWrites_0
  assign rv_core_rf_rf_18_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_18_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_18_port_0$whas ;

  // submodule rv_core_rf_rf_18_readBeforeLaterWrites_1
  assign rv_core_rf_rf_18_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_18_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_19_readBeforeLaterWrites_0
  assign rv_core_rf_rf_19_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_19_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_19_port_0$whas ;

  // submodule rv_core_rf_rf_19_readBeforeLaterWrites_1
  assign rv_core_rf_rf_19_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_19_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_1_readBeforeLaterWrites_0
  assign rv_core_rf_rf_1_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_1_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_1_port_0$whas ;

  // submodule rv_core_rf_rf_1_readBeforeLaterWrites_1
  assign rv_core_rf_rf_1_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_1_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_20_readBeforeLaterWrites_0
  assign rv_core_rf_rf_20_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_20_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_20_port_0$whas ;

  // submodule rv_core_rf_rf_20_readBeforeLaterWrites_1
  assign rv_core_rf_rf_20_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_20_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_21_readBeforeLaterWrites_0
  assign rv_core_rf_rf_21_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_21_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_21_port_0$whas ;

  // submodule rv_core_rf_rf_21_readBeforeLaterWrites_1
  assign rv_core_rf_rf_21_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_21_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_22_readBeforeLaterWrites_0
  assign rv_core_rf_rf_22_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_22_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_22_port_0$whas ;

  // submodule rv_core_rf_rf_22_readBeforeLaterWrites_1
  assign rv_core_rf_rf_22_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_22_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_23_readBeforeLaterWrites_0
  assign rv_core_rf_rf_23_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_23_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_23_port_0$whas ;

  // submodule rv_core_rf_rf_23_readBeforeLaterWrites_1
  assign rv_core_rf_rf_23_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_23_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_24_readBeforeLaterWrites_0
  assign rv_core_rf_rf_24_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_24_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_24_port_0$whas ;

  // submodule rv_core_rf_rf_24_readBeforeLaterWrites_1
  assign rv_core_rf_rf_24_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_24_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_25_readBeforeLaterWrites_0
  assign rv_core_rf_rf_25_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_25_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_25_port_0$whas ;

  // submodule rv_core_rf_rf_25_readBeforeLaterWrites_1
  assign rv_core_rf_rf_25_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_25_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_26_readBeforeLaterWrites_0
  assign rv_core_rf_rf_26_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_26_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_26_port_0$whas ;

  // submodule rv_core_rf_rf_26_readBeforeLaterWrites_1
  assign rv_core_rf_rf_26_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_26_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_27_readBeforeLaterWrites_0
  assign rv_core_rf_rf_27_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_27_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_27_port_0$whas ;

  // submodule rv_core_rf_rf_27_readBeforeLaterWrites_1
  assign rv_core_rf_rf_27_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_27_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_28_readBeforeLaterWrites_0
  assign rv_core_rf_rf_28_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_28_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_28_port_0$whas ;

  // submodule rv_core_rf_rf_28_readBeforeLaterWrites_1
  assign rv_core_rf_rf_28_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_28_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_29_readBeforeLaterWrites_0
  assign rv_core_rf_rf_29_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_29_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_29_port_0$whas ;

  // submodule rv_core_rf_rf_29_readBeforeLaterWrites_1
  assign rv_core_rf_rf_29_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_29_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_2_readBeforeLaterWrites_0
  assign rv_core_rf_rf_2_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_2_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_2_port_0$whas ;

  // submodule rv_core_rf_rf_2_readBeforeLaterWrites_1
  assign rv_core_rf_rf_2_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_2_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_30_readBeforeLaterWrites_0
  assign rv_core_rf_rf_30_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_30_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_30_port_0$whas ;

  // submodule rv_core_rf_rf_30_readBeforeLaterWrites_1
  assign rv_core_rf_rf_30_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_30_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_31_readBeforeLaterWrites_0
  assign rv_core_rf_rf_31_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_31_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_31_port_0$whas ;

  // submodule rv_core_rf_rf_31_readBeforeLaterWrites_1
  assign rv_core_rf_rf_31_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_31_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_3_readBeforeLaterWrites_0
  assign rv_core_rf_rf_3_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_3_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_3_port_0$whas ;

  // submodule rv_core_rf_rf_3_readBeforeLaterWrites_1
  assign rv_core_rf_rf_3_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_3_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_4_readBeforeLaterWrites_0
  assign rv_core_rf_rf_4_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_4_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_4_port_0$whas ;

  // submodule rv_core_rf_rf_4_readBeforeLaterWrites_1
  assign rv_core_rf_rf_4_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_4_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_5_readBeforeLaterWrites_0
  assign rv_core_rf_rf_5_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_5_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_5_port_0$whas ;

  // submodule rv_core_rf_rf_5_readBeforeLaterWrites_1
  assign rv_core_rf_rf_5_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_5_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_6_readBeforeLaterWrites_0
  assign rv_core_rf_rf_6_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_6_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_6_port_0$whas ;

  // submodule rv_core_rf_rf_6_readBeforeLaterWrites_1
  assign rv_core_rf_rf_6_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_6_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_7_readBeforeLaterWrites_0
  assign rv_core_rf_rf_7_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_7_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_7_port_0$whas ;

  // submodule rv_core_rf_rf_7_readBeforeLaterWrites_1
  assign rv_core_rf_rf_7_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_7_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_8_readBeforeLaterWrites_0
  assign rv_core_rf_rf_8_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_8_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_8_port_0$whas ;

  // submodule rv_core_rf_rf_8_readBeforeLaterWrites_1
  assign rv_core_rf_rf_8_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_8_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_rf_rf_9_readBeforeLaterWrites_0
  assign rv_core_rf_rf_9_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_rf_rf_9_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_9_port_0$whas ;

  // submodule rv_core_rf_rf_9_readBeforeLaterWrites_1
  assign rv_core_rf_rf_9_readBeforeLaterWrites_1$D_IN = 1'b0 ;
  assign rv_core_rf_rf_9_readBeforeLaterWrites_1$EN = 1'b0 ;

  // submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_0_readBeforeLaterWrites_0$EN =
	     rv_core_scoreboard_scores_0_port_0$whas ;

  // submodule rv_core_scoreboard_scores_0_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_0_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_0_port_1$whas ;

  // submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_10_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_10_port_0$whas ;

  // submodule rv_core_scoreboard_scores_10_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_10_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_10_port_1$whas ;

  // submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_11_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_11_port_0$whas ;

  // submodule rv_core_scoreboard_scores_11_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_11_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_11_port_1$whas ;

  // submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_12_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_12_port_0$whas ;

  // submodule rv_core_scoreboard_scores_12_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_12_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_12_port_1$whas ;

  // submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_13_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_13_port_0$whas ;

  // submodule rv_core_scoreboard_scores_13_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_13_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_13_port_1$whas ;

  // submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_14_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_14_port_0$whas ;

  // submodule rv_core_scoreboard_scores_14_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_14_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_14_port_1$whas ;

  // submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_15_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_15_port_0$whas ;

  // submodule rv_core_scoreboard_scores_15_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_15_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_15_port_1$whas ;

  // submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_16_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_16_port_0$whas ;

  // submodule rv_core_scoreboard_scores_16_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_16_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_16_port_1$whas ;

  // submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_17_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_17_port_0$whas ;

  // submodule rv_core_scoreboard_scores_17_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_17_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_17_port_1$whas ;

  // submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_18_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_18_port_0$whas ;

  // submodule rv_core_scoreboard_scores_18_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_18_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_18_port_1$whas ;

  // submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_19_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_19_port_0$whas ;

  // submodule rv_core_scoreboard_scores_19_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_19_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_19_port_1$whas ;

  // submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_1_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_1_port_0$whas ;

  // submodule rv_core_scoreboard_scores_1_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_1_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_1_port_1$whas ;

  // submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_20_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_20_port_0$whas ;

  // submodule rv_core_scoreboard_scores_20_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_20_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_20_port_1$whas ;

  // submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_21_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_21_port_0$whas ;

  // submodule rv_core_scoreboard_scores_21_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_21_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_21_port_1$whas ;

  // submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_22_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_22_port_0$whas ;

  // submodule rv_core_scoreboard_scores_22_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_22_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_22_port_1$whas ;

  // submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_23_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_23_port_0$whas ;

  // submodule rv_core_scoreboard_scores_23_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_23_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_23_port_1$whas ;

  // submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_24_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_24_port_0$whas ;

  // submodule rv_core_scoreboard_scores_24_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_24_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_24_port_1$whas ;

  // submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_25_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_25_port_0$whas ;

  // submodule rv_core_scoreboard_scores_25_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_25_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_25_port_1$whas ;

  // submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_26_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_26_port_0$whas ;

  // submodule rv_core_scoreboard_scores_26_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_26_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_26_port_1$whas ;

  // submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_27_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_27_port_0$whas ;

  // submodule rv_core_scoreboard_scores_27_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_27_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_27_port_1$whas ;

  // submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_28_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_28_port_0$whas ;

  // submodule rv_core_scoreboard_scores_28_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_28_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_28_port_1$whas ;

  // submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_29_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_29_port_0$whas ;

  // submodule rv_core_scoreboard_scores_29_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_29_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_29_port_1$whas ;

  // submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_2_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_2_port_0$whas ;

  // submodule rv_core_scoreboard_scores_2_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_2_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_2_port_1$whas ;

  // submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_30_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_30_port_0$whas ;

  // submodule rv_core_scoreboard_scores_30_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_30_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_30_port_1$whas ;

  // submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_31_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_31_port_0$whas ;

  // submodule rv_core_scoreboard_scores_31_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_31_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_31_port_1$whas ;

  // submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_3_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_3_port_0$whas ;

  // submodule rv_core_scoreboard_scores_3_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_3_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_3_port_1$whas ;

  // submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_4_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_4_port_0$whas ;

  // submodule rv_core_scoreboard_scores_4_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_4_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_4_port_1$whas ;

  // submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_5_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_5_port_0$whas ;

  // submodule rv_core_scoreboard_scores_5_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_5_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_5_port_1$whas ;

  // submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_6_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_6_port_0$whas ;

  // submodule rv_core_scoreboard_scores_6_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_6_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_6_port_1$whas ;

  // submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_7_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_7_port_0$whas ;

  // submodule rv_core_scoreboard_scores_7_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_7_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_7_port_1$whas ;

  // submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_8_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_8_port_0$whas ;

  // submodule rv_core_scoreboard_scores_8_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_8_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_8_port_1$whas ;

  // submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_0
  assign rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_9_readBeforeLaterWrites_0$EN =
	     rv_core_rf_rf_9_port_0$whas ;

  // submodule rv_core_scoreboard_scores_9_readBeforeLaterWrites_1
  assign rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$D_IN = 1'd1 ;
  assign rv_core_scoreboard_scores_9_readBeforeLaterWrites_1$EN =
	     rv_core_scoreboard_scores_9_port_1$whas ;

  // remaining internal signals
  assign IF_rv_core_fromDecode_first__002_BIT_99_031_AN_ETC___d1066 =
	     (rv_core_fromDecode$D_OUT[99] &&
	      rv_core_fromDecode$D_OUT[98:96] == 3'd2) ?
	       { {19{x__h59375[12]}}, x__h59375 } :
	       ((rv_core_fromDecode$D_OUT[99] &&
		 rv_core_fromDecode$D_OUT[98:96] == 3'd3) ?
		  { rv_core_fromDecode$D_OUT[95:76], 12'b0 } :
		  ((rv_core_fromDecode$D_OUT[99] &&
		    rv_core_fromDecode$D_OUT[98:96] == 3'd4) ?
		     { {11{x__h59538[20]}}, x__h59538 } :
		     32'd0)) ;
  assign NOT_rv_core_rf_rf_0_readBeforeLaterWrites_0_re_ETC___d1208 =
	     !rv_core_rf_rf_0_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_10_readBeforeLaterWrites_0_r_ETC___d1238 =
	     !rv_core_rf_rf_10_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_11_readBeforeLaterWrites_0_r_ETC___d1241 =
	     !rv_core_rf_rf_11_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_12_readBeforeLaterWrites_0_r_ETC___d1244 =
	     !rv_core_rf_rf_12_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_13_readBeforeLaterWrites_0_r_ETC___d1247 =
	     !rv_core_rf_rf_13_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_14_readBeforeLaterWrites_0_r_ETC___d1250 =
	     !rv_core_rf_rf_14_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_15_readBeforeLaterWrites_0_r_ETC___d1253 =
	     !rv_core_rf_rf_15_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_16_readBeforeLaterWrites_0_r_ETC___d1256 =
	     !rv_core_rf_rf_16_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_17_readBeforeLaterWrites_0_r_ETC___d1259 =
	     !rv_core_rf_rf_17_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_18_readBeforeLaterWrites_0_r_ETC___d1262 =
	     !rv_core_rf_rf_18_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_19_readBeforeLaterWrites_0_r_ETC___d1265 =
	     !rv_core_rf_rf_19_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_1_readBeforeLaterWrites_0_re_ETC___d1211 =
	     !rv_core_rf_rf_1_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_20_readBeforeLaterWrites_0_r_ETC___d1268 =
	     !rv_core_rf_rf_20_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_21_readBeforeLaterWrites_0_r_ETC___d1271 =
	     !rv_core_rf_rf_21_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_22_readBeforeLaterWrites_0_r_ETC___d1274 =
	     !rv_core_rf_rf_22_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_23_readBeforeLaterWrites_0_r_ETC___d1277 =
	     !rv_core_rf_rf_23_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_24_readBeforeLaterWrites_0_r_ETC___d1280 =
	     !rv_core_rf_rf_24_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_25_readBeforeLaterWrites_0_r_ETC___d1283 =
	     !rv_core_rf_rf_25_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_26_readBeforeLaterWrites_0_r_ETC___d1286 =
	     !rv_core_rf_rf_26_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_27_readBeforeLaterWrites_0_r_ETC___d1289 =
	     !rv_core_rf_rf_27_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_28_readBeforeLaterWrites_0_r_ETC___d1292 =
	     !rv_core_rf_rf_28_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_29_readBeforeLaterWrites_0_r_ETC___d1295 =
	     !rv_core_rf_rf_29_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_2_readBeforeLaterWrites_0_re_ETC___d1214 =
	     !rv_core_rf_rf_2_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_30_readBeforeLaterWrites_0_r_ETC___d1298 =
	     !rv_core_rf_rf_30_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_31_readBeforeLaterWrites_0_r_ETC___d1301 =
	     !rv_core_rf_rf_31_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_3_readBeforeLaterWrites_0_re_ETC___d1217 =
	     !rv_core_rf_rf_3_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_4_readBeforeLaterWrites_0_re_ETC___d1220 =
	     !rv_core_rf_rf_4_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_5_readBeforeLaterWrites_0_re_ETC___d1223 =
	     !rv_core_rf_rf_5_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_6_readBeforeLaterWrites_0_re_ETC___d1226 =
	     !rv_core_rf_rf_6_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_7_readBeforeLaterWrites_0_re_ETC___d1229 =
	     !rv_core_rf_rf_7_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_8_readBeforeLaterWrites_0_re_ETC___d1232 =
	     !rv_core_rf_rf_8_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign NOT_rv_core_rf_rf_9_readBeforeLaterWrites_0_re_ETC___d1235 =
	     !rv_core_rf_rf_9_readBeforeLaterWrites_0$Q_OUT ||
	     rv_core_fromExecute$D_OUT[6] ||
	     rv_core_fromExecute$D_OUT[4:3] != 2'b0 ||
	     CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 ;
  assign SEL_ARR_IF_rv_core_scoreboard_scores_0_readBef_ETC___d702 =
	     score1__h40258 == 2'd0 && score2__h40259 == 2'd0 &&
	     (rv_core_fromImem$D_OUT[6:2] == 5'b01101 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b11011 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b0 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b01100 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b11001 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b00100 ||
	      rv_core_fromImem$D_OUT[6:2] == 5'b00101) ;
  assign _theResult___fst__h59888 =
	     (rv_core_fromDecode$D_OUT[66] && rv_core_fromDecode$D_OUT[67]) ?
	       nextPC__h59891 :
	       _theResult___fst__h59954 ;
  assign _theResult___fst__h59954 =
	     (rv_core_fromDecode$D_OUT[66] && !rv_core_fromDecode$D_OUT[67]) ?
	       nextPC__h59957 :
	       _theResult___fst__h59974 ;
  assign _theResult___fst__h59974 =
	     IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 ?
	       nextPC__h59891 :
	       incPC__h59791 ;
  assign alu_src2__h60518 =
	     rv_core_fromDecode$D_OUT[69] ?
	       rv_core_fromDecode$D_OUT[31:0] :
	       imm__h58901 ;
  assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 =
	     bram_serverAdapterA_cnt +
	     (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 =
	     bram_serverAdapterB_cnt +
	     (bram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign data__h58906 =
	     (rv_core_fromDecode$D_OUT[66] && rv_core_fromDecode$D_OUT[69]) ?
	       imm__h58901 :
	       ((rv_core_fromDecode$D_OUT[66] &&
		 !rv_core_fromDecode$D_OUT[69]) ?
		  nextPC__h59891 :
		  rd_val__h60521) ;
  assign execute_bookkeeping_isUnsigned__h60338 =
	     !rv_core_fromDecode$D_OUT[70] &&
	     rv_core_fromDecode$D_OUT[68:67] == 2'b0 &&
	     rv_core_fromDecode$D_OUT[78] ;
  assign execute_bookkeeping_newrd__h60339 =
	     (!rv_core_fromDecode$D_OUT[70] &&
	      rv_core_fromDecode$D_OUT[68:67] == 2'b0) ?
	       x__h59724 :
	       ((rv_core_fromDecode$D_OUT[70:68] == 3'b110) ?
		  incPC__h59791 :
		  data__h58906) ;
  assign fetch_bookkeeping_epoch__h39977 =
	     rv_core_pc_port_0$whas ?
	       rv_core_epoch_port_0$wget :
	       rv_core_epoch_register ;
  assign imm__h58901 =
	     (rv_core_fromDecode$D_OUT[99] &&
	      rv_core_fromDecode$D_OUT[98:96] == 3'd0) ?
	       { {20{rv_core_fromDecodeD_OUT_BITS_95_TO_84__q3[11]}},
		 rv_core_fromDecodeD_OUT_BITS_95_TO_84__q3 } :
	       ((rv_core_fromDecode$D_OUT[99] &&
		 rv_core_fromDecode$D_OUT[98:96] == 3'd1) ?
		  { {20{x__h59305[11]}}, x__h59305 } :
		  IF_rv_core_fromDecode_first__002_BIT_99_031_AN_ETC___d1066) ;
  assign incPC__h59791 = rv_core_fromDecode$D_OUT[168:137] + 32'd4 ;
  assign mem_data0980_BITS_15_TO_0__q2 = mem_data__h60980[15:0] ;
  assign mem_data0980_BITS_7_TO_0__q1 = mem_data__h60980[7:0] ;
  assign mem_data__h60980 = rv_core_fromDmem$D_OUT[31:0] >> x__h61031 ;
  assign n__read__h42281 =
	     rv_core_scoreboard_scores_0_port_0$whas ?
	       rv_core_scoreboard_scores_0_port_0$wget :
	       rv_core_scoreboard_scores_0_register ;
  assign n__read__h42283 =
	     rv_core_rf_rf_1_port_0$whas ?
	       rv_core_scoreboard_scores_1_port_0$wget :
	       rv_core_scoreboard_scores_1_register ;
  assign n__read__h42285 =
	     rv_core_rf_rf_2_port_0$whas ?
	       rv_core_scoreboard_scores_2_port_0$wget :
	       rv_core_scoreboard_scores_2_register ;
  assign n__read__h42287 =
	     rv_core_rf_rf_3_port_0$whas ?
	       rv_core_scoreboard_scores_3_port_0$wget :
	       rv_core_scoreboard_scores_3_register ;
  assign n__read__h42289 =
	     rv_core_rf_rf_4_port_0$whas ?
	       rv_core_scoreboard_scores_4_port_0$wget :
	       rv_core_scoreboard_scores_4_register ;
  assign n__read__h42291 =
	     rv_core_rf_rf_5_port_0$whas ?
	       rv_core_scoreboard_scores_5_port_0$wget :
	       rv_core_scoreboard_scores_5_register ;
  assign n__read__h42293 =
	     rv_core_rf_rf_6_port_0$whas ?
	       rv_core_scoreboard_scores_6_port_0$wget :
	       rv_core_scoreboard_scores_6_register ;
  assign n__read__h42295 =
	     rv_core_rf_rf_7_port_0$whas ?
	       rv_core_scoreboard_scores_7_port_0$wget :
	       rv_core_scoreboard_scores_7_register ;
  assign n__read__h42297 =
	     rv_core_rf_rf_8_port_0$whas ?
	       rv_core_scoreboard_scores_8_port_0$wget :
	       rv_core_scoreboard_scores_8_register ;
  assign n__read__h42299 =
	     rv_core_rf_rf_9_port_0$whas ?
	       rv_core_scoreboard_scores_9_port_0$wget :
	       rv_core_scoreboard_scores_9_register ;
  assign n__read__h42301 =
	     rv_core_rf_rf_10_port_0$whas ?
	       rv_core_scoreboard_scores_10_port_0$wget :
	       rv_core_scoreboard_scores_10_register ;
  assign n__read__h42303 =
	     rv_core_rf_rf_11_port_0$whas ?
	       rv_core_scoreboard_scores_11_port_0$wget :
	       rv_core_scoreboard_scores_11_register ;
  assign n__read__h42305 =
	     rv_core_rf_rf_12_port_0$whas ?
	       rv_core_scoreboard_scores_12_port_0$wget :
	       rv_core_scoreboard_scores_12_register ;
  assign n__read__h42307 =
	     rv_core_rf_rf_13_port_0$whas ?
	       rv_core_scoreboard_scores_13_port_0$wget :
	       rv_core_scoreboard_scores_13_register ;
  assign n__read__h42309 =
	     rv_core_rf_rf_14_port_0$whas ?
	       rv_core_scoreboard_scores_14_port_0$wget :
	       rv_core_scoreboard_scores_14_register ;
  assign n__read__h42311 =
	     rv_core_rf_rf_15_port_0$whas ?
	       rv_core_scoreboard_scores_15_port_0$wget :
	       rv_core_scoreboard_scores_15_register ;
  assign n__read__h42313 =
	     rv_core_rf_rf_16_port_0$whas ?
	       rv_core_scoreboard_scores_16_port_0$wget :
	       rv_core_scoreboard_scores_16_register ;
  assign n__read__h42315 =
	     rv_core_rf_rf_17_port_0$whas ?
	       rv_core_scoreboard_scores_17_port_0$wget :
	       rv_core_scoreboard_scores_17_register ;
  assign n__read__h42317 =
	     rv_core_rf_rf_18_port_0$whas ?
	       rv_core_scoreboard_scores_18_port_0$wget :
	       rv_core_scoreboard_scores_18_register ;
  assign n__read__h42319 =
	     rv_core_rf_rf_19_port_0$whas ?
	       rv_core_scoreboard_scores_19_port_0$wget :
	       rv_core_scoreboard_scores_19_register ;
  assign n__read__h42321 =
	     rv_core_rf_rf_20_port_0$whas ?
	       rv_core_scoreboard_scores_20_port_0$wget :
	       rv_core_scoreboard_scores_20_register ;
  assign n__read__h42323 =
	     rv_core_rf_rf_21_port_0$whas ?
	       rv_core_scoreboard_scores_21_port_0$wget :
	       rv_core_scoreboard_scores_21_register ;
  assign n__read__h42325 =
	     rv_core_rf_rf_22_port_0$whas ?
	       rv_core_scoreboard_scores_22_port_0$wget :
	       rv_core_scoreboard_scores_22_register ;
  assign n__read__h42327 =
	     rv_core_rf_rf_23_port_0$whas ?
	       rv_core_scoreboard_scores_23_port_0$wget :
	       rv_core_scoreboard_scores_23_register ;
  assign n__read__h42329 =
	     rv_core_rf_rf_24_port_0$whas ?
	       rv_core_scoreboard_scores_24_port_0$wget :
	       rv_core_scoreboard_scores_24_register ;
  assign n__read__h42331 =
	     rv_core_rf_rf_25_port_0$whas ?
	       rv_core_scoreboard_scores_25_port_0$wget :
	       rv_core_scoreboard_scores_25_register ;
  assign n__read__h42333 =
	     rv_core_rf_rf_26_port_0$whas ?
	       rv_core_scoreboard_scores_26_port_0$wget :
	       rv_core_scoreboard_scores_26_register ;
  assign n__read__h42335 =
	     rv_core_rf_rf_27_port_0$whas ?
	       rv_core_scoreboard_scores_27_port_0$wget :
	       rv_core_scoreboard_scores_27_register ;
  assign n__read__h42337 =
	     rv_core_rf_rf_28_port_0$whas ?
	       rv_core_scoreboard_scores_28_port_0$wget :
	       rv_core_scoreboard_scores_28_register ;
  assign n__read__h42339 =
	     rv_core_rf_rf_29_port_0$whas ?
	       rv_core_scoreboard_scores_29_port_0$wget :
	       rv_core_scoreboard_scores_29_register ;
  assign n__read__h42341 =
	     rv_core_rf_rf_30_port_0$whas ?
	       rv_core_scoreboard_scores_30_port_0$wget :
	       rv_core_scoreboard_scores_30_register ;
  assign n__read__h42343 =
	     rv_core_rf_rf_31_port_0$whas ?
	       rv_core_scoreboard_scores_31_port_0$wget :
	       rv_core_scoreboard_scores_31_register ;
  assign n__read__h53808 =
	     rv_core_rf_rf_1_port_0$whas ?
	       rv_core_rf_rf_1_port_0$wget :
	       rv_core_rf_rf_1_register ;
  assign n__read__h53810 =
	     rv_core_rf_rf_2_port_0$whas ?
	       rv_core_rf_rf_2_port_0$wget :
	       rv_core_rf_rf_2_register ;
  assign n__read__h53812 =
	     rv_core_rf_rf_3_port_0$whas ?
	       rv_core_rf_rf_3_port_0$wget :
	       rv_core_rf_rf_3_register ;
  assign n__read__h53814 =
	     rv_core_rf_rf_4_port_0$whas ?
	       rv_core_rf_rf_4_port_0$wget :
	       rv_core_rf_rf_4_register ;
  assign n__read__h53816 =
	     rv_core_rf_rf_5_port_0$whas ?
	       rv_core_rf_rf_5_port_0$wget :
	       rv_core_rf_rf_5_register ;
  assign n__read__h53818 =
	     rv_core_rf_rf_6_port_0$whas ?
	       rv_core_rf_rf_6_port_0$wget :
	       rv_core_rf_rf_6_register ;
  assign n__read__h53820 =
	     rv_core_rf_rf_7_port_0$whas ?
	       rv_core_rf_rf_7_port_0$wget :
	       rv_core_rf_rf_7_register ;
  assign n__read__h53822 =
	     rv_core_rf_rf_8_port_0$whas ?
	       rv_core_rf_rf_8_port_0$wget :
	       rv_core_rf_rf_8_register ;
  assign n__read__h53824 =
	     rv_core_rf_rf_9_port_0$whas ?
	       rv_core_rf_rf_9_port_0$wget :
	       rv_core_rf_rf_9_register ;
  assign n__read__h53826 =
	     rv_core_rf_rf_10_port_0$whas ?
	       rv_core_rf_rf_10_port_0$wget :
	       rv_core_rf_rf_10_register ;
  assign n__read__h53828 =
	     rv_core_rf_rf_11_port_0$whas ?
	       rv_core_rf_rf_11_port_0$wget :
	       rv_core_rf_rf_11_register ;
  assign n__read__h53830 =
	     rv_core_rf_rf_12_port_0$whas ?
	       rv_core_rf_rf_12_port_0$wget :
	       rv_core_rf_rf_12_register ;
  assign n__read__h53832 =
	     rv_core_rf_rf_13_port_0$whas ?
	       rv_core_rf_rf_13_port_0$wget :
	       rv_core_rf_rf_13_register ;
  assign n__read__h53834 =
	     rv_core_rf_rf_14_port_0$whas ?
	       rv_core_rf_rf_14_port_0$wget :
	       rv_core_rf_rf_14_register ;
  assign n__read__h53836 =
	     rv_core_rf_rf_15_port_0$whas ?
	       rv_core_rf_rf_15_port_0$wget :
	       rv_core_rf_rf_15_register ;
  assign n__read__h53838 =
	     rv_core_rf_rf_16_port_0$whas ?
	       rv_core_rf_rf_16_port_0$wget :
	       rv_core_rf_rf_16_register ;
  assign n__read__h53840 =
	     rv_core_rf_rf_17_port_0$whas ?
	       rv_core_rf_rf_17_port_0$wget :
	       rv_core_rf_rf_17_register ;
  assign n__read__h53842 =
	     rv_core_rf_rf_18_port_0$whas ?
	       rv_core_rf_rf_18_port_0$wget :
	       rv_core_rf_rf_18_register ;
  assign n__read__h53844 =
	     rv_core_rf_rf_19_port_0$whas ?
	       rv_core_rf_rf_19_port_0$wget :
	       rv_core_rf_rf_19_register ;
  assign n__read__h53846 =
	     rv_core_rf_rf_20_port_0$whas ?
	       rv_core_rf_rf_20_port_0$wget :
	       rv_core_rf_rf_20_register ;
  assign n__read__h53848 =
	     rv_core_rf_rf_21_port_0$whas ?
	       rv_core_rf_rf_21_port_0$wget :
	       rv_core_rf_rf_21_register ;
  assign n__read__h53850 =
	     rv_core_rf_rf_22_port_0$whas ?
	       rv_core_rf_rf_22_port_0$wget :
	       rv_core_rf_rf_22_register ;
  assign n__read__h53852 =
	     rv_core_rf_rf_23_port_0$whas ?
	       rv_core_rf_rf_23_port_0$wget :
	       rv_core_rf_rf_23_register ;
  assign n__read__h53854 =
	     rv_core_rf_rf_24_port_0$whas ?
	       rv_core_rf_rf_24_port_0$wget :
	       rv_core_rf_rf_24_register ;
  assign n__read__h53856 =
	     rv_core_rf_rf_25_port_0$whas ?
	       rv_core_rf_rf_25_port_0$wget :
	       rv_core_rf_rf_25_register ;
  assign n__read__h53858 =
	     rv_core_rf_rf_26_port_0$whas ?
	       rv_core_rf_rf_26_port_0$wget :
	       rv_core_rf_rf_26_register ;
  assign n__read__h53860 =
	     rv_core_rf_rf_27_port_0$whas ?
	       rv_core_rf_rf_27_port_0$wget :
	       rv_core_rf_rf_27_register ;
  assign n__read__h53862 =
	     rv_core_rf_rf_28_port_0$whas ?
	       rv_core_rf_rf_28_port_0$wget :
	       rv_core_rf_rf_28_register ;
  assign n__read__h53864 =
	     rv_core_rf_rf_29_port_0$whas ?
	       rv_core_rf_rf_29_port_0$wget :
	       rv_core_rf_rf_29_register ;
  assign n__read__h53866 =
	     rv_core_rf_rf_30_port_0$whas ?
	       rv_core_rf_rf_30_port_0$wget :
	       rv_core_rf_rf_30_register ;
  assign n__read__h53868 =
	     rv_core_rf_rf_31_port_0$whas ?
	       rv_core_rf_rf_31_port_0$wget :
	       rv_core_rf_rf_31_register ;
  assign new_score__h47293 = old_score__h47292 + 2'd1 ;
  assign new_score__h61196 = old_score__h61195 - 2'd1 ;
  assign newpc__h39535 =
	     rv_core_pc_port_0$whas ?
	       rv_core_pc_port_0$wget :
	       rv_core_pc_register ;
  assign nextPC__h59891 = rv_core_fromDecode$D_OUT[168:137] + imm__h58901 ;
  assign nextPC__h59957 =
	     { rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[31:1],
	       1'd0 } ;
  assign nextPc__h59778 =
	     (rv_core_fromDecode$D_OUT[70:68] == 3'b110) ?
	       _theResult___fst__h59888 :
	       incPC__h59791 ;
  assign req_byte_en__h59077 =
	     rv_core_fromDecode$D_OUT[69] ?
	       CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5 :
	       4'd0 ;
  assign rv_core_fromDecodeD_OUT_BITS_63_TO_32__q4 =
	     rv_core_fromDecode$D_OUT[63:32] ;
  assign rv_core_fromDecodeD_OUT_BITS_95_TO_84__q3 =
	     rv_core_fromDecode$D_OUT[95:84] ;
  assign rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073 =
	     rv_core_fromDecode$D_OUT[63:32] + imm__h58901 ;
  assign rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1079 =
	     rv_core_fromDecode$D_OUT[63:32] ==
	     rv_core_fromDecode$D_OUT[31:0] ;
  assign rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1083 =
	     (rv_core_fromDecode$D_OUT[63:32] ^ 32'h80000000) <
	     (rv_core_fromDecode$D_OUT[31:0] ^ 32'h80000000) ;
  assign rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1087 =
	     rv_core_fromDecode$D_OUT[63:32] <
	     rv_core_fromDecode$D_OUT[31:0] ;
  assign rv_core_fromDecode_first__002_BIT_104_003_EQ_I_ETC___d1007 =
	     rv_core_fromDecode$D_OUT[104] == rv_core_epoch_register ;
  assign rv_core_fromFetchprim_first__00_BIT_0_01_EQ_IF_ETC___d602 =
	     rv_core_fromFetchprim$D_OUT[0] ==
	     fetch_bookkeeping_epoch__h39977 ;
  assign shift_amount__h58981 =
	     { rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[1:0],
	       3'b0 } ;
  assign v__h60853 =
	     (!rv_core_fromExecute$D_OUT[6] &&
	      rv_core_fromExecute$D_OUT[4:3] == 2'b0) ?
	       v__h60948 :
	       rv_core_fromExecute$D_OUT[71:40] ;
  assign x__h39845 = newpc__h39535 + 32'd4 ;
  assign x__h58718 = rv_core_epoch_register + 1'd1 ;
  assign x__h58876 =
	     rv_core_pc_readBeforeLaterWrites_0$Q_OUT ?
	       32'd0 :
	       rv_core_pc_register ;
  assign x__h59305 =
	     { rv_core_fromDecode$D_OUT[95:89],
	       rv_core_fromDecode$D_OUT[75:71] } ;
  assign x__h59375 =
	     { rv_core_fromDecode$D_OUT[95],
	       rv_core_fromDecode$D_OUT[71],
	       rv_core_fromDecode$D_OUT[94:89],
	       rv_core_fromDecode$D_OUT[75:72],
	       1'b0 } ;
  assign x__h59538 =
	     { rv_core_fromDecode$D_OUT[95],
	       rv_core_fromDecode$D_OUT[83:76],
	       rv_core_fromDecode$D_OUT[84],
	       rv_core_fromDecode$D_OUT[94:85],
	       1'b0 } ;
  assign x__h59703 =
	     { rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[31:2],
	       2'b0 } ;
  assign x__h59724 = rv_core_fromDecode$D_OUT[31:0] << shift_amount__h58981 ;
  assign x__h60263 =
	     rv_core_pc_readBeforeLaterWrites_0$Q_OUT ?
	       nextPc__h59778 :
	       rv_core_pc_register ;
  assign x__h60674 =
	     (rv_core_fromDecode$D_OUT[63:32] ^ 32'h80000000) <
	     (alu_src2__h60518 ^ 32'h80000000) ;
  assign x__h60681 = rv_core_fromDecode$D_OUT[63:32] < alu_src2__h60518 ;
  assign x__h61031 = { rv_core_fromExecute$D_OUT[73:72], 3'b0 } ;
  assign x__h68821 =
	     bram_serverAdapterB_outDataCore$EMPTY_N ?
	       bram_serverAdapterB_outDataCore$D_OUT :
	       bram_memory$DOB ;
  assign x__h69742 =
	     bram_serverAdapterA_outDataCore$EMPTY_N ?
	       bram_serverAdapterA_outDataCore$D_OUT :
	       bram_memory$DOA ;
  always@(rv_core_fromExecute$D_OUT or
	  rv_core_scoreboard_scores_0_register or
	  rv_core_scoreboard_scores_1_register or
	  rv_core_scoreboard_scores_2_register or
	  rv_core_scoreboard_scores_3_register or
	  rv_core_scoreboard_scores_4_register or
	  rv_core_scoreboard_scores_5_register or
	  rv_core_scoreboard_scores_6_register or
	  rv_core_scoreboard_scores_7_register or
	  rv_core_scoreboard_scores_8_register or
	  rv_core_scoreboard_scores_9_register or
	  rv_core_scoreboard_scores_10_register or
	  rv_core_scoreboard_scores_11_register or
	  rv_core_scoreboard_scores_12_register or
	  rv_core_scoreboard_scores_13_register or
	  rv_core_scoreboard_scores_14_register or
	  rv_core_scoreboard_scores_15_register or
	  rv_core_scoreboard_scores_16_register or
	  rv_core_scoreboard_scores_17_register or
	  rv_core_scoreboard_scores_18_register or
	  rv_core_scoreboard_scores_19_register or
	  rv_core_scoreboard_scores_20_register or
	  rv_core_scoreboard_scores_21_register or
	  rv_core_scoreboard_scores_22_register or
	  rv_core_scoreboard_scores_23_register or
	  rv_core_scoreboard_scores_24_register or
	  rv_core_scoreboard_scores_25_register or
	  rv_core_scoreboard_scores_26_register or
	  rv_core_scoreboard_scores_27_register or
	  rv_core_scoreboard_scores_28_register or
	  rv_core_scoreboard_scores_29_register or
	  rv_core_scoreboard_scores_30_register or
	  rv_core_scoreboard_scores_31_register)
  begin
    case (rv_core_fromExecute$D_OUT[11:7])
      5'd0: old_score__h61195 = rv_core_scoreboard_scores_0_register;
      5'd1: old_score__h61195 = rv_core_scoreboard_scores_1_register;
      5'd2: old_score__h61195 = rv_core_scoreboard_scores_2_register;
      5'd3: old_score__h61195 = rv_core_scoreboard_scores_3_register;
      5'd4: old_score__h61195 = rv_core_scoreboard_scores_4_register;
      5'd5: old_score__h61195 = rv_core_scoreboard_scores_5_register;
      5'd6: old_score__h61195 = rv_core_scoreboard_scores_6_register;
      5'd7: old_score__h61195 = rv_core_scoreboard_scores_7_register;
      5'd8: old_score__h61195 = rv_core_scoreboard_scores_8_register;
      5'd9: old_score__h61195 = rv_core_scoreboard_scores_9_register;
      5'd10: old_score__h61195 = rv_core_scoreboard_scores_10_register;
      5'd11: old_score__h61195 = rv_core_scoreboard_scores_11_register;
      5'd12: old_score__h61195 = rv_core_scoreboard_scores_12_register;
      5'd13: old_score__h61195 = rv_core_scoreboard_scores_13_register;
      5'd14: old_score__h61195 = rv_core_scoreboard_scores_14_register;
      5'd15: old_score__h61195 = rv_core_scoreboard_scores_15_register;
      5'd16: old_score__h61195 = rv_core_scoreboard_scores_16_register;
      5'd17: old_score__h61195 = rv_core_scoreboard_scores_17_register;
      5'd18: old_score__h61195 = rv_core_scoreboard_scores_18_register;
      5'd19: old_score__h61195 = rv_core_scoreboard_scores_19_register;
      5'd20: old_score__h61195 = rv_core_scoreboard_scores_20_register;
      5'd21: old_score__h61195 = rv_core_scoreboard_scores_21_register;
      5'd22: old_score__h61195 = rv_core_scoreboard_scores_22_register;
      5'd23: old_score__h61195 = rv_core_scoreboard_scores_23_register;
      5'd24: old_score__h61195 = rv_core_scoreboard_scores_24_register;
      5'd25: old_score__h61195 = rv_core_scoreboard_scores_25_register;
      5'd26: old_score__h61195 = rv_core_scoreboard_scores_26_register;
      5'd27: old_score__h61195 = rv_core_scoreboard_scores_27_register;
      5'd28: old_score__h61195 = rv_core_scoreboard_scores_28_register;
      5'd29: old_score__h61195 = rv_core_scoreboard_scores_29_register;
      5'd30: old_score__h61195 = rv_core_scoreboard_scores_30_register;
      5'd31: old_score__h61195 = rv_core_scoreboard_scores_31_register;
    endcase
  end
  always@(rv_core_fromExecute$D_OUT or
	  mem_data0980_BITS_7_TO_0__q1 or
	  mem_data0980_BITS_15_TO_0__q2 or mem_data__h60980)
  begin
    case (rv_core_fromExecute$D_OUT[76:74])
      3'b0:
	  v__h60948 =
	      { {24{mem_data0980_BITS_7_TO_0__q1[7]}},
		mem_data0980_BITS_7_TO_0__q1 };
      3'b001:
	  v__h60948 =
	      { {16{mem_data0980_BITS_15_TO_0__q2[15]}},
		mem_data0980_BITS_15_TO_0__q2 };
      3'b010: v__h60948 = mem_data__h60980;
      3'b100: v__h60948 = { 24'd0, mem_data__h60980[7:0] };
      3'b101: v__h60948 = { 16'd0, mem_data__h60980[15:0] };
      default: v__h60948 = rv_core_fromExecute$D_OUT[71:40];
    endcase
  end
  always@(rv_core_fromDecode$D_OUT or
	  rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1087 or
	  rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1079 or
	  rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1083)
  begin
    case (rv_core_fromDecode$D_OUT[78:76])
      3'b0:
	  IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1079;
      3'b001:
	  IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
	      !rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1079;
      3'b100:
	  IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1083;
      3'b101:
	  IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
	      !rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1083;
      3'b110:
	  IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1087;
      default: IF_rv_core_fromDecode_first__002_BITS_78_TO_76_ETC___d1093 =
		   !rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1087;
    endcase
  end
  always@(rv_core_fromDecode$D_OUT or
	  alu_src2__h60518 or
	  x__h60674 or x__h60681 or rv_core_fromDecodeD_OUT_BITS_63_TO_32__q4)
  begin
    case (rv_core_fromDecode$D_OUT[78:76])
      3'b0:
	  rd_val__h60521 =
	      (rv_core_fromDecode$D_OUT[69] && rv_core_fromDecode$D_OUT[94]) ?
		rv_core_fromDecode$D_OUT[63:32] - alu_src2__h60518 :
		rv_core_fromDecode$D_OUT[63:32] + alu_src2__h60518;
      3'b001:
	  rd_val__h60521 =
	      rv_core_fromDecode$D_OUT[63:32] << alu_src2__h60518[4:0];
      3'b010: rd_val__h60521 = { 31'd0, x__h60674 };
      3'b011: rd_val__h60521 = { 31'd0, x__h60681 };
      3'b100:
	  rd_val__h60521 = rv_core_fromDecode$D_OUT[63:32] ^ alu_src2__h60518;
      3'b101:
	  rd_val__h60521 =
	      rv_core_fromDecode$D_OUT[94] ?
		rv_core_fromDecode$D_OUT[63:32] >> alu_src2__h60518[4:0] |
		~(32'hFFFFFFFF >> alu_src2__h60518[4:0]) &
		{32{rv_core_fromDecodeD_OUT_BITS_63_TO_32__q4[31]}} :
		rv_core_fromDecode$D_OUT[63:32] >> alu_src2__h60518[4:0];
      3'b110:
	  rd_val__h60521 = rv_core_fromDecode$D_OUT[63:32] | alu_src2__h60518;
      3'b111:
	  rd_val__h60521 = rv_core_fromDecode$D_OUT[63:32] & alu_src2__h60518;
    endcase
  end
  always@(rv_core_fromDecode$D_OUT or
	  rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073)
  begin
    case (rv_core_fromDecode$D_OUT[77:76])
      2'b0:
	  CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5 =
	      4'b0001 <<
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[1:0];
      2'b01:
	  CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5 =
	      4'b0011 <<
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[1:0];
      2'b10:
	  CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5 =
	      4'b1111 <<
	      rv_core_fromDecode_first__002_BITS_63_TO_32_07_ETC___d1073[1:0];
      2'd3: CASE_rv_core_fromDecodeD_OUT_BITS_77_TO_76_0b_ETC__q5 = 4'd0;
    endcase
  end
  always@(rv_core_fromExecute$D_OUT or rv_core_fromDmem$EMPTY_N)
  begin
    case (rv_core_fromExecute$D_OUT[76:74])
      3'b0, 3'b001, 3'b100, 3'b101:
	  CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 =
	      rv_core_fromDmem$EMPTY_N;
      default: CASE_rv_core_fromExecuteD_OUT_BITS_76_TO_74_0_ETC__q6 =
		   rv_core_fromExecute$D_OUT[76:74] != 3'b010 ||
		   rv_core_fromDmem$EMPTY_N;
    endcase
  end
  always@(rv_core_fromExecute$D_OUT or
	  NOT_rv_core_rf_rf_0_readBeforeLaterWrites_0_re_ETC___d1208 or
	  NOT_rv_core_rf_rf_1_readBeforeLaterWrites_0_re_ETC___d1211 or
	  NOT_rv_core_rf_rf_2_readBeforeLaterWrites_0_re_ETC___d1214 or
	  NOT_rv_core_rf_rf_3_readBeforeLaterWrites_0_re_ETC___d1217 or
	  NOT_rv_core_rf_rf_4_readBeforeLaterWrites_0_re_ETC___d1220 or
	  NOT_rv_core_rf_rf_5_readBeforeLaterWrites_0_re_ETC___d1223 or
	  NOT_rv_core_rf_rf_6_readBeforeLaterWrites_0_re_ETC___d1226 or
	  NOT_rv_core_rf_rf_7_readBeforeLaterWrites_0_re_ETC___d1229 or
	  NOT_rv_core_rf_rf_8_readBeforeLaterWrites_0_re_ETC___d1232 or
	  NOT_rv_core_rf_rf_9_readBeforeLaterWrites_0_re_ETC___d1235 or
	  NOT_rv_core_rf_rf_10_readBeforeLaterWrites_0_r_ETC___d1238 or
	  NOT_rv_core_rf_rf_11_readBeforeLaterWrites_0_r_ETC___d1241 or
	  NOT_rv_core_rf_rf_12_readBeforeLaterWrites_0_r_ETC___d1244 or
	  NOT_rv_core_rf_rf_13_readBeforeLaterWrites_0_r_ETC___d1247 or
	  NOT_rv_core_rf_rf_14_readBeforeLaterWrites_0_r_ETC___d1250 or
	  NOT_rv_core_rf_rf_15_readBeforeLaterWrites_0_r_ETC___d1253 or
	  NOT_rv_core_rf_rf_16_readBeforeLaterWrites_0_r_ETC___d1256 or
	  NOT_rv_core_rf_rf_17_readBeforeLaterWrites_0_r_ETC___d1259 or
	  NOT_rv_core_rf_rf_18_readBeforeLaterWrites_0_r_ETC___d1262 or
	  NOT_rv_core_rf_rf_19_readBeforeLaterWrites_0_r_ETC___d1265 or
	  NOT_rv_core_rf_rf_20_readBeforeLaterWrites_0_r_ETC___d1268 or
	  NOT_rv_core_rf_rf_21_readBeforeLaterWrites_0_r_ETC___d1271 or
	  NOT_rv_core_rf_rf_22_readBeforeLaterWrites_0_r_ETC___d1274 or
	  NOT_rv_core_rf_rf_23_readBeforeLaterWrites_0_r_ETC___d1277 or
	  NOT_rv_core_rf_rf_24_readBeforeLaterWrites_0_r_ETC___d1280 or
	  NOT_rv_core_rf_rf_25_readBeforeLaterWrites_0_r_ETC___d1283 or
	  NOT_rv_core_rf_rf_26_readBeforeLaterWrites_0_r_ETC___d1286 or
	  NOT_rv_core_rf_rf_27_readBeforeLaterWrites_0_r_ETC___d1289 or
	  NOT_rv_core_rf_rf_28_readBeforeLaterWrites_0_r_ETC___d1292 or
	  NOT_rv_core_rf_rf_29_readBeforeLaterWrites_0_r_ETC___d1295 or
	  NOT_rv_core_rf_rf_30_readBeforeLaterWrites_0_r_ETC___d1298 or
	  NOT_rv_core_rf_rf_31_readBeforeLaterWrites_0_r_ETC___d1301)
  begin
    case (rv_core_fromExecute$D_OUT[11:7])
      5'd0:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_0_readBeforeLaterWrites_0_re_ETC___d1208;
      5'd1:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_1_readBeforeLaterWrites_0_re_ETC___d1211;
      5'd2:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_2_readBeforeLaterWrites_0_re_ETC___d1214;
      5'd3:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_3_readBeforeLaterWrites_0_re_ETC___d1217;
      5'd4:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_4_readBeforeLaterWrites_0_re_ETC___d1220;
      5'd5:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_5_readBeforeLaterWrites_0_re_ETC___d1223;
      5'd6:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_6_readBeforeLaterWrites_0_re_ETC___d1226;
      5'd7:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_7_readBeforeLaterWrites_0_re_ETC___d1229;
      5'd8:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_8_readBeforeLaterWrites_0_re_ETC___d1232;
      5'd9:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_9_readBeforeLaterWrites_0_re_ETC___d1235;
      5'd10:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_10_readBeforeLaterWrites_0_r_ETC___d1238;
      5'd11:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_11_readBeforeLaterWrites_0_r_ETC___d1241;
      5'd12:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_12_readBeforeLaterWrites_0_r_ETC___d1244;
      5'd13:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_13_readBeforeLaterWrites_0_r_ETC___d1247;
      5'd14:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_14_readBeforeLaterWrites_0_r_ETC___d1250;
      5'd15:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_15_readBeforeLaterWrites_0_r_ETC___d1253;
      5'd16:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_16_readBeforeLaterWrites_0_r_ETC___d1256;
      5'd17:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_17_readBeforeLaterWrites_0_r_ETC___d1259;
      5'd18:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_18_readBeforeLaterWrites_0_r_ETC___d1262;
      5'd19:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_19_readBeforeLaterWrites_0_r_ETC___d1265;
      5'd20:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_20_readBeforeLaterWrites_0_r_ETC___d1268;
      5'd21:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_21_readBeforeLaterWrites_0_r_ETC___d1271;
      5'd22:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_22_readBeforeLaterWrites_0_r_ETC___d1274;
      5'd23:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_23_readBeforeLaterWrites_0_r_ETC___d1277;
      5'd24:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_24_readBeforeLaterWrites_0_r_ETC___d1280;
      5'd25:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_25_readBeforeLaterWrites_0_r_ETC___d1283;
      5'd26:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_26_readBeforeLaterWrites_0_r_ETC___d1286;
      5'd27:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_27_readBeforeLaterWrites_0_r_ETC___d1289;
      5'd28:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_28_readBeforeLaterWrites_0_r_ETC___d1292;
      5'd29:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_29_readBeforeLaterWrites_0_r_ETC___d1295;
      5'd30:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_30_readBeforeLaterWrites_0_r_ETC___d1298;
      5'd31:
	  CASE_rv_core_fromExecute_first__180_BITS_11_TO_ETC___d1302 =
	      NOT_rv_core_rf_rf_31_readBeforeLaterWrites_0_r_ETC___d1301;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  rv_core_rf_rf_0_register or
	  n__read__h53808 or
	  n__read__h53810 or
	  n__read__h53812 or
	  n__read__h53814 or
	  n__read__h53816 or
	  n__read__h53818 or
	  n__read__h53820 or
	  n__read__h53822 or
	  n__read__h53824 or
	  n__read__h53826 or
	  n__read__h53828 or
	  n__read__h53830 or
	  n__read__h53832 or
	  n__read__h53834 or
	  n__read__h53836 or
	  n__read__h53838 or
	  n__read__h53840 or
	  n__read__h53842 or
	  n__read__h53844 or
	  n__read__h53846 or
	  n__read__h53848 or
	  n__read__h53850 or
	  n__read__h53852 or
	  n__read__h53854 or
	  n__read__h53856 or
	  n__read__h53858 or
	  n__read__h53860 or
	  n__read__h53862 or
	  n__read__h53864 or n__read__h53866 or n__read__h53868)
  begin
    case (rv_core_fromImem$D_OUT[19:15])
      5'd0: x__h51819 = rv_core_rf_rf_0_register;
      5'd1: x__h51819 = n__read__h53808;
      5'd2: x__h51819 = n__read__h53810;
      5'd3: x__h51819 = n__read__h53812;
      5'd4: x__h51819 = n__read__h53814;
      5'd5: x__h51819 = n__read__h53816;
      5'd6: x__h51819 = n__read__h53818;
      5'd7: x__h51819 = n__read__h53820;
      5'd8: x__h51819 = n__read__h53822;
      5'd9: x__h51819 = n__read__h53824;
      5'd10: x__h51819 = n__read__h53826;
      5'd11: x__h51819 = n__read__h53828;
      5'd12: x__h51819 = n__read__h53830;
      5'd13: x__h51819 = n__read__h53832;
      5'd14: x__h51819 = n__read__h53834;
      5'd15: x__h51819 = n__read__h53836;
      5'd16: x__h51819 = n__read__h53838;
      5'd17: x__h51819 = n__read__h53840;
      5'd18: x__h51819 = n__read__h53842;
      5'd19: x__h51819 = n__read__h53844;
      5'd20: x__h51819 = n__read__h53846;
      5'd21: x__h51819 = n__read__h53848;
      5'd22: x__h51819 = n__read__h53850;
      5'd23: x__h51819 = n__read__h53852;
      5'd24: x__h51819 = n__read__h53854;
      5'd25: x__h51819 = n__read__h53856;
      5'd26: x__h51819 = n__read__h53858;
      5'd27: x__h51819 = n__read__h53860;
      5'd28: x__h51819 = n__read__h53862;
      5'd29: x__h51819 = n__read__h53864;
      5'd30: x__h51819 = n__read__h53866;
      5'd31: x__h51819 = n__read__h53868;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  rv_core_rf_rf_0_register or
	  n__read__h53808 or
	  n__read__h53810 or
	  n__read__h53812 or
	  n__read__h53814 or
	  n__read__h53816 or
	  n__read__h53818 or
	  n__read__h53820 or
	  n__read__h53822 or
	  n__read__h53824 or
	  n__read__h53826 or
	  n__read__h53828 or
	  n__read__h53830 or
	  n__read__h53832 or
	  n__read__h53834 or
	  n__read__h53836 or
	  n__read__h53838 or
	  n__read__h53840 or
	  n__read__h53842 or
	  n__read__h53844 or
	  n__read__h53846 or
	  n__read__h53848 or
	  n__read__h53850 or
	  n__read__h53852 or
	  n__read__h53854 or
	  n__read__h53856 or
	  n__read__h53858 or
	  n__read__h53860 or
	  n__read__h53862 or
	  n__read__h53864 or n__read__h53866 or n__read__h53868)
  begin
    case (rv_core_fromImem$D_OUT[24:20])
      5'd0: x__h58382 = rv_core_rf_rf_0_register;
      5'd1: x__h58382 = n__read__h53808;
      5'd2: x__h58382 = n__read__h53810;
      5'd3: x__h58382 = n__read__h53812;
      5'd4: x__h58382 = n__read__h53814;
      5'd5: x__h58382 = n__read__h53816;
      5'd6: x__h58382 = n__read__h53818;
      5'd7: x__h58382 = n__read__h53820;
      5'd8: x__h58382 = n__read__h53822;
      5'd9: x__h58382 = n__read__h53824;
      5'd10: x__h58382 = n__read__h53826;
      5'd11: x__h58382 = n__read__h53828;
      5'd12: x__h58382 = n__read__h53830;
      5'd13: x__h58382 = n__read__h53832;
      5'd14: x__h58382 = n__read__h53834;
      5'd15: x__h58382 = n__read__h53836;
      5'd16: x__h58382 = n__read__h53838;
      5'd17: x__h58382 = n__read__h53840;
      5'd18: x__h58382 = n__read__h53842;
      5'd19: x__h58382 = n__read__h53844;
      5'd20: x__h58382 = n__read__h53846;
      5'd21: x__h58382 = n__read__h53848;
      5'd22: x__h58382 = n__read__h53850;
      5'd23: x__h58382 = n__read__h53852;
      5'd24: x__h58382 = n__read__h53854;
      5'd25: x__h58382 = n__read__h53856;
      5'd26: x__h58382 = n__read__h53858;
      5'd27: x__h58382 = n__read__h53860;
      5'd28: x__h58382 = n__read__h53862;
      5'd29: x__h58382 = n__read__h53864;
      5'd30: x__h58382 = n__read__h53866;
      5'd31: x__h58382 = n__read__h53868;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  n__read__h42281 or
	  n__read__h42283 or
	  n__read__h42285 or
	  n__read__h42287 or
	  n__read__h42289 or
	  n__read__h42291 or
	  n__read__h42293 or
	  n__read__h42295 or
	  n__read__h42297 or
	  n__read__h42299 or
	  n__read__h42301 or
	  n__read__h42303 or
	  n__read__h42305 or
	  n__read__h42307 or
	  n__read__h42309 or
	  n__read__h42311 or
	  n__read__h42313 or
	  n__read__h42315 or
	  n__read__h42317 or
	  n__read__h42319 or
	  n__read__h42321 or
	  n__read__h42323 or
	  n__read__h42325 or
	  n__read__h42327 or
	  n__read__h42329 or
	  n__read__h42331 or
	  n__read__h42333 or
	  n__read__h42335 or
	  n__read__h42337 or
	  n__read__h42339 or n__read__h42341 or n__read__h42343)
  begin
    case (rv_core_fromImem$D_OUT[11:7])
      5'd0: old_score__h47292 = n__read__h42281;
      5'd1: old_score__h47292 = n__read__h42283;
      5'd2: old_score__h47292 = n__read__h42285;
      5'd3: old_score__h47292 = n__read__h42287;
      5'd4: old_score__h47292 = n__read__h42289;
      5'd5: old_score__h47292 = n__read__h42291;
      5'd6: old_score__h47292 = n__read__h42293;
      5'd7: old_score__h47292 = n__read__h42295;
      5'd8: old_score__h47292 = n__read__h42297;
      5'd9: old_score__h47292 = n__read__h42299;
      5'd10: old_score__h47292 = n__read__h42301;
      5'd11: old_score__h47292 = n__read__h42303;
      5'd12: old_score__h47292 = n__read__h42305;
      5'd13: old_score__h47292 = n__read__h42307;
      5'd14: old_score__h47292 = n__read__h42309;
      5'd15: old_score__h47292 = n__read__h42311;
      5'd16: old_score__h47292 = n__read__h42313;
      5'd17: old_score__h47292 = n__read__h42315;
      5'd18: old_score__h47292 = n__read__h42317;
      5'd19: old_score__h47292 = n__read__h42319;
      5'd20: old_score__h47292 = n__read__h42321;
      5'd21: old_score__h47292 = n__read__h42323;
      5'd22: old_score__h47292 = n__read__h42325;
      5'd23: old_score__h47292 = n__read__h42327;
      5'd24: old_score__h47292 = n__read__h42329;
      5'd25: old_score__h47292 = n__read__h42331;
      5'd26: old_score__h47292 = n__read__h42333;
      5'd27: old_score__h47292 = n__read__h42335;
      5'd28: old_score__h47292 = n__read__h42337;
      5'd29: old_score__h47292 = n__read__h42339;
      5'd30: old_score__h47292 = n__read__h42341;
      5'd31: old_score__h47292 = n__read__h42343;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  n__read__h42281 or
	  n__read__h42283 or
	  n__read__h42285 or
	  n__read__h42287 or
	  n__read__h42289 or
	  n__read__h42291 or
	  n__read__h42293 or
	  n__read__h42295 or
	  n__read__h42297 or
	  n__read__h42299 or
	  n__read__h42301 or
	  n__read__h42303 or
	  n__read__h42305 or
	  n__read__h42307 or
	  n__read__h42309 or
	  n__read__h42311 or
	  n__read__h42313 or
	  n__read__h42315 or
	  n__read__h42317 or
	  n__read__h42319 or
	  n__read__h42321 or
	  n__read__h42323 or
	  n__read__h42325 or
	  n__read__h42327 or
	  n__read__h42329 or
	  n__read__h42331 or
	  n__read__h42333 or
	  n__read__h42335 or
	  n__read__h42337 or
	  n__read__h42339 or n__read__h42341 or n__read__h42343)
  begin
    case (rv_core_fromImem$D_OUT[19:15])
      5'd0: score1__h40258 = n__read__h42281;
      5'd1: score1__h40258 = n__read__h42283;
      5'd2: score1__h40258 = n__read__h42285;
      5'd3: score1__h40258 = n__read__h42287;
      5'd4: score1__h40258 = n__read__h42289;
      5'd5: score1__h40258 = n__read__h42291;
      5'd6: score1__h40258 = n__read__h42293;
      5'd7: score1__h40258 = n__read__h42295;
      5'd8: score1__h40258 = n__read__h42297;
      5'd9: score1__h40258 = n__read__h42299;
      5'd10: score1__h40258 = n__read__h42301;
      5'd11: score1__h40258 = n__read__h42303;
      5'd12: score1__h40258 = n__read__h42305;
      5'd13: score1__h40258 = n__read__h42307;
      5'd14: score1__h40258 = n__read__h42309;
      5'd15: score1__h40258 = n__read__h42311;
      5'd16: score1__h40258 = n__read__h42313;
      5'd17: score1__h40258 = n__read__h42315;
      5'd18: score1__h40258 = n__read__h42317;
      5'd19: score1__h40258 = n__read__h42319;
      5'd20: score1__h40258 = n__read__h42321;
      5'd21: score1__h40258 = n__read__h42323;
      5'd22: score1__h40258 = n__read__h42325;
      5'd23: score1__h40258 = n__read__h42327;
      5'd24: score1__h40258 = n__read__h42329;
      5'd25: score1__h40258 = n__read__h42331;
      5'd26: score1__h40258 = n__read__h42333;
      5'd27: score1__h40258 = n__read__h42335;
      5'd28: score1__h40258 = n__read__h42337;
      5'd29: score1__h40258 = n__read__h42339;
      5'd30: score1__h40258 = n__read__h42341;
      5'd31: score1__h40258 = n__read__h42343;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  n__read__h42281 or
	  n__read__h42283 or
	  n__read__h42285 or
	  n__read__h42287 or
	  n__read__h42289 or
	  n__read__h42291 or
	  n__read__h42293 or
	  n__read__h42295 or
	  n__read__h42297 or
	  n__read__h42299 or
	  n__read__h42301 or
	  n__read__h42303 or
	  n__read__h42305 or
	  n__read__h42307 or
	  n__read__h42309 or
	  n__read__h42311 or
	  n__read__h42313 or
	  n__read__h42315 or
	  n__read__h42317 or
	  n__read__h42319 or
	  n__read__h42321 or
	  n__read__h42323 or
	  n__read__h42325 or
	  n__read__h42327 or
	  n__read__h42329 or
	  n__read__h42331 or
	  n__read__h42333 or
	  n__read__h42335 or
	  n__read__h42337 or
	  n__read__h42339 or n__read__h42341 or n__read__h42343)
  begin
    case (rv_core_fromImem$D_OUT[24:20])
      5'd0: score2__h40259 = n__read__h42281;
      5'd1: score2__h40259 = n__read__h42283;
      5'd2: score2__h40259 = n__read__h42285;
      5'd3: score2__h40259 = n__read__h42287;
      5'd4: score2__h40259 = n__read__h42289;
      5'd5: score2__h40259 = n__read__h42291;
      5'd6: score2__h40259 = n__read__h42293;
      5'd7: score2__h40259 = n__read__h42295;
      5'd8: score2__h40259 = n__read__h42297;
      5'd9: score2__h40259 = n__read__h42299;
      5'd10: score2__h40259 = n__read__h42301;
      5'd11: score2__h40259 = n__read__h42303;
      5'd12: score2__h40259 = n__read__h42305;
      5'd13: score2__h40259 = n__read__h42307;
      5'd14: score2__h40259 = n__read__h42309;
      5'd15: score2__h40259 = n__read__h42311;
      5'd16: score2__h40259 = n__read__h42313;
      5'd17: score2__h40259 = n__read__h42315;
      5'd18: score2__h40259 = n__read__h42317;
      5'd19: score2__h40259 = n__read__h42319;
      5'd20: score2__h40259 = n__read__h42321;
      5'd21: score2__h40259 = n__read__h42323;
      5'd22: score2__h40259 = n__read__h42325;
      5'd23: score2__h40259 = n__read__h42327;
      5'd24: score2__h40259 = n__read__h42329;
      5'd25: score2__h40259 = n__read__h42331;
      5'd26: score2__h40259 = n__read__h42333;
      5'd27: score2__h40259 = n__read__h42335;
      5'd28: score2__h40259 = n__read__h42337;
      5'd29: score2__h40259 = n__read__h42339;
      5'd30: score2__h40259 = n__read__h42341;
      5'd31: score2__h40259 = n__read__h42343;
    endcase
  end
  always@(rv_core_fromImem$D_OUT)
  begin
    case (rv_core_fromImem$D_OUT[31:20])
      12'b0, 12'b000000000001, 12'b001100000010:
	  CASE_rv_core_fromImemD_OUT_BITS_31_TO_20_0b0__ETC__q7 =
	      rv_core_fromImem$D_OUT[19:15] == 5'b0;
      default: CASE_rv_core_fromImemD_OUT_BITS_31_TO_20_0b0__ETC__q7 =
		   rv_core_fromImem$D_OUT[31:20] == 12'b000100000101 &&
		   rv_core_fromImem$D_OUT[19:15] == 5'b0;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  CASE_rv_core_fromImemD_OUT_BITS_31_TO_20_0b0__ETC__q7)
  begin
    case (rv_core_fromImem$D_OUT[6:0])
      7'b1100011:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8 =
	      rv_core_fromImem$D_OUT[14:12] == 3'b0 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b001 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b100 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b101 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b110 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b111;
      7'b1100111:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8 =
	      rv_core_fromImem$D_OUT[14:12] == 3'b0;
      default: CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8 =
		   rv_core_fromImem$D_OUT[6:0] == 7'b1101111 ||
		   rv_core_fromImem$D_OUT[6:0] == 7'b1110011 &&
		   rv_core_fromImem$D_OUT[14:12] == 3'b0 &&
		   rv_core_fromImem$D_OUT[11:7] == 5'd0 &&
		   CASE_rv_core_fromImemD_OUT_BITS_31_TO_20_0b0__ETC__q7;
    endcase
  end
  always@(rv_core_fromImem$D_OUT)
  begin
    case (rv_core_fromImem$D_OUT[14:12])
      3'b0, 3'b101:
	  CASE_rv_core_fromImemD_OUT_BITS_14_TO_12_0b0__ETC__q9 =
	      rv_core_fromImem$D_OUT[31:25] == 7'b0 ||
	      rv_core_fromImem$D_OUT[31:25] == 7'b0100000;
      default: CASE_rv_core_fromImemD_OUT_BITS_14_TO_12_0b0__ETC__q9 =
		   (rv_core_fromImem$D_OUT[14:12] == 3'b001 ||
		    rv_core_fromImem$D_OUT[14:12] == 3'b010 ||
		    rv_core_fromImem$D_OUT[14:12] == 3'b011 ||
		    rv_core_fromImem$D_OUT[14:12] == 3'b100 ||
		    rv_core_fromImem$D_OUT[14:12] == 3'b110 ||
		    rv_core_fromImem$D_OUT[14:12] == 3'b111) &&
		   rv_core_fromImem$D_OUT[31:25] == 7'b0;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8 or
	  CASE_rv_core_fromImemD_OUT_BITS_14_TO_12_0b0__ETC__q9)
  begin
    case (rv_core_fromImem$D_OUT[6:0])
      7'b0100011:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10 =
	      rv_core_fromImem$D_OUT[14:12] == 3'b0 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b001 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b010;
      7'b0110011:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10 =
	      CASE_rv_core_fromImemD_OUT_BITS_14_TO_12_0b0__ETC__q9;
      default: CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10 =
		   rv_core_fromImem$D_OUT[6:0] == 7'b0110111 ||
		   CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1100_ETC__q8;
    endcase
  end
  always@(rv_core_fromImem$D_OUT or
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10)
  begin
    case (rv_core_fromImem$D_OUT[6:0])
      7'b0000011:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b11_r_ETC__q11 =
	      rv_core_fromImem$D_OUT[14:12] == 3'b0 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b001 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b010 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b100 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b101;
      7'b0010011:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b11_r_ETC__q11 =
	      rv_core_fromImem$D_OUT[14:12] == 3'b0 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b010 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b011 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b100 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b110 ||
	      rv_core_fromImem$D_OUT[14:12] == 3'b111 ||
	      ((rv_core_fromImem$D_OUT[14:12] == 3'b001) ?
		 rv_core_fromImem$D_OUT[31:26] == 6'b0 &&
		 !rv_core_fromImem$D_OUT[25] :
		 rv_core_fromImem$D_OUT[14:12] == 3'b101 &&
		 (rv_core_fromImem$D_OUT[31:26] == 6'b0 ||
		  rv_core_fromImem$D_OUT[31:26] == 6'b010000) &&
		 !rv_core_fromImem$D_OUT[25]);
      default: CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b11_r_ETC__q11 =
		   rv_core_fromImem$D_OUT[6:0] == 7'b0010111 ||
		   CASE_rv_core_fromImemD_OUT_BITS_6_TO_0_0b1000_ETC__q10;
    endcase
  end
  always@(rv_core_fromImem$D_OUT)
  begin
    case (rv_core_fromImem$D_OUT[6:2])
      5'b0, 5'b00001, 5'b00100, 5'b00110, 5'b11001:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12 = 3'd0;
      5'b00101, 5'b01101:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12 = 3'd3;
      5'b01000, 5'b01001:
	  CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12 = 3'd1;
      5'b11000: CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12 = 3'd2;
      default: CASE_rv_core_fromImemD_OUT_BITS_6_TO_2_0b0_0__ETC__q12 = 3'd4;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	cycle_count <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_epoch_register <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rv_core_instr_count <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_pc_register <= `BSV_ASSIGNMENT_DELAY 32'h0;
	rv_core_rf_rf_0_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_10_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_11_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_12_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_13_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_14_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_15_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_16_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_17_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_18_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_19_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_1_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_20_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_21_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_22_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_23_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_24_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_25_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_26_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_27_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_28_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_29_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_2_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_30_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_31_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_3_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_4_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_5_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_6_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_7_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_8_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_rf_rf_9_register <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rv_core_scoreboard_scores_0_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_10_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_11_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_12_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_13_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_14_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_15_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_16_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_17_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_18_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_19_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_1_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_20_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_21_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_22_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_23_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_24_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_25_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_26_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_27_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_28_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_29_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_2_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_30_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_31_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_3_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_4_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_5_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_6_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_7_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_8_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_scoreboard_scores_9_register <= `BSV_ASSIGNMENT_DELAY 2'd0;
	rv_core_toDmem_rv <= `BSV_ASSIGNMENT_DELAY 69'h0AAAAAAAAAAAAAAAAA;
	rv_core_toImem_rv <= `BSV_ASSIGNMENT_DELAY 69'h0AAAAAAAAAAAAAAAAA;
      end
    else
      begin
        if (bram_serverAdapterA_cnt$EN)
	  bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_cnt$D_IN;
	if (bram_serverAdapterA_s1$EN)
	  bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_s1$D_IN;
	if (bram_serverAdapterB_cnt$EN)
	  bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_cnt$D_IN;
	if (bram_serverAdapterB_s1$EN)
	  bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_s1$D_IN;
	if (cycle_count$EN)
	  cycle_count <= `BSV_ASSIGNMENT_DELAY cycle_count$D_IN;
	if (rv_core_epoch_register$EN)
	  rv_core_epoch_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_epoch_register$D_IN;
	if (rv_core_instr_count$EN)
	  rv_core_instr_count <= `BSV_ASSIGNMENT_DELAY
	      rv_core_instr_count$D_IN;
	if (rv_core_pc_register$EN)
	  rv_core_pc_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_pc_register$D_IN;
	if (rv_core_rf_rf_0_register$EN)
	  rv_core_rf_rf_0_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_0_register$D_IN;
	if (rv_core_rf_rf_10_register$EN)
	  rv_core_rf_rf_10_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_10_register$D_IN;
	if (rv_core_rf_rf_11_register$EN)
	  rv_core_rf_rf_11_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_11_register$D_IN;
	if (rv_core_rf_rf_12_register$EN)
	  rv_core_rf_rf_12_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_12_register$D_IN;
	if (rv_core_rf_rf_13_register$EN)
	  rv_core_rf_rf_13_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_13_register$D_IN;
	if (rv_core_rf_rf_14_register$EN)
	  rv_core_rf_rf_14_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_14_register$D_IN;
	if (rv_core_rf_rf_15_register$EN)
	  rv_core_rf_rf_15_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_15_register$D_IN;
	if (rv_core_rf_rf_16_register$EN)
	  rv_core_rf_rf_16_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_16_register$D_IN;
	if (rv_core_rf_rf_17_register$EN)
	  rv_core_rf_rf_17_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_17_register$D_IN;
	if (rv_core_rf_rf_18_register$EN)
	  rv_core_rf_rf_18_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_18_register$D_IN;
	if (rv_core_rf_rf_19_register$EN)
	  rv_core_rf_rf_19_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_19_register$D_IN;
	if (rv_core_rf_rf_1_register$EN)
	  rv_core_rf_rf_1_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_1_register$D_IN;
	if (rv_core_rf_rf_20_register$EN)
	  rv_core_rf_rf_20_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_20_register$D_IN;
	if (rv_core_rf_rf_21_register$EN)
	  rv_core_rf_rf_21_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_21_register$D_IN;
	if (rv_core_rf_rf_22_register$EN)
	  rv_core_rf_rf_22_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_22_register$D_IN;
	if (rv_core_rf_rf_23_register$EN)
	  rv_core_rf_rf_23_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_23_register$D_IN;
	if (rv_core_rf_rf_24_register$EN)
	  rv_core_rf_rf_24_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_24_register$D_IN;
	if (rv_core_rf_rf_25_register$EN)
	  rv_core_rf_rf_25_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_25_register$D_IN;
	if (rv_core_rf_rf_26_register$EN)
	  rv_core_rf_rf_26_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_26_register$D_IN;
	if (rv_core_rf_rf_27_register$EN)
	  rv_core_rf_rf_27_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_27_register$D_IN;
	if (rv_core_rf_rf_28_register$EN)
	  rv_core_rf_rf_28_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_28_register$D_IN;
	if (rv_core_rf_rf_29_register$EN)
	  rv_core_rf_rf_29_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_29_register$D_IN;
	if (rv_core_rf_rf_2_register$EN)
	  rv_core_rf_rf_2_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_2_register$D_IN;
	if (rv_core_rf_rf_30_register$EN)
	  rv_core_rf_rf_30_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_30_register$D_IN;
	if (rv_core_rf_rf_31_register$EN)
	  rv_core_rf_rf_31_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_31_register$D_IN;
	if (rv_core_rf_rf_3_register$EN)
	  rv_core_rf_rf_3_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_3_register$D_IN;
	if (rv_core_rf_rf_4_register$EN)
	  rv_core_rf_rf_4_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_4_register$D_IN;
	if (rv_core_rf_rf_5_register$EN)
	  rv_core_rf_rf_5_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_5_register$D_IN;
	if (rv_core_rf_rf_6_register$EN)
	  rv_core_rf_rf_6_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_6_register$D_IN;
	if (rv_core_rf_rf_7_register$EN)
	  rv_core_rf_rf_7_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_7_register$D_IN;
	if (rv_core_rf_rf_8_register$EN)
	  rv_core_rf_rf_8_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_8_register$D_IN;
	if (rv_core_rf_rf_9_register$EN)
	  rv_core_rf_rf_9_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_rf_rf_9_register$D_IN;
	if (rv_core_scoreboard_scores_0_register$EN)
	  rv_core_scoreboard_scores_0_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_0_register$D_IN;
	if (rv_core_scoreboard_scores_10_register$EN)
	  rv_core_scoreboard_scores_10_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_10_register$D_IN;
	if (rv_core_scoreboard_scores_11_register$EN)
	  rv_core_scoreboard_scores_11_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_11_register$D_IN;
	if (rv_core_scoreboard_scores_12_register$EN)
	  rv_core_scoreboard_scores_12_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_12_register$D_IN;
	if (rv_core_scoreboard_scores_13_register$EN)
	  rv_core_scoreboard_scores_13_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_13_register$D_IN;
	if (rv_core_scoreboard_scores_14_register$EN)
	  rv_core_scoreboard_scores_14_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_14_register$D_IN;
	if (rv_core_scoreboard_scores_15_register$EN)
	  rv_core_scoreboard_scores_15_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_15_register$D_IN;
	if (rv_core_scoreboard_scores_16_register$EN)
	  rv_core_scoreboard_scores_16_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_16_register$D_IN;
	if (rv_core_scoreboard_scores_17_register$EN)
	  rv_core_scoreboard_scores_17_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_17_register$D_IN;
	if (rv_core_scoreboard_scores_18_register$EN)
	  rv_core_scoreboard_scores_18_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_18_register$D_IN;
	if (rv_core_scoreboard_scores_19_register$EN)
	  rv_core_scoreboard_scores_19_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_19_register$D_IN;
	if (rv_core_scoreboard_scores_1_register$EN)
	  rv_core_scoreboard_scores_1_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_1_register$D_IN;
	if (rv_core_scoreboard_scores_20_register$EN)
	  rv_core_scoreboard_scores_20_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_20_register$D_IN;
	if (rv_core_scoreboard_scores_21_register$EN)
	  rv_core_scoreboard_scores_21_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_21_register$D_IN;
	if (rv_core_scoreboard_scores_22_register$EN)
	  rv_core_scoreboard_scores_22_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_22_register$D_IN;
	if (rv_core_scoreboard_scores_23_register$EN)
	  rv_core_scoreboard_scores_23_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_23_register$D_IN;
	if (rv_core_scoreboard_scores_24_register$EN)
	  rv_core_scoreboard_scores_24_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_24_register$D_IN;
	if (rv_core_scoreboard_scores_25_register$EN)
	  rv_core_scoreboard_scores_25_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_25_register$D_IN;
	if (rv_core_scoreboard_scores_26_register$EN)
	  rv_core_scoreboard_scores_26_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_26_register$D_IN;
	if (rv_core_scoreboard_scores_27_register$EN)
	  rv_core_scoreboard_scores_27_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_27_register$D_IN;
	if (rv_core_scoreboard_scores_28_register$EN)
	  rv_core_scoreboard_scores_28_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_28_register$D_IN;
	if (rv_core_scoreboard_scores_29_register$EN)
	  rv_core_scoreboard_scores_29_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_29_register$D_IN;
	if (rv_core_scoreboard_scores_2_register$EN)
	  rv_core_scoreboard_scores_2_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_2_register$D_IN;
	if (rv_core_scoreboard_scores_30_register$EN)
	  rv_core_scoreboard_scores_30_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_30_register$D_IN;
	if (rv_core_scoreboard_scores_31_register$EN)
	  rv_core_scoreboard_scores_31_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_31_register$D_IN;
	if (rv_core_scoreboard_scores_3_register$EN)
	  rv_core_scoreboard_scores_3_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_3_register$D_IN;
	if (rv_core_scoreboard_scores_4_register$EN)
	  rv_core_scoreboard_scores_4_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_4_register$D_IN;
	if (rv_core_scoreboard_scores_5_register$EN)
	  rv_core_scoreboard_scores_5_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_5_register$D_IN;
	if (rv_core_scoreboard_scores_6_register$EN)
	  rv_core_scoreboard_scores_6_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_6_register$D_IN;
	if (rv_core_scoreboard_scores_7_register$EN)
	  rv_core_scoreboard_scores_7_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_7_register$D_IN;
	if (rv_core_scoreboard_scores_8_register$EN)
	  rv_core_scoreboard_scores_8_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_8_register$D_IN;
	if (rv_core_scoreboard_scores_9_register$EN)
	  rv_core_scoreboard_scores_9_register <= `BSV_ASSIGNMENT_DELAY
	      rv_core_scoreboard_scores_9_register$D_IN;
	if (rv_core_toDmem_rv$EN)
	  rv_core_toDmem_rv <= `BSV_ASSIGNMENT_DELAY rv_core_toDmem_rv$D_IN;
	if (rv_core_toImem_rv$EN)
	  rv_core_toImem_rv <= `BSV_ASSIGNMENT_DELAY rv_core_toImem_rv$D_IN;
      end
    if (dreq$EN) dreq <= `BSV_ASSIGNMENT_DELAY dreq$D_IN;
    if (ireq$EN) ireq <= `BSV_ASSIGNMENT_DELAY ireq$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    bram_serverAdapterA_cnt = 3'h2;
    bram_serverAdapterA_s1 = 2'h2;
    bram_serverAdapterB_cnt = 3'h2;
    bram_serverAdapterB_s1 = 2'h2;
    cycle_count = 32'hAAAAAAAA;
    dreq = 68'hAAAAAAAAAAAAAAAAA;
    ireq = 68'hAAAAAAAAAAAAAAAAA;
    rv_core_epoch_register = 1'h0;
    rv_core_instr_count = 32'hAAAAAAAA;
    rv_core_pc_register = 32'hAAAAAAAA;
    rv_core_rf_rf_0_register = 32'hAAAAAAAA;
    rv_core_rf_rf_10_register = 32'hAAAAAAAA;
    rv_core_rf_rf_11_register = 32'hAAAAAAAA;
    rv_core_rf_rf_12_register = 32'hAAAAAAAA;
    rv_core_rf_rf_13_register = 32'hAAAAAAAA;
    rv_core_rf_rf_14_register = 32'hAAAAAAAA;
    rv_core_rf_rf_15_register = 32'hAAAAAAAA;
    rv_core_rf_rf_16_register = 32'hAAAAAAAA;
    rv_core_rf_rf_17_register = 32'hAAAAAAAA;
    rv_core_rf_rf_18_register = 32'hAAAAAAAA;
    rv_core_rf_rf_19_register = 32'hAAAAAAAA;
    rv_core_rf_rf_1_register = 32'hAAAAAAAA;
    rv_core_rf_rf_20_register = 32'hAAAAAAAA;
    rv_core_rf_rf_21_register = 32'hAAAAAAAA;
    rv_core_rf_rf_22_register = 32'hAAAAAAAA;
    rv_core_rf_rf_23_register = 32'hAAAAAAAA;
    rv_core_rf_rf_24_register = 32'hAAAAAAAA;
    rv_core_rf_rf_25_register = 32'hAAAAAAAA;
    rv_core_rf_rf_26_register = 32'hAAAAAAAA;
    rv_core_rf_rf_27_register = 32'hAAAAAAAA;
    rv_core_rf_rf_28_register = 32'hAAAAAAAA;
    rv_core_rf_rf_29_register = 32'hAAAAAAAA;
    rv_core_rf_rf_2_register = 32'hAAAAAAAA;
    rv_core_rf_rf_30_register = 32'hAAAAAAAA;
    rv_core_rf_rf_31_register = 32'hAAAAAAAA;
    rv_core_rf_rf_3_register = 32'hAAAAAAAA;
    rv_core_rf_rf_4_register = 32'hAAAAAAAA;
    rv_core_rf_rf_5_register = 32'hAAAAAAAA;
    rv_core_rf_rf_6_register = 32'hAAAAAAAA;
    rv_core_rf_rf_7_register = 32'hAAAAAAAA;
    rv_core_rf_rf_8_register = 32'hAAAAAAAA;
    rv_core_rf_rf_9_register = 32'hAAAAAAAA;
    rv_core_scoreboard_scores_0_register = 2'h2;
    rv_core_scoreboard_scores_10_register = 2'h2;
    rv_core_scoreboard_scores_11_register = 2'h2;
    rv_core_scoreboard_scores_12_register = 2'h2;
    rv_core_scoreboard_scores_13_register = 2'h2;
    rv_core_scoreboard_scores_14_register = 2'h2;
    rv_core_scoreboard_scores_15_register = 2'h2;
    rv_core_scoreboard_scores_16_register = 2'h2;
    rv_core_scoreboard_scores_17_register = 2'h2;
    rv_core_scoreboard_scores_18_register = 2'h2;
    rv_core_scoreboard_scores_19_register = 2'h2;
    rv_core_scoreboard_scores_1_register = 2'h2;
    rv_core_scoreboard_scores_20_register = 2'h2;
    rv_core_scoreboard_scores_21_register = 2'h2;
    rv_core_scoreboard_scores_22_register = 2'h2;
    rv_core_scoreboard_scores_23_register = 2'h2;
    rv_core_scoreboard_scores_24_register = 2'h2;
    rv_core_scoreboard_scores_25_register = 2'h2;
    rv_core_scoreboard_scores_26_register = 2'h2;
    rv_core_scoreboard_scores_27_register = 2'h2;
    rv_core_scoreboard_scores_28_register = 2'h2;
    rv_core_scoreboard_scores_29_register = 2'h2;
    rv_core_scoreboard_scores_2_register = 2'h2;
    rv_core_scoreboard_scores_30_register = 2'h2;
    rv_core_scoreboard_scores_31_register = 2'h2;
    rv_core_scoreboard_scores_3_register = 2'h2;
    rv_core_scoreboard_scores_4_register = 2'h2;
    rv_core_scoreboard_scores_5_register = 2'h2;
    rv_core_scoreboard_scores_6_register = 2'h2;
    rv_core_scoreboard_scores_7_register = 2'h2;
    rv_core_scoreboard_scores_8_register = 2'h2;
    rv_core_scoreboard_scores_9_register = 2'h2;
    rv_core_toDmem_rv = 69'h0AAAAAAAAAAAAAAAAA;
    rv_core_toImem_rv = 69'h0AAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterA_s1[1] &&
	  !bram_serverAdapterA_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterB_s1[1] &&
	  !bram_serverAdapterB_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40000000)
	$fwrite(32'h80000002, "%c", rv_core_toDmem_rv$port1__read[7:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40000000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40000004)
	$fwrite(32'h80000002, "%0d", rv_core_toDmem_rv$port1__read[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40000004)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40001000 &&
	  rv_core_toDmem_rv$port1__read[31:0] == 32'd0)
	$fdisplay(32'h80000002, "  \033[0;32mPASS\033[0m");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40001000 &&
	  rv_core_toDmem_rv$port1__read[31:0] != 32'd0)
	$fdisplay(32'h80000002,
		  "  \033[0;31mFAIL\033[0m (%0d)",
		  rv_core_toDmem_rv$port1__read[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40001000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core_toDmem_rv$port1__read[67:64] == 4'hF &&
	  rv_core_toDmem_rv$port1__read[63:32] == 32'h40001000)
	$finish(32'd1);
  end
  // synopsys translate_on
endmodule  // top_bsv

