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xc7a100t2default:defaultZ17-347hpxê
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310*common2
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8keyword '%s' is not allowed here in this mode of verilog2277*oasys2
unsigned2default:default2£
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42default:default8@Z8-2277hpxê
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8keyword '%s' is not allowed here in this mode of verilog2277*oasys2
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52default:default8@Z8-2277hpxê
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62default:default8@Z8-2277hpxê
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cache2default:default2
2default:default2ª
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62default:default8@Z8-6157hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2
cache2default:default2
2default:default2
12default:default2
12default:default2ª
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62default:default8@Z8-6155hpxê
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2default:default2©
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9	Parameter readInsistLoop bound to: 256 - type: integer 
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%s
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:	Parameter writeInsistLoop bound to: 256 - type: integer 
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8	Parameter ddr_startLoop bound to: 256 - type: integer 
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2default:default2ø
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52default:default8@Z8-6155hpxê
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ddr2_wr2default:default2
2default:default2ß
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32default:default8@Z8-6157hpxê
^
%s
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2	Parameter DQ_WIDTH bound to: 16 - type: integer 
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%s
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2	Parameter ECC_TEST bound to: OFF - type: string 
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4	Parameter ADDR_WIDTH bound to: 27 - type: integer 
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4	Parameter nCK_PER_CLK bound to: 4 - type: integer 
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4	Parameter DATA_WIDTH bound to: 16 - type: integer 
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7	Parameter PAYLOAD_WIDTH bound to: 16 - type: integer 
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9	Parameter APP_DATA_WIDTH bound to: 128 - type: integer 
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232default:default8@Z8-6157hpxê
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2default:default2¶
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.	Parameter CMD41 bound to: 4 - type: integer 
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1	Parameter POLL_CMD bound to: 5 - type: integer 
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%s
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-	Parameter IDLE bound to: 6 - type: integer 
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3	Parameter READ_BLOCK bound to: 7 - type: integer 
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8	Parameter READ_BLOCK_WAIT bound to: 8 - type: integer 
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8	Parameter READ_BLOCK_DATA bound to: 9 - type: integer 
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8	Parameter READ_BLOCK_CRC bound to: 10 - type: integer 
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2	Parameter SEND_CMD bound to: 11 - type: integer 
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;	Parameter RECEIVE_BYTE_WAIT bound to: 12 - type: integer 
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6	Parameter RECEIVE_BYTE bound to: 13 - type: integer 
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9	Parameter WRITE_BLOCK_CMD bound to: 14 - type: integer 
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%s
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:	Parameter WRITE_BLOCK_INIT bound to: 15 - type: integer 
2default:defaulthp
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%s
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:	Parameter WRITE_BLOCK_DATA bound to: 16 - type: integer 
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%s
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:	Parameter WRITE_BLOCK_BYTE bound to: 17 - type: integer 
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%s
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:	Parameter WRITE_BLOCK_WAIT bound to: 18 - type: integer 
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%s
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ÜRegister %s in module %s is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code 
4193*oasys2
	reg_q_reg2default:default2
DIVU2default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/DIVU.v2default:default2
422default:default8@Z8-5788hpxê
•
ÜRegister %s in module %s is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code 
4193*oasys2
	reg_b_reg2default:default2
DIVU2default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/DIVU.v2default:default2
402default:default8@Z8-5788hpxê
Î
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
DIVU2default:default2
2default:default2
292default:default2
12default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/DIVU.v2default:default2
232default:default8@Z8-6155hpxê
È
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
MDU2default:default2
2default:default2
302default:default2
12default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/MDU.v2default:default2
242default:default8@Z8-6155hpxê
Ã
0Net %s in module/entity %s does not have driver.3422*oasys2
hilo_temp_o2default:default2
ex2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
372default:default8@Z8-3848hpxê
Ê
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
ex2default:default2
2default:default2
312default:default2
12default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
32default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2
ex_mem2default:default2
2default:default2§
çD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex_mem.v2default:default2
32default:default8@Z8-6157hpxê
Ó
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
ex_mem2default:default2
2default:default2
322default:default2
12default:default2§
çD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex_mem.v2default:default2
32default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2
mem2default:default2
2default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
32default:default8@Z8-6157hpxê
˝
default block is never used226*oasys2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
722default:default8@Z8-226hpxê
˛
default block is never used226*oasys2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
1032default:default8@Z8-226hpxê
˛
default block is never used226*oasys2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
1852default:default8@Z8-226hpxê
Ë
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
mem2default:default2
2default:default2
332default:default2
12default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
32default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2
mem_wb2default:default2
2default:default2§
çD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem_wb.v2default:default2
32default:default8@Z8-6157hpxê
Ó
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
mem_wb2default:default2
2default:default2
342default:default2
12default:default2§
çD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem_wb.v2default:default2
32default:default8@Z8-6155hpxê
∂
synthesizing module '%s'%s4497*oasys2
hilo_reg2default:default2
2default:default2¶
èD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/hilo_reg.v2default:default2
32default:default8@Z8-6157hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2
hilo_reg2default:default2
2default:default2
352default:default2
12default:default2¶
èD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/hilo_reg.v2default:default2
32default:default8@Z8-6155hpxê
Æ
synthesizing module '%s'%s4497*oasys2
ctrl2default:default2
2default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ctrl.v2default:default2
32default:default8@Z8-6157hpxê
Í
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
ctrl2default:default2
2default:default2
362default:default2
12default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ctrl.v2default:default2
32default:default8@Z8-6155hpxê
Ë
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
CPU2default:default2
2default:default2
372default:default2
12default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/CPU.v2default:default2
32default:default8@Z8-6155hpxê
∂
synthesizing module '%s'%s4497*oasys2
data_ram2default:default2
2default:default2¶
èD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/data_ram.v2default:default2
32default:default8@Z8-6157hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2
data_ram2default:default2
2default:default2
382default:default2
12default:default2¶
èD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/data_ram.v2default:default2
32default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2
seg7x162default:default2
2default:default2ô
ÇD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/seg7x16.v2default:default2
22default:default8@Z8-6157hpxê
á
-case statement is not full and has no default155*oasys2ô
ÇD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/seg7x16.v2default:default2
672default:default8@Z8-155hpxê
‰
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
seg7x162default:default2
2default:default2
392default:default2
12default:default2ô
ÇD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/seg7x16.v2default:default2
22default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2
io_sel2default:default2
2default:default2Æ
óD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/loadboard/io_sel.v2default:default2
32default:default8@Z8-6157hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2
io_sel2default:default2
2default:default2
402default:default2
12default:default2Æ
óD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/loadboard/io_sel.v2default:default2
32default:default8@Z8-6155hpxê
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synthesizing module '%s'%s4497*oasys2

sw_mem_sel2default:default2
2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/loadboard/sw_mem_sel.v2default:default2
22default:default8@Z8-6157hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2

sw_mem_sel2default:default2
2default:default2
412default:default2
12default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/loadboard/sw_mem_sel.v2default:default2
22default:default8@Z8-6155hpxê
‹
synthesizing module '%s'%s4497*oasys2#
clk_wiz_for_cpu2default:default2
2default:default2≈
ÆD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/synth_1/.Xil/Vivado-7032-DESKTOP-HD/realtime/clk_wiz_for_cpu_stub.v2default:default2
52default:default8@Z8-6157hpxê
ò
'done synthesizing module '%s'%s (%s#%s)4495*oasys2#
clk_wiz_for_cpu2default:default2
2default:default2
422default:default2
12default:default2≈
ÆD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/synth_1/.Xil/Vivado-7032-DESKTOP-HD/realtime/clk_wiz_for_cpu_stub.v2default:default2
52default:default8@Z8-6155hpxê
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'done synthesizing module '%s'%s (%s#%s)4495*oasys2
SOPC2default:default2
2default:default2
432default:default2
12default:default2ï
D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/SOPC.v2default:default2
242default:default8@Z8-6155hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[31]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[30]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[29]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[28]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[27]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[26]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[25]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[24]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[23]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[22]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[21]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[20]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[19]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[18]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[17]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[16]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[15]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[14]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[13]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[12]2default:defaultZ8-3331hpxê
~
!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[1]2default:defaultZ8-3331hpxê
~
!design %s has unconnected port %s3331*oasys2
data_ram2default:default2
addr[0]2default:defaultZ8-3331hpxê

!design %s has unconnected port %s3331*oasys2
ctrl2default:default2 
Databus_busy2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
mem_wb2default:default2
stall[3]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
mem_wb2default:default2
stall[2]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
mem_wb2default:default2
stall[1]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
mem_wb2default:default2
stall[0]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
ex_mem2default:default2
stall[5]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
ex_mem2default:default2
stall[2]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
ex_mem2default:default2
stall[1]2default:defaultZ8-3331hpxê
}
!design %s has unconnected port %s3331*oasys2
ex_mem2default:default2
stall[0]2default:defaultZ8-3331hpxê
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!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[31]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[30]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[29]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[28]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[27]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[26]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[25]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[24]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[23]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[22]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[21]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[20]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[19]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[18]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[17]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
Lui_322default:default2
iData_b[16]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[63]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[62]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[61]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[60]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[59]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[58]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[57]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[56]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[55]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[54]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[53]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[52]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[51]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[50]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[49]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[48]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[47]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[46]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[45]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[44]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[43]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[42]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[41]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[40]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[39]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[38]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[37]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[36]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[35]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[34]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[33]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[32]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[31]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[30]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[29]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[28]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[27]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[26]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[25]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[24]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[23]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[22]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[21]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[20]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[19]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[18]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[17]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[16]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[15]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[14]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[13]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
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hilo_temp_o[12]2default:defaultZ8-3331hpxê
Ä
!design %s has unconnected port %s3331*oasys2
ex2default:default2#
hilo_temp_o[11]2default:defaultZ8-3331hpxê
›
ÅMessage '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33312default:default2
1002default:defaultZ17-14hpxê
•
%s*synth2å
xFinished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 484.918 ; gain = 164.281
2default:defaulthpxê
D
%s
*synth2,

Report Check Netlist: 
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
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%s
*synth2]
I|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
2default:defaulthp
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ê
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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ê
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%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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ê
~
%s
*synth2f
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2default:defaulthp
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ÉFinished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 484.918 ; gain = 164.281
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
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2default:defaulthp
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ê
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%s*synth2ñ
ÅFinished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 484.918 ; gain = 164.281
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
W
Loading part %s157*device2$
xc7a100tcsg324-12default:defaultZ21-403hpxê
K
)Preparing netlist for logic optimization
349*projectZ1-570hpxê
>

Processing XDC Constraints
244*projectZ1-262hpxê
=
Initializing timing engine
348*projectZ1-569hpxê
π
$Parsing XDC File [%s] for cell '%s'
848*designutils2µ
ûd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/SDTrans/SDTrans/SDTrans_in_context.xdc2default:default22
SD_0/SD_PHY_Controller/SDMEM	2default:default8Z20-848hpxê
¬
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2µ
ûd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/SDTrans/SDTrans/SDTrans_in_context.xdc2default:default22
SD_0/SD_PHY_Controller/SDMEM	2default:default8Z20-847hpxê
«
$Parsing XDC File [%s] for cell '%s'
848*designutils2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/ddr2_ram/ddr2_ram/ddr2_ram_in_context.xdc2default:default2=
'sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram	2default:default8Z20-848hpxê
–
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/ddr2_ram/ddr2_ram/ddr2_ram_in_context.xdc2default:default2=
'sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram	2default:default8Z20-847hpxê
∫
$Parsing XDC File [%s] for cell '%s'
848*designutils2ª
§d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc2default:default2-
sealedDDR_0/clk_divider	2default:default8Z20-848hpxê
√
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2ª
§d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc2default:default2-
sealedDDR_0/clk_divider	2default:default8Z20-847hpxê
ù
$Parsing XDC File [%s] for cell '%s'
848*designutils2Ø
òd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/cache/cache/cache_in_context.xdc2default:default2
cache0	2default:default8Z20-848hpxê
¶
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2Ø
òd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/cache/cache/cache_in_context.xdc2default:default2
cache0	2default:default8Z20-847hpxê
¿
$Parsing XDC File [%s] for cell '%s'
848*designutils2Õ
∂d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu/clk_wiz_for_cpu_in_context.xdc2default:default2!
clk_divider	2default:default8Z20-848hpxê
°
nA clock with name '%s' already exists, creating a clock with the same name will overwrite the previous clock.
576*constraints2
	clk100mhz2default:default2Õ
∂d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu/clk_wiz_for_cpu_in_context.xdc2default:default2
12default:default8@Z18-619hpxê
…
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2Õ
∂d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu/clk_wiz_for_cpu_in_context.xdc2default:default2!
clk_divider	2default:default8Z20-847hpxê
‚
Parsing XDC File [%s]
179*designutils2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc2default:default8Z20-179hpxê
õ
No nets matched '%s'.
507*	planAhead2
rst_IBUF2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc2default:default2
1122default:default8@Z12-507hpxê
È
FMissing value for option '%s', please type '%s -help' for usage info.
163*common2
objects2default:default2 
set_property2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc2default:default2
1122default:default8@Z17-163hpxê
Î
Finished Parsing XDC File [%s]
178*designutils2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc2default:default8Z20-178hpxê
…
ŸImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2û
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc2default:default2*
.Xil/SOPC_propImpl.xdc2default:defaultZ1-236hpxê
⁄
Parsing XDC File [%s]
179*designutils2ò
ÅD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/synth_1/dont_touch.xdc2default:default8Z20-179hpxê
„
Finished Parsing XDC File [%s]
178*designutils2ò
ÅD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/synth_1/dont_touch.xdc2default:default8Z20-178hpxê
H
&Completed Processing XDC Constraints

245*projectZ1-263hpxê
~
!Unisim Transformation Summary:
%s111*project29
%No Unisim elements were transformed.
2default:defaultZ1-111hpxê
ô
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common24
 Constraint Validation Runtime : 2default:default2
00:00:002default:default2 
00:00:00.0202default:default2
867.3242default:default2
0.0002default:defaultZ17-268hpxê
Õ
ΩClock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default2
cache02default:default2
clk2default:default2
10.0002default:defaultZ38-316hpxê
„
ΩClock period '%s' specified during out-of-context synthesis of instance '%s' at clock pin '%s' is different from the actual clock period '%s', this can lead to different synthesis results.
203*timing2
20.0002default:default20
SD_0/SD_PHY_Controller/SDMEM2default:default2
clk2default:default2
10.0002default:defaultZ38-316hpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s*synth2í
~Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 867.324 ; gain = 546.688
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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*synth2f
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*Start Loading Part and Timing Information
2default:defaulthp
x
ê
~
%s
*synth2f
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2default:defaulthp
x
ê
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%s
*synth23
Loading part: xc7a100tcsg324-1
2default:defaulthp
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ê
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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åFinished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 867.324 ; gain = 546.688
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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*synth2B
.Start Applying 'set_property' XDC Constraints
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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ê
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%s
*synth2f
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2default:defaulthp
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ê
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êFinished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 867.324 ; gain = 546.688
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Ÿ
merging register '%s' into '%s'3619*oasys2#
app_wdf_end_reg2default:default2

app_en_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
642default:default8@Z8-4471hpxê
⁄
merging register '%s' into '%s'3619*oasys2$
app_wdf_wren_reg2default:default2

app_en_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
652default:default8@Z8-4471hpxê
≈
+Unused sequential element %s was removed. 
4326*oasys2#
app_wdf_end_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
642default:default8@Z8-6014hpxê
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+Unused sequential element %s was removed. 
4326*oasys2$
app_wdf_wren_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
652default:default8@Z8-6014hpxê
»
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2
read_en2default:default2
42default:default2
52default:defaultZ8-5544hpxê
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3inferred FSM for state register '%s' in module '%s'802*oasys2

cstate_reg2default:default2%
ddr2_read_control2default:defaultZ8-802hpxê
w
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
app_cmd2default:defaultZ8-5546hpxê
v
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
cstate2default:defaultZ8-5546hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[3]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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cache_status_reg[3]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[2]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[2]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[1]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[1]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[0]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[0]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2%
ddr_to_imem_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2(
ddr_boot_block_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2*
ddr_boot_inblock_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
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loadData_ddrToImemDone2default:default2
322default:default2
252default:defaultZ8-5545hpxê
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state2default:defaultZ8-5546hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
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state2default:default2
272default:default2
252default:defaultZ8-5545hpxê
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272default:default2
252default:defaultZ8-5545hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
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ready_for_next_byte2default:defaultZ8-5546hpxê
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bit_counter2default:defaultZ8-5546hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
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3inferred FSM for state register '%s' in module '%s'802*oasys2"
bytes_read_reg2default:default2
labkit2default:defaultZ8-802hpxê
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test_state_reg2default:default2
labkit2default:defaultZ8-802hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
rd2default:defaultZ8-5546hpxê
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bytes2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2

bytes_read2default:default2
22default:default2
52default:defaultZ8-5544hpxê
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addr_sdmem2default:default2
32default:default2
52default:defaultZ8-5544hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2
sd_ready2default:default2
32default:default2
52default:defaultZ8-5544hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

test_state2default:defaultZ8-5546hpxê
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8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
rd2default:defaultZ8-5546hpxê
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bytes2default:default2
22default:default2
52default:defaultZ8-5544hpxê
À
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2

bytes_read2default:default2
22default:default2
52default:defaultZ8-5544hpxê
À
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2

addr_sdmem2default:default2
32default:default2
52default:defaultZ8-5544hpxê
…
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2
sd_ready2default:default2
32default:default2
52default:defaultZ8-5544hpxê
z
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

test_state2default:defaultZ8-5546hpxê
ƒ
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2
adr2default:default2
12default:default2
52default:defaultZ8-5544hpxê
ô
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2!

m_reg1_read_o2default:defaultZ8-5587hpxê
v
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
wreg_o2default:defaultZ8-5546hpxê
ô
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2!

m_reg2_read_o2default:defaultZ8-5587hpxê
}
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2!

m_reg2_read_o2default:defaultZ8-5546hpxê
ì
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
aluop_o2default:defaultZ8-5587hpxê
w
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
aluop_o2default:defaultZ8-5546hpxê
î
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
alusel_o2default:defaultZ8-5587hpxê
x
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
alusel_o2default:defaultZ8-5546hpxê
í
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
wreg_o2default:defaultZ8-5587hpxê
}
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2!

branch_flag_o2default:defaultZ8-5546hpxê

8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2#
preInstr_isLoad2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[0]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[1]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[2]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[3]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[4]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[5]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[6]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[7]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[8]2default:defaultZ8-5546hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
regs_reg[9]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[10]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[11]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[12]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[13]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[14]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[15]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[16]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[17]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[18]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[19]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[20]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[21]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[22]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[23]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[24]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[25]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[26]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[27]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[28]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[29]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[30]2default:defaultZ8-5546hpxê
|
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 
regs_reg[31]2default:defaultZ8-5546hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Œ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2
oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
˛
}HDL ADVISOR - The operator resource <%s> is shared. To prevent sharing consider applying a KEEP on the output of the operator4233*oasys2
adder2default:default2£
åD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/DIV_m.v2default:default2
182default:default8@Z8-5818hpxê
˝
}HDL ADVISOR - The operator resource <%s> is shared. To prevent sharing consider applying a KEEP on the output of the operator4233*oasys2
adder2default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/DIVU.v2default:default2
402default:default8@Z8-5818hpxê
t
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
busy2default:defaultZ8-5546hpxê

8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2#
mul_div_control2default:defaultZ8-5546hpxê
w
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
whilo_o2default:defaultZ8-5546hpxê
ó
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
alu_a_toalu2default:defaultZ8-5587hpxê
z
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

clz_result2default:defaultZ8-5546hpxê
x
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
m_mem_we2default:defaultZ8-5546hpxê
x
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
mem_ce_o2default:defaultZ8-5546hpxê
w
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
o_seg_r2default:defaultZ8-5546hpxê
ù
6No Re-encoding of one hot register '%s' in module '%s'3445*oasys2

cstate_reg2default:default2#
fsm158A042DCF002default:defaultZ8-3898hpxê
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!inferring latch for variable '%s'327*oasys2
app_cmd_reg2default:default2ß
êD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_wr.v2default:default2
842default:default8@Z8-327hpxê
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulthp
x
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2s
_                 iSTATE0 |                             0001 |                               00
2default:defaulthp
x
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%s
*synth2s
_                 iSTATE1 |                             0010 |                               01
2default:defaulthp
x
ê
ã
%s
*synth2s
_                 iSTATE2 |                             0100 |                               10
2default:defaulthp
x
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%s
*synth2s
_                  iSTATE |                             1000 |                               11
2default:defaulthp
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*synth2
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2default:defaulthp
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
x
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Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2"
bytes_read_reg2default:default2
one-hot2default:default2
labkit2default:defaultZ8-3354hpxê
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2t
`                   State |                     New Encoding |                Previous Encoding 
2default:defaulthp
x
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2s
_              STATE_INIT |                               00 |                              000
2default:defaulthp
x
ê
ã
%s
*synth2s
_        STATE_START_READ |                               01 |                              100
2default:defaulthp
x
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%s
*synth2s
_              STATE_READ |                               10 |                              011
2default:defaulthp
x
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%s
*synth2s
_              STATE_WAIT |                               11 |                              101
2default:defaulthp
x
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%s
*synth2x
d---------------------------------------------------------------------------------------------------
2default:defaulthp
x
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…
Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2"
test_state_reg2default:default2

sequential2default:default2
labkit2default:defaultZ8-3354hpxê
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!inferring latch for variable '%s'327*oasys2

reg1_o_reg2default:default2©
íD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ControlUnit.v2default:default2
5542default:default8@Z8-327hpxê
¨
!inferring latch for variable '%s'327*oasys2

reg2_o_reg2default:default2©
íD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ControlUnit.v2default:default2
5762default:default8@Z8-327hpxê
•
!inferring latch for variable '%s'327*oasys2
oData_C_reg2default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ALU.v2default:default2
2752default:default8@Z8-327hpxê
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!inferring latch for variable '%s'327*oasys2
	carry_reg2default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ALU.v2default:default2
502default:default8@Z8-327hpxê
•
!inferring latch for variable '%s'327*oasys2 
overflow_reg2default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ALU.v2default:default2
512default:default8@Z8-327hpxê
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!inferring latch for variable '%s'327*oasys2"
clz_result_reg2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
2292default:default8@Z8-327hpxê
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!inferring latch for variable '%s'327*oasys2
	cnt_o_reg2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
1262default:default8@Z8-327hpxê
ß
!inferring latch for variable '%s'327*oasys2#
alu_a_toalu_reg2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
752default:default8@Z8-327hpxê
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!inferring latch for variable '%s'327*oasys2#
alu_b_toalu_reg2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
762default:default8@Z8-327hpxê
¨
!inferring latch for variable '%s'327*oasys2(
alu_opcode_toalu_reg2default:default2†
âD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/ex.v2default:default2
772default:default8@Z8-327hpxê
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!inferring latch for variable '%s'327*oasys2"
mem_data_o_reg2default:default2°
äD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mem.v2default:default2
522default:default8@Z8-327hpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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ÅFinished RTL Optimization Phase 2 : Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 867.324 ; gain = 546.688
2default:defaulthpxê
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Report RTL Partitions: 
2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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*synth2f
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2default:defaulthp
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 Start RTL Component Statistics 
2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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.	   2 Input     33 Bit       Adders := 2     
2default:defaulthp
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%s
*synth2B
.	   3 Input     33 Bit       Adders := 8     
2default:defaulthp
x
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%s
*synth2B
.	   2 Input     32 Bit       Adders := 20    
2default:defaulthp
x
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%s
*synth2B
.	   2 Input     10 Bit       Adders := 2     
2default:defaulthp
x
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%s
*synth2B
.	   2 Input      9 Bit       Adders := 2     
2default:defaulthp
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%s
*synth2B
.	   2 Input      8 Bit       Adders := 2     
2default:defaulthp
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%s
*synth2B
.	   2 Input      6 Bit       Adders := 1     
2default:defaulthp
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%s
*synth2B
.	   2 Input      5 Bit       Adders := 8     
2default:defaulthp
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%s
*synth2B
.	   2 Input      4 Bit       Adders := 1     
2default:defaulthp
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*synth2B
.	   2 Input      3 Bit       Adders := 1     
2default:defaulthp
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2default:defaulthp
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%s
*synth2B
.	   2 Input      1 Bit         XORs := 1     
2default:defaulthp
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2default:defaulthp
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.	              128 Bit    Registers := 1     
2default:defaulthp
x
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%s
*synth2B
.	               64 Bit    Registers := 1     
2default:defaulthp
x
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%s
*synth2B
.	               56 Bit    Registers := 1     
2default:defaulthp
x
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*synth2B
.	               32 Bit    Registers := 64    
2default:defaulthp
x
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%s
*synth2B
.	               27 Bit    Registers := 2     
2default:defaulthp
x
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%s
*synth2B
.	               24 Bit    Registers := 4     
2default:defaulthp
x
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%s
*synth2B
.	               10 Bit    Registers := 2     
2default:defaulthp
x
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%s
*synth2B
.	                8 Bit    Registers := 7     
2default:defaulthp
x
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%s
*synth2B
.	                6 Bit    Registers := 1     
2default:defaulthp
x
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%s
*synth2B
.	                5 Bit    Registers := 8     
2default:defaulthp
x
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%s
*synth2B
.	                4 Bit    Registers := 1     
2default:defaulthp
x
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%s
*synth2B
.	                3 Bit    Registers := 7     
2default:defaulthp
x
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%s
*synth2B
.	                2 Bit    Registers := 1     
2default:defaulthp
x
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%s
*synth2B
.	                1 Bit    Registers := 48    
2default:defaulthp
x
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%s
*synth2'
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2default:defaulthp
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*synth2B
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2default:defaulthp
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8
%s
*synth2 
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2default:defaulthp
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%s
*synth2B
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2default:defaulthp
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9
%s
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2default:defaulthp
x
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%s
*synth2B
.	   2 Input     64 Bit        Muxes := 2     
2default:defaulthp
x
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Z
%s
*synth2B
.	   2 Input     33 Bit        Muxes := 2     
2default:defaulthp
x
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%s
*synth2B
.	   2 Input     32 Bit        Muxes := 102   
2default:defaulthp
x
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%s
*synth2B
.	   4 Input     32 Bit        Muxes := 12    
2default:defaulthp
x
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%s
*synth2B
.	   5 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     32 Bit        Muxes := 7     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input     32 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     24 Bit        Muxes := 12    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     24 Bit        Muxes := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     23 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     23 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     16 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     13 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input     10 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      9 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      8 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      7 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      6 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  33 Input      6 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      5 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      4 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 7     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      4 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      3 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      3 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  26 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 24    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      2 Bit        Muxes := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 141   
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 15    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 32    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      1 Bit        Muxes := 13    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   5 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
O
%s
*synth27
#Finished RTL Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Y
%s
*synth2A
-Start RTL Hierarchical Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
O
%s
*synth27
#Hierarchical RTL Component report 
2default:defaulthp
x
ê
G
%s
*synth2/
Module ddr2_write_control 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit       Adders := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	              128 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               27 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                4 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
F
%s
*synth2.
Module ddr2_read_control 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               27 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 1     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 5     
2default:defaulthp
x
ê
<
%s
*synth2$
Module ddr2_wr 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
>
%s
*synth2&
Module sealedDDR 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 16    
2default:defaulthp
x
ê
<
%s
*synth2$
Module DataBus 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      9 Bit       Adders := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      8 Bit       Adders := 2     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               24 Bit    Registers := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 10    
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     24 Bit        Muxes := 12    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     24 Bit        Muxes := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     23 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     23 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      9 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      8 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 30    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 18    
2default:defaulthp
x
ê
B
%s
*synth2*
Module clock_divider 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 1     
2default:defaulthp
x
ê
B
%s
*synth2*
Module sd_controller 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     10 Bit       Adders := 2     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               56 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               10 Bit    Registers := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                8 Bit    Registers := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 5     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input     10 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      5 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      4 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      3 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 12    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  20 Input      1 Bit        Muxes := 13    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
;
%s
*synth2#
Module labkit 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit       Adders := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                8 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 8     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     32 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   5 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     13 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      4 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 9     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 10    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   5 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
7
%s
*synth2
Module SD 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 2     
2default:defaulthp
x
ê
;
%s
*synth2#
Module pc_reg 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 1     
2default:defaulthp
x
ê
:
%s
*synth2"
Module if_id 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
7
%s
*synth2
Module id 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 11    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   5 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      7 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      3 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      2 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  29 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
:
%s
*synth2"
Module id_ex 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                8 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
<
%s
*synth2$
Module regfile 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 32    
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 8     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 32    
2default:defaulthp
x
ê
=
%s
*synth2%
Module Adder_32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     33 Bit       Adders := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 1     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
>
%s
*synth2&
Module Subber_32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     33 Bit       Adders := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
D
%s
*synth2,
Module barrelshifter32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit       Adders := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 15    
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
>
%s
*synth2&
Module BitCal_32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
8
%s
*synth2 
+---XORs : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit         XORs := 1     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
;
%s
*synth2#
Module Lui_32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
;
%s
*synth2#
Module Slt_32 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     33 Bit       Adders := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
8
%s
*synth2 
Module alu 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

Module MULT 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
?
%s
*synth2'
+---Multipliers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                32x32  Multipliers := 1     
2default:defaulthp
x
ê
:
%s
*synth2"
Module MULTU 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
?
%s
*synth2'
+---Multipliers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                32x32  Multipliers := 1     
2default:defaulthp
x
ê
8
%s
*synth2 
Module DIV 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     33 Bit       Adders := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      6 Bit       Adders := 1     
2default:defaulthp
x
ê
8
%s
*synth2 
+---XORs : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit         XORs := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 4     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                6 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     33 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 6     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      6 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 5     
2default:defaulthp
x
ê
9
%s
*synth2!

Module DIVU 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     33 Bit       Adders := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit       Adders := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 3     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     33 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 4     
2default:defaulthp
x
ê
8
%s
*synth2 
Module MDU 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 6     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      1 Bit        Muxes := 1     
2default:defaulthp
x
ê
7
%s
*synth2
Module ex 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit       Adders := 1     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   6 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  33 Input      6 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  26 Input      3 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	  25 Input      1 Bit        Muxes := 3     
2default:defaulthp
x
ê
;
%s
*synth2#
Module ex_mem 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               64 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 5     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                8 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                2 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     64 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      2 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
8
%s
*synth2 
Module mem 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input     32 Bit        Muxes := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 6     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input     16 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      5 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   4 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   3 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input      2 Bit        Muxes := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   9 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
;
%s
*synth2#
Module mem_wb 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 3     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                5 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                1 Bit    Registers := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      1 Bit        Muxes := 2     
2default:defaulthp
x
ê
=
%s
*synth2%
Module hilo_reg 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 2     
2default:defaulthp
x
ê
9
%s
*synth2!

Module ctrl 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      6 Bit        Muxes := 2     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      4 Bit        Muxes := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
Module data_ram 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
8
%s
*synth2 
+---RAMs : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               8K Bit         RAMs := 4     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 2     
2default:defaulthp
x
ê
<
%s
*synth2$
Module seg7x16 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
:
%s
*synth2"
+---Adders : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input      3 Bit       Adders := 1     
2default:defaulthp
x
ê
=
%s
*synth2%
+---Registers : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	               32 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                8 Bit    Registers := 1     
2default:defaulthp
x
ê
Z
%s
*synth2B
.	                3 Bit    Registers := 1     
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   8 Input      8 Bit        Muxes := 1     
2default:defaulthp
x
ê
?
%s
*synth2'
Module sw_mem_sel 
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
9
%s
*synth2!

+---Muxes : 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	   2 Input     32 Bit        Muxes := 1     
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
[
%s
*synth2C
/Finished RTL Hierarchical Component Statistics
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
H
%s
*synth20
Start Part Resource Summary
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
É
%s
*synth2k
WPart Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Finished Part Resource Summary
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
W
%s
*synth2?
+Start Cross Boundary and Area Optimization
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
]
%s
*synth2E
1Warning: Parallel synthesis criteria is not met 
2default:defaulthp
x
ê
Ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2'
sbbu_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2'
sbbu_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
sra_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
‹
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2*
sll_slr_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
srl_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
and_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
◊
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2%
or_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
xor_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
nor_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 
slt/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2!

sltu/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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+Unused sequential element %s was removed. 
4326*oasys2<
(ddr2_wr_ins/ddr2_write_ctr_imp/ACK_O_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
682default:default8@Z8-6014hpxê
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+Unused sequential element %s was removed. 
4326*oasys2>
*ddr2_wr_ins/ddr2_write_ctr_imp/read_en_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
672default:default8@Z8-6014hpxê
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+Unused sequential element %s was removed. 
4326*oasys2?
+ddr2_wr_ins/ddr2_write_ctr_imp/app_addr_reg2default:default2≤
õD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_write_control.v2default:default2
632default:default8@Z8-6014hpxê
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+Unused sequential element %s was removed. 
4326*oasys2A
-ddr2_wr_ins/ddr2_weight_load_ins/app_addr_reg2default:default2±
öD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/ddr2_read_control.v2default:default2
582default:default8@Z8-6014hpxê
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[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[0]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[0]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[1]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[1]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[2]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[2]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[3]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
‘
[ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2'
cache_status_reg[3]2default:default2
22default:default2
52default:defaultZ8-5544hpxê
◊
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2%
ddr_to_imem_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
‹
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2*
loadData_ddrToImemDone2default:default2
322default:default2
252default:defaultZ8-5545hpxê
‹
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2*
ddr_boot_inblock_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
⁄
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2(
ddr_boot_block_count2default:default2
322default:default2
252default:defaultZ8-5545hpxê
·
+Unused sequential element %s was removed. 
4326*oasys2D
0SD_PHY_Controller/sdcont/ready_for_next_byte_reg2default:default2≠
ñD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/ThreeLevelMem/sd_controller.v2default:default2
832default:default8@Z8-6014hpxê
î
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys28
$SD_PHY_Controller/sdcont/bit_counter2default:defaultZ8-5546hpxê
ï
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys29
%SD_PHY_Controller/sdcont/byte_counter2default:defaultZ8-5546hpxê
é
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys22
SD_PHY_Controller/sdcont/state2default:defaultZ8-5546hpxê
ï
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys29
%SD_PHY_Controller/sdcont/return_state2default:defaultZ8-5546hpxê
ï
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys29
%SD_PHY_Controller/sdcont/return_state2default:defaultZ8-5546hpxê
é
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys22
SD_PHY_Controller/sdcont/state2default:defaultZ8-5546hpxê
Î
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys29
%SD_PHY_Controller/sdcont/boot_counter2default:default2
272default:default2
252default:defaultZ8-5545hpxê
‰
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys22
SD_PHY_Controller/sdcont/state2default:default2
272default:default2
252default:defaultZ8-5545hpxê
ú
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2@
,SD_PHY_Controller/sdcont/ready_for_next_byte2default:defaultZ8-5546hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
lui_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2'
sbbu_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
Ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2'
sbbu_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
and_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
◊
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2%
or_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
xor_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
nor_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2!

sltu/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
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^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2 
slt/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
sra_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ÿ
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2&
srl_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
‹
^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2*
sll_slr_block/oData_Z02default:default2
322default:default2
252default:defaultZ8-5545hpxê
ﬁ
cNot enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is %s4267*oasys2
42default:default2¢
ãD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/new/PipelineCpu/mult.v2default:default2
92default:default8@Z8-5845hpxê
m
%s
*synth2U
ADSP Report: Generating DSP multiplier/z, operation Mode is: A*B.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
x
%s
*synth2`
LDSP Report: Generating DSP multiplier/z, operation Mode is: (PCIN>>17)+A*B.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
m
%s
*synth2U
ADSP Report: Generating DSP multiplier/z, operation Mode is: A*B.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
x
%s
*synth2`
LDSP Report: Generating DSP multiplier/z, operation Mode is: (PCIN>>17)+A*B.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
q
%s
*synth2Y
EDSP Report: operator multiplier/z is absorbed into DSP multiplier/z.
2default:defaulthp
x
ê
w
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
whilo_o2default:defaultZ8-5546hpxê
z
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2

clz_result2default:defaultZ8-5546hpxê
ó
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
alu_a_toalu2default:defaultZ8-5587hpxê
{
8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2
id0/aluop_o2default:defaultZ8-5546hpxê
ó
TROM size for "%s" is below threshold of ROM address width. It will be mapped to LUTs4039*oasys2
id0/aluop_o2default:defaultZ8-5587hpxê
≥
6propagating constant %s across sequential element (%s)3333*oasys2
12default:default2B
.\SD_0/SD_PHY_Controller/sdcont/cmd_out_reg[0] 2default:defaultZ8-3333hpxê
¥
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2C
/\SD_0/SD_PHY_Controller/flag_srd_adr_ready_reg 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[0] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[1] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[2] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[3] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[4] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SD_0/SD_PHY_Controller/sector_cnt_reg[3] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SD_0/SD_PHY_Controller/sector_cnt_reg[4] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SD_0/SD_PHY_Controller/sector_cnt_reg[2] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SD_0/SD_PHY_Controller/sector_cnt_reg[1] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\SD_0/SD_PHY_Controller/sector_cnt_reg[0] 2default:defaultZ8-3333hpxê
≤
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2A
-\SD_0/SD_PHY_Controller/write_bytes_next_reg 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\SD_0/SD_PHY_Controller/din_reg[5] 2default:defaultZ8-3333hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[29]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[31]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[31]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[30]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[30]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[28]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[28]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[27]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[26]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[27]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[27]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[20]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[21]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[22]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[23]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[24]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[25]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[19]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[11]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[19]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[12]2default:default2
FDCE2default:default2A
-databus_0/ddr_to_imem_firstcell_count_reg[19]2default:defaultZ8-3886hpxê
‰
"merging instance '%s' (%s) to '%s'3436*oasys2A
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?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[36]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[37]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[37]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[38]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[38]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[39]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[39]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[40]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[40]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[41]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[41]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[42]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[42]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[43]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[43]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[44]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[44]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[45]2default:defaultZ8-3886hpxê
à
"merging instance '%s' (%s) to '%s'3436*oasys2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[45]2default:default2
FDRE2default:default2S
?sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[46]2default:defaultZ8-3886hpxê
›
ÅMessage '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-38862default:default2
1002default:defaultZ17-14hpxê
«
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2V
B\sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[127] 2default:defaultZ8-3333hpxê
Ø
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2>
*\databus_0/ddr_boot_inblock_count_reg[23] 2default:defaultZ8-3333hpxê
≠
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\databus_0/bootdonoe_idle_count_reg[15] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\databus_0/cache_status_reg[3][22] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\databus_0/cache_status_reg[2][22] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\databus_0/cache_status_reg[1][22] 2default:defaultZ8-3333hpxê
®
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default27
#\databus_0/cache_status_reg[0][22] 2default:defaultZ8-3333hpxê
°
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default20
\databus_0/cur_state_reg[2] 2default:defaultZ8-3333hpxê
ö
6propagating constant %s across sequential element (%s)3333*oasys2
12default:default2)
\seg7/o_seg_r_reg[7] 2default:defaultZ8-3333hpxê
≠
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default2<
(\sealedDDR_0/ddr2_wr_ins/app_cmd_reg[2] 2default:defaultZ8-3333hpxê
—
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2N
:sealedDDR_0/ddr2_wr_ins/ddr2_weight_load_ins/cstate_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
Ω
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2:
&sealedDDR_0/ddr2_wr_ins/app_cmd_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
œ
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2L
8sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/cstate_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
–
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2M
9sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_cmd_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
◊
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2T
@sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_wdf_data_reg[127]2default:default2
SOPC2default:defaultZ8-3332hpxê
“
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2O
;sealedDDR_0/ddr2_wr_ins/ddr2_weight_load_ins/app_cmd_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
“
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2O
;sealedDDR_0/ddr2_wr_ins/ddr2_weight_load_ins/app_cmd_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
∫
ESequential element (%s) is unused and will be removed from module %s.3332*oasys27
#databus_0/ddr_to_imem_count_reg[31]2default:default2
SOPC2default:defaultZ8-3332hpxê
ƒ
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2A
-databus_0/ddr_to_imem_firstcell_count_reg[15]2default:default2
SOPC2default:defaultZ8-3332hpxê
±
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2.
databus_0/cur_state_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!databus_0/cache_status_reg[0][22]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!databus_0/cache_status_reg[1][22]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!databus_0/cache_status_reg[2][22]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!databus_0/cache_status_reg[3][22]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(databus_0/ddr_boot_inblock_count_reg[23]2default:default2
SOPC2default:defaultZ8-3332hpxê
Ω
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2:
&databus_0/bootdonoe_idle_count_reg[15]2default:default2
SOPC2default:defaultZ8-3332hpxê
∂
ESequential element (%s) is unused and will be removed from module %s.3332*oasys23
databus_0/sd_mem_read_write_reg2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[7]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[6]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[5]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[4]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[3]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[1]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/din_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
ƒ
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2A
-SD_0/SD_PHY_Controller/flag_srd_adr_ready_reg2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[7]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[6]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[5]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[4]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[3]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[1]2default:default2
SOPC2default:defaultZ8-3332hpxê
∏
ESequential element (%s) is unused and will be removed from module %s.3332*oasys25
!SD_0/SD_PHY_Controller/adr_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
√
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2@
,SD_0/SD_PHY_Controller/sdcont/cmd_out_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
¬
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2?
+SD_0/SD_PHY_Controller/write_bytes_next_reg2default:default2
SOPC2default:defaultZ8-3332hpxê
ƒ
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2A
-SD_0/SD_PHY_Controller/sd_write_nxt_first_reg2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/sector_cnt_reg[4]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/sector_cnt_reg[3]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/sector_cnt_reg[2]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/sector_cnt_reg[1]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/sector_cnt_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
¥
ESequential element (%s) is unused and will be removed from module %s.3332*oasys21
SD_0/SD_PHY_Controller/wr_reg2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[31]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[30]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[29]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[28]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[27]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[26]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[25]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[24]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[23]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[22]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[21]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[20]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[19]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[18]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[17]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[16]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[15]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[14]2default:default2
SOPC2default:defaultZ8-3332hpxê
¿
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2=
)SD_0/SD_PHY_Controller/addr_sdmem_reg[13]2default:default2
SOPC2default:defaultZ8-3332hpxê
ø
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2<
(SD_0/SD_PHY_Controller/addr_sdmem_reg[0]2default:default2
SOPC2default:defaultZ8-3332hpxê
™
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2)
i_ALU/slt/oData_C_reg2default:default2
ex2default:defaultZ8-3332hpxê
´
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
i_ALU/sltu/oData_C_reg2default:default2
ex2default:defaultZ8-3332hpxê
§
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2#
i_ALU/carry_reg2default:default2
ex2default:defaultZ8-3332hpxê
ß
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2&
i_ALU/overflow_reg2default:default2
ex2default:defaultZ8-3332hpxê
ß
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2&
clz_result_reg[31]2default:default2
ex2default:defaultZ8-3332hpxê
°
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2 
cnt_o_reg[1]2default:default2
ex2default:defaultZ8-3332hpxê
°
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2 
cnt_o_reg[0]2default:default2
ex2default:defaultZ8-3332hpxê
≥
ESequential element (%s) is unused and will be removed from module %s.3332*oasys21
id_ex0/ex_is_in_delayslot_reg2default:default2
CPU2default:defaultZ8-3332hpxê
≤
ESequential element (%s) is unused and will be removed from module %s.3332*oasys20
id_ex0/is_in_delayslot_o_reg2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[31]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[30]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[29]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[28]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[27]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[26]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[25]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[24]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[23]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[22]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[21]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[20]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[19]2default:default2
CPU2default:defaultZ8-3332hpxê
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ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[18]2default:default2
CPU2default:defaultZ8-3332hpxê
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ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[17]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
id_ex0/ex_inst_reg[16]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[63]2default:default2
CPU2default:defaultZ8-3332hpxê
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ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[62]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[61]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[60]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[59]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[58]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[57]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[56]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[55]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[54]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[53]2default:default2
CPU2default:defaultZ8-3332hpxê
¨
ESequential element (%s) is unused and will be removed from module %s.3332*oasys2*
ex_mem0/hilo_o_reg[52]2default:default2
CPU2default:defaultZ8-3332hpxê
›
ÅMessage '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances.
14*common2 
Synth 8-33322default:default2
1002default:defaultZ17-14hpxê
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s*synth2¢
çFinished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:01:02 . Memory (MB): peak = 867.324 ; gain = 546.688
2default:defaulthpxê
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ò
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Start ROM, RAM, DSP and Shift Register Reporting
2default:defaulthpxê
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%s*synth2f
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2default:defaulthpxê
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%s*synth2S
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Distributed RAM: Preliminary Mapping  Report (see note below)
2default:defaulthpxê
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%s*synth2x
d+------------+------------------------------+-----------+----------------------+------------------+
2default:defaulthpxê
ë
%s*synth2y
e|Module Name | RTL Object                   | Inference | Size (Depth x Width) | Primitives       | 
2default:defaulthpxê
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%s*synth2x
d+------------+------------------------------+-----------+----------------------+------------------+
2default:defaulthpxê
ë
%s*synth2y
e|SOPC        | data_ram0/m_data_block_0_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthpxê
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%s*synth2y
e|SOPC        | data_ram0/m_data_block_1_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthpxê
ë
%s*synth2y
e|SOPC        | data_ram0/m_data_block_2_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthpxê
ë
%s*synth2y
e|SOPC        | data_ram0/m_data_block_3_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthpxê
ë
%s*synth2y
e+------------+------------------------------+-----------+----------------------+------------------+

2default:defaulthpxê
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%s*synth2¨
óNote: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
2default:defaulthpxê
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%s*synth2G
3
DSP: Preliminary Mapping  Report (see note below)
2default:defaulthpxê
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%s*synth2ì
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
2default:defaulthpxê
Æ
%s*synth2ï
Ä|Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
2default:defaulthpxê
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%s*synth2ì
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
2default:defaulthpxê
Æ
%s*synth2ï
Ä|MDU         | A*B            | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
2default:defaulthpxê
Æ
%s*synth2ï
Ä|MDU         | (PCIN>>17)+A*B | 16     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
2default:defaulthpxê
Æ
%s*synth2ï
Ä|MDU         | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
2default:defaulthpxê
Æ
%s*synth2ï
Ä|MDU         | (PCIN>>17)+A*B | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
2default:defaulthpxê
Æ
%s*synth2ï
Ä+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

2default:defaulthpxê
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%s*synth2ê
˚Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
2default:defaulthpxê
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%s*synth2õ
Ü---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
2default:defaulthpxê
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%s*synth2f
R---------------------------------------------------------------------------------
2default:defaulthpxê
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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%s
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+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2:
&Start Applying XDC Timing Constraints
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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2Moved timing constraint from pin '%s' to pin '%s'
4028*oasys2B
.sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram/ui_clk2default:default2K
7sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram/bbstub_ui_clk/O2default:defaultZ8-5578hpxê
…
2Moved timing constraint from pin '%s' to pin '%s'
4028*oasys24
 sealedDDR_0/clk_divider/clk_out12default:default2=
)sealedDDR_0/clk_divider/bbstub_clk_out1/O2default:defaultZ8-5578hpxê
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redefining clock '%s'565*oasys2
	clk100mhz2default:defaultZ8-565hpxê
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2Moved timing constraint from pin '%s' to pin '%s'
4028*oasys2(
clk_divider/clk_out12default:default21
clk_divider/bbstub_clk_out1/O2default:defaultZ8-5578hpxê
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SMoved %s constraints on hierarchical pins to their respective driving/loading pins
4235*oasys2
32default:defaultZ8-5819hpxê
~
%s
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R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s*synth2ù
àFinished Applying XDC Timing Constraints : Time (s): cpu = 00:01:13 ; elapsed = 00:01:21 . Memory (MB): peak = 878.488 ; gain = 557.852
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2.
Start Timing Optimization
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ê
|Finished Timing Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:27 . Memory (MB): peak = 940.543 ; gain = 619.906
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2ò
É---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
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%s
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2default:defaulthp
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%s
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Distributed RAM: Final Mapping  Report
2default:defaulthp
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%s
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2default:defaulthp
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%s
*synth2y
e|Module Name | RTL Object                   | Inference | Size (Depth x Width) | Primitives       | 
2default:defaulthp
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%s
*synth2x
d+------------+------------------------------+-----------+----------------------+------------------+
2default:defaulthp
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ë
%s
*synth2y
e|SOPC        | data_ram0/m_data_block_0_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthp
x
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%s
*synth2y
e|SOPC        | data_ram0/m_data_block_1_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthp
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ë
%s
*synth2y
e|SOPC        | data_ram0/m_data_block_2_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthp
x
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ë
%s
*synth2y
e|SOPC        | data_ram0/m_data_block_3_reg | Implied   | 1 K x 8              | RAM256X1S x 32   | 
2default:defaulthp
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ë
%s
*synth2y
e+------------+------------------------------+-----------+----------------------+------------------+

2default:defaulthp
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%s
*synth2õ
Ü---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
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%s
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2default:defaulthp
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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++-+--------------+------------+----------+
2default:defaulthp
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%s
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2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2-
Start Technology Mapping
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][17] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][21] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][18] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][22] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][30] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][16] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][20] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][19] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][23] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][24] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][25] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][26] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][27] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][28] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][29] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][13] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][14] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][8] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][15] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][9] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][10] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][11] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][12] 2default:defaultZ8-3333hpxê
•
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default24
 \sccpu/regfile1/regs_reg[0][31] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][1] 2default:defaultZ8-3333hpxê
§
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][5] 2default:defaultZ8-3333hpxê
§
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][2] 2default:defaultZ8-3333hpxê
§
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][6] 2default:defaultZ8-3333hpxê
§
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][0] 2default:defaultZ8-3333hpxê
§
6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][4] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][3] 2default:defaultZ8-3333hpxê
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6propagating constant %s across sequential element (%s)3333*oasys2
02default:default23
\sccpu/regfile1/regs_reg[0][7] 2default:defaultZ8-3333hpxê
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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{Finished Technology Mapping : Time (s): cpu = 00:01:24 ; elapsed = 00:01:32 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
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2default:defaulthp
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2default:defaulthp
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Start IO Insertion
2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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Start Final Netlist Cleanup
2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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Finished Final Netlist Cleanup
2default:defaulthp
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2default:defaulthp
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2default:defaulthpxê
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Report Check Netlist: 
2default:defaulthp
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2default:defaulthp
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I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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2default:defaulthp
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#Start Renaming Generated Instances
2default:defaulthp
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2default:defaulthp
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2default:defaulthpxê
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2default:defaulthp
x
ê
E
%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
L
%s
*synth24
 Start Rebuilding User Hierarchy
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
∞
%s*synth2ó
ÇFinished Rebuilding User Hierarchy : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Start Renaming Generated Ports
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Ø
%s*synth2ñ
ÅFinished Renaming Generated Ports : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
M
%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
±
%s*synth2ò
ÉFinished Handling Custom Attributes : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
J
%s
*synth22
Start Renaming Generated Nets
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Æ
%s*synth2ï
ÄFinished Renaming Generated Nets : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
±
%s
*synth2ò
É---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23

Static Shift Register Report:
2default:defaulthp
x
ê
…
%s
*synth2∞
õ+------------+-----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
2default:defaulthp
x
ê
 
%s
*synth2±
ú|Module Name | RTL Name                                      | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 
2default:defaulthp
x
ê
…
%s
*synth2∞
õ+------------+-----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
2default:defaulthp
x
ê
 
%s
*synth2±
ú|SOPC        | SD_0/SD_PHY_Controller/sdcont/cmd_out_reg[55] | 8      | 1     | YES          | NO                 | YES               | 1      | 0       | 
2default:defaulthp
x
ê
 
%s
*synth2±
ú+------------+-----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+

2default:defaulthp
x
ê
¥
%s
*synth2õ
Ü---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Start Writing Synthesis Report
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
A
%s
*synth2)

Report BlackBoxes: 
2default:defaulthp
x
ê
Q
%s
*synth29
%+------+----------------+----------+
2default:defaulthp
x
ê
Q
%s
*synth29
%|      |BlackBox name   |Instances |
2default:defaulthp
x
ê
Q
%s
*synth29
%+------+----------------+----------+
2default:defaulthp
x
ê
Q
%s
*synth29
%|1     |cache           |         1|
2default:defaulthp
x
ê
Q
%s
*synth29
%|2     |clk_wiz_for_cpu |         1|
2default:defaulthp
x
ê
Q
%s
*synth29
%|3     |SDTrans         |         1|
2default:defaulthp
x
ê
Q
%s
*synth29
%|4     |clk_wiz_0       |         1|
2default:defaulthp
x
ê
Q
%s
*synth29
%|5     |ddr2_ram        |         1|
2default:defaulthp
x
ê
Q
%s
*synth29
%+------+----------------+----------+
2default:defaulthp
x
ê
A
%s*synth2)

Report Cell Usage: 
2default:defaulthpxê
M
%s*synth25
!+------+----------------+------+
2default:defaulthpxê
M
%s*synth25
!|      |Cell            |Count |
2default:defaulthpxê
M
%s*synth25
!+------+----------------+------+
2default:defaulthpxê
M
%s*synth25
!|1     |SDTrans         |     1|
2default:defaulthpxê
M
%s*synth25
!|2     |cache           |     1|
2default:defaulthpxê
M
%s*synth25
!|3     |clk_wiz_0       |     1|
2default:defaulthpxê
M
%s*synth25
!|4     |clk_wiz_for_cpu |     1|
2default:defaulthpxê
M
%s*synth25
!|5     |ddr2_ram        |     1|
2default:defaulthpxê
M
%s*synth25
!|6     |BUFG            |     4|
2default:defaulthpxê
M
%s*synth25
!|7     |CARRY4          |   304|
2default:defaulthpxê
M
%s*synth25
!|8     |DSP48E1_1       |     4|
2default:defaulthpxê
M
%s*synth25
!|9     |LUT1            |   244|
2default:defaulthpxê
M
%s*synth25
!|10    |LUT2            |   739|
2default:defaulthpxê
M
%s*synth25
!|11    |LUT3            |   494|
2default:defaulthpxê
M
%s*synth25
!|12    |LUT4            |   282|
2default:defaulthpxê
M
%s*synth25
!|13    |LUT5            |   537|
2default:defaulthpxê
M
%s*synth25
!|14    |LUT6            |  1508|
2default:defaulthpxê
M
%s*synth25
!|15    |MUXF7           |   268|
2default:defaulthpxê
M
%s*synth25
!|16    |MUXF8           |    32|
2default:defaulthpxê
M
%s*synth25
!|17    |RAM256X1S       |   128|
2default:defaulthpxê
M
%s*synth25
!|18    |SRL16E          |     1|
2default:defaulthpxê
M
%s*synth25
!|19    |FDCE            |   401|
2default:defaulthpxê
M
%s*synth25
!|20    |FDPE            |    27|
2default:defaulthpxê
M
%s*synth25
!|21    |FDRE            |  1922|
2default:defaulthpxê
M
%s*synth25
!|22    |FDSE            |    54|
2default:defaulthpxê
M
%s*synth25
!|23    |LD              |    75|
2default:defaulthpxê
M
%s*synth25
!|24    |LDC             |    96|
2default:defaulthpxê
M
%s*synth25
!|25    |IBUF            |    18|
2default:defaulthpxê
M
%s*synth25
!|26    |OBUF            |    25|
2default:defaulthpxê
M
%s*synth25
!|27    |OBUFT           |    13|
2default:defaulthpxê
M
%s*synth25
!+------+----------------+------+
2default:defaulthpxê
E
%s
*synth2-

Report Instance Areas: 
2default:defaulthp
x
ê
l
%s
*synth2T
@+------+---------------------------+-------------------+------+
2default:defaulthp
x
ê
l
%s
*synth2T
@|      |Instance                   |Module             |Cells |
2default:defaulthp
x
ê
l
%s
*synth2T
@+------+---------------------------+-------------------+------+
2default:defaulthp
x
ê
l
%s
*synth2T
@|1     |top                        |                   |  7406|
2default:defaulthp
x
ê
l
%s
*synth2T
@|2     |  SD_0                     |SD                 |   557|
2default:defaulthp
x
ê
l
%s
*synth2T
@|3     |    SD_PHY_Controller      |labkit             |   555|
2default:defaulthp
x
ê
l
%s
*synth2T
@|4     |      div1                 |clock_divider      |     2|
2default:defaulthp
x
ê
l
%s
*synth2T
@|5     |      div2                 |clock_divider_0    |     2|
2default:defaulthp
x
ê
l
%s
*synth2T
@|6     |      sdcont               |sd_controller      |   364|
2default:defaulthp
x
ê
l
%s
*synth2T
@|7     |  data_ram0                |data_ram           |   185|
2default:defaulthp
x
ê
l
%s
*synth2T
@|8     |  databus_0                |DataBus            |   244|
2default:defaulthp
x
ê
l
%s
*synth2T
@|9     |  sccpu                    |CPU                |  5457|
2default:defaulthp
x
ê
l
%s
*synth2T
@|10    |    ex0                    |ex                 |  1504|
2default:defaulthp
x
ê
l
%s
*synth2T
@|11    |      I_MDU                |MDU                |   745|
2default:defaulthp
x
ê
l
%s
*synth2T
@|12    |        DIV                |DIV                |   413|
2default:defaulthp
x
ê
l
%s
*synth2T
@|13    |        DIVU               |DIVU               |   269|
2default:defaulthp
x
ê
l
%s
*synth2T
@|14    |        multiplier         |MULT               |    63|
2default:defaulthp
x
ê
l
%s
*synth2T
@|15    |      i_ALU                |alu                |    67|
2default:defaulthp
x
ê
l
%s
*synth2T
@|16    |        sbbu_block         |Subber_32          |    16|
2default:defaulthp
x
ê
l
%s
*synth2T
@|17    |        slt                |Slt_32             |    51|
2default:defaulthp
x
ê
l
%s
*synth2T
@|18    |    ex_mem0                |ex_mem             |   416|
2default:defaulthp
x
ê
l
%s
*synth2T
@|19    |    hilo_reg0              |hilo_reg           |    64|
2default:defaulthp
x
ê
l
%s
*synth2T
@|20    |    id0                    |id                 |   177|
2default:defaulthp
x
ê
l
%s
*synth2T
@|21    |    id_ex0                 |id_ex              |   702|
2default:defaulthp
x
ê
l
%s
*synth2T
@|22    |    if_id0                 |if_id              |   447|
2default:defaulthp
x
ê
l
%s
*synth2T
@|23    |    mem0                   |mem                |    32|
2default:defaulthp
x
ê
l
%s
*synth2T
@|24    |    mem_wb0                |mem_wb             |   230|
2default:defaulthp
x
ê
l
%s
*synth2T
@|25    |    pc_reg0                |pc_reg             |    45|
2default:defaulthp
x
ê
l
%s
*synth2T
@|26    |    regfile1               |regfile            |  1840|
2default:defaulthp
x
ê
l
%s
*synth2T
@|27    |  sealedDDR_0              |sealedDDR          |   782|
2default:defaulthp
x
ê
l
%s
*synth2T
@|28    |    ddr2_wr_ins            |ddr2_wr            |   389|
2default:defaulthp
x
ê
l
%s
*synth2T
@|29    |      ddr2_weight_load_ins |ddr2_read_control  |     7|
2default:defaulthp
x
ê
l
%s
*synth2T
@|30    |      ddr2_write_ctr_imp   |ddr2_write_control |    45|
2default:defaulthp
x
ê
l
%s
*synth2T
@|31    |  seg7                     |seg7x16            |    88|
2default:defaulthp
x
ê
l
%s
*synth2T
@+------+---------------------------+-------------------+------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Ø
%s*synth2ñ
ÅFinished Writing Synthesis Report : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
t
%s
*synth2\
HSynthesis finished with 0 errors, 0 critical warnings and 491 warnings.
2default:defaulthp
x
ê
´
%s
*synth2í
~Synthesis Optimization Runtime : Time (s): cpu = 00:01:09 ; elapsed = 00:01:22 . Memory (MB): peak = 984.301 ; gain = 281.258
2default:defaulthp
x
ê
¨
%s
*synth2ì
Synthesis Optimization Complete : Time (s): cpu = 00:01:27 ; elapsed = 00:01:35 . Memory (MB): peak = 984.301 ; gain = 663.664
2default:defaulthp
x
ê
B
 Translating synthesized netlist
350*projectZ1-571hpxê
g
-Analyzing %s Unisim elements for replacement
17*netlist2
9252default:defaultZ29-17hpxê
j
2Unisim Transformation completed in %s CPU seconds
28*netlist2
02default:defaultZ29-28hpxê
K
)Preparing netlist for logic optimization
349*projectZ1-570hpxê
g
1Inserted %s IBUFs to IO ports without IO buffers.100*opt2
12default:defaultZ31-140hpxê
v
)Pushed %s inverter(s) to %s load pin(s).
98*opt2
12default:default2
322default:defaultZ31-138hpxê
–
!Unisim Transformation Summary:
%s111*project2ä
ı  A total of 299 instances were transformed.
  LD => LDCE: 75 instances
  LDC => LDCE: 64 instances
  LDC => LDCE (inverted pins: G): 32 instances
  RAM256X1S => RAM256X1S (MUXF7, MUXF7, MUXF8, RAMS64E, RAMS64E, RAMS64E, RAMS64E): 128 instances
2default:defaultZ1-111hpxê
U
Releasing license: %s
83*common2
	Synthesis2default:defaultZ17-83hpxê
…
G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
4402default:default2
2672default:default2
12default:default2
02default:defaultZ4-41hpxê
^
%s completed successfully
29*	vivadotcl2 
synth_design2default:defaultZ4-42hpxê
Ö
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
synth_design: 2default:default2
00:01:312default:default2
00:01:402default:default2
984.3012default:default2
663.6642default:defaultZ17-268hpxê
K
"No constraint will be written out.1103*constraintsZ18-5210hpxê
ı
 The %s '%s' has been generated.
621*common2

checkpoint2default:default2è
{D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/synth_1/SOPC.dcp2default:defaultZ17-1381hpxê
é
%s4*runtcl2r
^Executing : report_utilization -file SOPC_utilization_synth.rpt -pb SOPC_utilization_synth.pb
2default:defaulthpxê
à
sreport_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.146 . Memory (MB): peak = 984.301 ; gain = 0.000
*commonhpxê
Ä
Exiting %s at %s...
206*common2
Vivado2default:default2,
Tue Dec 25 20:06:57 20182default:defaultZ17-206hpxê


End Record