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    <h2>Address space editor</h2>
    <p>
      Address space editor can be used to edit the details of an
      address space within component.  <i>Address space</i> defines a
      logical address space seen by a master <i>bus interface</i>. It can be
      split into smaller <i>sgements</i>.
    </p>
    <p>
      On the left side are the editor fields that can be used to set
      the details of an address space. The right side contains a
      visualization displaying the address space in its current state and
	  automatically updates on changes.
	  It displays how the segments are positioned within the address space. 
	  Mismatches, e.g. sum of segment ranges being greater than address block range, can 
      be easily spotted from the visualization.
    </p>
	<p>
	    <b>Name</b> is a mandatory identifier for the <i>address space</i>.
    </p>
    <p>
        <b>Display name</b> is an optional and used for a more user-friendly identifier.
    </p>
    <p>
        <b>Description</b> is an optional field for textual description of the <i>address space</i>.		
    </p>
    <p>
        <b>Addressable unit bits</b> (AUB) specifies the number of bits each address increment contains, 
        e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map.
    </p>
    <p>
      <b>Range</b> is the size of the address space expressed as addressable units, i.e. the number of
      separate addresses.
    </p>
    <p>
      <b>Width</b> is the data width of a row in bits. It defines the maximum size for a single transfer.
    </p>
	<p>
        <b>Is present</b> is optional and allows enabling/disabling of a <i>address space</i>
        presence in a <i>component</i>. Value 1 indicates that the <i>address space</i>
        is present in the <i>component</i> whereas value 0 marks the address space to be
        treated as if it does not exist. Is present can be given as a SystemVerilog expression,
        but it must evaluate to 1 or 0.</p>
	<p>
    <p>
      <b>Master interface binding</b> shows the master <i>bus interfaces</i> bound to the address space. 
	  The binding can be set in the bus interface editor.
    </p>
	
    <h3>Segments</h3>
    <p>
      <b>Segments</b> editor can be used to describe sections of the address space, i.e. split it into smaller
        segments.
    </p>
	<p>
	    <b>Name</b> is a mandatory identifier for the <i>segment</i>.
    </p>
    <p>
      <b>Offset</b> is mandatory and defines the starting address of the <i>segment</i> in address unit bits.
	</p>
	<p>
		<b>Range</b> is mandatory and defines the size of the <i>segment</i> in address unit bits.
    </p>
		<p>
        <b>Is present</b> is optional and allows enabling/disabling of a <i>segment</i>
        presence in an <i>address space</i>. Value 1 indicates that the <i>segment</i>
        is present in the <i>address space</i> whereas value 0 marks the segment to be
        treated as if it does not exist. Is present can be given as a SystemVerilog expression,
        but it must evaluate to 1 or 0.</p>
	<p>
	 <p>
        <b>Description</b> is an optional field for textual description of the <i>segment</i>.		
    </p>

    <h3>Local memory map</h3>
    <p>
      <b>Local memory map</b> is optional but some processors require specifying a memory map that is local
      to the component. It consists of <i>address blocks</i> similarly to the <i>memory map</i> of a slave
      <i>bus interface</i>.
	  Hence, the address blocks can contain either memory or registers, and registers can contain bit fields.
    </p>
    <p>
      Local memory map is useful for storing the programmer's view to interrupts registers, timers,
      and other local things. The overall address space of a component is a concatenation of local memory map
      (e.g. timers) and the memory maps of other units (e.g. registers of accelerator A, registers of
      accelerator B etc.)
    </p>
	
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