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    <h2>Address block editor</h2>
    <p>
        Address block editor is used to edit the details of an address block and the registers
        contained within it.
    </p>
    <p>
        <b>Name</b> is a mandatory identifier for the <i>address block</i>. The name must
        be unique within all the <i>address blocks</i> of the containing <i>memory map</i>.
    </p>
    <p>
        <b>Display name</b> is an optional and used for a more user-friendly identifier.
    </p>
    <p>
        <b>Description</b> is an optional field for textual description of the <i>address block</i>.
    </p>
    <p>
        <b>Base address</b> is mandatory and specifies the starting address for the <i>address
            block</i> in address unit bits.
    </p>
    <p>
        <b>Range</b> is mandatory and specifies the size of the block in <i>address units bits</i>.
    </p>
    <p>
        <b>Width</b> is mandatory and defines the data width of a row in the <i>address block</i>.
        The width value is given in bits.
    </p>

	<p>
        <b>Is present</b> is optional and allows enabling/disabling of a <i>address block</i>
        presence in a <i>memory map</i>. Value 1 indicates that the <i>address block</i>
        is present in the <i>memory map</i> whereas value 0 marks the address block to be
        treated as if it does not exist. Is present can be given as a SystemVerilog expression,
        but it must evaluate to 1 or 0.</p>
	<p>

    <p>
        <b>Usage</b> is a mandatory value to specify the usage of the address block and
        may have one of the following values:
    </p>
    <ul>
        <li><b>Memory</b> The <i>address block</i> is ROM, RAM or write-only memory as defined
            by <b>access</b>. Registers and register files within will be considered virtual.</li>
        <li><b>Register</b> The <i>address block</i> range may contain registers.</li>
        <li><b>Reserved</b> The <i>address block</i> is reserved for other usage and shall not
            contain registers or register files. </li>
    </ul>
    <p>
        <b>Access</b> is optional and specifies the accessability of the address block.
        The possible values are:
    </p>
    <ul>
        <li><b>read-write</b>. Both read and write transactions may have an effect on this <i>
            address block</i>.</li>
        <li><b>read-only</b>. Only read transactions are allowed in this <i>address block</i>.</li>
        <li><b>write-only</b>. Only write transactions are allowed in this <i>address block</i>.</li>
        <li><b>read-writeOnce</b>. Read actions and the first write action may have an effect
            on this <i>address block</i>.</li>
        <li><b>writeOnce</b>. Only the first write action affects the contents of this <i>address
            block</i>.</li>
    </ul>
    <p>
        <b>Volatile</b> is optional and indicates whether the stored value may change without
        the master's write operation or not.
    </p>

    <h3>Registers table</h3>
    <p>
        The register table enables the user to define <i>registers</i> for the <i>address block</i>,
        with each row representing a single register. Each register must also contain at
        least one bit <i>field</i>.
    </p>

    <p>
        <b>Name</b> is a mandatory identifier for the <i>register</i>.</p>
    <p>
        <b>Offset</b> is mandatory and specifies the location of the <i>register</i> from
        the start of the containing <i>address block</i> expressed as number of addressing
        units. The actual address of the <i>register</i> is the sum of <i>address block</i>'s
        base address and the <i>register</i> offset. E.g. if the base address is 'h100 and
        the register offset is 'h4, the register's address is 'h104. Offset can be given
        as a SystemVerilog expression.
    </p>
    <p>
        <b>Size</b> is mandatory and defines the number of data bits the <i>register</i>
        contains. Size must be less than or equal to the width of the containing <i>address
            block</i>.
    </p>
    <p>
        <b>Dimension</b> is optional and assigns an array dimension to the <i>register</i>.
        The <i>register</i> will be repeated in the <i>address block</i> as many times as
        indicated by the dimension value. By default, the dimension is presumed to be 0.
        Dimension 0 means that the <i>register</i> is not an array and will appear exactly
        once.
    </p>
    <p>
        <b>Volatile</b> is optional and indicates whether the <i>register</i> value may
        change without a write operation to it, i.e. by an interrupt event, or not.
    </p>
    <p>
        <b>Access</b> is optional and specifies the accessibility of the <i>register</i>.
        The possible values are:
    </p>
    <ul>
        <li><b>read-write</b>. Both read and write transactions may have an effect on this <i>
            register</i>.</li>
        <li><b>read-only</b>. Only read transactions are allowed in this <i>register</i>.</li>
        <li><b>write-only</b>. Only write transactions are allowed in this <i>register</i>.</li>
        <li><b>read-writeOnce</b>. Both read and write transactions may have an effect on this
            <i>register</i>. Only the first write transaction, after an event that caused the
            reset value of the <i>register</i> to be loaded, may affet the contents of the <i>register</i>,
            and read transactions return a value related to the values in the <i>register</i>.</li>
        <li><b>writeOnce</b>. Only the first write transaction affects the contents of the <i>
            register</i>.</li>
    </ul>
    <p>
        <b>Is present</b> is optional and allows enabling/disabling of a <i>register</i>
        presence in an <i>address block</i>. Value 1 indicates that the <i>register</i>
        is present in the <i>address block</i> whereas value 0 marks the register to be
        treated as if it does not exist. Is present can be given as a SystemVerilog expression,
        but it must evaluate to 1 or 0.</p>
    <p>
        <b>Description</b> is an optional field for textual description of the <i>register</i>.
    </p>

	<h3>Register files table</h3>
    <p>
        The register files table enables the user to define <i>register files</i> for the
		<i>address block</i> where each row represents a single register file.
		Register files are used to group together <i>registers</i>.
    </p>

    <p>
        <b>Name</b> is a mandatory identifier for the <i>register file</i>.</p>
    <p>
        <b>Offset</b> is mandatory and specifies the location of the <i>register file</i> from
        the start of the containing <i>address block</i> expressed as number of addressing
        units. Offset can be given as a SystemVerilog expression.
    </p>
    <p>
	   <b>Range</b> is mandatory and specifies the size of the <i>register file</i> in address
	   unit bits.
    </p>
    <p>
        <b>Dimension</b> is optional and assigns an array dimension to the <i>register file</i>.
        The <i>register file</i> will be repeated in the <i>address block</i> as many times as
        indicated by the dimension value. By default, the dimension is presumed to be 0.
        Dimension 0 means that the <i>register file</i> is not an array and will appear exactly
        once.
    </p>

	<p>
        <b>Is present</b> is optional and allows enabling/disabling of a <i>register file</i>
        presence in an <i>address block</i>. Value 1 indicates that the <i>register file</i>
        is present in the <i>address block</i> whereas value 0 marks the register to be
        treated as if it does not exist. Is present can be given as a SystemVerilog expression,
        but it must evaluate to 1 or 0.</p>
    <p>
        <b>Description</b> is an optional field for textual description of the <i>register file</i>.
    </p>
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