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    <title>CPUs editor</title>
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    <h2>CPUs editor</h2>
    <p>
      The cpus editor lists the programmable cores the component
      contains. This way the tools can recognize them and distinguish
      from hardwired components. One component can have multiple cores.
    </p>
	<p>
	    <b>Name</b> is a mandatory identifier for the <i>cpu</i>.
    </p>
    <p>
        <b>Display name</b> is an optional and used for a more user-friendly identifier.
    </p>
    <p>
      <b>Short description</b> is an optional field for compact description of the <i>cpu</i>.
    </p>
    <p>
      <b>Memory map reference</b> is mandatory and maps the address space defined 
      by range and width to a <i>memory map</i> in the <i>component</i>.
    </p>
    <p>
      <b>Range</b> </b> is mandatory and defines the address range in the memory
      map accessible by the <i>cpu</i>.
    </p>
    <p>
      <b>Width</b> is mandatory and defines the bit width of a row in the memory
      map for the <i>cpu</i>.
    </p>
    <p>
      <b>Address unit bits</b> (AUB) is an optinal field that defines the number 
      of data bits each address increment in the address space contains. 
      The default setting for a <i>cpu</i> address space is byte addressable (8 bits).
    </p>
	<p>
        <b>Description</b> is an optional field for textual description of the <i>cpu</i>.		
    </p>
    <p>
      Cpus editor provides a context menu (right mouse button) with
      the following options:
    </p>
    <ul>
      <li>Add new cpu (Add row)</li>
      <li>Remove cpu (Remove row)</li>
      <li>Clear the selected cells</li>
      <li>Copy the contents of the selected cells to clipboard</li>
      <li>Paste the contents of the clipboard to the selected cells</li>
      <li>Import a csv-file to the editor</li>
      <li>Export the contents of the editor to a csv-file</li>
    </ul>
    <hr>
    <p>
      EXAMPLE.
      Example SoC has two CPUs and both refer to a memory map. 
      The first memory map is bound to an initiator bus interface using
      a subspace map whereas the second has only a memory map with registers. 
      Consequently, cpuA has access to the global address space of the 
      initiator bus interface and cpuB does not.<br>
      <img src="../images/cpus22.png" alt="example">
    </p>
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