;
; Z80 EIPC (Z84C15) REGISTERS
;
EIPC_SCRP	.EQU	$EE		; SYSTEM CONTROL REGISTER POINTER
EIPC_SCDP	.EQU	$EF		; SYSTEM CONTROL DATA PORT
EIPC_WDTMR	.EQU	$F0		; WATCHDOG TIMER MASTER REGISTER
EIPC_WDTCR	.EQU	$F1		; WATCHDOG TIMER COMMAND REGISTER
EIPC_INTPR	.EQU	$F4		; INTERRUPT PRIORITY REGISTER
;
; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP)
;
EIPC_WCR	.EQU	$00		; WAIT STATE CONTROL REGISTER
EIPC_MWBR	.EQU	$01		; MEMORY WAIT BOUNDARY REGISTER
EIPC_CSBR	.EQU	$02		; CHIP SELECT BOUNDARY REGISTER
EIPC_MCR	.EQU	$03		; MISCELLANEOUS CONTROL REGISTER
;
; WAIT STATE VALUES (FOR EIPC_WCR)
;
EIPC_IO_0WS	.EQU	$00		; NO (ZERO) I/O WAIT STATES
EIPC_IO_2WS	.EQU	$01		; 2 I/O WAIT STATES
EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
EIPC_MEM_2WS	.EQU	$08		; 2 MEMORY WAIT STATES
EIPC_MEM_3WS	.EQU	$0C		; 3 MEMORY WAIT STATES
EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ
EIPC_INT_1WS	.EQU	$20		; 1 WAIT STATE ON INT. VECTOR READ
EIPC_CHAIN_0WS	.EQU	$00		; 0 WAIT ON INT ACK. / 0 WAIT ON RETI
EIPC_CHAIN_2WS	.EQU	$40		; 2 WAIT ON INT ACK. / 0 WAIT ON RETI
EIPC_CHAIN_4WS	.EQU	$80		; 4 WAIT ON INT ACK. / 2 WAIT ON RETI
EIPC_CHAIN_6WS	.EQU	$C0		; 6 WAIT ON INT ACK. / 4 WAIT ON RETI
;
; MISCELLANEOUS CONTROL REGISTER VALUES
;
EIPC_CS0_DIS	.EQU	$00		; DISABLE /CS0
EIPC_CS0_ENA	.EQU	$01		; ENABLE /CS0
EIPC_CS1_DIS	.EQU	$00		; DISABLE /CS1
EIPC_CS1_ENA	.EQU	$02		; ENABLE /CS1
EIPC_32CRC_DIS	.EQU	$00		; DISABLE 32-BIT CRC FOR SIO CHANNEL A
EIPC_32CRC_ENA	.EQU	$04		; ENABLE 32-BIT CRC FOR SIO CHANNEL A
EIPC_RSTOUT_DIS	.EQU	$08		; DISABLE RESET OUTPUT
EIPC_RSTOUT_ENA	.EQU	$00		; ENABLE RESET OUTPUT
EIPC_CLKDIV1	.EQU	$10		; DIVIDE XTAL/CGC CLOCK BY ONE
EIPC_CLKDIV2	.EQU	$00		; DIVIDE XTAL/CGC CLOCK BY TWO
;
; WATCHDOG TIMER MASTER REGISTER VALUES
;
EIPC_WDT_CONST	.EQU	$03		; MUST SET LOWER THREE BITS TO 011
EIPC_HALT_IDLE1 .EQU	$00		; HALT / POWER DOWN MODE - IDLE 1 MODE
EIPC_HALT_IDLE2 .EQU	$08		; HALT / POWER DOWN MODE - IDLE 2 MODE
EIPC_HALT_STOP	.EQU	$10		; HALT / POWER DOWN MODE - STOP MODE
EIPC_HALT_RUN	.EQU	$18		; HALT / POWER DOWN MODE - RUN MODE
EIPC_WDT_P2_16	.EQU	$00		; SET WATCHDOG PERIOD TO TOC * 2^16
EIPC_WDT_P2_18	.EQU	$20		; SET WATCHDOG PERIOD TO TOC * 2^18
EIPC_WDT_P2_20	.EQU	$40		; SET WATCHDOG PERIOD TO TOC * 2^20
EIPC_WDT_P2_22	.EQU	$60		; SET WATCHDOG PERIOD TO TOC * 2^22
EIPC_WDTE	.EQU	$80		; ENABLE WATCHDOG TIMER
;
; WATCHDOG TIMER COMMAND REGISTER VALUES
; 
EIPC_DIS_WDT	.EQU	$B1		; DISABLE WATCHDOG TIMER
EIPC_CLR_WDT	.EQU	$4E		; CLEAR WATCHDOG TIMER
EIPC_HLT_MODE	.EQU	$DB		; CHANGE HALT MODE
;
; INTERRUPT PRIORITY REGISTER VALUES
;
EIPC_CTC_SIO_PIO	.EQU	$00	; PRIORITY HIGH TO LOW: CTC, SIO, PIO
EIPC_SIO_CTC_PIO	.EQU	$01	; PRIORITY HIGH TO LOW: SIO, CTC, PIO
EIPC_CTC_PIO_SIO	.EQU	$02	; PRIORITY HIGH TO LOW: CTC, PIO, SIO
EIPC_PIO_SIO_CTC	.EQU	$03	; PRIORITY HIGH TO LOW: PIO, SIO, CTC
EIPC_PIC_CTC_SIO	.EQU	$04	; PRIORITY HIGH TO LOW: PIO, CTC, SIO
EIPC_SIO_PIO_CTC	.EQU	$05	; PRIORITY HIGH TO LOW: SIO, PIO, CTC
