<stg><name>CAT_I_I_I_O.1</name>


<trans_list>

<trans id="117" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="118" from="2" to="2">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="119" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="120" from="3" to="4">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="124" from="3" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="122" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="123" from="5" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="145" from="6" to="10">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="146" from="6" to="7">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="142" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="143" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="144" from="9" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="131" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="132" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="133" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="134" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="151" from="14" to="18">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="152" from="14" to="15">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="148" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="149" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="150" from="17" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %x1_tmp_bits_read_2 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %x1_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="x1_tmp_bits_read_2"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %1

]]></Node>
<StgValue><ssdm name="br_ln168"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="21" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:0  %j_0 = phi i7 [ 32, %0 ], [ %j, %2 ]

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="22" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
:1  %icmp_ln168 = icmp eq i7 %j_0, -64

]]></Node>
<StgValue><ssdm name="icmp_ln168"/></StgValue>
</operation>

<operation id="23" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:3  br i1 %icmp_ln168, label %.preheader365.preheader, label %2

]]></Node>
<StgValue><ssdm name="br_ln168"/></StgValue>
</operation>

<operation id="25" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="14" bw="64" op_0_bw="7">
<![CDATA[
:0  %zext_ln168 = zext i7 %j_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln168"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="15" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %w_digits_data_V_addr = getelementptr [64 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln168

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="16" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
:2  store i64 0, i64* %w_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="store_ln168"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="17" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
:3  %j = add i7 %j_0, 1

]]></Node>
<StgValue><ssdm name="j"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="0">
<![CDATA[
:4  br label %1

]]></Node>
<StgValue><ssdm name="br_ln168"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="20" bw="0" op_0_bw="0">
<![CDATA[
.preheader365.preheader:0  br label %.preheader365

]]></Node>
<StgValue><ssdm name="br_ln170"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="31" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader365:0  %i_0 = phi i6 [ %i, %3 ], [ 0, %.preheader365.preheader ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="32" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader365:1  %icmp_ln170 = icmp eq i6 %i_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln170"/></StgValue>
</operation>

<operation id="33" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader365:2  %empty_102 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_102"/></StgValue>
</operation>

<operation id="34" st_id="3" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader365:3  %i = add i6 %i_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="35" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader365:4  br i1 %icmp_ln170, label %.preheader.preheader, label %3

]]></Node>
<StgValue><ssdm name="br_ln170"/></StgValue>
</operation>

<operation id="36" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="28" bw="64" op_0_bw="6">
<![CDATA[
:0  %zext_ln170 = zext i6 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln170"/></StgValue>
</operation>

<operation id="37" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %x0_digits_data_V_add = getelementptr [32 x i64]* %x0_digits_data_V, i64 0, i64 %zext_ln170

]]></Node>
<StgValue><ssdm name="x0_digits_data_V_add"/></StgValue>
</operation>

<operation id="38" st_id="3" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="64" op_0_bw="5">
<![CDATA[
:2  %x0_digits_data_V_loa = load i64* %x0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="39" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln170" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="35" bw="0" op_0_bw="0">
<![CDATA[
.preheader.preheader:0  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln175"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="40" st_id="4" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="64" op_0_bw="5">
<![CDATA[
:2  %x0_digits_data_V_loa = load i64* %x0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x0_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="41" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %w_digits_data_V_addr_9 = getelementptr [64 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln170

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_9"/></StgValue>
</operation>

<operation id="42" st_id="5" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
:4  store i64 %x0_digits_data_V_loa, i64* %w_digits_data_V_addr_9, align 8

]]></Node>
<StgValue><ssdm name="store_ln170"/></StgValue>
</operation>

<operation id="43" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="0" op_0_bw="0">
<![CDATA[
:5  br label %.preheader365

]]></Node>
<StgValue><ssdm name="br_ln170"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="44" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader:0  %p_0136_0 = phi i2 [ %trunc_ln, %hls_label_42 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="p_0136_0"/></StgValue>
</operation>

<operation id="45" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader:1  %j1_0 = phi i6 [ %j_8, %hls_label_42 ], [ 16, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="j1_0"/></StgValue>
</operation>

<operation id="46" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader:2  %i2_0 = phi i6 [ %i_35, %hls_label_42 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="47" st_id="6" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:3  %icmp_ln175 = icmp eq i6 %i2_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln175"/></StgValue>
</operation>

<operation id="48" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:4  %empty_103 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_103"/></StgValue>
</operation>

<operation id="49" st_id="6" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:5  %i_35 = add i6 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i_35"/></StgValue>
</operation>

<operation id="50" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:6  br i1 %icmp_ln175, label %4, label %hls_label_42

]]></Node>
<StgValue><ssdm name="br_ln175"/></StgValue>
</operation>

<operation id="51" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="64" op_0_bw="6">
<![CDATA[
hls_label_42:3  %zext_ln180 = zext i6 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln180"/></StgValue>
</operation>

<operation id="52" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_42:4  %x1_digits_data_V_add = getelementptr [32 x i64]* %x1_digits_data_V, i64 0, i64 %zext_ln180

]]></Node>
<StgValue><ssdm name="x1_digits_data_V_add"/></StgValue>
</operation>

<operation id="53" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="64" op_0_bw="5">
<![CDATA[
hls_label_42:5  %x1_digits_data_V_loa = load i64* %x1_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x1_digits_data_V_loa"/></StgValue>
</operation>

<operation id="54" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="64" op_0_bw="6">
<![CDATA[
hls_label_42:7  %zext_ln181 = zext i6 %j1_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln181"/></StgValue>
</operation>

<operation id="55" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_42:8  %w_digits_data_V_addr_11 = getelementptr [64 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln181

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_11"/></StgValue>
</operation>

<operation id="56" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="64" op_0_bw="6">
<![CDATA[
hls_label_42:9  %w_digits_data_V_load_6 = load i64* %w_digits_data_V_addr_11, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_6"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="57" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="64" op_0_bw="5">
<![CDATA[
hls_label_42:5  %x1_digits_data_V_loa = load i64* %x1_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x1_digits_data_V_loa"/></StgValue>
</operation>

<operation id="58" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="64" op_0_bw="6">
<![CDATA[
hls_label_42:9  %w_digits_data_V_load_6 = load i64* %w_digits_data_V_addr_11, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_6"/></StgValue>
</operation>

<operation id="59" st_id="7" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
hls_label_42:19  %j_8 = add i6 %j1_0, 1

]]></Node>
<StgValue><ssdm name="j_8"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="60" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="65" op_0_bw="2">
<![CDATA[
hls_label_42:0  %zext_ln175 = zext i2 %p_0136_0 to i65

]]></Node>
<StgValue><ssdm name="zext_ln175"/></StgValue>
</operation>

<operation id="61" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="65" op_0_bw="64">
<![CDATA[
hls_label_42:6  %zext_ln700 = zext i64 %x1_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln700"/></StgValue>
</operation>

<operation id="62" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="64" op_0_bw="2">
<![CDATA[
hls_label_42:11  %zext_ln700_44 = zext i2 %p_0136_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_44"/></StgValue>
</operation>

<operation id="63" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_42:12  %tmp_V_35 = add i65 %zext_ln700, %zext_ln175

]]></Node>
<StgValue><ssdm name="tmp_V_35"/></StgValue>
</operation>

<operation id="64" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_42:15  %add_ln209_19 = add i64 %w_digits_data_V_load_6, %zext_ln700_44

]]></Node>
<StgValue><ssdm name="add_ln209_19"/></StgValue>
</operation>

<operation id="65" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_42:16  %add_ln209_9 = add i64 %add_ln209_19, %x1_digits_data_V_loa

]]></Node>
<StgValue><ssdm name="add_ln209_9"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="66" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_42:1  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str29)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="67" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_42:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln177"/></StgValue>
</operation>

<operation id="68" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="66" op_0_bw="64">
<![CDATA[
hls_label_42:10  %zext_ln700_43 = zext i64 %w_digits_data_V_load_6 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_43"/></StgValue>
</operation>

<operation id="69" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="66" op_0_bw="65">
<![CDATA[
hls_label_42:13  %zext_ln700_45 = zext i65 %tmp_V_35 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_45"/></StgValue>
</operation>

<operation id="70" st_id="9" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_42:14  %tmp_V = add i66 %zext_ln700_45, %zext_ln700_43

]]></Node>
<StgValue><ssdm name="tmp_V"/></StgValue>
</operation>

<operation id="71" st_id="9" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="0" op_0_bw="64" op_1_bw="6" op_2_bw="64">
<![CDATA[
hls_label_42:17  store i64 %add_ln209_9, i64* %w_digits_data_V_addr_11, align 8

]]></Node>
<StgValue><ssdm name="store_ln182"/></StgValue>
</operation>

<operation id="72" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_42:18  %trunc_ln = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln"/></StgValue>
</operation>

<operation id="73" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_42:20  %empty_104 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str29, i32 %tmp)

]]></Node>
<StgValue><ssdm name="empty_104"/></StgValue>
</operation>

<operation id="74" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln175" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="0" op_0_bw="0">
<![CDATA[
hls_label_42:21  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln175"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="75" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:0  %w_digits_data_V_addr_10 = getelementptr [64 x i64]* %w_digits_data_V, i64 0, i64 48

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_10"/></StgValue>
</operation>

<operation id="76" st_id="10" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="69" bw="64" op_0_bw="6">
<![CDATA[
:1  %w_digits_data_V_load = load i64* %w_digits_data_V_addr_10, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="77" st_id="11" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="69" bw="64" op_0_bw="6">
<![CDATA[
:1  %w_digits_data_V_load = load i64* %w_digits_data_V_addr_10, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load"/></StgValue>
</operation>

<operation id="78" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="33" op_0_bw="2">
<![CDATA[
:2  %zext_ln1468 = zext i2 %p_0136_0 to i33

]]></Node>
<StgValue><ssdm name="zext_ln1468"/></StgValue>
</operation>

<operation id="79" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="71" bw="33" op_0_bw="32">
<![CDATA[
:3  %zext_ln209 = zext i32 %x1_tmp_bits_read_2 to i33

]]></Node>
<StgValue><ssdm name="zext_ln209"/></StgValue>
</operation>

<operation id="80" st_id="11" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
:4  %add_ln209 = add i33 %zext_ln209, %zext_ln1468

]]></Node>
<StgValue><ssdm name="add_ln209"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="81" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="73" bw="64" op_0_bw="33">
<![CDATA[
:5  %zext_ln209_3 = zext i33 %add_ln209 to i64

]]></Node>
<StgValue><ssdm name="zext_ln209_3"/></StgValue>
</operation>

<operation id="82" st_id="12" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
:6  %add_ln209_2 = add i64 %zext_ln209_3, %w_digits_data_V_load

]]></Node>
<StgValue><ssdm name="add_ln209_2"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="83" st_id="13" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="75" bw="0" op_0_bw="64" op_1_bw="6" op_2_bw="64">
<![CDATA[
:7  store i64 %add_ln209_2, i64* %w_digits_data_V_addr_10, align 8

]]></Node>
<StgValue><ssdm name="store_ln186"/></StgValue>
</operation>

<operation id="84" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="0" op_0_bw="0">
<![CDATA[
:8  br label %5

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="85" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
:0  %p_0136_2 = phi i2 [ 0, %4 ], [ %trunc_ln858_s, %hls_label_43 ]

]]></Node>
<StgValue><ssdm name="p_0136_2"/></StgValue>
</operation>

<operation id="86" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:1  %j1_1 = phi i7 [ 32, %4 ], [ %j_9, %hls_label_43 ]

]]></Node>
<StgValue><ssdm name="j1_1"/></StgValue>
</operation>

<operation id="87" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:2  %i3_0 = phi i6 [ 0, %4 ], [ %i_36, %hls_label_43 ]

]]></Node>
<StgValue><ssdm name="i3_0"/></StgValue>
</operation>

<operation id="88" st_id="14" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="81" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %icmp_ln191 = icmp eq i6 %i3_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln191"/></StgValue>
</operation>

<operation id="89" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4  %empty_105 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_105"/></StgValue>
</operation>

<operation id="90" st_id="14" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="83" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:5  %i_36 = add i6 %i3_0, 1

]]></Node>
<StgValue><ssdm name="i_36"/></StgValue>
</operation>

<operation id="91" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="84" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6  br i1 %icmp_ln191, label %6, label %hls_label_43

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>

<operation id="92" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="64" op_0_bw="6">
<![CDATA[
hls_label_43:3  %zext_ln196 = zext i6 %i3_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln196"/></StgValue>
</operation>

<operation id="93" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_43:4  %x2_digits_data_V_add = getelementptr [32 x i64]* %x2_digits_data_V, i64 0, i64 %zext_ln196

]]></Node>
<StgValue><ssdm name="x2_digits_data_V_add"/></StgValue>
</operation>

<operation id="94" st_id="14" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="64" op_0_bw="5">
<![CDATA[
hls_label_43:5  %x2_digits_data_V_loa = load i64* %x2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x2_digits_data_V_loa"/></StgValue>
</operation>

<operation id="95" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="64" op_0_bw="7">
<![CDATA[
hls_label_43:7  %zext_ln197 = zext i7 %j1_1 to i64

]]></Node>
<StgValue><ssdm name="zext_ln197"/></StgValue>
</operation>

<operation id="96" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_43:8  %w_digits_data_V_addr_12 = getelementptr [64 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln197

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_12"/></StgValue>
</operation>

<operation id="97" st_id="14" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="64" op_0_bw="6">
<![CDATA[
hls_label_43:9  %w_digits_data_V_load_7 = load i64* %w_digits_data_V_addr_12, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_7"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="98" st_id="15" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="64" op_0_bw="5">
<![CDATA[
hls_label_43:5  %x2_digits_data_V_loa = load i64* %x2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="x2_digits_data_V_loa"/></StgValue>
</operation>

<operation id="99" st_id="15" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="64" op_0_bw="6">
<![CDATA[
hls_label_43:9  %w_digits_data_V_load_7 = load i64* %w_digits_data_V_addr_12, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_7"/></StgValue>
</operation>

<operation id="100" st_id="15" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
hls_label_43:19  %j_9 = add i7 %j1_1, 1

]]></Node>
<StgValue><ssdm name="j_9"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="101" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="65" op_0_bw="2">
<![CDATA[
hls_label_43:0  %zext_ln191 = zext i2 %p_0136_2 to i65

]]></Node>
<StgValue><ssdm name="zext_ln191"/></StgValue>
</operation>

<operation id="102" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="65" op_0_bw="64">
<![CDATA[
hls_label_43:6  %zext_ln700_46 = zext i64 %x2_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln700_46"/></StgValue>
</operation>

<operation id="103" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="64" op_0_bw="2">
<![CDATA[
hls_label_43:11  %zext_ln700_48 = zext i2 %p_0136_2 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_48"/></StgValue>
</operation>

<operation id="104" st_id="16" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_43:12  %tmp_V_36 = add i65 %zext_ln700_46, %zext_ln191

]]></Node>
<StgValue><ssdm name="tmp_V_36"/></StgValue>
</operation>

<operation id="105" st_id="16" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_43:15  %add_ln209_20 = add i64 %w_digits_data_V_load_7, %zext_ln700_48

]]></Node>
<StgValue><ssdm name="add_ln209_20"/></StgValue>
</operation>

<operation id="106" st_id="16" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_43:16  %add_ln209_10 = add i64 %add_ln209_20, %x2_digits_data_V_loa

]]></Node>
<StgValue><ssdm name="add_ln209_10"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="107" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_43:1  %tmp_s = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str30)

]]></Node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="108" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_43:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln193"/></StgValue>
</operation>

<operation id="109" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="66" op_0_bw="64">
<![CDATA[
hls_label_43:10  %zext_ln700_47 = zext i64 %w_digits_data_V_load_7 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_47"/></StgValue>
</operation>

<operation id="110" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="66" op_0_bw="65">
<![CDATA[
hls_label_43:13  %zext_ln700_49 = zext i65 %tmp_V_36 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_49"/></StgValue>
</operation>

<operation id="111" st_id="17" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_43:14  %tmp_V_34 = add i66 %zext_ln700_49, %zext_ln700_47

]]></Node>
<StgValue><ssdm name="tmp_V_34"/></StgValue>
</operation>

<operation id="112" st_id="17" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="0" op_0_bw="64" op_1_bw="6" op_2_bw="64">
<![CDATA[
hls_label_43:17  store i64 %add_ln209_10, i64* %w_digits_data_V_addr_12, align 8

]]></Node>
<StgValue><ssdm name="store_ln198"/></StgValue>
</operation>

<operation id="113" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_43:18  %trunc_ln858_s = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V_34, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln858_s"/></StgValue>
</operation>

<operation id="114" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_43:20  %empty_106 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str30, i32 %tmp_s)

]]></Node>
<StgValue><ssdm name="empty_106"/></StgValue>
</operation>

<operation id="115" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="0" op_0_bw="0">
<![CDATA[
hls_label_43:21  br label %5

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="116" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="109" bw="0">
<![CDATA[
:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
