<stg><name>mul_I_O</name>


<trans_list>

<trans id="181" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="182" from="2" to="2">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="183" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="184" from="3" to="4">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="204" from="3" to="24">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="1"/>
<literal name="icmp_ln129" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="205" from="3" to="19">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="1"/>
<literal name="icmp_ln129" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="233" from="4" to="15">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="234" from="4" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="223" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="224" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="225" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="227" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="228" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="229" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="230" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="231" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="14" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="198" from="15" to="16">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="199" from="15" to="18">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="201" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="202" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="203" from="18" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="239" from="19" to="23">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="240" from="19" to="20">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="236" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="237" from="21" to="22">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="238" from="22" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="212" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="213" from="24" to="30">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln143" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="214" from="24" to="25">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln143" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="245" from="25" to="29">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="246" from="25" to="26">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="242" from="26" to="27">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="243" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="244" from="28" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="221" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="31" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
:0  %v_tmp_bits_read_1 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %v_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="v_tmp_bits_read_1"/></StgValue>
</operation>

<operation id="32" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
:1  %u_tmp_bits_read_1 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %u_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="u_tmp_bits_read_1"/></StgValue>
</operation>

<operation id="33" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %1

]]></Node>
<StgValue><ssdm name="br_ln105"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="34" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
:0  %j_0 = phi i5 [ 0, %0 ], [ %j, %2 ]

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="35" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
:1  %icmp_ln105 = icmp eq i5 %j_0, -16

]]></Node>
<StgValue><ssdm name="icmp_ln105"/></StgValue>
</operation>

<operation id="36" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="37" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:3  %j = add i5 %j_0, 1

]]></Node>
<StgValue><ssdm name="j"/></StgValue>
</operation>

<operation id="38" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln105, label %.preheader567.preheader, label %2

]]></Node>
<StgValue><ssdm name="br_ln105"/></StgValue>
</operation>

<operation id="39" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="16" bw="64" op_0_bw="5">
<![CDATA[
:0  %zext_ln105 = zext i5 %j_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln105"/></StgValue>
</operation>

<operation id="40" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="17" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %w_digits_data_V_addr = getelementptr [16 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln105

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr"/></StgValue>
</operation>

<operation id="41" st_id="2" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:2  store i64 0, i64* %w_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="store_ln105"/></StgValue>
</operation>

<operation id="42" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="19" bw="0" op_0_bw="0">
<![CDATA[
:3  br label %1

]]></Node>
<StgValue><ssdm name="br_ln105"/></StgValue>
</operation>

<operation id="43" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln105" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="0">
<![CDATA[
.preheader567.preheader:0  br label %.preheader567

]]></Node>
<StgValue><ssdm name="br_ln108"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="44" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
.preheader567:0  %j1_0 = phi i4 [ %j_2, %._crit_edge568 ], [ 0, %.preheader567.preheader ]

]]></Node>
<StgValue><ssdm name="j1_0"/></StgValue>
</operation>

<operation id="45" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader567:1  %icmp_ln108 = icmp eq i4 %j1_0, -8

]]></Node>
<StgValue><ssdm name="icmp_ln108"/></StgValue>
</operation>

<operation id="46" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader567:2  %empty_9 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8)

]]></Node>
<StgValue><ssdm name="empty_9"/></StgValue>
</operation>

<operation id="47" st_id="3" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader567:3  %j_2 = add i4 %j1_0, 1

]]></Node>
<StgValue><ssdm name="j_2"/></StgValue>
</operation>

<operation id="48" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader567:4  br i1 %icmp_ln108, label %4, label %.preheader566.preheader

]]></Node>
<StgValue><ssdm name="br_ln108"/></StgValue>
</operation>

<operation id="49" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="64" op_0_bw="4">
<![CDATA[
.preheader566.preheader:0  %zext_ln116 = zext i4 %j1_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln116"/></StgValue>
</operation>

<operation id="50" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="3" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
.preheader566.preheader:1  %v_digits_data_V_addr = getelementptr [8 x i64]* %v_digits_data_V, i64 0, i64 %zext_ln116

]]></Node>
<StgValue><ssdm name="v_digits_data_V_addr"/></StgValue>
</operation>

<operation id="51" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="0">
<![CDATA[
.preheader566.preheader:2  br label %.preheader566

]]></Node>
<StgValue><ssdm name="br_ln111"/></StgValue>
</operation>

<operation id="52" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="1" op_0_bw="2" op_1_bw="2">
<![CDATA[
:0  %icmp_ln129 = icmp eq i2 %v_tmp_bits_read_1, 0

]]></Node>
<StgValue><ssdm name="icmp_ln129"/></StgValue>
</operation>

<operation id="53" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:1  br i1 %icmp_ln129, label %._crit_edge569, label %.preheader565.preheader

]]></Node>
<StgValue><ssdm name="br_ln129"/></StgValue>
</operation>

<operation id="54" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln108" val="1"/>
<literal name="icmp_ln129" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="0" op_0_bw="0">
<![CDATA[
.preheader565.preheader:0  br label %.preheader565

]]></Node>
<StgValue><ssdm name="br_ln133"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="55" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
.preheader566:0  %p_0176_1 = phi i64 [ %trunc_ln1, %hls_label_26 ], [ 0, %.preheader566.preheader ]

]]></Node>
<StgValue><ssdm name="p_0176_1"/></StgValue>
</operation>

<operation id="56" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
.preheader566:1  %i_0 = phi i4 [ %add_ln111, %hls_label_26 ], [ 0, %.preheader566.preheader ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="57" st_id="4" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader566:2  %icmp_ln111 = icmp eq i4 %i_0, -8

]]></Node>
<StgValue><ssdm name="icmp_ln111"/></StgValue>
</operation>

<operation id="58" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader566:3  %empty_10 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8)

]]></Node>
<StgValue><ssdm name="empty_10"/></StgValue>
</operation>

<operation id="59" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader566:4  %add_ln111 = add i4 %i_0, 1

]]></Node>
<StgValue><ssdm name="add_ln111"/></StgValue>
</operation>

<operation id="60" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader566:5  br i1 %icmp_ln111, label %3, label %hls_label_26

]]></Node>
<StgValue><ssdm name="br_ln111"/></StgValue>
</operation>

<operation id="61" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
hls_label_26:3  %add_ln114 = add i4 %i_0, %j1_0

]]></Node>
<StgValue><ssdm name="add_ln114"/></StgValue>
</operation>

<operation id="62" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="64" op_0_bw="4">
<![CDATA[
hls_label_26:4  %zext_ln116_1 = zext i4 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln116_1"/></StgValue>
</operation>

<operation id="63" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="3" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_26:5  %u_digits_data_V_addr = getelementptr [8 x i64]* %u_digits_data_V, i64 0, i64 %zext_ln116_1

]]></Node>
<StgValue><ssdm name="u_digits_data_V_addr"/></StgValue>
</operation>

<operation id="64" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="64" op_0_bw="3">
<![CDATA[
hls_label_26:6  %u_digits_data_V_load = load i64* %u_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="u_digits_data_V_load"/></StgValue>
</operation>

<operation id="65" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="64" op_0_bw="3">
<![CDATA[
hls_label_26:8  %v_digits_data_V_load = load i64* %v_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="v_digits_data_V_load"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="66" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="64" op_0_bw="3">
<![CDATA[
hls_label_26:6  %u_digits_data_V_load = load i64* %u_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="u_digits_data_V_load"/></StgValue>
</operation>

<operation id="67" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="64" op_0_bw="3">
<![CDATA[
hls_label_26:8  %v_digits_data_V_load = load i64* %v_digits_data_V_addr, align 8

]]></Node>
<StgValue><ssdm name="v_digits_data_V_load"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="68" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="128" op_0_bw="64">
<![CDATA[
hls_label_26:7  %zext_ln700 = zext i64 %u_digits_data_V_load to i128

]]></Node>
<StgValue><ssdm name="zext_ln700"/></StgValue>
</operation>

<operation id="69" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="128" op_0_bw="64">
<![CDATA[
hls_label_26:9  %zext_ln700_1 = zext i64 %v_digits_data_V_load to i128

]]></Node>
<StgValue><ssdm name="zext_ln700_1"/></StgValue>
</operation>

<operation id="70" st_id="6" stage="6" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="71" st_id="7" stage="5" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="72" st_id="8" stage="4" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="73" st_id="9" stage="3" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="74" st_id="10" stage="2" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="75" st_id="11" stage="1" lat="6">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:10  %mul_ln700 = mul i128 %zext_ln700, %zext_ln700_1

]]></Node>
<StgValue><ssdm name="mul_ln700"/></StgValue>
</operation>

<operation id="76" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="64" op_0_bw="4">
<![CDATA[
hls_label_26:11  %zext_ln116_2 = zext i4 %add_ln114 to i64

]]></Node>
<StgValue><ssdm name="zext_ln116_2"/></StgValue>
</operation>

<operation id="77" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_26:12  %w_digits_data_V_addr_1 = getelementptr [16 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln116_2

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_1"/></StgValue>
</operation>

<operation id="78" st_id="11" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="64" op_0_bw="4">
<![CDATA[
hls_label_26:13  %w_digits_data_V_load_1 = load i64* %w_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_1"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="79" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="128" op_0_bw="64">
<![CDATA[
hls_label_26:0  %zext_ln111 = zext i64 %p_0176_1 to i128

]]></Node>
<StgValue><ssdm name="zext_ln111"/></StgValue>
</operation>

<operation id="80" st_id="12" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="64" op_0_bw="4">
<![CDATA[
hls_label_26:13  %w_digits_data_V_load_1 = load i64* %w_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_1"/></StgValue>
</operation>

<operation id="81" st_id="12" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:15  %add_ln700 = add i128 %zext_ln111, %mul_ln700

]]></Node>
<StgValue><ssdm name="add_ln700"/></StgValue>
</operation>

<operation id="82" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="64" op_0_bw="128">
<![CDATA[
hls_label_26:16  %trunc_ln700 = trunc i128 %add_ln700 to i64

]]></Node>
<StgValue><ssdm name="trunc_ln700"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="83" st_id="13" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_26:18  %add_ln209_1 = add i64 %trunc_ln700, %w_digits_data_V_load_1

]]></Node>
<StgValue><ssdm name="add_ln209_1"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="84" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_26:1  %tmp_1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str54)

]]></Node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="85" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_26:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln113"/></StgValue>
</operation>

<operation id="86" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="128" op_0_bw="64">
<![CDATA[
hls_label_26:14  %zext_ln700_2 = zext i64 %w_digits_data_V_load_1 to i128

]]></Node>
<StgValue><ssdm name="zext_ln700_2"/></StgValue>
</operation>

<operation id="87" st_id="14" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="128" op_0_bw="128" op_1_bw="128">
<![CDATA[
hls_label_26:17  %k_V = add i128 %zext_ln700_2, %add_ln700

]]></Node>
<StgValue><ssdm name="k_V"/></StgValue>
</operation>

<operation id="88" st_id="14" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="64" op_1_bw="4" op_2_bw="64">
<![CDATA[
hls_label_26:19  store i64 %add_ln209_1, i64* %w_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="store_ln117"/></StgValue>
</operation>

<operation id="89" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="64" op_0_bw="64" op_1_bw="128" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_26:20  %trunc_ln1 = call i64 @_ssdm_op_PartSelect.i64.i128.i32.i32(i128 %k_V, i32 64, i32 127)

]]></Node>
<StgValue><ssdm name="trunc_ln1"/></StgValue>
</operation>

<operation id="90" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_26:21  %empty_11 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str54, i32 %tmp_1)

]]></Node>
<StgValue><ssdm name="empty_11"/></StgValue>
</operation>

<operation id="91" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln111" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="0" op_0_bw="0">
<![CDATA[
hls_label_26:22  br label %.preheader566

]]></Node>
<StgValue><ssdm name="br_ln111"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="92" st_id="15" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="64" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:0  %icmp_ln883 = icmp eq i64 %p_0176_1, 0

]]></Node>
<StgValue><ssdm name="icmp_ln883"/></StgValue>
</operation>

<operation id="93" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="65" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:1  br i1 %icmp_ln883, label %._crit_edge568, label %_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16

]]></Node>
<StgValue><ssdm name="br_ln121"/></StgValue>
</operation>

<operation id="94" st_id="15" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:0  %xor_ln123 = xor i4 %j1_0, -8

]]></Node>
<StgValue><ssdm name="xor_ln123"/></StgValue>
</operation>

<operation id="95" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="64" op_0_bw="4">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:1  %zext_ln123 = zext i4 %xor_ln123 to i64

]]></Node>
<StgValue><ssdm name="zext_ln123"/></StgValue>
</operation>

<operation id="96" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:2  %w_digits_data_V_addr_3 = getelementptr [16 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln123

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_3"/></StgValue>
</operation>

<operation id="97" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="64" op_0_bw="4">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:3  %w_digits_data_V_load = load i64* %w_digits_data_V_addr_3, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="98" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="64" op_0_bw="4">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:3  %w_digits_data_V_load = load i64* %w_digits_data_V_addr_3, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="99" st_id="17" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="71" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:4  %add_ln209_2 = add i64 %w_digits_data_V_load, %p_0176_1

]]></Node>
<StgValue><ssdm name="add_ln209_2"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="100" st_id="18" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="0" op_0_bw="64" op_1_bw="4" op_2_bw="64">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:5  store i64 %add_ln209_2, i64* %w_digits_data_V_addr_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln124"/></StgValue>
</operation>

<operation id="101" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln883" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="0" op_0_bw="0">
<![CDATA[
_ZrSILi128ELb0EER11ap_int_baseIXT_EXT0_EES2_i.exit16:6  br label %._crit_edge568

]]></Node>
<StgValue><ssdm name="br_ln126"/></StgValue>
</operation>

<operation id="102" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="75" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge568:0  br label %.preheader567

]]></Node>
<StgValue><ssdm name="br_ln108"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="103" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader565:0  %p_0288_0 = phi i2 [ %trunc_ln858_1, %hls_label_27 ], [ 0, %.preheader565.preheader ]

]]></Node>
<StgValue><ssdm name="p_0288_0"/></StgValue>
</operation>

<operation id="104" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="83" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
.preheader565:1  %i2_0 = phi i4 [ %i, %hls_label_27 ], [ 0, %.preheader565.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="105" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="84" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader565:2  %j3_0 = phi i5 [ %j_1, %hls_label_27 ], [ 8, %.preheader565.preheader ]

]]></Node>
<StgValue><ssdm name="j3_0"/></StgValue>
</operation>

<operation id="106" st_id="19" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="85" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader565:3  %icmp_ln133 = icmp eq i4 %i2_0, -8

]]></Node>
<StgValue><ssdm name="icmp_ln133"/></StgValue>
</operation>

<operation id="107" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="86" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader565:4  %empty_12 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8)

]]></Node>
<StgValue><ssdm name="empty_12"/></StgValue>
</operation>

<operation id="108" st_id="19" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="87" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader565:5  %i = add i4 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="109" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader565:6  br i1 %icmp_ln133, label %._crit_edge569.loopexit, label %hls_label_27

]]></Node>
<StgValue><ssdm name="br_ln133"/></StgValue>
</operation>

<operation id="110" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="64" op_0_bw="4">
<![CDATA[
hls_label_27:3  %zext_ln136 = zext i4 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln136"/></StgValue>
</operation>

<operation id="111" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="3" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_27:4  %u_digits_data_V_addr_1 = getelementptr [8 x i64]* %u_digits_data_V, i64 0, i64 %zext_ln136

]]></Node>
<StgValue><ssdm name="u_digits_data_V_addr_1"/></StgValue>
</operation>

<operation id="112" st_id="19" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="64" op_0_bw="3">
<![CDATA[
hls_label_27:5  %u_digits_data_V_load_1 = load i64* %u_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="u_digits_data_V_load_1"/></StgValue>
</operation>

<operation id="113" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="64" op_0_bw="5">
<![CDATA[
hls_label_27:7  %zext_ln137 = zext i5 %j3_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln137"/></StgValue>
</operation>

<operation id="114" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_27:8  %w_digits_data_V_addr_2 = getelementptr [16 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln137

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_2"/></StgValue>
</operation>

<operation id="115" st_id="19" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="64" op_0_bw="4">
<![CDATA[
hls_label_27:9  %w_digits_data_V_load_2 = load i64* %w_digits_data_V_addr_2, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_2"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="116" st_id="20" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="64" op_0_bw="3">
<![CDATA[
hls_label_27:5  %u_digits_data_V_load_1 = load i64* %u_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="u_digits_data_V_load_1"/></StgValue>
</operation>

<operation id="117" st_id="20" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="64" op_0_bw="4">
<![CDATA[
hls_label_27:9  %w_digits_data_V_load_2 = load i64* %w_digits_data_V_addr_2, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_2"/></StgValue>
</operation>

<operation id="118" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
hls_label_27:20  %j_1 = add i5 %j3_0, 1

]]></Node>
<StgValue><ssdm name="j_1"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="119" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="65" op_0_bw="2">
<![CDATA[
hls_label_27:0  %zext_ln133 = zext i2 %p_0288_0 to i65

]]></Node>
<StgValue><ssdm name="zext_ln133"/></StgValue>
</operation>

<operation id="120" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="65" op_0_bw="64">
<![CDATA[
hls_label_27:6  %zext_ln700_3 = zext i64 %u_digits_data_V_load_1 to i65

]]></Node>
<StgValue><ssdm name="zext_ln700_3"/></StgValue>
</operation>

<operation id="121" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="64" op_0_bw="2">
<![CDATA[
hls_label_27:11  %zext_ln700_5 = zext i2 %p_0288_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_5"/></StgValue>
</operation>

<operation id="122" st_id="21" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_27:12  %tmp_V_4 = add i65 %zext_ln700_3, %zext_ln133

]]></Node>
<StgValue><ssdm name="tmp_V_4"/></StgValue>
</operation>

<operation id="123" st_id="21" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_27:15  %add_ln209_4 = add i64 %w_digits_data_V_load_2, %zext_ln700_5

]]></Node>
<StgValue><ssdm name="add_ln209_4"/></StgValue>
</operation>

<operation id="124" st_id="21" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_27:16  %add_ln209 = add i64 %add_ln209_4, %u_digits_data_V_load_1

]]></Node>
<StgValue><ssdm name="add_ln209"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="125" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_27:1  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str56)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="126" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_27:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln135"/></StgValue>
</operation>

<operation id="127" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="66" op_0_bw="64">
<![CDATA[
hls_label_27:10  %zext_ln700_4 = zext i64 %w_digits_data_V_load_2 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_4"/></StgValue>
</operation>

<operation id="128" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="66" op_0_bw="65">
<![CDATA[
hls_label_27:13  %zext_ln700_6 = zext i65 %tmp_V_4 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_6"/></StgValue>
</operation>

<operation id="129" st_id="22" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_27:14  %tmp_V = add i66 %zext_ln700_6, %zext_ln700_4

]]></Node>
<StgValue><ssdm name="tmp_V"/></StgValue>
</operation>

<operation id="130" st_id="22" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="0" op_0_bw="64" op_1_bw="4" op_2_bw="64">
<![CDATA[
hls_label_27:17  store i64 %add_ln209, i64* %w_digits_data_V_addr_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln138"/></StgValue>
</operation>

<operation id="131" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_27:18  %trunc_ln858_1 = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln858_1"/></StgValue>
</operation>

<operation id="132" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_27:19  %empty_13 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str56, i32 %tmp)

]]></Node>
<StgValue><ssdm name="empty_13"/></StgValue>
</operation>

<operation id="133" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln133" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="0" op_0_bw="0">
<![CDATA[
hls_label_27:21  br label %.preheader565

]]></Node>
<StgValue><ssdm name="br_ln133"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="134" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="113" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge569.loopexit:0  br label %._crit_edge569

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="135" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="115" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
._crit_edge569:0  %w_tmp_bits_0 = phi i2 [ 0, %4 ], [ %p_0288_0, %._crit_edge569.loopexit ]

]]></Node>
<StgValue><ssdm name="w_tmp_bits_0"/></StgValue>
</operation>

<operation id="136" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="116" bw="3" op_0_bw="2">
<![CDATA[
._crit_edge569:1  %zext_ln143 = zext i2 %w_tmp_bits_0 to i3

]]></Node>
<StgValue><ssdm name="zext_ln143"/></StgValue>
</operation>

<operation id="137" st_id="24" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="117" bw="1" op_0_bw="2" op_1_bw="2">
<![CDATA[
._crit_edge569:2  %icmp_ln143 = icmp eq i2 %u_tmp_bits_read_1, 0

]]></Node>
<StgValue><ssdm name="icmp_ln143"/></StgValue>
</operation>

<operation id="138" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge569:3  br i1 %icmp_ln143, label %._crit_edge570, label %.preheader.preheader

]]></Node>
<StgValue><ssdm name="br_ln143"/></StgValue>
</operation>

<operation id="139" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln143" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="0" op_0_bw="0">
<![CDATA[
.preheader.preheader:0  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln147"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="140" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="122" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader:0  %p_0356_0 = phi i2 [ %trunc_ln858_2, %hls_label_28 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="p_0356_0"/></StgValue>
</operation>

<operation id="141" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="123" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
.preheader:1  %i6_0 = phi i4 [ %i_1, %hls_label_28 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="i6_0"/></StgValue>
</operation>

<operation id="142" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="124" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader:2  %j7_0 = phi i5 [ %j_3, %hls_label_28 ], [ 8, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="j7_0"/></StgValue>
</operation>

<operation id="143" st_id="25" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader:3  %icmp_ln147 = icmp eq i4 %i6_0, -8

]]></Node>
<StgValue><ssdm name="icmp_ln147"/></StgValue>
</operation>

<operation id="144" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="126" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:4  %empty_14 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 8, i64 8, i64 8)

]]></Node>
<StgValue><ssdm name="empty_14"/></StgValue>
</operation>

<operation id="145" st_id="25" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
.preheader:5  %i_1 = add i4 %i6_0, 1

]]></Node>
<StgValue><ssdm name="i_1"/></StgValue>
</operation>

<operation id="146" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:6  br i1 %icmp_ln147, label %5, label %hls_label_28

]]></Node>
<StgValue><ssdm name="br_ln147"/></StgValue>
</operation>

<operation id="147" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="133" bw="64" op_0_bw="4">
<![CDATA[
hls_label_28:3  %zext_ln150 = zext i4 %i6_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln150"/></StgValue>
</operation>

<operation id="148" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="134" bw="3" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_28:4  %v_digits_data_V_addr_1 = getelementptr [8 x i64]* %v_digits_data_V, i64 0, i64 %zext_ln150

]]></Node>
<StgValue><ssdm name="v_digits_data_V_addr_1"/></StgValue>
</operation>

<operation id="149" st_id="25" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="135" bw="64" op_0_bw="3">
<![CDATA[
hls_label_28:5  %v_digits_data_V_load_1 = load i64* %v_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="v_digits_data_V_load_1"/></StgValue>
</operation>

<operation id="150" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="137" bw="64" op_0_bw="5">
<![CDATA[
hls_label_28:7  %zext_ln151 = zext i5 %j7_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln151"/></StgValue>
</operation>

<operation id="151" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="138" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_28:8  %w_digits_data_V_addr_4 = getelementptr [16 x i64]* %w_digits_data_V, i64 0, i64 %zext_ln151

]]></Node>
<StgValue><ssdm name="w_digits_data_V_addr_4"/></StgValue>
</operation>

<operation id="152" st_id="25" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="64" op_0_bw="4">
<![CDATA[
hls_label_28:9  %w_digits_data_V_load_3 = load i64* %w_digits_data_V_addr_4, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_3"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="153" st_id="26" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="135" bw="64" op_0_bw="3">
<![CDATA[
hls_label_28:5  %v_digits_data_V_load_1 = load i64* %v_digits_data_V_addr_1, align 8

]]></Node>
<StgValue><ssdm name="v_digits_data_V_load_1"/></StgValue>
</operation>

<operation id="154" st_id="26" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="64" op_0_bw="4">
<![CDATA[
hls_label_28:9  %w_digits_data_V_load_3 = load i64* %w_digits_data_V_addr_4, align 8

]]></Node>
<StgValue><ssdm name="w_digits_data_V_load_3"/></StgValue>
</operation>

<operation id="155" st_id="26" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="150" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
hls_label_28:20  %j_3 = add i5 %j7_0, 1

]]></Node>
<StgValue><ssdm name="j_3"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="156" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="130" bw="65" op_0_bw="2">
<![CDATA[
hls_label_28:0  %zext_ln147 = zext i2 %p_0356_0 to i65

]]></Node>
<StgValue><ssdm name="zext_ln147"/></StgValue>
</operation>

<operation id="157" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="136" bw="65" op_0_bw="64">
<![CDATA[
hls_label_28:6  %zext_ln700_7 = zext i64 %v_digits_data_V_load_1 to i65

]]></Node>
<StgValue><ssdm name="zext_ln700_7"/></StgValue>
</operation>

<operation id="158" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="141" bw="64" op_0_bw="2">
<![CDATA[
hls_label_28:11  %zext_ln700_9 = zext i2 %p_0356_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_9"/></StgValue>
</operation>

<operation id="159" st_id="27" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="142" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_28:12  %tmp_V_5 = add i65 %zext_ln700_7, %zext_ln147

]]></Node>
<StgValue><ssdm name="tmp_V_5"/></StgValue>
</operation>

<operation id="160" st_id="27" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="145" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_28:15  %add_ln209_5 = add i64 %w_digits_data_V_load_3, %zext_ln700_9

]]></Node>
<StgValue><ssdm name="add_ln209_5"/></StgValue>
</operation>

<operation id="161" st_id="27" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="146" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_28:16  %add_ln209_3 = add i64 %add_ln209_5, %v_digits_data_V_load_1

]]></Node>
<StgValue><ssdm name="add_ln209_3"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="162" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="131" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_28:1  %tmp_2 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str57)

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>

<operation id="163" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="132" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_28:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln149"/></StgValue>
</operation>

<operation id="164" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="66" op_0_bw="64">
<![CDATA[
hls_label_28:10  %zext_ln700_8 = zext i64 %w_digits_data_V_load_3 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_8"/></StgValue>
</operation>

<operation id="165" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="143" bw="66" op_0_bw="65">
<![CDATA[
hls_label_28:13  %zext_ln700_10 = zext i65 %tmp_V_5 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_10"/></StgValue>
</operation>

<operation id="166" st_id="28" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="144" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_28:14  %tmp_V_3 = add i66 %zext_ln700_10, %zext_ln700_8

]]></Node>
<StgValue><ssdm name="tmp_V_3"/></StgValue>
</operation>

<operation id="167" st_id="28" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="0" op_0_bw="64" op_1_bw="4" op_2_bw="64">
<![CDATA[
hls_label_28:17  store i64 %add_ln209_3, i64* %w_digits_data_V_addr_4, align 8

]]></Node>
<StgValue><ssdm name="store_ln152"/></StgValue>
</operation>

<operation id="168" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_28:18  %trunc_ln858_2 = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V_3, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln858_2"/></StgValue>
</operation>

<operation id="169" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="149" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_28:19  %empty_15 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str57, i32 %tmp_2)

]]></Node>
<StgValue><ssdm name="empty_15"/></StgValue>
</operation>

<operation id="170" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln147" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="0" op_0_bw="0">
<![CDATA[
hls_label_28:21  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln147"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="171" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="153" bw="3" op_0_bw="2">
<![CDATA[
:0  %zext_ln155 = zext i2 %p_0356_0 to i3

]]></Node>
<StgValue><ssdm name="zext_ln155"/></StgValue>
</operation>

<operation id="172" st_id="29" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="154" bw="3" op_0_bw="3" op_1_bw="3">
<![CDATA[
:1  %add_ln155 = add i3 %zext_ln143, %zext_ln155

]]></Node>
<StgValue><ssdm name="add_ln155"/></StgValue>
</operation>

<operation id="173" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="155" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %._crit_edge570

]]></Node>
<StgValue><ssdm name="br_ln156"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="174" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="157" bw="3" op_0_bw="3" op_1_bw="0" op_2_bw="3" op_3_bw="0">
<![CDATA[
._crit_edge570:0  %w_tmp_bits_1 = phi i3 [ %zext_ln143, %._crit_edge569 ], [ %add_ln155, %5 ]

]]></Node>
<StgValue><ssdm name="w_tmp_bits_1"/></StgValue>
</operation>

<operation id="175" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="158" bw="4" op_0_bw="3">
<![CDATA[
._crit_edge570:1  %zext_ln157 = zext i3 %w_tmp_bits_1 to i4

]]></Node>
<StgValue><ssdm name="zext_ln157"/></StgValue>
</operation>

<operation id="176" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="159" bw="4" op_0_bw="2">
<![CDATA[
._crit_edge570:2  %zext_ln157_1 = zext i2 %v_tmp_bits_read_1 to i4

]]></Node>
<StgValue><ssdm name="zext_ln157_1"/></StgValue>
</operation>

<operation id="177" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="160" bw="4" op_0_bw="2">
<![CDATA[
._crit_edge570:3  %zext_ln157_2 = zext i2 %u_tmp_bits_read_1 to i4

]]></Node>
<StgValue><ssdm name="zext_ln157_2"/></StgValue>
</operation>

<operation id="178" st_id="30" stage="1" lat="1">
<core>Mul</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="161" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
._crit_edge570:4  %mul_ln157 = mul i4 %zext_ln157_1, %zext_ln157_2

]]></Node>
<StgValue><ssdm name="mul_ln157"/></StgValue>
</operation>

<operation id="179" st_id="30" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="162" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
._crit_edge570:5  %add_ln157 = add i4 %mul_ln157, %zext_ln157

]]></Node>
<StgValue><ssdm name="add_ln157"/></StgValue>
</operation>

<operation id="180" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="163" bw="0" op_0_bw="4">
<![CDATA[
._crit_edge570:6  ret i4 %add_ln157

]]></Node>
<StgValue><ssdm name="ret_ln158"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
