<stg><name>karastuba_mul_ADD_SU</name>


<trans_list>

<trans id="108" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="134" from="2" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="135" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="131" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="132" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="133" from="5" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="115" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="141" from="7" to="12">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="142" from="7" to="8">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="137" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="138" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="139" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="140" from="11" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="123" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="124" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="146" from="14" to="17">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="147" from="14" to="15">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="144" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="145" from="16" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %cross_mul_tmp_bits_r = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %cross_mul_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="cross_mul_tmp_bits_r"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:1  %z2_tmp_bits_read_3 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %z2_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="z2_tmp_bits_read_3"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %z0_tmp_bits_read_3 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %z0_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="z0_tmp_bits_read_3"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="64" op_0_bw="64">
<![CDATA[
:3  %add2_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V"/></StgValue>
</operation>

<operation id="22" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64">
<![CDATA[
:4  %z1_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="z1_digits_data_V"/></StgValue>
</operation>

<operation id="23" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64">
<![CDATA[
:5  %p_res_digits_data_V = alloca [128 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_res_digits_data_V"/></StgValue>
</operation>

<operation id="24" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0">
<![CDATA[
:6  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln54"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="25" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader.i:0  %p_088_0_i = phi i2 [ %trunc_ln, %hls_label_47 ], [ 0, %0 ]

]]></Node>
<StgValue><ssdm name="p_088_0_i"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader.i:1  %i_0_i = phi i7 [ %i, %hls_label_47 ], [ 0, %0 ]

]]></Node>
<StgValue><ssdm name="i_0_i"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i:2  %icmp_ln54 = icmp eq i7 %i_0_i, -64

]]></Node>
<StgValue><ssdm name="icmp_ln54"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i:3  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i:4  %i = add i7 %i_0_i, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i:5  br i1 %icmp_ln54, label %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit", label %hls_label_47

]]></Node>
<StgValue><ssdm name="br_ln54"/></StgValue>
</operation>

<operation id="31" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="64" op_0_bw="7">
<![CDATA[
hls_label_47:3  %zext_ln59 = zext i7 %i_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln59"/></StgValue>
</operation>

<operation id="32" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="27" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_47:4  %z0_digits_data_V_add = getelementptr [64 x i64]* %z0_digits_data_V, i64 0, i64 %zext_ln59

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_add"/></StgValue>
</operation>

<operation id="33" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="28" bw="64" op_0_bw="6">
<![CDATA[
hls_label_47:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="34" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_47:7  %z2_digits_data_V_add = getelementptr [64 x i64]* %z2_digits_data_V, i64 0, i64 %zext_ln59

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_add"/></StgValue>
</operation>

<operation id="35" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="64" op_0_bw="6">
<![CDATA[
hls_label_47:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="36" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="28" bw="64" op_0_bw="6">
<![CDATA[
hls_label_47:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="37" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="64" op_0_bw="6">
<![CDATA[
hls_label_47:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="38" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="65" op_0_bw="2">
<![CDATA[
hls_label_47:0  %zext_ln54 = zext i2 %p_088_0_i to i65

]]></Node>
<StgValue><ssdm name="zext_ln54"/></StgValue>
</operation>

<operation id="39" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="65" op_0_bw="64">
<![CDATA[
hls_label_47:6  %zext_ln209 = zext i64 %z0_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln209"/></StgValue>
</operation>

<operation id="40" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="33" bw="64" op_0_bw="2">
<![CDATA[
hls_label_47:10  %zext_ln700_16 = zext i2 %p_088_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_16"/></StgValue>
</operation>

<operation id="41" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_47:11  %add_ln700 = add i65 %zext_ln209, %zext_ln54

]]></Node>
<StgValue><ssdm name="add_ln700"/></StgValue>
</operation>

<operation id="42" st_id="4" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_47:14  %add_ln209_14 = add i64 %z2_digits_data_V_loa, %zext_ln700_16

]]></Node>
<StgValue><ssdm name="add_ln209_14"/></StgValue>
</operation>

<operation id="43" st_id="4" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_47:15  %add_ln209_5 = add i64 %add_ln209_14, %z0_digits_data_V_loa

]]></Node>
<StgValue><ssdm name="add_ln209_5"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="44" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_47:1  %tmp_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str17)

]]></Node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="45" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_47:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln56"/></StgValue>
</operation>

<operation id="46" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="32" bw="66" op_0_bw="64">
<![CDATA[
hls_label_47:9  %zext_ln700 = zext i64 %z2_digits_data_V_loa to i66

]]></Node>
<StgValue><ssdm name="zext_ln700"/></StgValue>
</operation>

<operation id="47" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="35" bw="66" op_0_bw="65">
<![CDATA[
hls_label_47:12  %zext_ln700_17 = zext i65 %add_ln700 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_17"/></StgValue>
</operation>

<operation id="48" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_47:13  %tmp_V = add i66 %zext_ln700_17, %zext_ln700

]]></Node>
<StgValue><ssdm name="tmp_V"/></StgValue>
</operation>

<operation id="49" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="39" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_47:16  %add2_digits_data_V_a = getelementptr [64 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln59

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a"/></StgValue>
</operation>

<operation id="50" st_id="5" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_47:17  store i64 %add_ln209_5, i64* %add2_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln61"/></StgValue>
</operation>

<operation id="51" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_47:18  %trunc_ln = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln"/></StgValue>
</operation>

<operation id="52" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_47:19  %empty_84 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str17, i32 %tmp_i)

]]></Node>
<StgValue><ssdm name="empty_84"/></StgValue>
</operation>

<operation id="53" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln54" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="0" op_0_bw="0">
<![CDATA[
hls_label_47:20  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln54"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="54" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="32" op_0_bw="2">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:0  %zext_ln64 = zext i2 %p_088_0_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln64"/></StgValue>
</operation>

<operation id="55" st_id="6" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:1  %add_ln64 = add i32 %zext_ln64, %z0_tmp_bits_read_3

]]></Node>
<StgValue><ssdm name="add_ln64"/></StgValue>
</operation>

<operation id="56" st_id="6" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:2  %add2_tmp_bits = add i32 %add_ln64, %z2_tmp_bits_read_3

]]></Node>
<StgValue><ssdm name="add2_tmp_bits"/></StgValue>
</operation>

<operation id="57" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:3  br label %.preheader.i12

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="58" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
<![CDATA[
.preheader.i12:0  %op2_assign = phi i1 [ %tmp, %hls_label_48 ], [ false, %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="op2_assign"/></StgValue>
</operation>

<operation id="59" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader.i12:1  %i_0_i11 = phi i7 [ %i_31, %hls_label_48 ], [ 0, %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="i_0_i11"/></StgValue>
</operation>

<operation id="60" st_id="7" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i12:2  %exitcond_i = icmp eq i7 %i_0_i11, -64

]]></Node>
<StgValue><ssdm name="exitcond_i"/></StgValue>
</operation>

<operation id="61" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i12:3  %empty_85 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_85"/></StgValue>
</operation>

<operation id="62" st_id="7" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i12:4  %i_31 = add i7 %i_0_i11, 1

]]></Node>
<StgValue><ssdm name="i_31"/></StgValue>
</operation>

<operation id="63" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i12:5  br i1 %exitcond_i, label %"sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit", label %hls_label_48

]]></Node>
<StgValue><ssdm name="br_ln78"/></StgValue>
</operation>

<operation id="64" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="64" op_0_bw="7">
<![CDATA[
hls_label_48:2  %zext_ln81 = zext i7 %i_0_i11 to i64

]]></Node>
<StgValue><ssdm name="zext_ln81"/></StgValue>
</operation>

<operation id="65" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_48:3  %cross_mul_digits_dat = getelementptr [64 x i64]* %cross_mul_digits_data_V, i64 0, i64 %zext_ln81

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat"/></StgValue>
</operation>

<operation id="66" st_id="7" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="64" op_0_bw="6">
<![CDATA[
hls_label_48:4  %cross_mul_digits_dat_5 = load i64* %cross_mul_digits_dat, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_5"/></StgValue>
</operation>

<operation id="67" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_48:6  %add2_digits_data_V_a_3 = getelementptr [64 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln81

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a_3"/></StgValue>
</operation>

<operation id="68" st_id="7" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="64" op_0_bw="6">
<![CDATA[
hls_label_48:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_3, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="69" st_id="8" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="64" op_0_bw="6">
<![CDATA[
hls_label_48:4  %cross_mul_digits_dat_5 = load i64* %cross_mul_digits_dat, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_5"/></StgValue>
</operation>

<operation id="70" st_id="8" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="64" op_0_bw="6">
<![CDATA[
hls_label_48:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_3, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="71" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="65" op_0_bw="64">
<![CDATA[
hls_label_48:5  %zext_ln180 = zext i64 %cross_mul_digits_dat_5 to i65

]]></Node>
<StgValue><ssdm name="zext_ln180"/></StgValue>
</operation>

<operation id="72" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="65" op_0_bw="64">
<![CDATA[
hls_label_48:8  %zext_ln701 = zext i64 %add2_digits_data_V_l to i65

]]></Node>
<StgValue><ssdm name="zext_ln701"/></StgValue>
</operation>

<operation id="73" st_id="9" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_48:9  %tmp_V_25 = sub i65 %zext_ln180, %zext_ln701

]]></Node>
<StgValue><ssdm name="tmp_V_25"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="74" st_id="10" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="65" op_0_bw="1" op_1_bw="65" op_2_bw="65">
<![CDATA[
hls_label_48:10  %select_ln701 = select i1 %op2_assign, i65 -1, i65 0

]]></Node>
<StgValue><ssdm name="select_ln701"/></StgValue>
</operation>

<operation id="75" st_id="10" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="64" op_0_bw="1" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_48:11  %select_ln701_3 = select i1 %op2_assign, i64 -1, i64 0

]]></Node>
<StgValue><ssdm name="select_ln701_3"/></StgValue>
</operation>

<operation id="76" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="64" op_0_bw="65">
<![CDATA[
hls_label_48:12  %trunc_ln701 = trunc i65 %tmp_V_25 to i64

]]></Node>
<StgValue><ssdm name="trunc_ln701"/></StgValue>
</operation>

<operation id="77" st_id="10" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_48:13  %tmp_V_26 = add i65 %select_ln701, %tmp_V_25

]]></Node>
<StgValue><ssdm name="tmp_V_26"/></StgValue>
</operation>

<operation id="78" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="1" op_0_bw="1" op_1_bw="65" op_2_bw="32">
<![CDATA[
hls_label_48:14  %tmp = call i1 @_ssdm_op_BitSelect.i1.i65.i32(i65 %tmp_V_26, i32 64)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="79" st_id="10" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_48:15  %add_ln700_15 = add i64 %trunc_ln701, %select_ln701_3

]]></Node>
<StgValue><ssdm name="add_ln700_15"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="80" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_48:0  %tmp_i1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str16)

]]></Node>
<StgValue><ssdm name="tmp_i1"/></StgValue>
</operation>

<operation id="81" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_48:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln80"/></StgValue>
</operation>

<operation id="82" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_48:16  %z1_digits_data_V_add = getelementptr [64 x i64]* %z1_digits_data_V, i64 0, i64 %zext_ln81

]]></Node>
<StgValue><ssdm name="z1_digits_data_V_add"/></StgValue>
</operation>

<operation id="83" st_id="11" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_48:17  store i64 %add_ln700_15, i64* %z1_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln89"/></StgValue>
</operation>

<operation id="84" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_48:18  %empty_86 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str16, i32 %tmp_i1)

]]></Node>
<StgValue><ssdm name="empty_86"/></StgValue>
</operation>

<operation id="85" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="0" op_0_bw="0">
<![CDATA[
hls_label_48:19  br label %.preheader.i12

]]></Node>
<StgValue><ssdm name="br_ln78"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="86" st_id="12" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:0  %p_neg207_i = select i1 %op2_assign, i32 -1, i32 0

]]></Node>
<StgValue><ssdm name="p_neg207_i"/></StgValue>
</operation>

<operation id="87" st_id="12" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:1  %add_ln96 = add i32 %cross_mul_tmp_bits_r, %p_neg207_i

]]></Node>
<StgValue><ssdm name="add_ln96"/></StgValue>
</operation>

<operation id="88" st_id="12" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:2  %z1_tmp_bits = sub i32 %add_ln96, %add2_tmp_bits

]]></Node>
<StgValue><ssdm name="z1_tmp_bits"/></StgValue>
</operation>

<operation id="89" st_id="12" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="81" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="32" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:3  call fastcc void @CAT_I_I_I_O([64 x i64]* %z0_digits_data_V, i32 %z1_tmp_bits, [64 x i64]* %z1_digits_data_V, [64 x i64]* %z2_digits_data_V, [128 x i64]* %p_res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln331"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="90" st_id="13" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="81" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="32" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:3  call fastcc void @CAT_I_I_I_O([64 x i64]* %z0_digits_data_V, i32 %z1_tmp_bits, [64 x i64]* %z1_digits_data_V, [64 x i64]* %z2_digits_data_V, [128 x i64]* %p_res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln331"/></StgValue>
</operation>

<operation id="91" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="0" op_0_bw="0">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:4  br label %1

]]></Node>
<StgValue><ssdm name="br_ln364"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="92" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="84" bw="8" op_0_bw="8" op_1_bw="0" op_2_bw="8" op_3_bw="0">
<![CDATA[
:0  %i5_0 = phi i8 [ 0, %"sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit" ], [ %i_32, %hls_label_46 ]

]]></Node>
<StgValue><ssdm name="i5_0"/></StgValue>
</operation>

<operation id="93" st_id="14" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="85" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
:1  %icmp_ln364 = icmp eq i8 %i5_0, -128

]]></Node>
<StgValue><ssdm name="icmp_ln364"/></StgValue>
</operation>

<operation id="94" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="86" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_87 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 128, i64 128, i64 128)

]]></Node>
<StgValue><ssdm name="empty_87"/></StgValue>
</operation>

<operation id="95" st_id="14" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="87" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
:3  %i_32 = add i8 %i5_0, 1

]]></Node>
<StgValue><ssdm name="i_32"/></StgValue>
</operation>

<operation id="96" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln364, label %2, label %hls_label_46

]]></Node>
<StgValue><ssdm name="br_ln364"/></StgValue>
</operation>

<operation id="97" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="64" op_0_bw="8">
<![CDATA[
hls_label_46:2  %zext_ln367 = zext i8 %i5_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln367"/></StgValue>
</operation>

<operation id="98" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="7" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_46:3  %p_res_digits_data_V_a = getelementptr [128 x i64]* %p_res_digits_data_V, i64 0, i64 %zext_ln367

]]></Node>
<StgValue><ssdm name="p_res_digits_data_V_a"/></StgValue>
</operation>

<operation id="99" st_id="14" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="64" op_0_bw="7">
<![CDATA[
hls_label_46:4  %p_res_digits_data_V_l = load i64* %p_res_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="p_res_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="100" st_id="15" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="64" op_0_bw="7">
<![CDATA[
hls_label_46:4  %p_res_digits_data_V_l = load i64* %p_res_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="p_res_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="101" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_46:0  %tmp_1 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str11)

]]></Node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="102" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_46:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln366"/></StgValue>
</operation>

<operation id="103" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="7" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_46:5  %res_digits_data_V_ad = getelementptr [128 x i64]* %res_digits_data_V, i64 0, i64 %zext_ln367

]]></Node>
<StgValue><ssdm name="res_digits_data_V_ad"/></StgValue>
</operation>

<operation id="104" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="0" op_0_bw="64" op_1_bw="7">
<![CDATA[
hls_label_46:6  store i64 %p_res_digits_data_V_l, i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="store_ln367"/></StgValue>
</operation>

<operation id="105" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_46:7  %empty_88 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str11, i32 %tmp_1)

]]></Node>
<StgValue><ssdm name="empty_88"/></StgValue>
</operation>

<operation id="106" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln364" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="0" op_0_bw="0">
<![CDATA[
hls_label_46:8  br label %1

]]></Node>
<StgValue><ssdm name="br_ln364"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="107" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="100" bw="0">
<![CDATA[
:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln371"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
