<annotationInfo>
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<item  id="10" filename="multest.cc" linenumber="412" name="i" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="i_fu_104_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="416" name="tmp_4" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="tmp_4_fu_110_p4" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="416" name="icmp_ln416" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="icmp_ln416_fu_120_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="8" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="419" name="add_ln419" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="add_ln419_fu_126_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="419" name="zext_ln419" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="zext_ln419_fu_137_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="417" name="zext_ln417" contextFuncName="karastuba_mul" moduleName="Loop_1_proc" rtlName="zext_ln417_fu_132_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="105" name="icmp_ln105" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln105_fu_314_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="105" name="j" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="j_fu_320_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="105" name="zext_ln105" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln105_fu_326_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="108" name="icmp_ln108" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln108_fu_331_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="108" name="j_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="j_2_fu_337_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="116" name="zext_ln116" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln116_fu_343_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="111" name="icmp_ln111" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln111_fu_353_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="37" filename="multest.cc" linenumber="111" name="add_ln111" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln111_fu_359_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="111" name="zext_ln111" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln111_fu_394_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="114" name="add_ln114" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln114_fu_365_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="116" name="zext_ln116_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln116_1_fu_371_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="47" filename="multest.cc" linenumber="116" name="zext_ln700" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="grp_fu_384_p00" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="116" name="zext_ln700_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="grp_fu_384_p10" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="50" filename="multest.cc" linenumber="116" name="mul_ln700" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="karastuba_mul_mulbkb_U5" latency="5" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="116" name="zext_ln116_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln116_2_fu_390_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="116" name="zext_ln700_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_2_fu_412_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="116" name="add_ln700" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln700_fu_398_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="135" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="116" name="trunc_ln700" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="trunc_ln700_fu_403_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="116" name="k_V" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="k_V_fu_416_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="135" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="117" name="add_ln209_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_1_fu_407_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="118" name="trunc_ln1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="p_0176_1_reg_188" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="121" name="icmp_ln883" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln883_fu_431_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="29" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="67" filename="multest.cc" linenumber="123" name="xor_ln123" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="xor_ln123_fu_437_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="5" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="68" filename="multest.cc" linenumber="123" name="zext_ln123" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln123_fu_443_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="124" name="add_ln209_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_2_fu_448_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="129" name="icmp_ln129" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln129_fu_348_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="8" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="85" filename="multest.cc" linenumber="133" name="icmp_ln133" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln133_fu_454_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="133" name="i" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="i_fu_460_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="90" filename="multest.cc" linenumber="133" name="zext_ln133" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln133_fu_482_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="136" name="zext_ln136" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln136_fu_466_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="136" name="zext_ln700_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_3_fu_486_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="137" name="zext_ln137" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln137_fu_471_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="136" name="zext_ln700_4" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_4_fu_512_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="136" name="zext_ln700_5" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_5_fu_490_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="136" name="tmp_V_4" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="tmp_V_4_fu_494_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="136" name="zext_ln700_6" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_6_fu_516_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="104" filename="multest.cc" linenumber="137" name="tmp_V" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="tmp_V_fu_519_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="138" name="add_ln209_4" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_4_fu_500_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="138" name="add_ln209" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_fu_506_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="108" filename="multest.cc" linenumber="139" name="trunc_ln858_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="p_0288_0_reg_211" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="110" filename="multest.cc" linenumber="133" name="j_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="j_1_fu_476_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="143" name="zext_ln143" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln143_fu_535_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="143" name="icmp_ln143" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln143_fu_539_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="8" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="125" filename="multest.cc" linenumber="147" name="icmp_ln147" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="icmp_ln147_fu_544_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="127" filename="multest.cc" linenumber="147" name="i_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="i_1_fu_550_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="130" filename="multest.cc" linenumber="147" name="zext_ln147" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln147_fu_572_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="133" filename="multest.cc" linenumber="150" name="zext_ln150" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln150_fu_556_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="136" filename="multest.cc" linenumber="150" name="zext_ln700_7" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_7_fu_576_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="137" filename="multest.cc" linenumber="151" name="zext_ln151" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln151_fu_561_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="140" filename="multest.cc" linenumber="150" name="zext_ln700_8" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_8_fu_602_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="141" filename="multest.cc" linenumber="150" name="zext_ln700_9" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_9_fu_580_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="150" name="tmp_V_5" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="tmp_V_5_fu_584_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="143" filename="multest.cc" linenumber="150" name="zext_ln700_10" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_10_fu_606_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="144" filename="multest.cc" linenumber="151" name="tmp_V_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="tmp_V_3_fu_609_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="145" filename="multest.cc" linenumber="152" name="add_ln209_5" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_5_fu_590_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="146" filename="multest.cc" linenumber="152" name="add_ln209_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_3_fu_596_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="153" name="trunc_ln858_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="p_0356_0_reg_258" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="150" filename="multest.cc" linenumber="147" name="j_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="j_3_fu_566_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="153" filename="multest.cc" linenumber="155" name="zext_ln155" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln155_fu_625_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="154" filename="multest.cc" linenumber="155" name="add_ln155" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln155_fu_629_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="158" filename="multest.cc" linenumber="157" name="zext_ln157" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln157_fu_634_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="159" filename="multest.cc" linenumber="157" name="zext_ln157_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln157_fu_644_p00" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="160" filename="multest.cc" linenumber="157" name="zext_ln157_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln157_fu_644_p10" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="161" filename="multest.cc" linenumber="157" name="mul_ln157" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln157_fu_644_p2" latency="0" BRAM="-1" DSP="0" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="162" filename="multest.cc" linenumber="157" name="add_ln157" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln157_fu_650_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="233" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;16, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="234" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;16, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="icmp_ln54_fu_192_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="54" name="i" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="i_fu_198_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln54_fu_210_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln59_fu_204_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="60" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln209_fu_214_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_fu_241_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="59" name="zext_ln700_11" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_11_fu_218_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln700_fu_222_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="zext_ln700_12" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_12_fu_244_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="60" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="tmp_V_fu_247_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="61" name="add_ln209_6" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln209_6_fu_228_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="61" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add0_digits_data_V_d0" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="p_088_0_i_reg_134" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="54" name="icmp_ln54_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="icmp_ln54_1_fu_263_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="54" name="i_2" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="i_2_fu_269_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="54" name="zext_ln54_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln54_1_fu_281_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="59" name="zext_ln59_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln59_1_fu_275_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="60" name="zext_ln209_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln209_1_fu_285_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="59" name="zext_ln700_13" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_13_fu_312_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="59" name="zext_ln700_14" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_14_fu_289_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="add_ln700_7" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln700_7_fu_293_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="zext_ln700_15" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_15_fu_315_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="60" name="tmp_V_6" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="tmp_V_6_fu_318_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="61" name="add_ln209_7" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln209_7_fu_299_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="61" name="add_ln209_4" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add1_digits_data_V_d0" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="62" name="trunc_ln858_3" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="p_088_0_i1_reg_157" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="220" name="res_tmp_bits_write_a" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="grp_mul_I_O_fu_180" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="258" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="258" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="258" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="258" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="258" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="258" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="258" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="258" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="262" name="icmp_ln262" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln262_fu_525_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="262" name="i" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_fu_531_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="265" name="zext_ln265" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln265_fu_537_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="50" filename="multest.cc" linenumber="267" name="icmp_ln267" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln267_fu_542_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="267" name="i_5" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_5_fu_548_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="270" name="zext_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln270_fu_565_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="270" name="xor_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="xor_ln270_fu_554_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="5" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="270" name="zext_ln270_1" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln270_1_fu_560_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="272" name="icmp_ln272" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln272_fu_571_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="76" filename="multest.cc" linenumber="272" name="i_6" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_6_fu_577_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="81" filename="multest.cc" linenumber="275" name="zext_ln275" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln275_fu_583_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="277" name="icmp_ln277" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln277_fu_588_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="277" name="i_7" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_7_fu_594_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="280" name="zext_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln280_fu_611_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="104" filename="multest.cc" linenumber="280" name="xor_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="xor_ln280_fu_600_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="5" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="280" name="zext_ln280_1" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln280_1_fu_606_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="220" name="z0_tmp_bits_i" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="grp_mul_I_O_fu_485" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="220" name="z2_tmp_bits_i" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="grp_mul_I_O_fu_496" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="119" filename="multest.cc" linenumber="292" name="cross_mul_tmp_bits_i" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="grp_karastuba_mul_templa_2_fu_476" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="292" name="p_cross_mul_tmp_bits" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="p_cross_mul_tmp_bits_fu_617_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="124" filename="multest.cc" linenumber="294" name="icmp_ln294" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln294_fu_621_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="126" filename="multest.cc" linenumber="294" name="i_8" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_8_fu_627_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="131" filename="multest.cc" linenumber="297" name="zext_ln297" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln297_fu_633_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="300" name="icmp_ln300" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln300_fu_638_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="144" filename="multest.cc" linenumber="300" name="i_9" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_9_fu_644_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="149" filename="multest.cc" linenumber="303" name="zext_ln303" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln303_fu_650_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="160" filename="multest.cc" linenumber="306" name="icmp_ln306" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="icmp_ln306_fu_655_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="162" filename="multest.cc" linenumber="306" name="i_10" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="i_10_fu_661_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="167" filename="multest.cc" linenumber="309" name="zext_ln309" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln309_fu_667_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="175" filename="multest.cc" linenumber="312" name="zext_ln312" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln312_fu_672_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="177" filename="multest.cc" linenumber="312" name="zext_ln312_1" contextFuncName="karastuba_mul_MUL_stage&lt;16, 64&gt;" moduleName="karastuba_mul_MUL_st.2" rtlName="zext_ln312_1_fu_681_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="168" name="icmp_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln168_fu_248_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="168" name="zext_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln168_fu_254_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="168" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_fu_259_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="170" name="icmp_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln170_fu_265_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="170" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_fu_271_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="170" name="zext_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln170_fu_277_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="175" name="icmp_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln175_fu_282_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="175" name="i_33" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_33_fu_288_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="175" name="zext_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln175_fu_310_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln180_fu_294_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="180" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_fu_314_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="181" name="zext_ln181" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln181_fu_299_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="180" name="zext_ln700_36" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_36_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="180" name="zext_ln700_37" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_37_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="180" name="tmp_V_30" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_30_fu_321_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="zext_ln700_38" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_38_fu_342_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="181" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_fu_345_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="182" name="add_ln209_17" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_17_fu_327_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="182" name="add_ln209_11" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_11_fu_333_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="183" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="p_0136_0_reg_174" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="184" name="j_6" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_6_fu_304_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="186" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln1468_fu_361_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="186" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln209_fu_365_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="186" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_fu_368_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="186" name="zext_ln209_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln209_2_fu_374_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="186" name="add_ln209_3" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_3_fu_377_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="81" filename="multest.cc" linenumber="191" name="icmp_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln191_fu_383_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="83" filename="multest.cc" linenumber="191" name="i_34" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_34_fu_389_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="86" filename="multest.cc" linenumber="191" name="zext_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln191_fu_411_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln196_fu_395_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="92" filename="multest.cc" linenumber="196" name="zext_ln700_39" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_39_fu_415_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="197" name="zext_ln197" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln197_fu_400_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="196" name="zext_ln700_40" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_40_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="196" name="zext_ln700_41" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_41_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="196" name="tmp_V_31" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_31_fu_422_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="zext_ln700_42" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_42_fu_443_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="197" name="tmp_V_29" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_29_fu_446_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="198" name="add_ln209_18" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_18_fu_428_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="198" name="add_ln209_12" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_12_fu_434_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="104" filename="multest.cc" linenumber="199" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="p_0136_2_reg_209" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="200" name="j_7" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_7_fu_405_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="325" name="add2_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="326" name="z1_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="327" name="p_res_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_res_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln54_fu_444_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="54" name="i_23" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="i_23_fu_450_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln54_fu_462_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln59_fu_456_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="36" filename="multest.cc" linenumber="60" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln209_fu_466_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="39" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_fu_489_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="59" name="zext_ln700_23" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_23_fu_469_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln700_fu_473_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="59" name="zext_ln700_24" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_24_fu_492_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="60" name="tmp_V_9" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_9_fu_495_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="61" name="add_ln209_11" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_11_fu_479_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="61" name="add_ln209_7" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_7_fu_484_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_088_0_i_reg_280" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="64" name="zext_ln64" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln64_fu_511_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="64" name="add_ln64" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln64_fu_515_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="64" name="add2_tmp_bits" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add2_tmp_bits_fu_520_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="78" name="exitcond_i" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="exitcond_i_fu_525_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="78" name="i_24" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="i_24_fu_531_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="81" name="zext_ln81" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln81_fu_537_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="69" filename="multest.cc" linenumber="81" name="zext_ln180" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln180_fu_543_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="82" name="zext_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln701_fu_546_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="82" name="tmp_V_10" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_10_fu_549_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="83" name="select_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="select_ln701_fu_555_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="83" name="select_ln701_1" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="select_ln701_1_fu_563_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="76" filename="multest.cc" linenumber="83" name="trunc_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="trunc_ln701_fu_571_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="83" name="tmp_V_11" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_11_fu_574_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="78" filename="multest.cc" linenumber="85" name="tmp_1" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_1_reg_946" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="88" name="add_ln700_15" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln700_15_fu_587_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="85" filename="multest.cc" linenumber="85" name="p_neg207_i" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_neg207_i_fu_593_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="86" filename="multest.cc" linenumber="96" name="add_ln96" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln96_fu_601_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="96" name="z1_tmp_bits" contextFuncName="sub_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="z1_tmp_bits_fu_606_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="88" filename="multest.cc" linenumber="331" name="_ln331" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="grp_CAT_I_I_I_O_2_fu_428" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="334" name="icmp_ln334" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln334_fu_612_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="20" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="338" name="icmp_ln338" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln338_fu_617_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="338" name="i" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="i_fu_623_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="338" name="zext_ln338" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln338_fu_645_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="341" name="zext_ln341" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln341_fu_629_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="108" filename="multest.cc" linenumber="341" name="zext_ln700_25" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_25_fu_649_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="109" filename="multest.cc" linenumber="342" name="zext_ln342" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln342_fu_634_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="112" filename="multest.cc" linenumber="341" name="zext_ln700_26" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_26_fu_673_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="113" filename="multest.cc" linenumber="341" name="zext_ln700_27" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_27_fu_652_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="114" filename="multest.cc" linenumber="341" name="tmp_V_15" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_15_fu_656_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="115" filename="multest.cc" linenumber="341" name="zext_ln700_28" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_28_fu_677_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="342" name="tmp_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_fu_680_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="343" name="add_ln209_12" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_12_fu_662_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="343" name="add_ln209" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_fu_668_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="344" name="trunc_ln858_8" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_0106_0_reg_326" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="122" filename="multest.cc" linenumber="338" name="j" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="j_fu_639_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="128" filename="multest.cc" linenumber="348" name="zext_ln348" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln348_fu_696_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="129" filename="multest.cc" linenumber="348" name="icmp_ln348" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln348_fu_700_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="20" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="137" filename="multest.cc" linenumber="352" name="icmp_ln352" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln352_fu_705_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="139" filename="multest.cc" linenumber="352" name="i_25" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="i_25_fu_711_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="352" name="zext_ln352" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln352_fu_733_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="145" filename="multest.cc" linenumber="355" name="zext_ln355" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln355_fu_717_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="355" name="zext_ln700_29" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_29_fu_737_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="149" filename="multest.cc" linenumber="356" name="zext_ln356" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln356_fu_722_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="152" filename="multest.cc" linenumber="355" name="zext_ln700_30" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_30_fu_761_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="153" filename="multest.cc" linenumber="355" name="zext_ln700_31" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_31_fu_740_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="154" filename="multest.cc" linenumber="355" name="tmp_V_16" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_16_fu_744_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="155" filename="multest.cc" linenumber="355" name="zext_ln700_32" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln700_32_fu_765_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="156" filename="multest.cc" linenumber="356" name="tmp_V_14" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="tmp_V_14_fu_768_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="157" filename="multest.cc" linenumber="357" name="add_ln209_13" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_13_fu_750_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="158" filename="multest.cc" linenumber="357" name="add_ln209_6" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="add_ln209_6_fu_756_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="160" filename="multest.cc" linenumber="358" name="trunc_ln858_9" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_0103_0_reg_373" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="162" filename="multest.cc" linenumber="352" name="j_4" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="j_4_fu_727_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="165" filename="multest.cc" linenumber="360" name="zext_ln360" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln360_fu_784_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="166" filename="multest.cc" linenumber="360" name="p_res_tmp_bits" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_res_tmp_bits_fu_788_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="170" filename="multest.cc" linenumber="362" name="zext_ln362" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln362_fu_797_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="171" filename="multest.cc" linenumber="362" name="mul_ln362" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="karastuba_mul_mulsc4_U33" latency="4" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="172" filename="multest.cc" linenumber="362" name="p_res_tmp_bits_2" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="p_res_tmp_bits_2_fu_801_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="39" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="176" filename="multest.cc" linenumber="364" name="icmp_ln364" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="icmp_ln364_fu_806_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="178" filename="multest.cc" linenumber="364" name="i_26" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="i_26_fu_812_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="183" filename="multest.cc" linenumber="367" name="zext_ln367" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;16, 64&gt;" moduleName="karastuba_mul_ADD_SU.2" rtlName="zext_ln367_fu_818_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="385" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="386" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="387" name="cross_mul_digits_dat" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="cross_mul_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="388" name="inter_lhs_digits_dat" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="inter_lhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="389" name="inter_rhs_digits_dat" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="inter_rhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="390" name="tmp" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="karastuba_mul_MUL_st_2_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="390" name="z0_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z0_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="390" name="z2_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z2_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="390" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="cross_mul_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="390" name="inter_lhs_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="inter_lhs_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="390" name="inter_rhs_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="inter_rhs_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="21" filename="multest.cc" linenumber="391" name="_ln391" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="karastuba_mul_ADD_SU_2_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="233" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="234" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="icmp_ln54_fu_196_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="54" name="i" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="i_fu_202_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln54_fu_214_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="21" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln59_fu_208_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_fu_218_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="59" name="zext_ln700_16" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_16_fu_241_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="zext_ln700_17" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_17_fu_221_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln700_fu_225_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="59" name="zext_ln700_18" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_18_fu_244_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="60" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="tmp_V_fu_247_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="61" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_fu_231_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="61" name="add_ln209_8" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_8_fu_236_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="36" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="p_088_0_i_reg_136" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="54" name="icmp_ln54_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="icmp_ln54_2_fu_263_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="54" name="i_3" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="i_3_fu_269_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="54" name="zext_ln54_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln54_2_fu_281_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="59" name="zext_ln59_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln59_2_fu_275_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="59" name="zext_ln700_19" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_19_fu_285_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="59" name="zext_ln700_20" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_20_fu_308_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="zext_ln700_21" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_21_fu_288_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="add_ln700_10" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln700_10_fu_292_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="59" name="zext_ln700_22" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_22_fu_311_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="60" name="tmp_V_7" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="tmp_V_7_fu_314_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="61" name="add_ln209_9" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_9_fu_298_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="61" name="add_ln209_10" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_10_fu_303_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="67" filename="multest.cc" linenumber="62" name="trunc_ln858_4" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="p_088_0_i3_reg_159" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="241" name="_ln241" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="grp_karastuba_mul_templa_5_fu_182" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="258" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="258" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="258" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="258" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="258" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="258" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="258" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="258" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="262" name="icmp_ln262" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln262_fu_540_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="262" name="i" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_fu_546_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="38" filename="multest.cc" linenumber="265" name="zext_ln265" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln265_fu_552_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="267" name="icmp_ln267" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln267_fu_557_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="267" name="i_11" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_11_fu_563_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="270" name="zext_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln270_fu_580_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="270" name="xor_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="xor_ln270_fu_569_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="6" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="270" name="zext_ln270_2" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln270_2_fu_575_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="272" name="icmp_ln272" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln272_fu_586_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="272" name="i_12" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_12_fu_592_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="275" name="zext_ln275" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln275_fu_598_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="277" name="icmp_ln277" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln277_fu_603_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="277" name="i_13" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_13_fu_609_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="280" name="zext_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln280_fu_626_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="107" filename="multest.cc" linenumber="280" name="xor_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="xor_ln280_fu_615_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="6" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="108" filename="multest.cc" linenumber="280" name="zext_ln280_2" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln280_2_fu_621_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="123" filename="multest.cc" linenumber="290" name="_ln290" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="grp_karastuba_mul_templa_5_fu_490" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="124" filename="multest.cc" linenumber="291" name="_ln291" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="grp_karastuba_mul_templa_5_fu_502" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="125" filename="multest.cc" linenumber="292" name="_ln292" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="grp_karastuba_mul_templa_1_fu_480" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="129" filename="multest.cc" linenumber="294" name="icmp_ln294" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln294_fu_647_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="131" filename="multest.cc" linenumber="294" name="i_14" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_14_fu_653_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="136" filename="multest.cc" linenumber="297" name="zext_ln297" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln297_fu_659_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="300" name="icmp_ln300" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln300_fu_667_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="150" filename="multest.cc" linenumber="300" name="i_15" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_15_fu_673_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="155" filename="multest.cc" linenumber="303" name="zext_ln303" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln303_fu_679_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="167" filename="multest.cc" linenumber="306" name="icmp_ln306" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="icmp_ln306_fu_687_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="169" filename="multest.cc" linenumber="306" name="i_16" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="i_16_fu_693_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="174" filename="multest.cc" linenumber="309" name="zext_ln309" contextFuncName="karastuba_mul_MUL_stage&lt;32, 64&gt;" moduleName="karastuba_mul_MUL_st.1" rtlName="zext_ln309_fu_699_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="168" name="icmp_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln168_fu_248_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="168" name="zext_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln168_fu_254_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="168" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_fu_259_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="170" name="icmp_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln170_fu_265_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="170" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_fu_271_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="170" name="zext_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln170_fu_277_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="175" name="icmp_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln175_fu_282_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="175" name="i_35" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_35_fu_288_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="175" name="zext_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln175_fu_310_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln180_fu_294_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="180" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_fu_314_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="181" name="zext_ln181" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln181_fu_299_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="180" name="zext_ln700_43" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_43_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="180" name="zext_ln700_44" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_44_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="180" name="tmp_V_35" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_35_fu_321_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="zext_ln700_45" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_45_fu_342_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="181" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_fu_345_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="182" name="add_ln209_19" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_19_fu_327_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="182" name="add_ln209_9" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_9_fu_333_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="183" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="p_0136_0_reg_174" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="184" name="j_8" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_8_fu_304_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="186" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln1468_fu_361_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="186" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln209_fu_365_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="186" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_fu_368_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="186" name="zext_ln209_3" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln209_3_fu_374_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="186" name="add_ln209_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_2_fu_377_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="81" filename="multest.cc" linenumber="191" name="icmp_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln191_fu_383_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="83" filename="multest.cc" linenumber="191" name="i_36" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_36_fu_389_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="86" filename="multest.cc" linenumber="191" name="zext_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln191_fu_411_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln196_fu_395_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="92" filename="multest.cc" linenumber="196" name="zext_ln700_46" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_46_fu_415_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="197" name="zext_ln197" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln197_fu_400_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="196" name="zext_ln700_47" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_47_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="196" name="zext_ln700_48" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_48_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="196" name="tmp_V_36" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_36_fu_422_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="zext_ln700_49" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_49_fu_443_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="197" name="tmp_V_34" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_34_fu_446_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="198" name="add_ln209_20" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_20_fu_428_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="198" name="add_ln209_10" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_10_fu_434_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="104" filename="multest.cc" linenumber="199" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="p_0136_2_reg_209" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="200" name="j_9" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_9_fu_405_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="325" name="add2_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="326" name="z1_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="327" name="p_res_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_res_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln54_fu_444_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="54" name="i_27" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="i_27_fu_450_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln54_fu_462_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln59_fu_456_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="36" filename="multest.cc" linenumber="60" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln209_fu_466_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="39" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_fu_489_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="59" name="zext_ln700_26" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_26_fu_469_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln700_fu_473_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="59" name="zext_ln700_27" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_27_fu_492_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="60" name="tmp_V_17" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_17_fu_495_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="61" name="add_ln209_14" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_14_fu_479_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="61" name="add_ln209_6" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_6_fu_484_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_088_0_i_reg_280" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="64" name="zext_ln64" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln64_fu_511_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="64" name="add_ln64" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln64_fu_515_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="64" name="add2_tmp_bits" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add2_tmp_bits_fu_520_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="78" name="exitcond_i" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="exitcond_i_fu_525_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="78" name="i_28" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="i_28_fu_531_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="81" name="zext_ln81" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln81_fu_537_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="69" filename="multest.cc" linenumber="81" name="zext_ln180" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln180_fu_543_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="82" name="zext_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln701_fu_546_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="82" name="tmp_V_18" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_18_fu_549_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="83" name="select_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="select_ln701_fu_555_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="83" name="select_ln701_2" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="select_ln701_2_fu_563_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="76" filename="multest.cc" linenumber="83" name="trunc_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="trunc_ln701_fu_571_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="83" name="tmp_V_19" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_19_fu_574_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="78" filename="multest.cc" linenumber="85" name="tmp_3" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_3_reg_946" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="88" name="add_ln700_21" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln700_21_fu_587_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="85" filename="multest.cc" linenumber="85" name="p_neg207_i" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_neg207_i_fu_593_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="86" filename="multest.cc" linenumber="96" name="add_ln96" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln96_fu_601_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="96" name="z1_tmp_bits" contextFuncName="sub_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="z1_tmp_bits_fu_606_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="88" filename="multest.cc" linenumber="331" name="_ln331" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="grp_CAT_I_I_I_O_1_fu_428" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="334" name="icmp_ln334" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln334_fu_612_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="20" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="338" name="icmp_ln338" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln338_fu_617_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="338" name="i" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="i_fu_623_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="338" name="zext_ln338" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln338_fu_645_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="341" name="zext_ln341" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln341_fu_629_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="108" filename="multest.cc" linenumber="341" name="zext_ln700_28" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_28_fu_649_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="109" filename="multest.cc" linenumber="342" name="zext_ln342" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln342_fu_634_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="112" filename="multest.cc" linenumber="341" name="zext_ln700_29" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_29_fu_673_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="113" filename="multest.cc" linenumber="341" name="zext_ln700_30" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_30_fu_652_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="114" filename="multest.cc" linenumber="341" name="tmp_V_23" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_23_fu_656_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="115" filename="multest.cc" linenumber="341" name="zext_ln700_31" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_31_fu_677_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="342" name="tmp_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_fu_680_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="343" name="add_ln209_15" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_15_fu_662_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="343" name="add_ln209" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_fu_668_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="344" name="trunc_ln858_6" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_0106_0_reg_326" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="122" filename="multest.cc" linenumber="338" name="j" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="j_fu_639_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="128" filename="multest.cc" linenumber="348" name="zext_ln348" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln348_fu_696_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="129" filename="multest.cc" linenumber="348" name="icmp_ln348" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln348_fu_700_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="20" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="137" filename="multest.cc" linenumber="352" name="icmp_ln352" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln352_fu_705_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="139" filename="multest.cc" linenumber="352" name="i_29" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="i_29_fu_711_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="352" name="zext_ln352" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln352_fu_733_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="145" filename="multest.cc" linenumber="355" name="zext_ln355" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln355_fu_717_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="355" name="zext_ln700_32" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_32_fu_737_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="149" filename="multest.cc" linenumber="356" name="zext_ln356" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln356_fu_722_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="152" filename="multest.cc" linenumber="355" name="zext_ln700_33" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_33_fu_761_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="153" filename="multest.cc" linenumber="355" name="zext_ln700_34" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_34_fu_740_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="154" filename="multest.cc" linenumber="355" name="tmp_V_24" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_24_fu_744_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="155" filename="multest.cc" linenumber="355" name="zext_ln700_35" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln700_35_fu_765_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="156" filename="multest.cc" linenumber="356" name="tmp_V_22" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="tmp_V_22_fu_768_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="157" filename="multest.cc" linenumber="357" name="add_ln209_16" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_16_fu_750_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="158" filename="multest.cc" linenumber="357" name="add_ln209_5" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="add_ln209_5_fu_756_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="160" filename="multest.cc" linenumber="358" name="trunc_ln858_7" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_0103_0_reg_373" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="162" filename="multest.cc" linenumber="352" name="j_5" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="j_5_fu_727_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="165" filename="multest.cc" linenumber="360" name="zext_ln360" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln360_fu_784_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="166" filename="multest.cc" linenumber="360" name="p_res_tmp_bits" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_res_tmp_bits_fu_788_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="170" filename="multest.cc" linenumber="362" name="zext_ln362" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln362_fu_797_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="171" filename="multest.cc" linenumber="362" name="mul_ln362" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="karastuba_mul_mulsc4_U80" latency="4" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="172" filename="multest.cc" linenumber="362" name="p_res_tmp_bits_3" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="p_res_tmp_bits_3_fu_801_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="39" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="176" filename="multest.cc" linenumber="364" name="icmp_ln364" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="icmp_ln364_fu_806_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="178" filename="multest.cc" linenumber="364" name="i_30" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="i_30_fu_812_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="183" filename="multest.cc" linenumber="367" name="zext_ln367" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;32, 64&gt;" moduleName="karastuba_mul_ADD_SU.1" rtlName="zext_ln367_fu_818_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="385" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="386" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="387" name="cross_mul_digits_dat" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="cross_mul_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="388" name="inter_lhs_digits_dat" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="inter_lhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="389" name="inter_rhs_digits_dat" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="inter_rhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="390" name="tmp" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="karastuba_mul_MUL_st_1_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="390" name="z0_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z0_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="390" name="z2_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z2_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="390" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="cross_mul_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="390" name="inter_lhs_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="inter_lhs_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="390" name="inter_rhs_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="inter_rhs_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="21" filename="multest.cc" linenumber="391" name="_ln391" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="karastuba_mul_ADD_SU_1_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="233" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="234" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="icmp_ln54_fu_196_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="54" name="i" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="i_fu_202_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln54_fu_214_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="21" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln59_fu_208_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_fu_218_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="59" name="zext_ln700_11" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_11_fu_241_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="zext_ln700_12" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_12_fu_221_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln700_fu_225_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="59" name="zext_ln700_13" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_13_fu_244_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="60" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="tmp_V_fu_247_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="61" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_fu_231_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="61" name="add_ln209_6" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_6_fu_236_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="36" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="p_088_0_i_reg_136" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="54" name="icmp_ln54_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="icmp_ln54_1_fu_263_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="54" name="i_4" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="i_4_fu_269_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="54" name="zext_ln54_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln54_1_fu_281_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="59" name="zext_ln59_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln59_1_fu_275_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="59" name="zext_ln700_14" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_14_fu_285_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="59" name="zext_ln700_15" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_15_fu_308_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="zext_ln700_16" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_16_fu_288_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="add_ln700_7" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln700_7_fu_292_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="59" name="zext_ln700_17" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_17_fu_311_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="60" name="tmp_V_8" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="tmp_V_8_fu_314_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="61" name="add_ln209_7" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_7_fu_298_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="61" name="add_ln209_8" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_8_fu_303_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="67" filename="multest.cc" linenumber="62" name="trunc_ln858_3" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="p_088_0_i3_reg_159" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="241" name="_ln241" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="grp_karastuba_mul_templa_4_fu_182" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="258" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="258" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="258" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="258" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="258" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="258" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="258" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="258" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="262" name="icmp_ln262" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln262_fu_514_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="262" name="i" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_fu_520_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="265" name="zext_ln265" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln265_fu_526_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="47" filename="multest.cc" linenumber="267" name="icmp_ln267" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln267_fu_531_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="267" name="i_17" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_17_fu_537_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="270" name="zext_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln270_fu_554_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="270" name="xor_ln270" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="xor_ln270_fu_543_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="270" name="zext_ln270_1" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln270_1_fu_549_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="272" name="icmp_ln272" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln272_fu_560_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="272" name="i_18" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_18_fu_566_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="78" filename="multest.cc" linenumber="275" name="zext_ln275" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln275_fu_572_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="277" name="icmp_ln277" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln277_fu_577_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="95" filename="multest.cc" linenumber="277" name="i_19" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_19_fu_583_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="280" name="zext_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln280_fu_600_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="280" name="xor_ln280" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="xor_ln280_fu_589_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="280" name="zext_ln280_1" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln280_1_fu_595_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="290" name="_ln290" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="grp_karastuba_mul_templa_4_fu_472" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="291" name="_ln291" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="grp_karastuba_mul_templa_4_fu_484" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="119" filename="multest.cc" linenumber="292" name="_ln292" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="grp_karastuba_mul_templa_fu_462" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="123" filename="multest.cc" linenumber="294" name="icmp_ln294" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln294_fu_621_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="125" filename="multest.cc" linenumber="294" name="i_20" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_20_fu_627_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="130" filename="multest.cc" linenumber="297" name="zext_ln297" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln297_fu_633_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="300" name="icmp_ln300" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln300_fu_641_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="144" filename="multest.cc" linenumber="300" name="i_21" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_21_fu_647_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="149" filename="multest.cc" linenumber="303" name="zext_ln303" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln303_fu_653_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="161" filename="multest.cc" linenumber="306" name="icmp_ln306" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="icmp_ln306_fu_661_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="163" filename="multest.cc" linenumber="306" name="i_22" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="i_22_fu_667_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="168" filename="multest.cc" linenumber="309" name="zext_ln309" contextFuncName="karastuba_mul_MUL_stage&lt;64, 64&gt;" moduleName="karastuba_mul_MUL_st" rtlName="zext_ln309_fu_673_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="168" name="icmp_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln168_fu_248_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="168" name="zext_ln168" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln168_fu_254_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="168" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_fu_259_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="170" name="icmp_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln170_fu_265_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="170" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_fu_271_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="170" name="zext_ln170" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln170_fu_277_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="40" filename="multest.cc" linenumber="175" name="icmp_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln175_fu_282_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="175" name="i_37" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_37_fu_288_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="175" name="zext_ln175" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln175_fu_310_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln180_fu_294_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="180" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_fu_314_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="181" name="zext_ln181" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln181_fu_299_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="55" filename="multest.cc" linenumber="180" name="zext_ln700_46" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_46_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="180" name="zext_ln700_47" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_47_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="180" name="tmp_V_40" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_40_fu_321_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="zext_ln700_48" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_48_fu_342_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="181" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_fu_345_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="182" name="add_ln209_21" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_21_fu_327_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="182" name="add_ln209_7" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_7_fu_333_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="183" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="p_0136_0_reg_174" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="184" name="j_10" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_10_fu_304_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="186" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln1468_fu_361_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="186" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln209_fu_365_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="186" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_fu_368_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="186" name="zext_ln209_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln209_2_fu_374_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="186" name="add_ln209_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_1_fu_377_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="81" filename="multest.cc" linenumber="191" name="icmp_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln191_fu_383_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="83" filename="multest.cc" linenumber="191" name="i_38" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_38_fu_389_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="86" filename="multest.cc" linenumber="191" name="zext_ln191" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln191_fu_411_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln196_fu_395_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="92" filename="multest.cc" linenumber="196" name="zext_ln700_49" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_49_fu_415_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="197" name="zext_ln197" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln197_fu_400_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="196" name="zext_ln700_50" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_50_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="196" name="zext_ln700_51" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_51_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="196" name="tmp_V_41" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_41_fu_422_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="zext_ln700_52" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_52_fu_443_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="197" name="tmp_V_39" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_39_fu_446_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="198" name="add_ln209_22" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_22_fu_428_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="198" name="add_ln209_8" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_8_fu_434_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="104" filename="multest.cc" linenumber="199" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="p_0136_2_reg_209" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="200" name="j_11" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_11_fu_405_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="325" name="add2_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="326" name="z1_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="327" name="p_res_digits_data_V" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="p_res_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="54" name="icmp_ln54" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="icmp_ln54_fu_271_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="54" name="i" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="i_fu_277_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="54" name="zext_ln54" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln54_fu_289_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="59" name="zext_ln59" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln59_fu_283_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="60" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln209_fu_293_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="59" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln700_fu_316_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="33" filename="multest.cc" linenumber="59" name="zext_ln700_16" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln700_16_fu_296_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="34" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln700_fu_300_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="59" name="zext_ln700_17" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln700_17_fu_319_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="36" filename="multest.cc" linenumber="60" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="tmp_V_fu_322_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="37" filename="multest.cc" linenumber="61" name="add_ln209_14" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln209_14_fu_306_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="38" filename="multest.cc" linenumber="61" name="add_ln209_5" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln209_5_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="62" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="p_088_0_i_reg_203" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="64" name="zext_ln64" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln64_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="64" name="add_ln64" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln64_fu_342_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="47" filename="multest.cc" linenumber="64" name="add2_tmp_bits" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add2_tmp_bits_fu_347_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="78" name="exitcond_i" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="exitcond_i_fu_352_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="78" name="i_31" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="i_31_fu_358_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="81" name="zext_ln81" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln81_fu_364_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="81" name="zext_ln180" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln180_fu_370_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="82" name="zext_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln701_fu_373_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="82" name="tmp_V_25" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="tmp_V_25_fu_376_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="67" filename="multest.cc" linenumber="83" name="select_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="select_ln701_fu_382_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="68" filename="multest.cc" linenumber="83" name="select_ln701_3" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="select_ln701_3_fu_390_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="69" filename="multest.cc" linenumber="83" name="trunc_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="trunc_ln701_fu_398_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="83" name="tmp_V_26" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="tmp_V_26_fu_401_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="85" name="tmp" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="tmp_reg_567" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="88" name="add_ln700_15" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln700_15_fu_414_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="78" filename="multest.cc" linenumber="85" name="p_neg207_i" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="p_neg207_i_fu_420_p3" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="2" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="96" name="add_ln96" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="add_ln96_fu_428_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="80" filename="multest.cc" linenumber="96" name="z1_tmp_bits" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_ADD_SU" rtlName="z1_tmp_bits_fu_433_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="32" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="81" filename="multest.cc" linenumber="331" name="_ln331" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="grp_CAT_I_I_I_O_fu_260" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="85" filename="multest.cc" linenumber="364" name="icmp_ln364" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="icmp_ln364_fu_439_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="364" name="i_32" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="i_32_fu_445_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="92" filename="multest.cc" linenumber="367" name="zext_ln367" contextFuncName="karastuba_mul_ADD_SUB_CAT_stage&lt;64, 64&gt;" moduleName="karastuba_mul_ADD_SU" rtlName="zext_ln367_fu_451_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="5" filename="multest.cc" linenumber="385" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="386" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="387" name="cross_mul_digits_dat" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="cross_mul_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="388" name="inter_lhs_digits_dat" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="inter_lhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="389" name="inter_rhs_digits_dat" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="inter_rhs_digits_dat_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="390" name="call_ret" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="karastuba_mul_MUL_st_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="390" name="z0_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z0_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="390" name="z2_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z2_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="390" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="cross_mul_tmp_bits_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="391" name="_ln391" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="karastuba_mul_ADD_SU_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="425" name="icmp_ln425" contextFuncName="karastuba_mul" moduleName="Loop_2_proc" rtlName="icmp_ln425_fu_74_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="425" name="i" contextFuncName="karastuba_mul" moduleName="Loop_2_proc" rtlName="i_fu_80_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="428" name="zext_ln428" contextFuncName="karastuba_mul" moduleName="Loop_2_proc" rtlName="zext_ln428_fu_86_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="423" name="_ln423" contextFuncName="karastuba_mul" moduleName="karastuba_mul" rtlName="karastuba_mul_templa_3_U0" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation_dataflow"><\/item>
</annotationInfo>
