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.triton/dump/0359b089f02b5ddabaef8985c60f3daf/triton_.ttgir

@@ -0,0 +1,21 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<12865792> : tensor<1024xi32, #blocked>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked>
+    %5 = arith.cmpi slt, %4, %cst : tensor<1024xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked>
+    %7 = tt.addptr %6, %4 : tensor<1024x!tt.ptr<f32, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %8 = tt.load %7, %5 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xf32, #blocked>
+    %9 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %10 = tt.addptr %9, %4 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %11 = arith.truncf %8 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked>
+    tt.store %10, %11, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/0ef13ec90cf21db4d33a072ff09ec2d4/triton_.ptx

@@ -0,0 +1,734 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7de8
+
+.visible .entry triton__0d1d2d3d4d5d6d7de8(
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_7,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_8
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<49>;
+	.reg .b16 	%rs<33>;
+	.reg .b32 	%r<72>;
+	.reg .f32 	%f<98>;
+	.reg .b64 	%rd<66>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd17, [triton__0d1d2d3d4d5d6d7de8_param_6];
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7de8_param_5];
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6d7de8_param_4];
+	ld.param.u64 	%rd28, [triton__0d1d2d3d4d5d6d7de8_param_0];
+	ld.param.u64 	%rd29, [triton__0d1d2d3d4d5d6d7de8_param_1];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r13, %tid.x;
+	ld.param.u64 	%rd26, [triton__0d1d2d3d4d5d6d7de8_param_2];
+	bfe.u32 	%r14, %r13, 3, 4;
+	ld.param.u64 	%rd27, [triton__0d1d2d3d4d5d6d7de8_param_3];
+	.loc	1 24 33
+	and.b32  	%r1, %r13, 7;
+	.loc	1 21 28
+	mov.u32 %r6, %ctaid.x;
+	.loc	1 21 34
+	cvt.s64.s32 	%rd1, %r6;
+	.loc	1 21 46
+	mul.wide.s32 	%rd30, %r6, 64;
+	cvt.u64.u32 	%rd2, %r14;
+	.loc	1 22 23
+	or.b64  	%rd31, %rd30, %rd2;
+	.loc	1 26 30
+	shl.b64 	%rd32, %rd31, 3;
+	add.s64 	%rd19, %rd29, %rd32;
+	add.s64 	%rd21, %rd19, 128;
+	add.s64 	%rd23, %rd19, 256;
+	add.s64 	%rd25, %rd19, 384;
+	mov.pred 	%p1, -1;
+	.loc	1 26 35
+	mov.u64 %rd18, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd18 }, [ %rd19 + 0 ];
+	mov.u64 %rd20, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd20 }, [ %rd21 + 0 ];
+	mov.u64 %rd22, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd22 }, [ %rd23 + 0 ];
+	mov.u64 %rd24, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd24 }, [ %rd25 + 0 ];
+	.loc	1 27 19
+	mov.u32 %r10, 0x0;
+	@%p1 ld.global.b32 { %r10 }, [ %rd26 + 0 ];
+	.loc	1 29 19
+	mov.u32 %r11, 0x0;
+	@%p1 ld.global.b32 { %r11 }, [ %rd27 + 0 ];
+	.loc	1 38 23
+	setp.eq.s64 	%p7, %rd18, -1;
+	setp.eq.s64 	%p8, %rd20, -1;
+	setp.eq.s64 	%p9, %rd22, -1;
+	setp.eq.s64 	%p10, %rd24, -1;
+	.loc	1 39 22
+	div.full.f32 %r9, %r10, %r11;
+	mov.b32 	%f25, %r9;
+	.loc	1 41 37
+	selp.f32 	%f4, 0f00000000, %f25, %p10;
+	selp.f32 	%f3, 0f00000000, %f25, %p9;
+	selp.f32 	%f2, 0f00000000, %f25, %p8;
+	selp.f32 	%f1, 0f00000000, %f25, %p7;
+	.loc	1 32 36
+	mul.wide.s32 	%rd33, %r6, 12865792;
+	mul.wide.u32 	%rd34, %r14, 201028;
+	add.s64 	%rd35, %rd33, %rd34;
+	cvt.u64.u32 	%rd36, %r13;
+	and.b64  	%rd3, %rd36, 7;
+	mul.wide.u32 	%rd37, %r1, 4;
+	add.s64 	%rd38, %rd35, %rd37;
+	add.s64 	%rd39, %rd38, %rd28;
+	add.s64 	%rd65, %rd39, 9649344;
+	mov.f32 	%f94, 0f00000000;
+	mov.b32 	%r70, -8;
+	mov.u64 	%rd63, %rd65;
+	mov.f32 	%f95, %f94;
+	mov.f32 	%f96, %f94;
+	mov.f32 	%f97, %f94;
+$L__BB0_1:
+	add.s32 	%r70, %r70, 8;
+	.loc	1 33 27
+	add.s32 	%r23, %r70, %r1;
+	.loc	1 34 25
+	setp.lt.u32 	%p11, %r23, 50257;
+	.loc	1 36 34
+	add.s64 	%rd40, %rd63, -9649344;
+	add.s64 	%rd41, %rd63, -6432896;
+	add.s64 	%rd42, %rd63, -3216448;
+	mov.b32 	%r54, 0;
+	.loc	1 36 52
+	mov.u32 %r15, 0x0;
+	@%p11 ld.global.L1::evict_last.b32 { %r15 }, [ %rd40 + 0 ];
+	@!%p11 mov.u32 %r15, %r54;
+	mov.u32 %r17, 0x0;
+	@%p11 ld.global.L1::evict_last.b32 { %r17 }, [ %rd41 + 0 ];
+	@!%p11 mov.u32 %r17, %r54;
+	mov.u32 %r19, 0x0;
+	@%p11 ld.global.L1::evict_last.b32 { %r19 }, [ %rd42 + 0 ];
+	@!%p11 mov.u32 %r19, %r54;
+	mov.u32 %r21, 0x0;
+	@%p11 ld.global.L1::evict_last.b32 { %r21 }, [ %rd63 + 0 ];
+	@!%p11 mov.u32 %r21, %r54;
+	mov.b32 	%f26, %r21;
+	mov.b32 	%f27, %r19;
+	mov.b32 	%f28, %r17;
+	mov.b32 	%f29, %r15;
+	.loc	1 42 23
+	mul.f32 	%f30, %f1, %f29;
+	mul.f32 	%f31, %f2, %f28;
+	mul.f32 	%f32, %f3, %f27;
+	mul.f32 	%f33, %f4, %f26;
+	.loc	1 45 40
+	selp.f32 	%f34, %f33, 0f80000000, %p11;
+	selp.f32 	%f35, %f32, 0f80000000, %p11;
+	selp.f32 	%f36, %f31, 0f80000000, %p11;
+	selp.f32 	%f37, %f30, 0f80000000, %p11;
+	add.f32 	%f94, %f94, %f37;
+	add.f32 	%f95, %f95, %f36;
+	add.f32 	%f96, %f96, %f35;
+	add.f32 	%f97, %f97, %f34;
+	.loc	1 32 36
+	add.s64 	%rd63, %rd63, 32;
+	setp.lt.u32 	%p19, %r70, 50249;
+	@%p19 bra 	$L__BB0_1;
+$L__tmp1:
+	.loc	2 243 36
+	mov.b32 	%r25, %f94;
+	shfl.sync.bfly.b32	%r26, %r25, 4, 31, -1;
+	mov.b32 	%f38, %r26;
+$L__tmp2:
+	.loc	2 233 15
+	add.f32 	%f39, %f94, %f38;
+$L__tmp3:
+	.loc	2 243 36
+	mov.b32 	%r27, %f39;
+	shfl.sync.bfly.b32	%r28, %r27, 2, 31, -1;
+	mov.b32 	%f40, %r28;
+$L__tmp4:
+	.loc	2 233 15
+	add.f32 	%f41, %f39, %f40;
+$L__tmp5:
+	.loc	2 243 36
+	mov.b32 	%r29, %f41;
+	shfl.sync.bfly.b32	%r30, %r29, 1, 31, -1;
+	mov.b32 	%f42, %r30;
+$L__tmp6:
+	.loc	2 233 15
+	add.f32 	%f13, %f41, %f42;
+$L__tmp7:
+	.loc	2 243 36
+	mov.b32 	%r31, %f95;
+	shfl.sync.bfly.b32	%r32, %r31, 4, 31, -1;
+	mov.b32 	%f43, %r32;
+$L__tmp8:
+	.loc	2 233 15
+	add.f32 	%f44, %f95, %f43;
+$L__tmp9:
+	.loc	2 243 36
+	mov.b32 	%r33, %f44;
+	shfl.sync.bfly.b32	%r34, %r33, 2, 31, -1;
+	mov.b32 	%f45, %r34;
+$L__tmp10:
+	.loc	2 233 15
+	add.f32 	%f46, %f44, %f45;
+$L__tmp11:
+	.loc	2 243 36
+	mov.b32 	%r35, %f46;
+	shfl.sync.bfly.b32	%r36, %r35, 1, 31, -1;
+	mov.b32 	%f47, %r36;
+$L__tmp12:
+	.loc	2 233 15
+	add.f32 	%f14, %f46, %f47;
+$L__tmp13:
+	.loc	2 243 36
+	mov.b32 	%r37, %f96;
+	shfl.sync.bfly.b32	%r38, %r37, 4, 31, -1;
+	mov.b32 	%f48, %r38;
+$L__tmp14:
+	.loc	2 233 15
+	add.f32 	%f49, %f96, %f48;
+$L__tmp15:
+	.loc	2 243 36
+	mov.b32 	%r39, %f49;
+	shfl.sync.bfly.b32	%r40, %r39, 2, 31, -1;
+	mov.b32 	%f50, %r40;
+$L__tmp16:
+	.loc	2 233 15
+	add.f32 	%f51, %f49, %f50;
+$L__tmp17:
+	.loc	2 243 36
+	mov.b32 	%r41, %f51;
+	shfl.sync.bfly.b32	%r42, %r41, 1, 31, -1;
+	mov.b32 	%f52, %r42;
+$L__tmp18:
+	.loc	2 233 15
+	add.f32 	%f15, %f51, %f52;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r43, %f97;
+	shfl.sync.bfly.b32	%r44, %r43, 4, 31, -1;
+	mov.b32 	%f53, %r44;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f54, %f97, %f53;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r45, %f54;
+	shfl.sync.bfly.b32	%r46, %r45, 2, 31, -1;
+	mov.b32 	%f55, %r46;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f56, %f54, %f55;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r47, %f56;
+	shfl.sync.bfly.b32	%r48, %r47, 1, 31, -1;
+	mov.b32 	%f57, %r48;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f16, %f56, %f57;
+$L__tmp25:
+	.loc	1 51 36
+	shl.b64 	%rd44, %rd3, 1;
+	add.s64 	%rd7, %rd17, %rd44;
+	mul.lo.s64 	%rd45, %rd1, 6432896;
+	mul.lo.s64 	%rd46, %rd2, 100514;
+	add.s64 	%rd64, %rd45, %rd46;
+	add.s64 	%rd9, %rd16, %rd44;
+	add.s64 	%rd10, %rd15, %rd44;
+	mov.b32 	%r71, -8;
+	mov.u16 	%rs2, 0;
+$L__BB0_3:
+	add.s32 	%r71, %r71, 8;
+	.loc	1 52 27
+	add.s32 	%r69, %r71, %r1;
+	.loc	1 53 25
+	setp.lt.u32 	%p20, %r69, 50257;
+	.loc	1 55 35
+	add.s64 	%rd47, %rd10, %rd64;
+	add.s64 	%rd48, %rd47, 1608224;
+	add.s64 	%rd49, %rd47, 3216448;
+	.loc	1 55 53
+	add.s64 	%rd50, %rd47, 4824672;
+	mov.u16 %rs1, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs1 }, [ %rd47 + 0 ];
+	@!%p20 mov.u16 %rs1, %rs2;
+	mov.u16 %rs3, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs3 }, [ %rd48 + 0 ];
+	@!%p20 mov.u16 %rs3, %rs2;
+	mov.u16 %rs5, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs5 }, [ %rd49 + 0 ];
+	@!%p20 mov.u16 %rs5, %rs2;
+	mov.u16 %rs7, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs7 }, [ %rd50 + 0 ];
+	@!%p20 mov.u16 %rs7, %rs2;
+	.loc	1 55 105
+	cvt.f32.bf16 %r49, %rs1;
+	mov.b32 	%f66, %r49;
+	cvt.f32.bf16 %r50, %rs3;
+	mov.b32 	%f67, %r50;
+	cvt.f32.bf16 %r51, %rs5;
+	mov.b32 	%f68, %r51;
+	cvt.f32.bf16 %r52, %rs7;
+	mov.b32 	%f69, %r52;
+	.loc	1 56 35
+	add.s64 	%rd51, %rd65, -9649344;
+	add.s64 	%rd52, %rd65, -6432896;
+	add.s64 	%rd53, %rd65, -3216448;
+	.loc	1 56 53
+	mov.u32 %r53, 0x0;
+	@%p20 ld.global.L1::evict_first.b32 { %r53 }, [ %rd51 + 0 ];
+	@!%p20 mov.u32 %r53, %r54;
+	mov.b32 	%f70, %r53;
+	mov.u32 %r55, 0x0;
+	@%p20 ld.global.L1::evict_first.b32 { %r55 }, [ %rd52 + 0 ];
+	@!%p20 mov.u32 %r55, %r54;
+	mov.b32 	%f71, %r55;
+	mov.u32 %r57, 0x0;
+	@%p20 ld.global.L1::evict_first.b32 { %r57 }, [ %rd53 + 0 ];
+	@!%p20 mov.u32 %r57, %r54;
+	mov.b32 	%f72, %r57;
+	mov.u32 %r59, 0x0;
+	@%p20 ld.global.L1::evict_first.b32 { %r59 }, [ %rd65 + 0 ];
+	@!%p20 mov.u32 %r59, %r54;
+	mov.b32 	%f73, %r59;
+	.loc	1 57 35
+	add.s64 	%rd55, %rd9, %rd64;
+	add.s64 	%rd56, %rd55, 1608224;
+	add.s64 	%rd57, %rd55, 3216448;
+	.loc	1 57 53
+	add.s64 	%rd58, %rd55, 4824672;
+	mov.u16 %rs13, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs13 }, [ %rd55 + 0 ];
+	@!%p20 mov.u16 %rs13, %rs2;
+	mov.u16 %rs15, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs15 }, [ %rd56 + 0 ];
+	@!%p20 mov.u16 %rs15, %rs2;
+	mov.u16 %rs17, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs17 }, [ %rd57 + 0 ];
+	@!%p20 mov.u16 %rs17, %rs2;
+	mov.u16 %rs19, 0x0;
+	@%p20 ld.global.L1::evict_first.b16 { %rs19 }, [ %rd58 + 0 ];
+	@!%p20 mov.u16 %rs19, %rs2;
+	.loc	1 57 105
+	cvt.f32.bf16 %r61, %rs13;
+	mov.b32 	%f74, %r61;
+	cvt.f32.bf16 %r62, %rs15;
+	mov.b32 	%f75, %r62;
+	cvt.f32.bf16 %r63, %rs17;
+	mov.b32 	%f76, %r63;
+	cvt.f32.bf16 %r64, %rs19;
+	mov.b32 	%f77, %r64;
+	.loc	1 65 23
+	mul.f32 	%f59, %f74, 0f3FB8AA3B;
+	ex2.approx.f32 %f58, %f59;
+	mul.f32 	%f61, %f75, 0f3FB8AA3B;
+	ex2.approx.f32 %f60, %f61;
+	mul.f32 	%f63, %f76, 0f3FB8AA3B;
+	ex2.approx.f32 %f62, %f63;
+	mul.f32 	%f65, %f77, 0f3FB8AA3B;
+	ex2.approx.f32 %f64, %f65;
+	.loc	1 66 24
+	mul.f32 	%f78, %f13, %f58;
+	mul.f32 	%f79, %f14, %f60;
+	mul.f32 	%f80, %f15, %f62;
+	mul.f32 	%f81, %f16, %f64;
+	.loc	1 67 24
+	neg.f32 	%f82, %f78;
+	fma.rn.f32 	%f83, %f1, %f70, %f82;
+	neg.f32 	%f84, %f79;
+	fma.rn.f32 	%f85, %f2, %f71, %f84;
+	neg.f32 	%f86, %f80;
+	fma.rn.f32 	%f87, %f3, %f72, %f86;
+	neg.f32 	%f88, %f81;
+	fma.rn.f32 	%f89, %f4, %f73, %f88;
+	.loc	1 69 24
+	add.f32 	%f90, %f66, %f83;
+	add.f32 	%f91, %f67, %f85;
+	add.f32 	%f92, %f68, %f87;
+	add.f32 	%f93, %f69, %f89;
+	.loc	1 70 29
+	add.s64 	%rd59, %rd7, %rd64;
+	add.s64 	%rd60, %rd59, 1608224;
+	add.s64 	%rd61, %rd59, 3216448;
+	.loc	1 70 54
+	add.s64 	%rd62, %rd59, 4824672;
+	mov.b32 	%r65, %f90;
+	cvt.rn.bf16.f32 %rs25, %r65;
+	mov.b32 	%r66, %f91;
+	cvt.rn.bf16.f32 %rs26, %r66;
+	mov.b32 	%r67, %f92;
+	cvt.rn.bf16.f32 %rs27, %r67;
+	mov.b32 	%r68, %f93;
+	cvt.rn.bf16.f32 %rs28, %r68;
+	@%p20 st.global.b16 [ %rd59 + 0 ], { %rs25 };
+	@%p20 st.global.b16 [ %rd60 + 0 ], { %rs26 };
+	@%p20 st.global.b16 [ %rd61 + 0 ], { %rs27 };
+	@%p20 st.global.b16 [ %rd62 + 0 ], { %rs28 };
+	.loc	1 51 36
+	add.s64 	%rd65, %rd65, 32;
+	add.s64 	%rd64, %rd64, 16;
+	setp.lt.u32 	%p48, %r71, 50249;
+	@%p48 bra 	$L__BB0_3;
+	.loc	1 51 4
+	ret;
+$L__tmp26:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/kz/ckzgl7thb4xdfkfnd2tidks6mt5f3hauwfyjflbtzyepo5oxkvhk.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
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+.b8 87
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+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 278
+.b8 2
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+.b32 .debug_abbrev
+.b8 8
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+.b32 .debug_line
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+.b8 116
+.b8 47
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+.b8 122
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
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+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp24
+.b8 2
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+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp25
+.b8 2
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+.b8 4
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp25
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
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+.b8 110
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+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/199215289adb100508718a5a762ba4d7/triton_.llir

@@ -0,0 +1,184 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
+@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
+@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp7 < 50257"
+@global_smem = external local_unnamed_addr addrspace(3) global [0 x i8]
+
+declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr
+
+define void @triton__0d1d2de(ptr addrspace(1) %0, ptr addrspace(1) %1, i64 %2) local_unnamed_addr !dbg !7 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %5 = and i32 %4, 127, !dbg !10
+  %6 = shl nuw nsw i32 %5, 1, !dbg !10
+  %7 = or i32 %6, 1, !dbg !10
+  %8 = or i32 %6, 256, !dbg !10
+  %9 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #2, !dbg !11
+  %10 = sext i32 %9 to i64, !dbg !12
+  %11 = shl nsw i64 %10, 9, !dbg !13
+  %12 = zext nneg i32 %6 to i64
+  %13 = zext nneg i32 %8 to i64
+  %14 = or i64 %11, %12, !dbg !14
+  %15 = or i64 %11, %13, !dbg !14
+  %16 = getelementptr i64, ptr addrspace(1) %0, i64 %14, !dbg !15
+  %17 = getelementptr i64, ptr addrspace(1) %0, i64 %15, !dbg !15
+  %18 = tail call { i64, i64 } asm sideeffect "mov.u64 $0, 0x0;\0A\09mov.u64 $1, 0x0;\0A\09@$3 ld.global.v2.b64 { $0, $1 }, [ $2 + 0 ];", "=l,=l,l,b"(ptr addrspace(1) %16, i1 true) #2, !dbg !16
+  %19 = extractvalue { i64, i64 } %18, 0, !dbg !16
+  %20 = extractvalue { i64, i64 } %18, 1, !dbg !16
+  %21 = tail call { i64, i64 } asm sideeffect "mov.u64 $0, 0x0;\0A\09mov.u64 $1, 0x0;\0A\09@$3 ld.global.v2.b64 { $0, $1 }, [ $2 + 0 ];", "=l,=l,l,b"(ptr addrspace(1) %17, i1 true) #2, !dbg !16
+  %22 = extractvalue { i64, i64 } %21, 0, !dbg !16
+  %23 = extractvalue { i64, i64 } %21, 1, !dbg !16
+  %24 = insertelement <4 x i64> poison, i64 %23, i64 0, !dbg !17
+  %25 = insertelement <4 x i64> %24, i64 %22, i64 1, !dbg !17
+  %26 = insertelement <4 x i64> %25, i64 %20, i64 2, !dbg !17
+  %27 = insertelement <4 x i64> %26, i64 %19, i64 3, !dbg !17
+  %28 = icmp eq <4 x i64> %27, <i64 -1, i64 -1, i64 -1, i64 -1>, !dbg !17
+  %29 = select <4 x i1> %28, <4 x i64> zeroinitializer, <4 x i64> %27, !dbg !18
+  %30 = add <4 x i64> %29, <i64 50257, i64 50257, i64 50257, i64 50257>, !dbg !19
+  %31 = icmp slt <4 x i64> %29, zeroinitializer, !dbg !20
+  %32 = select <4 x i1> %31, <4 x i64> %30, <4 x i64> %29, !dbg !21
+  %33 = icmp ult <4 x i64> %32, <i64 50257, i64 50257, i64 50257, i64 50257>, !dbg !22
+  %34 = getelementptr i8, ptr addrspace(3) @global_smem, i64 %12, !dbg !22
+  %35 = extractelement <4 x i1> %33, i64 3, !dbg !22
+  %36 = zext i1 %35 to i8, !dbg !22
+  %37 = insertelement <1 x i8> undef, i8 %36, i64 0, !dbg !22
+  store <1 x i8> %37, ptr addrspace(3) %34, align 1, !dbg !22
+  %38 = zext nneg i32 %7 to i64, !dbg !22
+  %39 = getelementptr i8, ptr addrspace(3) @global_smem, i64 %38, !dbg !22
+  %40 = extractelement <4 x i1> %33, i64 2, !dbg !22
+  %41 = zext i1 %40 to i8, !dbg !22
+  %42 = insertelement <1 x i8> undef, i8 %41, i64 0, !dbg !22
+  store <1 x i8> %42, ptr addrspace(3) %39, align 1, !dbg !22
+  tail call void @llvm.nvvm.barrier0(), !dbg !22
+  %43 = zext nneg i32 %5 to i64, !dbg !22
+  %44 = getelementptr i8, ptr addrspace(3) @global_smem, i64 %43, !dbg !22
+  %45 = load i8, ptr addrspace(3) %44, align 1, !dbg !22
+  %46 = or i32 %5, 128, !dbg !22
+  %47 = zext nneg i32 %46 to i64, !dbg !22
+  %48 = getelementptr i8, ptr addrspace(3) @global_smem, i64 %47, !dbg !22
+  %49 = load i8, ptr addrspace(3) %48, align 1, !dbg !22
+  tail call void @llvm.nvvm.barrier0(), !dbg !22
+  %50 = extractelement <4 x i1> %33, i64 1, !dbg !22
+  %51 = zext i1 %50 to i8, !dbg !22
+  %52 = insertelement <1 x i8> undef, i8 %51, i64 0, !dbg !22
+  store <1 x i8> %52, ptr addrspace(3) %34, align 1, !dbg !22
+  %53 = extractelement <4 x i1> %33, i64 0, !dbg !22
+  %54 = zext i1 %53 to i8, !dbg !22
+  %55 = insertelement <1 x i8> undef, i8 %54, i64 0, !dbg !22
+  store <1 x i8> %55, ptr addrspace(3) %39, align 1, !dbg !22
+  tail call void @llvm.nvvm.barrier0(), !dbg !22
+  %56 = load i8, ptr addrspace(3) %44, align 1, !dbg !22
+  %57 = load i8, ptr addrspace(3) %48, align 1, !dbg !22
+  %58 = insertelement <4 x i8> poison, i8 %49, i64 0, !dbg !22
+  %59 = insertelement <4 x i8> %58, i8 %45, i64 1, !dbg !22
+  %60 = insertelement <4 x i8> %59, i8 %56, i64 2, !dbg !22
+  %61 = insertelement <4 x i8> %60, i8 %57, i64 3, !dbg !22
+  %62 = icmp eq <4 x i8> %61, zeroinitializer, !dbg !22
+  %63 = bitcast <4 x i1> %62 to i4, !dbg !23
+  %.not = icmp eq i4 %63, 0, !dbg !23
+  br i1 %.not, label %65, label %64, !dbg !23
+
+64:                                               ; preds = %3
+  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !23
+  br label %65, !dbg !23
+
+65:                                               ; preds = %64, %3
+  %66 = or i32 %6, 257, !dbg !10
+  %67 = zext nneg i32 %66 to i64
+  %68 = or i64 %11, %67, !dbg !14
+  %69 = or i64 %11, %38, !dbg !14
+  %70 = mul nsw i64 %14, 50257, !dbg !24
+  %71 = mul nsw i64 %69, 50257, !dbg !24
+  %72 = mul nsw i64 %15, 50257, !dbg !24
+  %73 = mul nsw i64 %68, 50257, !dbg !24
+  %74 = extractelement <4 x i64> %32, i64 3, !dbg !25
+  %75 = getelementptr float, ptr addrspace(1) %1, i64 %74, !dbg !25
+  %76 = getelementptr float, ptr addrspace(1) %75, i64 %70, !dbg !25
+  %77 = extractelement <4 x i64> %32, i64 2, !dbg !25
+  %78 = getelementptr float, ptr addrspace(1) %1, i64 %77, !dbg !25
+  %79 = getelementptr float, ptr addrspace(1) %78, i64 %71, !dbg !25
+  %80 = extractelement <4 x i64> %32, i64 1, !dbg !25
+  %81 = getelementptr float, ptr addrspace(1) %1, i64 %80, !dbg !25
+  %82 = getelementptr float, ptr addrspace(1) %81, i64 %72, !dbg !25
+  %83 = extractelement <4 x i64> %32, i64 0, !dbg !25
+  %84 = getelementptr float, ptr addrspace(1) %1, i64 %83, !dbg !25
+  %85 = getelementptr float, ptr addrspace(1) %84, i64 %73, !dbg !25
+  tail call void @llvm.nvvm.barrier0(), !dbg !26
+  %86 = getelementptr i64, ptr addrspace(3) @global_smem, i64 %12, !dbg !26
+  %87 = ptrtoint ptr addrspace(1) %76 to i64, !dbg !26
+  %88 = insertelement <1 x i64> undef, i64 %87, i64 0, !dbg !26
+  store <1 x i64> %88, ptr addrspace(3) %86, align 8, !dbg !26
+  %89 = getelementptr i64, ptr addrspace(3) @global_smem, i64 %38, !dbg !26
+  %90 = ptrtoint ptr addrspace(1) %79 to i64, !dbg !26
+  %91 = insertelement <1 x i64> undef, i64 %90, i64 0, !dbg !26
+  store <1 x i64> %91, ptr addrspace(3) %89, align 8, !dbg !26
+  tail call void @llvm.nvvm.barrier0(), !dbg !26
+  %92 = getelementptr i64, ptr addrspace(3) @global_smem, i64 %43, !dbg !26
+  %93 = load i64, ptr addrspace(3) %92, align 8, !dbg !26
+  %94 = inttoptr i64 %93 to ptr addrspace(1), !dbg !26
+  %95 = getelementptr i64, ptr addrspace(3) @global_smem, i64 %47, !dbg !26
+  %96 = load i64, ptr addrspace(3) %95, align 8, !dbg !26
+  %97 = inttoptr i64 %96 to ptr addrspace(1), !dbg !26
+  tail call void @llvm.nvvm.barrier0(), !dbg !26
+  %98 = ptrtoint ptr addrspace(1) %82 to i64, !dbg !26
+  %99 = insertelement <1 x i64> undef, i64 %98, i64 0, !dbg !26
+  store <1 x i64> %99, ptr addrspace(3) %86, align 8, !dbg !26
+  %100 = ptrtoint ptr addrspace(1) %85 to i64, !dbg !26
+  %101 = insertelement <1 x i64> undef, i64 %100, i64 0, !dbg !26
+  store <1 x i64> %101, ptr addrspace(3) %89, align 8, !dbg !26
+  tail call void @llvm.nvvm.barrier0(), !dbg !26
+  %102 = load i64, ptr addrspace(3) %92, align 8, !dbg !26
+  %103 = inttoptr i64 %102 to ptr addrspace(1), !dbg !26
+  %104 = load i64, ptr addrspace(3) %95, align 8, !dbg !26
+  %105 = inttoptr i64 %104 to ptr addrspace(1), !dbg !26
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 -1082130432, ptr addrspace(1) %94, i1 true) #2, !dbg !26
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 -1082130432, ptr addrspace(1) %97, i1 true) #2, !dbg !26
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 -1082130432, ptr addrspace(1) %103, i1 true) #2, !dbg !26
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 -1082130432, ptr addrspace(1) %105, i1 true) #2, !dbg !26
+  ret void, !dbg !27
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #1
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind }
+attributes #2 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "chlrkgpvvbdizdz7sllquet2j7zhtes6meh6kenrqxov26mswvw7.py", directory: "/tmp/torchinductor_root/hl")
+!4 = !{ptr @triton__0d1d2de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2de, !"maxntidx", i32 128}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2de", linkageName: "triton__0d1d2de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 21, column: 36, scope: !7)
+!11 = !DILocation(line: 20, column: 28, scope: !7)
+!12 = !DILocation(line: 20, column: 34, scope: !7)
+!13 = !DILocation(line: 20, column: 46, scope: !7)
+!14 = !DILocation(line: 21, column: 23, scope: !7)
+!15 = !DILocation(line: 24, column: 30, scope: !7)
+!16 = !DILocation(line: 24, column: 35, scope: !7)
+!17 = !DILocation(line: 26, column: 19, scope: !7)
+!18 = !DILocation(line: 28, column: 32, scope: !7)
+!19 = !DILocation(line: 29, column: 18, scope: !7)
+!20 = !DILocation(line: 30, column: 18, scope: !7)
+!21 = !DILocation(line: 31, column: 32, scope: !7)
+!22 = !DILocation(line: 32, column: 36, scope: !7)
+!23 = !DILocation(line: 32, column: 51, scope: !7)
+!24 = !DILocation(line: 34, column: 39, scope: !7)
+!25 = !DILocation(line: 34, column: 25, scope: !7)
+!26 = !DILocation(line: 34, column: 51, scope: !7)
+!27 = !DILocation(line: 34, column: 4, scope: !7)

.triton/dump/199215289adb100508718a5a762ba4d7/triton_.ttgir

@@ -0,0 +1,38 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i64 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<50257> : tensor<512xi64, #blocked>
+    %cst_0 = arith.constant dense<0> : tensor<512xi64, #blocked>
+    %cst_1 = arith.constant dense<-1> : tensor<512xi64, #blocked>
+    %cst_2 = arith.constant dense<-1.000000e+00> : tensor<512xf32, #blocked1>
+    %c512_i64 = arith.constant 512 : i64
+    %0 = tt.get_program_id x : i32
+    %1 = arith.extsi %0 : i32 to i64
+    %2 = arith.muli %1, %c512_i64 : i64
+    %3 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked>
+    %4 = arith.extsi %3 : tensor<512xi32, #blocked> to tensor<512xi64, #blocked>
+    %5 = tt.splat %2 : (i64) -> tensor<512xi64, #blocked>
+    %6 = arith.addi %5, %4 : tensor<512xi64, #blocked>
+    %7 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<512x!tt.ptr<i64, 1>, #blocked>
+    %8 = tt.addptr %7, %6 : tensor<512x!tt.ptr<i64, 1>, #blocked>, tensor<512xi64, #blocked>
+    %9 = tt.load %8 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xi64, #blocked>
+    %10 = arith.cmpi ne, %9, %cst_1 : tensor<512xi64, #blocked>
+    %11 = arith.select %10, %9, %cst_0 : tensor<512xi1, #blocked>, tensor<512xi64, #blocked>
+    %12 = arith.addi %11, %cst : tensor<512xi64, #blocked>
+    %13 = arith.cmpi slt, %11, %cst_0 : tensor<512xi64, #blocked>
+    %14 = arith.select %13, %12, %11 : tensor<512xi1, #blocked>, tensor<512xi64, #blocked>
+    %15 = arith.cmpi sge, %14, %cst_0 : tensor<512xi64, #blocked>
+    %16 = arith.cmpi slt, %14, %cst : tensor<512xi64, #blocked>
+    %17 = arith.andi %15, %16 : tensor<512xi1, #blocked>
+    %18 = triton_gpu.convert_layout %17 : (tensor<512xi1, #blocked>) -> tensor<512xi1, #blocked1>
+    tt.assert %18, "index out of bounds: 0 <= tmp7 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<512xi1, #blocked1>
+    %19 = arith.muli %6, %cst : tensor<512xi64, #blocked>
+    %20 = arith.addi %14, %19 : tensor<512xi64, #blocked>
+    %21 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>, #blocked>
+    %22 = tt.addptr %21, %20 : tensor<512x!tt.ptr<f32, 1>, #blocked>, tensor<512xi64, #blocked>
+    %23 = triton_gpu.convert_layout %22 : (tensor<512x!tt.ptr<f32, 1>, #blocked>) -> tensor<512x!tt.ptr<f32, 1>, #blocked1>
+    tt.store %23, %cst_2 {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/199215289adb100508718a5a762ba4d7/triton_.ttir

@@ -0,0 +1,34 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i64 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<50257> : tensor<512xi64>
+    %cst_0 = arith.constant dense<0> : tensor<512xi64>
+    %c512_i64 = arith.constant 512 : i64
+    %cst_1 = arith.constant dense<-1.000000e+00> : tensor<512xf32>
+    %cst_2 = arith.constant dense<-1> : tensor<512xi64>
+    %0 = tt.get_program_id x : i32
+    %1 = arith.extsi %0 : i32 to i64
+    %2 = arith.muli %1, %c512_i64 : i64
+    %3 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32>
+    %4 = arith.extsi %3 : tensor<512xi32> to tensor<512xi64>
+    %5 = tt.splat %2 : (i64) -> tensor<512xi64>
+    %6 = arith.addi %5, %4 : tensor<512xi64>
+    %7 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<512x!tt.ptr<i64, 1>>
+    %8 = tt.addptr %7, %6 : tensor<512x!tt.ptr<i64, 1>>, tensor<512xi64>
+    %9 = tt.load %8 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xi64>
+    %10 = arith.cmpi ne, %9, %cst_2 : tensor<512xi64>
+    %11 = arith.select %10, %9, %cst_0 : tensor<512xi1>, tensor<512xi64>
+    %12 = arith.addi %11, %cst : tensor<512xi64>
+    %13 = arith.cmpi slt, %11, %cst_0 : tensor<512xi64>
+    %14 = arith.select %13, %12, %11 : tensor<512xi1>, tensor<512xi64>
+    %15 = arith.cmpi sge, %14, %cst_0 : tensor<512xi64>
+    %16 = arith.cmpi slt, %14, %cst : tensor<512xi64>
+    %17 = arith.andi %15, %16 : tensor<512xi1>
+    tt.assert %17, "index out of bounds: 0 <= tmp7 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<512xi1>
+    %18 = arith.muli %6, %cst : tensor<512xi64>
+    %19 = arith.addi %14, %18 : tensor<512xi64>
+    %20 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>>
+    %21 = tt.addptr %20, %19 : tensor<512x!tt.ptr<f32, 1>>, tensor<512xi64>
+    tt.store %21, %cst_1 {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32>
+    tt.return
+  }
+}

.triton/dump/1c14bdb6903aa6825e214bbdf57fd077/triton_.ttgir

@@ -0,0 +1,19 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<1024xi32, #blocked>
+    %5 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<f32, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xf32, #blocked>
+    %8 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %9 = tt.addptr %8, %4 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %10 = arith.truncf %7 : tensor<1024xf32, #blocked> to tensor<1024xbf16, #blocked>
+    tt.store %9, %10 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/246118bec10f09cdce32d0be7c22b5ae/triton_.ttgir

@@ -0,0 +1,18 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i64 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<512xf32, #blocked>
+    %c512_i64 = arith.constant 512 : i64
+    %0 = tt.get_program_id x : i32
+    %1 = arith.extsi %0 : i32 to i64
+    %2 = arith.muli %1, %c512_i64 : i64
+    %3 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked>
+    %4 = arith.extsi %3 : tensor<512xi32, #blocked> to tensor<512xi64, #blocked>
+    %5 = tt.splat %2 : (i64) -> tensor<512xi64, #blocked>
+    %6 = arith.addi %5, %4 : tensor<512xi64, #blocked>
+    %7 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>, #blocked>
+    %8 = tt.addptr %7, %6 : tensor<512x!tt.ptr<f32, 1>, #blocked>, tensor<512xi64, #blocked>
+    tt.store %8, %cst {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/24a29ccba6fa75ba50c8f1e68f7098d8/triton_.ptx

@@ -0,0 +1,525 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7de8
+
+.visible .entry triton__0d1d2d3d4d5d6d7de8(
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_7,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_8
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<16>;
+	.reg .b16 	%rs<9>;
+	.reg .b32 	%r<31>;
+	.reg .f32 	%f<23>;
+	.reg .b64 	%rd<51>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd20, [triton__0d1d2d3d4d5d6d7de8_param_6];
+	ld.param.u64 	%rd19, [triton__0d1d2d3d4d5d6d7de8_param_5];
+	ld.param.u64 	%rd18, [triton__0d1d2d3d4d5d6d7de8_param_4];
+	ld.param.u64 	%rd25, [triton__0d1d2d3d4d5d6d7de8_param_0];
+	ld.param.u64 	%rd26, [triton__0d1d2d3d4d5d6d7de8_param_1];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r13, %tid.x;
+	ld.param.u64 	%rd23, [triton__0d1d2d3d4d5d6d7de8_param_2];
+	bfe.u32 	%r14, %r13, 2, 6;
+	ld.param.u64 	%rd24, [triton__0d1d2d3d4d5d6d7de8_param_3];
+	.loc	1 24 33
+	and.b32  	%r1, %r13, 3;
+	.loc	1 21 28
+	mov.u32 %r6, %ctaid.x;
+	.loc	1 21 34
+	cvt.s64.s32 	%rd1, %r6;
+	.loc	1 21 46
+	mul.wide.s32 	%rd27, %r6, 64;
+	cvt.u64.u32 	%rd2, %r14;
+	.loc	1 22 23
+	or.b64  	%rd28, %rd27, %rd2;
+	.loc	1 26 30
+	shl.b64 	%rd29, %rd28, 3;
+	add.s64 	%rd22, %rd26, %rd29;
+	mov.pred 	%p1, -1;
+	.loc	1 26 35
+	mov.u64 %rd21, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd21 }, [ %rd22 + 0 ];
+	.loc	1 27 19
+	mov.u32 %r10, 0x0;
+	@%p1 ld.global.b32 { %r10 }, [ %rd23 + 0 ];
+	.loc	1 29 19
+	mov.u32 %r11, 0x0;
+	@%p1 ld.global.b32 { %r11 }, [ %rd24 + 0 ];
+	.loc	1 38 23
+	setp.eq.s64 	%p4, %rd21, -1;
+	.loc	1 39 22
+	div.full.f32 %r9, %r10, %r11;
+	mov.b32 	%f6, %r9;
+	.loc	1 41 37
+	selp.f32 	%f1, 0f00000000, %f6, %p4;
+	.loc	1 32 36
+	mul.wide.s32 	%rd30, %r6, 12865792;
+	mul.wide.u32 	%rd31, %r14, 201028;
+	add.s64 	%rd32, %rd30, %rd31;
+	cvt.u64.u32 	%rd33, %r13;
+	and.b64  	%rd3, %rd33, 3;
+	mul.wide.u32 	%rd34, %r1, 4;
+	add.s64 	%rd35, %rd32, %rd34;
+	add.s64 	%rd50, %rd25, %rd35;
+	mov.f32 	%f22, 0f00000000;
+	mov.b32 	%r29, -4;
+	mov.u64 	%rd46, %rd50;
+$L__BB0_1:
+	add.s32 	%r29, %r29, 4;
+	.loc	1 33 27
+	add.s32 	%r17, %r29, %r1;
+	.loc	1 34 25
+	setp.lt.u32 	%p5, %r17, 50257;
+	mov.b32 	%r16, 0;
+	.loc	1 36 52
+	mov.u32 %r15, 0x0;
+	@%p5 ld.global.L1::evict_last.b32 { %r15 }, [ %rd46 + 0 ];
+	@!%p5 mov.u32 %r15, %r16;
+	mov.b32 	%f7, %r15;
+	.loc	1 42 23
+	mul.f32 	%f8, %f1, %f7;
+	.loc	1 45 40
+	selp.f32 	%f9, %f8, 0f80000000, %p5;
+	add.f32 	%f22, %f22, %f9;
+	.loc	1 32 36
+	add.s64 	%rd46, %rd46, 16;
+	setp.lt.u32 	%p7, %r29, 50253;
+	@%p7 bra 	$L__BB0_1;
+$L__tmp1:
+	.loc	2 243 36
+	mov.b32 	%r19, %f22;
+	shfl.sync.bfly.b32	%r20, %r19, 2, 31, -1;
+	mov.b32 	%f10, %r20;
+$L__tmp2:
+	.loc	2 233 15
+	add.f32 	%f11, %f22, %f10;
+$L__tmp3:
+	.loc	2 243 36
+	mov.b32 	%r21, %f11;
+	shfl.sync.bfly.b32	%r22, %r21, 1, 31, -1;
+	mov.b32 	%f12, %r22;
+$L__tmp4:
+	.loc	2 233 15
+	add.f32 	%f4, %f11, %f12;
+$L__tmp5:
+	.loc	1 51 36
+	mul.lo.s64 	%rd37, %rd1, 3216448;
+	mul.lo.s64 	%rd38, %rd2, 50257;
+	add.s64 	%rd39, %rd37, %rd38;
+	add.s64 	%rd40, %rd39, %rd3;
+	shl.b64 	%rd41, %rd40, 1;
+	add.s64 	%rd49, %rd20, %rd41;
+	add.s64 	%rd48, %rd19, %rd41;
+	add.s64 	%rd47, %rd18, %rd41;
+	mov.b32 	%r30, -4;
+	mov.u16 	%rs2, 0;
+$L__BB0_3:
+	add.s32 	%r30, %r30, 4;
+	.loc	1 52 27
+	add.s32 	%r28, %r30, %r1;
+	.loc	1 53 25
+	setp.lt.u32 	%p8, %r28, 50257;
+	.loc	1 55 53
+	mov.u16 %rs1, 0x0;
+	@%p8 ld.global.L1::evict_first.b16 { %rs1 }, [ %rd47 + 0 ];
+	@!%p8 mov.u16 %rs1, %rs2;
+	.loc	1 55 105
+	cvt.f32.bf16 %r23, %rs1;
+	mov.b32 	%f15, %r23;
+	.loc	1 56 53
+	mov.u32 %r24, 0x0;
+	@%p8 ld.global.L1::evict_first.b32 { %r24 }, [ %rd50 + 0 ];
+	@!%p8 mov.u32 %r24, %r16;
+	mov.b32 	%f16, %r24;
+	.loc	1 57 53
+	mov.u16 %rs4, 0x0;
+	@%p8 ld.global.L1::evict_first.b16 { %rs4 }, [ %rd48 + 0 ];
+	@!%p8 mov.u16 %rs4, %rs2;
+	.loc	1 57 105
+	cvt.f32.bf16 %r26, %rs4;
+	mov.b32 	%f17, %r26;
+	.loc	1 65 23
+	mul.f32 	%f14, %f17, 0f3FB8AA3B;
+	ex2.approx.f32 %f13, %f14;
+	.loc	1 66 24
+	mul.f32 	%f18, %f4, %f13;
+	.loc	1 67 24
+	neg.f32 	%f19, %f18;
+	fma.rn.f32 	%f20, %f1, %f16, %f19;
+	.loc	1 69 24
+	add.f32 	%f21, %f15, %f20;
+	.loc	1 70 54
+	mov.b32 	%r27, %f21;
+	cvt.rn.bf16.f32 %rs7, %r27;
+	@%p8 st.global.b16 [ %rd49 + 0 ], { %rs7 };
+	.loc	1 51 36
+	add.s64 	%rd50, %rd50, 16;
+	add.s64 	%rd49, %rd49, 8;
+	add.s64 	%rd48, %rd48, 8;
+	add.s64 	%rd47, %rd47, 8;
+	setp.lt.u32 	%p15, %r30, 50253;
+	@%p15 bra 	$L__BB0_3;
+	.loc	1 51 4
+	ret;
+$L__tmp6:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/kz/ckzgl7thb4xdfkfnd2tidks6mt5f3hauwfyjflbtzyepo5oxkvhk.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
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+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 278
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+.b8 0
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+.b64 $L__func_end0
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+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp4
+.b8 2
+.b8 46
+.b8 27
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp5
+.b8 2
+.b8 46
+.b8 27
+.b8 4
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp5
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/294d626e055d1f63037cabf3cda4f2ac/triton_.ttgir

@@ -0,0 +1,24 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked1>
+    %4 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %5 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked1>
+    %6 = arith.addi %4, %2 : tensor<1024xi32, #blocked>
+    %7 = arith.addi %5, %3 : tensor<1024xi32, #blocked1>
+    %8 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %9 = tt.addptr %8, %6 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %10 = tt.load %9 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %11 = triton_gpu.convert_layout %10 : (tensor<1024xbf16, #blocked>) -> tensor<1024xbf16, #blocked1>
+    %12 = arith.extf %11 : tensor<1024xbf16, #blocked1> to tensor<1024xf32, #blocked1>
+    %13 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked1>
+    %14 = tt.addptr %13, %7 : tensor<1024x!tt.ptr<f32, 1>, #blocked1>, tensor<1024xi32, #blocked1>
+    tt.store %14, %12 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/33dcd7dc40e8b1089e9a4c61a9c826b5/triton_.llir

@@ -0,0 +1,793 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3d4d5d6d7de8(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, i64 %7, i64 %8) local_unnamed_addr !dbg !5 {
+  %10 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %11 = lshr i32 %10, 5, !dbg !8
+  %urem = and i32 %10, 255, !dbg !9
+  %12 = or i32 %urem, 256, !dbg !9
+  %13 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !10
+  %14 = sext i32 %13 to i64, !dbg !11
+  %15 = shl nsw i64 %14, 3, !dbg !12
+  %16 = or i64 %15, 1, !dbg !13
+  %17 = or i64 %15, 2, !dbg !13
+  %18 = or i64 %15, 3, !dbg !13
+  %19 = or i64 %15, 4, !dbg !13
+  %20 = or i64 %15, 5, !dbg !13
+  %21 = or i64 %15, 6, !dbg !13
+  %22 = or i64 %15, 7, !dbg !13
+  %23 = insertelement <2 x i32> poison, i32 %urem, i64 0
+  %24 = insertelement <2 x i32> %23, i32 %12, i64 1
+  %25 = zext nneg <2 x i32> %24 to <2 x i64>
+  %26 = getelementptr i64, ptr addrspace(1) %1, i64 %15, !dbg !14
+  %27 = getelementptr i64, ptr addrspace(1) %1, i64 %16, !dbg !14
+  %28 = getelementptr i64, ptr addrspace(1) %1, i64 %17, !dbg !14
+  %29 = getelementptr i64, ptr addrspace(1) %1, i64 %18, !dbg !14
+  %30 = getelementptr i64, ptr addrspace(1) %1, i64 %19, !dbg !14
+  %31 = getelementptr i64, ptr addrspace(1) %1, i64 %20, !dbg !14
+  %32 = getelementptr i64, ptr addrspace(1) %1, i64 %21, !dbg !14
+  %33 = getelementptr i64, ptr addrspace(1) %1, i64 %22, !dbg !14
+  %34 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %26, i1 true) #3, !dbg !15
+  %35 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %27, i1 true) #3, !dbg !15
+  %36 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %28, i1 true) #3, !dbg !15
+  %37 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %29, i1 true) #3, !dbg !15
+  %38 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %30, i1 true) #3, !dbg !15
+  %39 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %31, i1 true) #3, !dbg !15
+  %40 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %32, i1 true) #3, !dbg !15
+  %41 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %33, i1 true) #3, !dbg !15
+  %42 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %2, i1 true) #3, !dbg !16
+  %43 = bitcast i32 %42 to float, !dbg !16
+  %44 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %3, i1 true) #3, !dbg !17
+  %45 = bitcast i32 %44 to float, !dbg !17
+  %46 = mul nsw i64 %14, 402056, !dbg !18
+  %47 = mul nsw i64 %16, 50257, !dbg !18
+  %48 = mul nsw i64 %17, 50257, !dbg !18
+  %49 = mul nsw i64 %18, 50257, !dbg !18
+  %50 = mul nsw i64 %19, 50257, !dbg !18
+  %51 = mul nsw i64 %20, 50257, !dbg !18
+  %52 = mul nsw i64 %21, 50257, !dbg !18
+  %53 = mul nsw i64 %22, 50257, !dbg !18
+  %54 = insertelement <8 x i64> poison, i64 %34, i64 0, !dbg !19
+  %55 = insertelement <8 x i64> %54, i64 %35, i64 1, !dbg !19
+  %56 = insertelement <8 x i64> %55, i64 %36, i64 2, !dbg !19
+  %57 = insertelement <8 x i64> %56, i64 %37, i64 3, !dbg !19
+  %58 = insertelement <8 x i64> %57, i64 %38, i64 4, !dbg !19
+  %59 = insertelement <8 x i64> %58, i64 %39, i64 5, !dbg !19
+  %60 = insertelement <8 x i64> %59, i64 %40, i64 6, !dbg !19
+  %61 = insertelement <8 x i64> %60, i64 %41, i64 7, !dbg !19
+  %62 = icmp eq <8 x i64> %61, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, !dbg !19
+  %63 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %43, float %45) #3, !dbg !20
+  %64 = insertelement <8 x float> poison, float %63, i64 0, !dbg !21
+  %65 = shufflevector <8 x float> %64, <8 x float> poison, <8 x i32> zeroinitializer, !dbg !21
+  %66 = select <8 x i1> %62, <8 x float> zeroinitializer, <8 x float> %65, !dbg !21
+  %67 = shufflevector <8 x float> %66, <8 x float> poison, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>, !dbg !21
+  br label %68, !dbg !22
+
+68:                                               ; preds = %9, %68
+  %69 = phi i32 [ 0, %9 ], [ %135, %68 ]
+  %70 = phi <16 x float> [ zeroinitializer, %9 ], [ %134, %68 ]
+  %71 = zext nneg i32 %69 to i64, !dbg !23
+  %72 = insertelement <2 x i64> poison, i64 %71, i64 0, !dbg !23
+  %73 = shufflevector <2 x i64> %72, <2 x i64> poison, <2 x i32> zeroinitializer, !dbg !23
+  %74 = or <2 x i64> %73, %25, !dbg !23
+  %75 = icmp ult <2 x i64> %74, <i64 50257, i64 50257>, !dbg !24
+  %76 = shufflevector <2 x i1> %75, <2 x i1> poison, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>, !dbg !24
+  %77 = extractelement <2 x i64> %74, i64 0, !dbg !25
+  %78 = getelementptr float, ptr addrspace(1) %0, i64 %77, !dbg !25
+  %79 = getelementptr float, ptr addrspace(1) %78, i64 %46, !dbg !25
+  %80 = extractelement <2 x i64> %74, i64 1, !dbg !25
+  %81 = getelementptr float, ptr addrspace(1) %0, i64 %80, !dbg !25
+  %82 = getelementptr float, ptr addrspace(1) %81, i64 %46, !dbg !25
+  %83 = getelementptr float, ptr addrspace(1) %78, i64 %47, !dbg !25
+  %84 = getelementptr float, ptr addrspace(1) %81, i64 %47, !dbg !25
+  %85 = getelementptr float, ptr addrspace(1) %78, i64 %48, !dbg !25
+  %86 = getelementptr float, ptr addrspace(1) %81, i64 %48, !dbg !25
+  %87 = getelementptr float, ptr addrspace(1) %78, i64 %49, !dbg !25
+  %88 = getelementptr float, ptr addrspace(1) %81, i64 %49, !dbg !25
+  %89 = getelementptr float, ptr addrspace(1) %78, i64 %50, !dbg !25
+  %90 = getelementptr float, ptr addrspace(1) %81, i64 %50, !dbg !25
+  %91 = getelementptr float, ptr addrspace(1) %78, i64 %51, !dbg !25
+  %92 = getelementptr float, ptr addrspace(1) %81, i64 %51, !dbg !25
+  %93 = getelementptr float, ptr addrspace(1) %78, i64 %52, !dbg !25
+  %94 = getelementptr float, ptr addrspace(1) %81, i64 %52, !dbg !25
+  %95 = getelementptr float, ptr addrspace(1) %78, i64 %53, !dbg !25
+  %96 = getelementptr float, ptr addrspace(1) %81, i64 %53, !dbg !25
+  %97 = extractelement <2 x i1> %75, i64 0, !dbg !26
+  %98 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %79, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %99 = extractelement <2 x i1> %75, i64 1, !dbg !26
+  %100 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %82, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %101 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %83, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %102 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %84, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %103 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %85, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %104 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %86, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %105 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %87, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %106 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %88, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %107 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %89, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %108 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %90, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %109 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %91, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %110 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %92, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %111 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %93, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %112 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %94, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %113 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %95, i1 %97, i32 0, i1 %97) #3, !dbg !26
+  %114 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %96, i1 %99, i32 0, i1 %99) #3, !dbg !26
+  %115 = insertelement <16 x i32> poison, i32 %98, i64 0, !dbg !26
+  %116 = insertelement <16 x i32> %115, i32 %100, i64 1, !dbg !26
+  %117 = insertelement <16 x i32> %116, i32 %101, i64 2, !dbg !26
+  %118 = insertelement <16 x i32> %117, i32 %102, i64 3, !dbg !26
+  %119 = insertelement <16 x i32> %118, i32 %103, i64 4, !dbg !26
+  %120 = insertelement <16 x i32> %119, i32 %104, i64 5, !dbg !26
+  %121 = insertelement <16 x i32> %120, i32 %105, i64 6, !dbg !26
+  %122 = insertelement <16 x i32> %121, i32 %106, i64 7, !dbg !26
+  %123 = insertelement <16 x i32> %122, i32 %107, i64 8, !dbg !26
+  %124 = insertelement <16 x i32> %123, i32 %108, i64 9, !dbg !26
+  %125 = insertelement <16 x i32> %124, i32 %109, i64 10, !dbg !26
+  %126 = insertelement <16 x i32> %125, i32 %110, i64 11, !dbg !26
+  %127 = insertelement <16 x i32> %126, i32 %111, i64 12, !dbg !26
+  %128 = insertelement <16 x i32> %127, i32 %112, i64 13, !dbg !26
+  %129 = insertelement <16 x i32> %128, i32 %113, i64 14, !dbg !26
+  %130 = insertelement <16 x i32> %129, i32 %114, i64 15, !dbg !26
+  %131 = bitcast <16 x i32> %130 to <16 x float>, !dbg !26
+  %132 = fmul <16 x float> %67, %131, !dbg !27
+  %133 = select <16 x i1> %76, <16 x float> %132, <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, !dbg !28
+  %134 = fadd <16 x float> %70, %133, !dbg !28
+  %135 = add nuw nsw i32 %69, 512, !dbg !22
+  %136 = icmp ult i32 %69, 49745, !dbg !22
+  br i1 %136, label %68, label %137, !dbg !22
+
+137:                                              ; preds = %68
+  %138 = and i32 %10, 31, !dbg !8
+  %139 = and i32 %11, 7, !dbg !9
+  %shift = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %140 = fadd <16 x float> %134, %shift, !dbg !29
+  %141 = extractelement <16 x float> %140, i64 0, !dbg !29
+  %shift54 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %142 = fadd <16 x float> %134, %shift54, !dbg !29
+  %143 = extractelement <16 x float> %142, i64 2, !dbg !29
+  %shift55 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %144 = fadd <16 x float> %134, %shift55, !dbg !29
+  %145 = extractelement <16 x float> %144, i64 4, !dbg !29
+  %shift56 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %146 = fadd <16 x float> %134, %shift56, !dbg !29
+  %147 = extractelement <16 x float> %146, i64 6, !dbg !29
+  %shift57 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %148 = fadd <16 x float> %134, %shift57, !dbg !29
+  %149 = extractelement <16 x float> %148, i64 8, !dbg !29
+  %shift58 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %150 = fadd <16 x float> %134, %shift58, !dbg !29
+  %151 = extractelement <16 x float> %150, i64 10, !dbg !29
+  %shift59 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 13, i32 poison, i32 poison, i32 poison>, !dbg !29
+  %152 = fadd <16 x float> %134, %shift59, !dbg !29
+  %153 = extractelement <16 x float> %152, i64 12, !dbg !29
+  %shift60 = shufflevector <16 x float> %134, <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 15, i32 poison>, !dbg !29
+  %154 = fadd <16 x float> %134, %shift60, !dbg !29
+  %155 = extractelement <16 x float> %154, i64 14, !dbg !29
+  %156 = bitcast float %141 to i32, !dbg !35
+  %157 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %156, i32 16, i32 31), !dbg !35
+  %158 = bitcast i32 %157 to float, !dbg !35
+  %159 = fadd float %141, %158, !dbg !29
+  %160 = bitcast float %159 to i32, !dbg !35
+  %161 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %160, i32 8, i32 31), !dbg !35
+  %162 = bitcast i32 %161 to float, !dbg !35
+  %163 = fadd float %159, %162, !dbg !29
+  %164 = bitcast float %163 to i32, !dbg !35
+  %165 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %164, i32 4, i32 31), !dbg !35
+  %166 = bitcast i32 %165 to float, !dbg !35
+  %167 = fadd float %163, %166, !dbg !29
+  %168 = bitcast float %167 to i32, !dbg !35
+  %169 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %168, i32 2, i32 31), !dbg !35
+  %170 = bitcast i32 %169 to float, !dbg !35
+  %171 = fadd float %167, %170, !dbg !29
+  %172 = bitcast float %171 to i32, !dbg !35
+  %173 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %172, i32 1, i32 31), !dbg !35
+  %174 = bitcast i32 %173 to float, !dbg !35
+  %175 = fadd float %171, %174, !dbg !29
+  %176 = bitcast float %143 to i32, !dbg !35
+  %177 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %176, i32 16, i32 31), !dbg !35
+  %178 = bitcast i32 %177 to float, !dbg !35
+  %179 = fadd float %143, %178, !dbg !29
+  %180 = bitcast float %179 to i32, !dbg !35
+  %181 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %180, i32 8, i32 31), !dbg !35
+  %182 = bitcast i32 %181 to float, !dbg !35
+  %183 = fadd float %179, %182, !dbg !29
+  %184 = bitcast float %183 to i32, !dbg !35
+  %185 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %184, i32 4, i32 31), !dbg !35
+  %186 = bitcast i32 %185 to float, !dbg !35
+  %187 = fadd float %183, %186, !dbg !29
+  %188 = bitcast float %187 to i32, !dbg !35
+  %189 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %188, i32 2, i32 31), !dbg !35
+  %190 = bitcast i32 %189 to float, !dbg !35
+  %191 = fadd float %187, %190, !dbg !29
+  %192 = bitcast float %191 to i32, !dbg !35
+  %193 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %192, i32 1, i32 31), !dbg !35
+  %194 = bitcast i32 %193 to float, !dbg !35
+  %195 = fadd float %191, %194, !dbg !29
+  %196 = bitcast float %145 to i32, !dbg !35
+  %197 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %196, i32 16, i32 31), !dbg !35
+  %198 = bitcast i32 %197 to float, !dbg !35
+  %199 = fadd float %145, %198, !dbg !29
+  %200 = bitcast float %199 to i32, !dbg !35
+  %201 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %200, i32 8, i32 31), !dbg !35
+  %202 = bitcast i32 %201 to float, !dbg !35
+  %203 = fadd float %199, %202, !dbg !29
+  %204 = bitcast float %203 to i32, !dbg !35
+  %205 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %204, i32 4, i32 31), !dbg !35
+  %206 = bitcast i32 %205 to float, !dbg !35
+  %207 = fadd float %203, %206, !dbg !29
+  %208 = bitcast float %207 to i32, !dbg !35
+  %209 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %208, i32 2, i32 31), !dbg !35
+  %210 = bitcast i32 %209 to float, !dbg !35
+  %211 = fadd float %207, %210, !dbg !29
+  %212 = bitcast float %211 to i32, !dbg !35
+  %213 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %212, i32 1, i32 31), !dbg !35
+  %214 = bitcast i32 %213 to float, !dbg !35
+  %215 = fadd float %211, %214, !dbg !29
+  %216 = bitcast float %147 to i32, !dbg !35
+  %217 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %216, i32 16, i32 31), !dbg !35
+  %218 = bitcast i32 %217 to float, !dbg !35
+  %219 = fadd float %147, %218, !dbg !29
+  %220 = bitcast float %219 to i32, !dbg !35
+  %221 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %220, i32 8, i32 31), !dbg !35
+  %222 = bitcast i32 %221 to float, !dbg !35
+  %223 = fadd float %219, %222, !dbg !29
+  %224 = bitcast float %223 to i32, !dbg !35
+  %225 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %224, i32 4, i32 31), !dbg !35
+  %226 = bitcast i32 %225 to float, !dbg !35
+  %227 = fadd float %223, %226, !dbg !29
+  %228 = bitcast float %227 to i32, !dbg !35
+  %229 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %228, i32 2, i32 31), !dbg !35
+  %230 = bitcast i32 %229 to float, !dbg !35
+  %231 = fadd float %227, %230, !dbg !29
+  %232 = bitcast float %231 to i32, !dbg !35
+  %233 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %232, i32 1, i32 31), !dbg !35
+  %234 = bitcast i32 %233 to float, !dbg !35
+  %235 = fadd float %231, %234, !dbg !29
+  %236 = bitcast float %149 to i32, !dbg !35
+  %237 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %236, i32 16, i32 31), !dbg !35
+  %238 = bitcast i32 %237 to float, !dbg !35
+  %239 = fadd float %149, %238, !dbg !29
+  %240 = bitcast float %239 to i32, !dbg !35
+  %241 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %240, i32 8, i32 31), !dbg !35
+  %242 = bitcast i32 %241 to float, !dbg !35
+  %243 = fadd float %239, %242, !dbg !29
+  %244 = bitcast float %243 to i32, !dbg !35
+  %245 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %244, i32 4, i32 31), !dbg !35
+  %246 = bitcast i32 %245 to float, !dbg !35
+  %247 = fadd float %243, %246, !dbg !29
+  %248 = bitcast float %247 to i32, !dbg !35
+  %249 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %248, i32 2, i32 31), !dbg !35
+  %250 = bitcast i32 %249 to float, !dbg !35
+  %251 = fadd float %247, %250, !dbg !29
+  %252 = bitcast float %251 to i32, !dbg !35
+  %253 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %252, i32 1, i32 31), !dbg !35
+  %254 = bitcast i32 %253 to float, !dbg !35
+  %255 = fadd float %251, %254, !dbg !29
+  %256 = bitcast float %151 to i32, !dbg !35
+  %257 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %256, i32 16, i32 31), !dbg !35
+  %258 = bitcast i32 %257 to float, !dbg !35
+  %259 = fadd float %151, %258, !dbg !29
+  %260 = bitcast float %259 to i32, !dbg !35
+  %261 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %260, i32 8, i32 31), !dbg !35
+  %262 = bitcast i32 %261 to float, !dbg !35
+  %263 = fadd float %259, %262, !dbg !29
+  %264 = bitcast float %263 to i32, !dbg !35
+  %265 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %264, i32 4, i32 31), !dbg !35
+  %266 = bitcast i32 %265 to float, !dbg !35
+  %267 = fadd float %263, %266, !dbg !29
+  %268 = bitcast float %267 to i32, !dbg !35
+  %269 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %268, i32 2, i32 31), !dbg !35
+  %270 = bitcast i32 %269 to float, !dbg !35
+  %271 = fadd float %267, %270, !dbg !29
+  %272 = bitcast float %271 to i32, !dbg !35
+  %273 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %272, i32 1, i32 31), !dbg !35
+  %274 = bitcast i32 %273 to float, !dbg !35
+  %275 = fadd float %271, %274, !dbg !29
+  %276 = bitcast float %153 to i32, !dbg !35
+  %277 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %276, i32 16, i32 31), !dbg !35
+  %278 = bitcast i32 %277 to float, !dbg !35
+  %279 = fadd float %153, %278, !dbg !29
+  %280 = bitcast float %279 to i32, !dbg !35
+  %281 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %280, i32 8, i32 31), !dbg !35
+  %282 = bitcast i32 %281 to float, !dbg !35
+  %283 = fadd float %279, %282, !dbg !29
+  %284 = bitcast float %283 to i32, !dbg !35
+  %285 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %284, i32 4, i32 31), !dbg !35
+  %286 = bitcast i32 %285 to float, !dbg !35
+  %287 = fadd float %283, %286, !dbg !29
+  %288 = bitcast float %287 to i32, !dbg !35
+  %289 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %288, i32 2, i32 31), !dbg !35
+  %290 = bitcast i32 %289 to float, !dbg !35
+  %291 = fadd float %287, %290, !dbg !29
+  %292 = bitcast float %291 to i32, !dbg !35
+  %293 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %292, i32 1, i32 31), !dbg !35
+  %294 = bitcast i32 %293 to float, !dbg !35
+  %295 = fadd float %291, %294, !dbg !29
+  %296 = bitcast float %155 to i32, !dbg !35
+  %297 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %296, i32 16, i32 31), !dbg !35
+  %298 = bitcast i32 %297 to float, !dbg !35
+  %299 = fadd float %155, %298, !dbg !29
+  %300 = bitcast float %299 to i32, !dbg !35
+  %301 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %300, i32 8, i32 31), !dbg !35
+  %302 = bitcast i32 %301 to float, !dbg !35
+  %303 = fadd float %299, %302, !dbg !29
+  %304 = bitcast float %303 to i32, !dbg !35
+  %305 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %304, i32 4, i32 31), !dbg !35
+  %306 = bitcast i32 %305 to float, !dbg !35
+  %307 = fadd float %303, %306, !dbg !29
+  %308 = bitcast float %307 to i32, !dbg !35
+  %309 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %308, i32 2, i32 31), !dbg !35
+  %310 = bitcast i32 %309 to float, !dbg !35
+  %311 = fadd float %307, %310, !dbg !29
+  %312 = bitcast float %311 to i32, !dbg !35
+  %313 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %312, i32 1, i32 31), !dbg !35
+  %314 = bitcast i32 %313 to float, !dbg !35
+  %315 = fadd float %311, %314, !dbg !29
+  %316 = icmp eq i32 %138, 0, !dbg !35
+  %317 = zext nneg i32 %139 to i64, !dbg !35
+  %318 = getelementptr float, ptr addrspace(3) @global_smem, i64 %317, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %318, float %175, i1 %316) #3, !dbg !35
+  %319 = or i32 %139, 8, !dbg !35
+  %320 = zext nneg i32 %319 to i64, !dbg !35
+  %321 = getelementptr float, ptr addrspace(3) @global_smem, i64 %320, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %321, float %195, i1 %316) #3, !dbg !35
+  %322 = or i32 %139, 16, !dbg !35
+  %323 = zext nneg i32 %322 to i64, !dbg !35
+  %324 = getelementptr float, ptr addrspace(3) @global_smem, i64 %323, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %324, float %215, i1 %316) #3, !dbg !35
+  %325 = or i32 %139, 24, !dbg !35
+  %326 = zext nneg i32 %325 to i64, !dbg !35
+  %327 = getelementptr float, ptr addrspace(3) @global_smem, i64 %326, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %327, float %235, i1 %316) #3, !dbg !35
+  %328 = or i32 %139, 32, !dbg !35
+  %329 = zext nneg i32 %328 to i64, !dbg !35
+  %330 = getelementptr float, ptr addrspace(3) @global_smem, i64 %329, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %330, float %255, i1 %316) #3, !dbg !35
+  %331 = or i32 %139, 40, !dbg !35
+  %332 = zext nneg i32 %331 to i64, !dbg !35
+  %333 = getelementptr float, ptr addrspace(3) @global_smem, i64 %332, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %333, float %275, i1 %316) #3, !dbg !35
+  %334 = or i32 %139, 48, !dbg !35
+  %335 = zext nneg i32 %334 to i64, !dbg !35
+  %336 = getelementptr float, ptr addrspace(3) @global_smem, i64 %335, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %336, float %295, i1 %316) #3, !dbg !35
+  %337 = or i32 %139, 56, !dbg !35
+  %338 = zext nneg i32 %337 to i64, !dbg !35
+  %339 = getelementptr float, ptr addrspace(3) @global_smem, i64 %338, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %339, float %315, i1 %316) #3, !dbg !35
+  tail call void @llvm.nvvm.barrier0(), !dbg !35
+  %340 = icmp slt i32 %10, 64, !dbg !35
+  %341 = sext i32 %10 to i64, !dbg !35
+  %342 = getelementptr float, ptr addrspace(3) @global_smem, i64 %341, !dbg !35
+  %343 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %342, i1 %340) #3, !dbg !35
+  %344 = bitcast float %343 to i32, !dbg !35
+  %345 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %344, i32 4, i32 31), !dbg !35
+  %346 = bitcast i32 %345 to float, !dbg !35
+  %347 = fadd float %343, %346, !dbg !29
+  %348 = bitcast float %347 to i32, !dbg !35
+  %349 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %348, i32 2, i32 31), !dbg !35
+  %350 = bitcast i32 %349 to float, !dbg !35
+  %351 = fadd float %347, %350, !dbg !29
+  %352 = bitcast float %351 to i32, !dbg !35
+  %353 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %352, i32 1, i32 31), !dbg !35
+  %354 = bitcast i32 %353 to float, !dbg !35
+  %355 = fadd float %351, %354, !dbg !29
+  %356 = and i32 %10, 7, !dbg !35
+  %357 = icmp eq i32 %356, 0, !dbg !35
+  %358 = and i1 %340, %357, !dbg !35
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %342, float %355, i1 %358) #3, !dbg !35
+  tail call void @llvm.nvvm.barrier0(), !dbg !35
+  %359 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !35
+  %360 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 32), align 4, !dbg !35
+  %361 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 64), align 4, !dbg !35
+  %362 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 96), align 4, !dbg !35
+  %363 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 128), align 4, !dbg !35
+  %364 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 160), align 4, !dbg !35
+  %365 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 192), align 4, !dbg !35
+  %366 = load float, ptr addrspace(3) getelementptr ([0 x i8], ptr addrspace(3) @global_smem, i64 0, i64 224), align 4, !dbg !35
+  %367 = extractelement <2 x i64> %25, i64 0, !dbg !37
+  %368 = extractelement <2 x i64> %25, i64 1, !dbg !37
+  %369 = extractelement <8 x float> %66, i64 0, !dbg !38
+  %370 = extractelement <8 x float> %66, i64 1, !dbg !38
+  %371 = extractelement <8 x float> %66, i64 2, !dbg !38
+  %372 = extractelement <8 x float> %66, i64 3, !dbg !38
+  %373 = extractelement <8 x float> %66, i64 4, !dbg !38
+  %374 = extractelement <8 x float> %66, i64 5, !dbg !38
+  %375 = extractelement <8 x float> %66, i64 6, !dbg !38
+  %376 = extractelement <8 x float> %66, i64 7, !dbg !38
+  br label %377, !dbg !39
+
+377:                                              ; preds = %137, %377
+  %378 = phi i32 [ 0, %137 ], [ %672, %377 ]
+  %379 = zext nneg i32 %378 to i64, !dbg !37
+  %380 = or i64 %367, %379, !dbg !37
+  %381 = or i64 %368, %379, !dbg !37
+  %382 = icmp ult i64 %380, 50257, !dbg !40
+  %383 = icmp ult i64 %381, 50257, !dbg !40
+  %384 = add nsw i64 %380, %46, !dbg !41
+  %385 = add nsw i64 %381, %46, !dbg !41
+  %386 = add nsw i64 %380, %47, !dbg !41
+  %387 = add nsw i64 %381, %47, !dbg !41
+  %388 = add nsw i64 %380, %48, !dbg !41
+  %389 = add nsw i64 %381, %48, !dbg !41
+  %390 = add nsw i64 %380, %49, !dbg !41
+  %391 = add nsw i64 %381, %49, !dbg !41
+  %392 = add nsw i64 %380, %50, !dbg !41
+  %393 = add nsw i64 %381, %50, !dbg !41
+  %394 = add nsw i64 %380, %51, !dbg !41
+  %395 = add nsw i64 %381, %51, !dbg !41
+  %396 = add nsw i64 %380, %52, !dbg !41
+  %397 = add nsw i64 %381, %52, !dbg !41
+  %398 = add nsw i64 %380, %53, !dbg !41
+  %399 = add nsw i64 %381, %53, !dbg !41
+  %400 = getelementptr i16, ptr addrspace(1) %4, i64 %384, !dbg !42
+  %401 = getelementptr i16, ptr addrspace(1) %4, i64 %385, !dbg !42
+  %402 = getelementptr i16, ptr addrspace(1) %4, i64 %386, !dbg !42
+  %403 = getelementptr i16, ptr addrspace(1) %4, i64 %387, !dbg !42
+  %404 = getelementptr i16, ptr addrspace(1) %4, i64 %388, !dbg !42
+  %405 = getelementptr i16, ptr addrspace(1) %4, i64 %389, !dbg !42
+  %406 = getelementptr i16, ptr addrspace(1) %4, i64 %390, !dbg !42
+  %407 = getelementptr i16, ptr addrspace(1) %4, i64 %391, !dbg !42
+  %408 = getelementptr i16, ptr addrspace(1) %4, i64 %392, !dbg !42
+  %409 = getelementptr i16, ptr addrspace(1) %4, i64 %393, !dbg !42
+  %410 = getelementptr i16, ptr addrspace(1) %4, i64 %394, !dbg !42
+  %411 = getelementptr i16, ptr addrspace(1) %4, i64 %395, !dbg !42
+  %412 = getelementptr i16, ptr addrspace(1) %4, i64 %396, !dbg !42
+  %413 = getelementptr i16, ptr addrspace(1) %4, i64 %397, !dbg !42
+  %414 = getelementptr i16, ptr addrspace(1) %4, i64 %398, !dbg !42
+  %415 = getelementptr i16, ptr addrspace(1) %4, i64 %399, !dbg !42
+  %416 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %400, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %417 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %401, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %418 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %402, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %419 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %403, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %420 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %404, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %421 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %405, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %422 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %406, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %423 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %407, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %424 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %408, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %425 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %409, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %426 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %410, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %427 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %411, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %428 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %412, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %429 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %413, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %430 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %414, i1 %382, i16 0, i1 %382) #3, !dbg !43
+  %431 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %415, i1 %383, i16 0, i1 %383) #3, !dbg !43
+  %432 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %416) #3, !dbg !44
+  %433 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %417) #3, !dbg !44
+  %434 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %418) #3, !dbg !44
+  %435 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %419) #3, !dbg !44
+  %436 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %420) #3, !dbg !44
+  %437 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %421) #3, !dbg !44
+  %438 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %422) #3, !dbg !44
+  %439 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %423) #3, !dbg !44
+  %440 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %424) #3, !dbg !44
+  %441 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %425) #3, !dbg !44
+  %442 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %426) #3, !dbg !44
+  %443 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %427) #3, !dbg !44
+  %444 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %428) #3, !dbg !44
+  %445 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %429) #3, !dbg !44
+  %446 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %430) #3, !dbg !44
+  %447 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %431) #3, !dbg !44
+  %448 = getelementptr float, ptr addrspace(1) %0, i64 %384, !dbg !45
+  %449 = getelementptr float, ptr addrspace(1) %0, i64 %385, !dbg !45
+  %450 = getelementptr float, ptr addrspace(1) %0, i64 %386, !dbg !45
+  %451 = getelementptr float, ptr addrspace(1) %0, i64 %387, !dbg !45
+  %452 = getelementptr float, ptr addrspace(1) %0, i64 %388, !dbg !45
+  %453 = getelementptr float, ptr addrspace(1) %0, i64 %389, !dbg !45
+  %454 = getelementptr float, ptr addrspace(1) %0, i64 %390, !dbg !45
+  %455 = getelementptr float, ptr addrspace(1) %0, i64 %391, !dbg !45
+  %456 = getelementptr float, ptr addrspace(1) %0, i64 %392, !dbg !45
+  %457 = getelementptr float, ptr addrspace(1) %0, i64 %393, !dbg !45
+  %458 = getelementptr float, ptr addrspace(1) %0, i64 %394, !dbg !45
+  %459 = getelementptr float, ptr addrspace(1) %0, i64 %395, !dbg !45
+  %460 = getelementptr float, ptr addrspace(1) %0, i64 %396, !dbg !45
+  %461 = getelementptr float, ptr addrspace(1) %0, i64 %397, !dbg !45
+  %462 = getelementptr float, ptr addrspace(1) %0, i64 %398, !dbg !45
+  %463 = getelementptr float, ptr addrspace(1) %0, i64 %399, !dbg !45
+  %464 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %448, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %465 = bitcast i32 %464 to float, !dbg !46
+  %466 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %449, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %467 = bitcast i32 %466 to float, !dbg !46
+  %468 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %450, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %469 = bitcast i32 %468 to float, !dbg !46
+  %470 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %451, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %471 = bitcast i32 %470 to float, !dbg !46
+  %472 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %452, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %473 = bitcast i32 %472 to float, !dbg !46
+  %474 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %453, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %475 = bitcast i32 %474 to float, !dbg !46
+  %476 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %454, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %477 = bitcast i32 %476 to float, !dbg !46
+  %478 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %455, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %479 = bitcast i32 %478 to float, !dbg !46
+  %480 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %456, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %481 = bitcast i32 %480 to float, !dbg !46
+  %482 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %457, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %483 = bitcast i32 %482 to float, !dbg !46
+  %484 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %458, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %485 = bitcast i32 %484 to float, !dbg !46
+  %486 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %459, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %487 = bitcast i32 %486 to float, !dbg !46
+  %488 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %460, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %489 = bitcast i32 %488 to float, !dbg !46
+  %490 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %461, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %491 = bitcast i32 %490 to float, !dbg !46
+  %492 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %462, i1 %382, i32 0, i1 %382) #3, !dbg !46
+  %493 = bitcast i32 %492 to float, !dbg !46
+  %494 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %463, i1 %383, i32 0, i1 %383) #3, !dbg !46
+  %495 = bitcast i32 %494 to float, !dbg !46
+  %496 = getelementptr i16, ptr addrspace(1) %5, i64 %384, !dbg !47
+  %497 = getelementptr i16, ptr addrspace(1) %5, i64 %385, !dbg !47
+  %498 = getelementptr i16, ptr addrspace(1) %5, i64 %386, !dbg !47
+  %499 = getelementptr i16, ptr addrspace(1) %5, i64 %387, !dbg !47
+  %500 = getelementptr i16, ptr addrspace(1) %5, i64 %388, !dbg !47
+  %501 = getelementptr i16, ptr addrspace(1) %5, i64 %389, !dbg !47
+  %502 = getelementptr i16, ptr addrspace(1) %5, i64 %390, !dbg !47
+  %503 = getelementptr i16, ptr addrspace(1) %5, i64 %391, !dbg !47
+  %504 = getelementptr i16, ptr addrspace(1) %5, i64 %392, !dbg !47
+  %505 = getelementptr i16, ptr addrspace(1) %5, i64 %393, !dbg !47
+  %506 = getelementptr i16, ptr addrspace(1) %5, i64 %394, !dbg !47
+  %507 = getelementptr i16, ptr addrspace(1) %5, i64 %395, !dbg !47
+  %508 = getelementptr i16, ptr addrspace(1) %5, i64 %396, !dbg !47
+  %509 = getelementptr i16, ptr addrspace(1) %5, i64 %397, !dbg !47
+  %510 = getelementptr i16, ptr addrspace(1) %5, i64 %398, !dbg !47
+  %511 = getelementptr i16, ptr addrspace(1) %5, i64 %399, !dbg !47
+  %512 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %496, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %513 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %497, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %514 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %498, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %515 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %499, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %516 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %500, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %517 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %501, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %518 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %502, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %519 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %503, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %520 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %504, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %521 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %505, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %522 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %506, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %523 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %507, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %524 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %508, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %525 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %509, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %526 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %510, i1 %382, i16 0, i1 %382) #3, !dbg !48
+  %527 = tail call i16 asm sideeffect "mov.u16 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b16 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u16 $0, $3;", "=c,l,b,c,b"(ptr addrspace(1) %511, i1 %383, i16 0, i1 %383) #3, !dbg !48
+  %528 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %512) #3, !dbg !49
+  %529 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %513) #3, !dbg !49
+  %530 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %514) #3, !dbg !49
+  %531 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %515) #3, !dbg !49
+  %532 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %516) #3, !dbg !49
+  %533 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %517) #3, !dbg !49
+  %534 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %518) #3, !dbg !49
+  %535 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %519) #3, !dbg !49
+  %536 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %520) #3, !dbg !49
+  %537 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %521) #3, !dbg !49
+  %538 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %522) #3, !dbg !49
+  %539 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %523) #3, !dbg !49
+  %540 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %524) #3, !dbg !49
+  %541 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %525) #3, !dbg !49
+  %542 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %526) #3, !dbg !49
+  %543 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %527) #3, !dbg !49
+  %544 = fmul float %369, %465, !dbg !38
+  %545 = fmul float %369, %467, !dbg !38
+  %546 = fmul float %370, %469, !dbg !38
+  %547 = fmul float %370, %471, !dbg !38
+  %548 = fmul float %371, %473, !dbg !38
+  %549 = fmul float %371, %475, !dbg !38
+  %550 = fmul float %372, %477, !dbg !38
+  %551 = fmul float %372, %479, !dbg !38
+  %552 = fmul float %373, %481, !dbg !38
+  %553 = fmul float %373, %483, !dbg !38
+  %554 = fmul float %374, %485, !dbg !38
+  %555 = fmul float %374, %487, !dbg !38
+  %556 = fmul float %375, %489, !dbg !38
+  %557 = fmul float %375, %491, !dbg !38
+  %558 = fmul float %376, %493, !dbg !38
+  %559 = fmul float %376, %495, !dbg !38
+  %560 = fmul float %528, 0x3FF7154760000000, !dbg !50
+  %561 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %560) #3, !dbg !50
+  %562 = fmul float %529, 0x3FF7154760000000, !dbg !50
+  %563 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %562) #3, !dbg !50
+  %564 = fmul float %530, 0x3FF7154760000000, !dbg !50
+  %565 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %564) #3, !dbg !50
+  %566 = fmul float %531, 0x3FF7154760000000, !dbg !50
+  %567 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %566) #3, !dbg !50
+  %568 = fmul float %532, 0x3FF7154760000000, !dbg !50
+  %569 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %568) #3, !dbg !50
+  %570 = fmul float %533, 0x3FF7154760000000, !dbg !50
+  %571 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %570) #3, !dbg !50
+  %572 = fmul float %534, 0x3FF7154760000000, !dbg !50
+  %573 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %572) #3, !dbg !50
+  %574 = fmul float %535, 0x3FF7154760000000, !dbg !50
+  %575 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %574) #3, !dbg !50
+  %576 = fmul float %536, 0x3FF7154760000000, !dbg !50
+  %577 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %576) #3, !dbg !50
+  %578 = fmul float %537, 0x3FF7154760000000, !dbg !50
+  %579 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %578) #3, !dbg !50
+  %580 = fmul float %538, 0x3FF7154760000000, !dbg !50
+  %581 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %580) #3, !dbg !50
+  %582 = fmul float %539, 0x3FF7154760000000, !dbg !50
+  %583 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %582) #3, !dbg !50
+  %584 = fmul float %540, 0x3FF7154760000000, !dbg !50
+  %585 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %584) #3, !dbg !50
+  %586 = fmul float %541, 0x3FF7154760000000, !dbg !50
+  %587 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %586) #3, !dbg !50
+  %588 = fmul float %542, 0x3FF7154760000000, !dbg !50
+  %589 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %588) #3, !dbg !50
+  %590 = fmul float %543, 0x3FF7154760000000, !dbg !50
+  %591 = tail call float asm "ex2.approx.f32 $0, $1;", "=f,f"(float %590) #3, !dbg !50
+  %592 = fmul float %359, %561, !dbg !51
+  %593 = fmul float %359, %563, !dbg !51
+  %594 = fmul float %360, %565, !dbg !51
+  %595 = fmul float %360, %567, !dbg !51
+  %596 = fmul float %361, %569, !dbg !51
+  %597 = fmul float %361, %571, !dbg !51
+  %598 = fmul float %362, %573, !dbg !51
+  %599 = fmul float %362, %575, !dbg !51
+  %600 = fmul float %363, %577, !dbg !51
+  %601 = fmul float %363, %579, !dbg !51
+  %602 = fmul float %364, %581, !dbg !51
+  %603 = fmul float %364, %583, !dbg !51
+  %604 = fmul float %365, %585, !dbg !51
+  %605 = fmul float %365, %587, !dbg !51
+  %606 = fmul float %366, %589, !dbg !51
+  %607 = fmul float %366, %591, !dbg !51
+  %608 = fsub float %544, %592, !dbg !52
+  %609 = fsub float %545, %593, !dbg !52
+  %610 = fsub float %546, %594, !dbg !52
+  %611 = fsub float %547, %595, !dbg !52
+  %612 = fsub float %548, %596, !dbg !52
+  %613 = fsub float %549, %597, !dbg !52
+  %614 = fsub float %550, %598, !dbg !52
+  %615 = fsub float %551, %599, !dbg !52
+  %616 = fsub float %552, %600, !dbg !52
+  %617 = fsub float %553, %601, !dbg !52
+  %618 = fsub float %554, %602, !dbg !52
+  %619 = fsub float %555, %603, !dbg !52
+  %620 = fsub float %556, %604, !dbg !52
+  %621 = fsub float %557, %605, !dbg !52
+  %622 = fsub float %558, %606, !dbg !52
+  %623 = fsub float %559, %607, !dbg !52
+  %624 = fadd float %432, %608, !dbg !53
+  %625 = fadd float %433, %609, !dbg !53
+  %626 = fadd float %434, %610, !dbg !53
+  %627 = fadd float %435, %611, !dbg !53
+  %628 = fadd float %436, %612, !dbg !53
+  %629 = fadd float %437, %613, !dbg !53
+  %630 = fadd float %438, %614, !dbg !53
+  %631 = fadd float %439, %615, !dbg !53
+  %632 = fadd float %440, %616, !dbg !53
+  %633 = fadd float %441, %617, !dbg !53
+  %634 = fadd float %442, %618, !dbg !53
+  %635 = fadd float %443, %619, !dbg !53
+  %636 = fadd float %444, %620, !dbg !53
+  %637 = fadd float %445, %621, !dbg !53
+  %638 = fadd float %446, %622, !dbg !53
+  %639 = fadd float %447, %623, !dbg !53
+  %640 = getelementptr i16, ptr addrspace(1) %6, i64 %384, !dbg !54
+  %641 = getelementptr i16, ptr addrspace(1) %6, i64 %385, !dbg !54
+  %642 = getelementptr i16, ptr addrspace(1) %6, i64 %386, !dbg !54
+  %643 = getelementptr i16, ptr addrspace(1) %6, i64 %387, !dbg !54
+  %644 = getelementptr i16, ptr addrspace(1) %6, i64 %388, !dbg !54
+  %645 = getelementptr i16, ptr addrspace(1) %6, i64 %389, !dbg !54
+  %646 = getelementptr i16, ptr addrspace(1) %6, i64 %390, !dbg !54
+  %647 = getelementptr i16, ptr addrspace(1) %6, i64 %391, !dbg !54
+  %648 = getelementptr i16, ptr addrspace(1) %6, i64 %392, !dbg !54
+  %649 = getelementptr i16, ptr addrspace(1) %6, i64 %393, !dbg !54
+  %650 = getelementptr i16, ptr addrspace(1) %6, i64 %394, !dbg !54
+  %651 = getelementptr i16, ptr addrspace(1) %6, i64 %395, !dbg !54
+  %652 = getelementptr i16, ptr addrspace(1) %6, i64 %396, !dbg !54
+  %653 = getelementptr i16, ptr addrspace(1) %6, i64 %397, !dbg !54
+  %654 = getelementptr i16, ptr addrspace(1) %6, i64 %398, !dbg !54
+  %655 = getelementptr i16, ptr addrspace(1) %6, i64 %399, !dbg !54
+  %656 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %624) #3, !dbg !55
+  %657 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %625) #3, !dbg !55
+  %658 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %626) #3, !dbg !55
+  %659 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %627) #3, !dbg !55
+  %660 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %628) #3, !dbg !55
+  %661 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %629) #3, !dbg !55
+  %662 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %630) #3, !dbg !55
+  %663 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %631) #3, !dbg !55
+  %664 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %632) #3, !dbg !55
+  %665 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %633) #3, !dbg !55
+  %666 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %634) #3, !dbg !55
+  %667 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %635) #3, !dbg !55
+  %668 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %636) #3, !dbg !55
+  %669 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %637) #3, !dbg !55
+  %670 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %638) #3, !dbg !55
+  %671 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %639) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %656, ptr addrspace(1) %640, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %657, ptr addrspace(1) %641, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %658, ptr addrspace(1) %642, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %659, ptr addrspace(1) %643, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %660, ptr addrspace(1) %644, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %661, ptr addrspace(1) %645, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %662, ptr addrspace(1) %646, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %663, ptr addrspace(1) %647, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %664, ptr addrspace(1) %648, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %665, ptr addrspace(1) %649, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %666, ptr addrspace(1) %650, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %667, ptr addrspace(1) %651, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %668, ptr addrspace(1) %652, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %669, ptr addrspace(1) %653, i1 %383) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %670, ptr addrspace(1) %654, i1 %382) #3, !dbg !55
+  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %671, ptr addrspace(1) %655, i1 %383) #3, !dbg !55
+  %672 = add nuw nsw i32 %378, 512, !dbg !39
+  %673 = icmp ult i32 %378, 49745, !dbg !39
+  br i1 %673, label %377, label %674, !dbg !39
+
+674:                                              ; preds = %377
+  ret void, !dbg !56
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "ckzgl7thb4xdfkfnd2tidks6mt5f3hauwfyjflbtzyepo5oxkvhk.py", directory: "/tmp/torchinductor_root/kz")
+!3 = !{ptr @triton__0d1d2d3d4d5d6d7de8, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3d4d5d6d7de8, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6d7de8", linkageName: "triton__0d1d2d3d4d5d6d7de8", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 22, column: 44, scope: !5)
+!9 = !DILocation(line: 24, column: 33, scope: !5)
+!10 = !DILocation(line: 21, column: 28, scope: !5)
+!11 = !DILocation(line: 21, column: 34, scope: !5)
+!12 = !DILocation(line: 21, column: 46, scope: !5)
+!13 = !DILocation(line: 22, column: 23, scope: !5)
+!14 = !DILocation(line: 26, column: 30, scope: !5)
+!15 = !DILocation(line: 26, column: 35, scope: !5)
+!16 = !DILocation(line: 27, column: 19, scope: !5)
+!17 = !DILocation(line: 29, column: 19, scope: !5)
+!18 = !DILocation(line: 36, column: 46, scope: !5)
+!19 = !DILocation(line: 38, column: 23, scope: !5)
+!20 = !DILocation(line: 39, column: 22, scope: !5)
+!21 = !DILocation(line: 41, column: 37, scope: !5)
+!22 = !DILocation(line: 32, column: 36, scope: !5)
+!23 = !DILocation(line: 33, column: 27, scope: !5)
+!24 = !DILocation(line: 34, column: 25, scope: !5)
+!25 = !DILocation(line: 36, column: 34, scope: !5)
+!26 = !DILocation(line: 36, column: 52, scope: !5)
+!27 = !DILocation(line: 42, column: 23, scope: !5)
+!28 = !DILocation(line: 45, column: 40, scope: !5)
+!29 = !DILocation(line: 233, column: 15, scope: !30, inlinedAt: !33)
+!30 = distinct !DILexicalBlockFile(scope: !32, file: !31, discriminator: 0)
+!31 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!32 = distinct !DILexicalBlockFile(scope: !5, file: !31, discriminator: 0)
+!33 = !DILocation(line: 243, column: 36, scope: !30, inlinedAt: !34)
+!34 = !DILocation(line: 46, column: 27, scope: !30)
+!35 = !DILocation(line: 243, column: 36, scope: !32, inlinedAt: !36)
+!36 = !DILocation(line: 46, column: 27, scope: !32)
+!37 = !DILocation(line: 52, column: 27, scope: !5)
+!38 = !DILocation(line: 63, column: 24, scope: !5)
+!39 = !DILocation(line: 51, column: 36, scope: !5)
+!40 = !DILocation(line: 53, column: 25, scope: !5)
+!41 = !DILocation(line: 55, column: 41, scope: !5)
+!42 = !DILocation(line: 55, column: 35, scope: !5)
+!43 = !DILocation(line: 55, column: 53, scope: !5)
+!44 = !DILocation(line: 55, column: 105, scope: !5)
+!45 = !DILocation(line: 56, column: 35, scope: !5)
+!46 = !DILocation(line: 56, column: 53, scope: !5)
+!47 = !DILocation(line: 57, column: 35, scope: !5)
+!48 = !DILocation(line: 57, column: 53, scope: !5)
+!49 = !DILocation(line: 57, column: 105, scope: !5)
+!50 = !DILocation(line: 65, column: 23, scope: !5)
+!51 = !DILocation(line: 66, column: 24, scope: !5)
+!52 = !DILocation(line: 67, column: 24, scope: !5)
+!53 = !DILocation(line: 69, column: 24, scope: !5)
+!54 = !DILocation(line: 70, column: 29, scope: !5)
+!55 = !DILocation(line: 70, column: 54, scope: !5)
+!56 = !DILocation(line: 51, column: 4, scope: !5)

.triton/dump/33dcd7dc40e8b1089e9a4c61a9c826b5/triton_.ptx

@@ -0,0 +1,1517 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7de8
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6d7de8(
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_7,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_8
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<176>;
+	.reg .b16 	%rs<129>;
+	.reg .b32 	%r<238>;
+	.reg .f32 	%f<393>;
+	.reg .b64 	%rd<166>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd39, [triton__0d1d2d3d4d5d6d7de8_param_6];
+	ld.param.u64 	%rd38, [triton__0d1d2d3d4d5d6d7de8_param_5];
+	ld.param.u64 	%rd37, [triton__0d1d2d3d4d5d6d7de8_param_4];
+	ld.param.u64 	%rd36, [triton__0d1d2d3d4d5d6d7de8_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r1, %tid.x;
+	ld.param.u64 	%rd59, [triton__0d1d2d3d4d5d6d7de8_param_1];
+	shr.u32 	%r2, %r1, 5;
+	ld.param.u64 	%rd56, [triton__0d1d2d3d4d5d6d7de8_param_2];
+	.loc	1 24 33
+	and.b32  	%r9, %r1, 255;
+	ld.param.u64 	%rd57, [triton__0d1d2d3d4d5d6d7de8_param_3];
+	or.b32  	%r10, %r9, 256;
+	.loc	1 21 28
+	mov.u32 %r3, %ctaid.x;
+	.loc	1 21 34
+	cvt.s64.s32 	%rd1, %r3;
+	.loc	1 21 46
+	mul.wide.s32 	%rd60, %r3, 8;
+	.loc	1 22 23
+	or.b64  	%rd61, %rd60, 1;
+	cvt.u64.u32 	%rd2, %r9;
+	cvt.u64.u32 	%rd3, %r10;
+	.loc	1 26 30
+	shl.b64 	%rd62, %rd60, 3;
+	add.s64 	%rd41, %rd59, %rd62;
+	add.s64 	%rd43, %rd41, 8;
+	add.s64 	%rd45, %rd41, 16;
+	add.s64 	%rd47, %rd41, 24;
+	add.s64 	%rd49, %rd41, 32;
+	add.s64 	%rd51, %rd41, 40;
+	add.s64 	%rd53, %rd41, 48;
+	add.s64 	%rd55, %rd41, 56;
+	mov.pred 	%p1, -1;
+	.loc	1 26 35
+	mov.u64 %rd40, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd40 }, [ %rd41 + 0 ];
+	mov.u64 %rd42, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd42 }, [ %rd43 + 0 ];
+	mov.u64 %rd44, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd44 }, [ %rd45 + 0 ];
+	mov.u64 %rd46, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd46 }, [ %rd47 + 0 ];
+	mov.u64 %rd48, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd48 }, [ %rd49 + 0 ];
+	mov.u64 %rd50, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd50 }, [ %rd51 + 0 ];
+	mov.u64 %rd52, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd52 }, [ %rd53 + 0 ];
+	mov.u64 %rd54, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd54 }, [ %rd55 + 0 ];
+	.loc	1 27 19
+	mov.u32 %r7, 0x0;
+	@%p1 ld.global.b32 { %r7 }, [ %rd56 + 0 ];
+	.loc	1 29 19
+	mov.u32 %r8, 0x0;
+	@%p1 ld.global.b32 { %r8 }, [ %rd57 + 0 ];
+	.loc	1 36 46
+	mul.wide.s32 	%rd4, %r3, 402056;
+	mul.lo.s64 	%rd5, %rd61, 50257;
+	.loc	1 38 23
+	setp.eq.s64 	%p11, %rd40, -1;
+	setp.eq.s64 	%p12, %rd42, -1;
+	setp.eq.s64 	%p13, %rd44, -1;
+	setp.eq.s64 	%p14, %rd46, -1;
+	setp.eq.s64 	%p15, %rd48, -1;
+	setp.eq.s64 	%p16, %rd50, -1;
+	setp.eq.s64 	%p17, %rd52, -1;
+	setp.eq.s64 	%p18, %rd54, -1;
+	.loc	1 39 22
+	div.full.f32 %r6, %r7, %r8;
+	mov.b32 	%f89, %r6;
+	.loc	1 41 37
+	selp.f32 	%f8, 0f00000000, %f89, %p18;
+	selp.f32 	%f7, 0f00000000, %f89, %p17;
+	selp.f32 	%f6, 0f00000000, %f89, %p16;
+	selp.f32 	%f5, 0f00000000, %f89, %p15;
+	selp.f32 	%f4, 0f00000000, %f89, %p14;
+	selp.f32 	%f3, 0f00000000, %f89, %p13;
+	selp.f32 	%f2, 0f00000000, %f89, %p12;
+	selp.f32 	%f1, 0f00000000, %f89, %p11;
+	mov.f32 	%f377, 0f00000000;
+	mov.u64 	%rd157, 0;
+	shl.b64 	%rd83, %rd4, 2;
+	shl.b64 	%rd86, %rd5, 2;
+	mov.f32 	%f378, %f377;
+	mov.f32 	%f379, %f377;
+	mov.f32 	%f380, %f377;
+	mov.f32 	%f381, %f377;
+	mov.f32 	%f382, %f377;
+	mov.f32 	%f383, %f377;
+	mov.f32 	%f384, %f377;
+	mov.f32 	%f385, %f377;
+	mov.f32 	%f386, %f377;
+	mov.f32 	%f387, %f377;
+	mov.f32 	%f388, %f377;
+	mov.f32 	%f389, %f377;
+	mov.f32 	%f390, %f377;
+	mov.f32 	%f391, %f377;
+	mov.f32 	%f392, %f377;
+$L__BB0_1:
+	.loc	1 33 27
+	or.b64  	%rd79, %rd157, %rd2;
+	or.b64  	%rd80, %rd157, %rd3;
+	.loc	1 34 25
+	setp.lt.u64 	%p22, %rd80, 50257;
+	setp.lt.u64 	%p20, %rd79, 50257;
+	.loc	1 36 34
+	shl.b64 	%rd81, %rd79, 2;
+	add.s64 	%rd82, %rd36, %rd81;
+	add.s64 	%rd63, %rd82, %rd83;
+	shl.b64 	%rd84, %rd80, 2;
+	add.s64 	%rd85, %rd36, %rd84;
+	add.s64 	%rd64, %rd85, %rd83;
+	add.s64 	%rd65, %rd82, %rd86;
+	add.s64 	%rd66, %rd85, %rd86;
+	add.s64 	%rd67, %rd65, 201028;
+	add.s64 	%rd68, %rd66, 201028;
+	add.s64 	%rd69, %rd65, 402056;
+	add.s64 	%rd70, %rd66, 402056;
+	add.s64 	%rd71, %rd65, 603084;
+	add.s64 	%rd72, %rd66, 603084;
+	add.s64 	%rd73, %rd65, 804112;
+	add.s64 	%rd74, %rd66, 804112;
+	add.s64 	%rd75, %rd65, 1005140;
+	add.s64 	%rd76, %rd66, 1005140;
+	add.s64 	%rd77, %rd65, 1206168;
+	add.s64 	%rd78, %rd66, 1206168;
+	mov.b32 	%r173, 0;
+	.loc	1 36 52
+	mov.u32 %r11, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r11 }, [ %rd63 + 0 ];
+	@!%p20 mov.u32 %r11, %r173;
+	mov.u32 %r13, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r13 }, [ %rd64 + 0 ];
+	@!%p22 mov.u32 %r13, %r173;
+	mov.u32 %r15, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r15 }, [ %rd65 + 0 ];
+	@!%p20 mov.u32 %r15, %r173;
+	mov.u32 %r17, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r17 }, [ %rd66 + 0 ];
+	@!%p22 mov.u32 %r17, %r173;
+	mov.u32 %r19, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r19 }, [ %rd67 + 0 ];
+	@!%p20 mov.u32 %r19, %r173;
+	mov.u32 %r21, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r21 }, [ %rd68 + 0 ];
+	@!%p22 mov.u32 %r21, %r173;
+	mov.u32 %r23, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r23 }, [ %rd69 + 0 ];
+	@!%p20 mov.u32 %r23, %r173;
+	mov.u32 %r25, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r25 }, [ %rd70 + 0 ];
+	@!%p22 mov.u32 %r25, %r173;
+	mov.u32 %r27, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r27 }, [ %rd71 + 0 ];
+	@!%p20 mov.u32 %r27, %r173;
+	mov.u32 %r29, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r29 }, [ %rd72 + 0 ];
+	@!%p22 mov.u32 %r29, %r173;
+	mov.u32 %r31, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r31 }, [ %rd73 + 0 ];
+	@!%p20 mov.u32 %r31, %r173;
+	mov.u32 %r33, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r33 }, [ %rd74 + 0 ];
+	@!%p22 mov.u32 %r33, %r173;
+	mov.u32 %r35, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r35 }, [ %rd75 + 0 ];
+	@!%p20 mov.u32 %r35, %r173;
+	mov.u32 %r37, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r37 }, [ %rd76 + 0 ];
+	@!%p22 mov.u32 %r37, %r173;
+	mov.u32 %r39, 0x0;
+	@%p20 ld.global.L1::evict_last.b32 { %r39 }, [ %rd77 + 0 ];
+	@!%p20 mov.u32 %r39, %r173;
+	mov.u32 %r41, 0x0;
+	@%p22 ld.global.L1::evict_last.b32 { %r41 }, [ %rd78 + 0 ];
+	@!%p22 mov.u32 %r41, %r173;
+	mov.b32 	%f90, %r41;
+	mov.b32 	%f91, %r39;
+	mov.b32 	%f92, %r37;
+	mov.b32 	%f93, %r35;
+	mov.b32 	%f94, %r33;
+	mov.b32 	%f95, %r31;
+	mov.b32 	%f96, %r29;
+	mov.b32 	%f97, %r27;
+	mov.b32 	%f98, %r25;
+	mov.b32 	%f99, %r23;
+	mov.b32 	%f100, %r21;
+	mov.b32 	%f101, %r19;
+	mov.b32 	%f102, %r17;
+	mov.b32 	%f103, %r15;
+	mov.b32 	%f104, %r13;
+	mov.b32 	%f105, %r11;
+	.loc	1 42 23
+	mul.f32 	%f106, %f1, %f105;
+	mul.f32 	%f107, %f1, %f104;
+	mul.f32 	%f108, %f2, %f103;
+	mul.f32 	%f109, %f2, %f102;
+	mul.f32 	%f110, %f3, %f101;
+	mul.f32 	%f111, %f3, %f100;
+	mul.f32 	%f112, %f4, %f99;
+	mul.f32 	%f113, %f4, %f98;
+	mul.f32 	%f114, %f5, %f97;
+	mul.f32 	%f115, %f5, %f96;
+	mul.f32 	%f116, %f6, %f95;
+	mul.f32 	%f117, %f6, %f94;
+	mul.f32 	%f118, %f7, %f93;
+	mul.f32 	%f119, %f7, %f92;
+	mul.f32 	%f120, %f8, %f91;
+	mul.f32 	%f121, %f8, %f90;
+	.loc	1 45 40
+	selp.f32 	%f122, %f121, 0f80000000, %p22;
+	selp.f32 	%f123, %f120, 0f80000000, %p20;
+	selp.f32 	%f124, %f119, 0f80000000, %p22;
+	selp.f32 	%f125, %f118, 0f80000000, %p20;
+	selp.f32 	%f126, %f117, 0f80000000, %p22;
+	selp.f32 	%f127, %f116, 0f80000000, %p20;
+	selp.f32 	%f128, %f115, 0f80000000, %p22;
+	selp.f32 	%f129, %f114, 0f80000000, %p20;
+	selp.f32 	%f130, %f113, 0f80000000, %p22;
+	selp.f32 	%f131, %f112, 0f80000000, %p20;
+	selp.f32 	%f132, %f111, 0f80000000, %p22;
+	selp.f32 	%f133, %f110, 0f80000000, %p20;
+	selp.f32 	%f134, %f109, 0f80000000, %p22;
+	selp.f32 	%f135, %f108, 0f80000000, %p20;
+	selp.f32 	%f136, %f107, 0f80000000, %p22;
+	selp.f32 	%f137, %f106, 0f80000000, %p20;
+	add.f32 	%f377, %f377, %f137;
+	add.f32 	%f378, %f378, %f136;
+	add.f32 	%f379, %f379, %f135;
+	add.f32 	%f380, %f380, %f134;
+	add.f32 	%f381, %f381, %f133;
+	add.f32 	%f382, %f382, %f132;
+	add.f32 	%f383, %f383, %f131;
+	add.f32 	%f384, %f384, %f130;
+	add.f32 	%f385, %f385, %f129;
+	add.f32 	%f386, %f386, %f128;
+	add.f32 	%f387, %f387, %f127;
+	add.f32 	%f388, %f388, %f126;
+	add.f32 	%f389, %f389, %f125;
+	add.f32 	%f390, %f390, %f124;
+	add.f32 	%f391, %f391, %f123;
+	add.f32 	%f392, %f392, %f122;
+	.loc	1 32 36
+	add.s64 	%rd157, %rd157, 512;
+	cvt.u32.u64 	%r43, %rd157;
+	add.s32 	%r44, %r43, -512;
+	setp.lt.u32 	%p51, %r44, 49745;
+	@%p51 bra 	$L__BB0_1;
+	.loc	1 22 44
+	and.b32  	%r65, %r1, 31;
+	.loc	1 24 33
+	and.b32  	%r66, %r2, 7;
+$L__tmp1:
+	.loc	2 233 15
+	add.f32 	%f138, %f377, %f378;
+	add.f32 	%f139, %f379, %f380;
+	add.f32 	%f140, %f381, %f382;
+	add.f32 	%f141, %f383, %f384;
+	add.f32 	%f142, %f385, %f386;
+	add.f32 	%f143, %f387, %f388;
+	add.f32 	%f144, %f389, %f390;
+	add.f32 	%f145, %f391, %f392;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r67, %f138;
+	shfl.sync.bfly.b32	%r68, %r67, 16, 31, -1;
+	mov.b32 	%f146, %r68;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f147, %f138, %f146;
+$L__tmp4:
+	.loc	2 243 36
+	mov.b32 	%r69, %f147;
+	shfl.sync.bfly.b32	%r70, %r69, 8, 31, -1;
+	mov.b32 	%f148, %r70;
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f149, %f147, %f148;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r71, %f149;
+	shfl.sync.bfly.b32	%r72, %r71, 4, 31, -1;
+	mov.b32 	%f150, %r72;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f151, %f149, %f150;
+$L__tmp8:
+	.loc	2 243 36
+	mov.b32 	%r73, %f151;
+	shfl.sync.bfly.b32	%r74, %r73, 2, 31, -1;
+	mov.b32 	%f152, %r74;
+$L__tmp9:
+	.loc	2 233 15
+	add.f32 	%f153, %f151, %f152;
+$L__tmp10:
+	.loc	2 243 36
+	mov.b32 	%r75, %f153;
+	shfl.sync.bfly.b32	%r76, %r75, 1, 31, -1;
+	mov.b32 	%f154, %r76;
+$L__tmp11:
+	.loc	2 233 15
+	add.f32 	%f155, %f153, %f154;
+$L__tmp12:
+	.loc	2 243 36
+	mov.b32 	%r77, %f139;
+	shfl.sync.bfly.b32	%r78, %r77, 16, 31, -1;
+	mov.b32 	%f156, %r78;
+$L__tmp13:
+	.loc	2 233 15
+	add.f32 	%f157, %f139, %f156;
+$L__tmp14:
+	.loc	2 243 36
+	mov.b32 	%r79, %f157;
+	shfl.sync.bfly.b32	%r80, %r79, 8, 31, -1;
+	mov.b32 	%f158, %r80;
+$L__tmp15:
+	.loc	2 233 15
+	add.f32 	%f159, %f157, %f158;
+$L__tmp16:
+	.loc	2 243 36
+	mov.b32 	%r81, %f159;
+	shfl.sync.bfly.b32	%r82, %r81, 4, 31, -1;
+	mov.b32 	%f160, %r82;
+$L__tmp17:
+	.loc	2 233 15
+	add.f32 	%f161, %f159, %f160;
+$L__tmp18:
+	.loc	2 243 36
+	mov.b32 	%r83, %f161;
+	shfl.sync.bfly.b32	%r84, %r83, 2, 31, -1;
+	mov.b32 	%f162, %r84;
+$L__tmp19:
+	.loc	2 233 15
+	add.f32 	%f163, %f161, %f162;
+$L__tmp20:
+	.loc	2 243 36
+	mov.b32 	%r85, %f163;
+	shfl.sync.bfly.b32	%r86, %r85, 1, 31, -1;
+	mov.b32 	%f164, %r86;
+$L__tmp21:
+	.loc	2 233 15
+	add.f32 	%f165, %f163, %f164;
+$L__tmp22:
+	.loc	2 243 36
+	mov.b32 	%r87, %f140;
+	shfl.sync.bfly.b32	%r88, %r87, 16, 31, -1;
+	mov.b32 	%f166, %r88;
+$L__tmp23:
+	.loc	2 233 15
+	add.f32 	%f167, %f140, %f166;
+$L__tmp24:
+	.loc	2 243 36
+	mov.b32 	%r89, %f167;
+	shfl.sync.bfly.b32	%r90, %r89, 8, 31, -1;
+	mov.b32 	%f168, %r90;
+$L__tmp25:
+	.loc	2 233 15
+	add.f32 	%f169, %f167, %f168;
+$L__tmp26:
+	.loc	2 243 36
+	mov.b32 	%r91, %f169;
+	shfl.sync.bfly.b32	%r92, %r91, 4, 31, -1;
+	mov.b32 	%f170, %r92;
+$L__tmp27:
+	.loc	2 233 15
+	add.f32 	%f171, %f169, %f170;
+$L__tmp28:
+	.loc	2 243 36
+	mov.b32 	%r93, %f171;
+	shfl.sync.bfly.b32	%r94, %r93, 2, 31, -1;
+	mov.b32 	%f172, %r94;
+$L__tmp29:
+	.loc	2 233 15
+	add.f32 	%f173, %f171, %f172;
+$L__tmp30:
+	.loc	2 243 36
+	mov.b32 	%r95, %f173;
+	shfl.sync.bfly.b32	%r96, %r95, 1, 31, -1;
+	mov.b32 	%f174, %r96;
+$L__tmp31:
+	.loc	2 233 15
+	add.f32 	%f175, %f173, %f174;
+$L__tmp32:
+	.loc	2 243 36
+	mov.b32 	%r97, %f141;
+	shfl.sync.bfly.b32	%r98, %r97, 16, 31, -1;
+	mov.b32 	%f176, %r98;
+$L__tmp33:
+	.loc	2 233 15
+	add.f32 	%f177, %f141, %f176;
+$L__tmp34:
+	.loc	2 243 36
+	mov.b32 	%r99, %f177;
+	shfl.sync.bfly.b32	%r100, %r99, 8, 31, -1;
+	mov.b32 	%f178, %r100;
+$L__tmp35:
+	.loc	2 233 15
+	add.f32 	%f179, %f177, %f178;
+$L__tmp36:
+	.loc	2 243 36
+	mov.b32 	%r101, %f179;
+	shfl.sync.bfly.b32	%r102, %r101, 4, 31, -1;
+	mov.b32 	%f180, %r102;
+$L__tmp37:
+	.loc	2 233 15
+	add.f32 	%f181, %f179, %f180;
+$L__tmp38:
+	.loc	2 243 36
+	mov.b32 	%r103, %f181;
+	shfl.sync.bfly.b32	%r104, %r103, 2, 31, -1;
+	mov.b32 	%f182, %r104;
+$L__tmp39:
+	.loc	2 233 15
+	add.f32 	%f183, %f181, %f182;
+$L__tmp40:
+	.loc	2 243 36
+	mov.b32 	%r105, %f183;
+	shfl.sync.bfly.b32	%r106, %r105, 1, 31, -1;
+	mov.b32 	%f184, %r106;
+$L__tmp41:
+	.loc	2 233 15
+	add.f32 	%f185, %f183, %f184;
+$L__tmp42:
+	.loc	2 243 36
+	mov.b32 	%r107, %f142;
+	shfl.sync.bfly.b32	%r108, %r107, 16, 31, -1;
+	mov.b32 	%f186, %r108;
+$L__tmp43:
+	.loc	2 233 15
+	add.f32 	%f187, %f142, %f186;
+$L__tmp44:
+	.loc	2 243 36
+	mov.b32 	%r109, %f187;
+	shfl.sync.bfly.b32	%r110, %r109, 8, 31, -1;
+	mov.b32 	%f188, %r110;
+$L__tmp45:
+	.loc	2 233 15
+	add.f32 	%f189, %f187, %f188;
+$L__tmp46:
+	.loc	2 243 36
+	mov.b32 	%r111, %f189;
+	shfl.sync.bfly.b32	%r112, %r111, 4, 31, -1;
+	mov.b32 	%f190, %r112;
+$L__tmp47:
+	.loc	2 233 15
+	add.f32 	%f191, %f189, %f190;
+$L__tmp48:
+	.loc	2 243 36
+	mov.b32 	%r113, %f191;
+	shfl.sync.bfly.b32	%r114, %r113, 2, 31, -1;
+	mov.b32 	%f192, %r114;
+$L__tmp49:
+	.loc	2 233 15
+	add.f32 	%f193, %f191, %f192;
+$L__tmp50:
+	.loc	2 243 36
+	mov.b32 	%r115, %f193;
+	shfl.sync.bfly.b32	%r116, %r115, 1, 31, -1;
+	mov.b32 	%f194, %r116;
+$L__tmp51:
+	.loc	2 233 15
+	add.f32 	%f195, %f193, %f194;
+$L__tmp52:
+	.loc	2 243 36
+	mov.b32 	%r117, %f143;
+	shfl.sync.bfly.b32	%r118, %r117, 16, 31, -1;
+	mov.b32 	%f196, %r118;
+$L__tmp53:
+	.loc	2 233 15
+	add.f32 	%f197, %f143, %f196;
+$L__tmp54:
+	.loc	2 243 36
+	mov.b32 	%r119, %f197;
+	shfl.sync.bfly.b32	%r120, %r119, 8, 31, -1;
+	mov.b32 	%f198, %r120;
+$L__tmp55:
+	.loc	2 233 15
+	add.f32 	%f199, %f197, %f198;
+$L__tmp56:
+	.loc	2 243 36
+	mov.b32 	%r121, %f199;
+	shfl.sync.bfly.b32	%r122, %r121, 4, 31, -1;
+	mov.b32 	%f200, %r122;
+$L__tmp57:
+	.loc	2 233 15
+	add.f32 	%f201, %f199, %f200;
+$L__tmp58:
+	.loc	2 243 36
+	mov.b32 	%r123, %f201;
+	shfl.sync.bfly.b32	%r124, %r123, 2, 31, -1;
+	mov.b32 	%f202, %r124;
+$L__tmp59:
+	.loc	2 233 15
+	add.f32 	%f203, %f201, %f202;
+$L__tmp60:
+	.loc	2 243 36
+	mov.b32 	%r125, %f203;
+	shfl.sync.bfly.b32	%r126, %r125, 1, 31, -1;
+	mov.b32 	%f204, %r126;
+$L__tmp61:
+	.loc	2 233 15
+	add.f32 	%f205, %f203, %f204;
+$L__tmp62:
+	.loc	2 243 36
+	mov.b32 	%r127, %f144;
+	shfl.sync.bfly.b32	%r128, %r127, 16, 31, -1;
+	mov.b32 	%f206, %r128;
+$L__tmp63:
+	.loc	2 233 15
+	add.f32 	%f207, %f144, %f206;
+$L__tmp64:
+	.loc	2 243 36
+	mov.b32 	%r129, %f207;
+	shfl.sync.bfly.b32	%r130, %r129, 8, 31, -1;
+	mov.b32 	%f208, %r130;
+$L__tmp65:
+	.loc	2 233 15
+	add.f32 	%f209, %f207, %f208;
+$L__tmp66:
+	.loc	2 243 36
+	mov.b32 	%r131, %f209;
+	shfl.sync.bfly.b32	%r132, %r131, 4, 31, -1;
+	mov.b32 	%f210, %r132;
+$L__tmp67:
+	.loc	2 233 15
+	add.f32 	%f211, %f209, %f210;
+$L__tmp68:
+	.loc	2 243 36
+	mov.b32 	%r133, %f211;
+	shfl.sync.bfly.b32	%r134, %r133, 2, 31, -1;
+	mov.b32 	%f212, %r134;
+$L__tmp69:
+	.loc	2 233 15
+	add.f32 	%f213, %f211, %f212;
+$L__tmp70:
+	.loc	2 243 36
+	mov.b32 	%r135, %f213;
+	shfl.sync.bfly.b32	%r136, %r135, 1, 31, -1;
+	mov.b32 	%f214, %r136;
+$L__tmp71:
+	.loc	2 233 15
+	add.f32 	%f215, %f213, %f214;
+$L__tmp72:
+	.loc	2 243 36
+	mov.b32 	%r137, %f145;
+	shfl.sync.bfly.b32	%r138, %r137, 16, 31, -1;
+	mov.b32 	%f216, %r138;
+$L__tmp73:
+	.loc	2 233 15
+	add.f32 	%f217, %f145, %f216;
+$L__tmp74:
+	.loc	2 243 36
+	mov.b32 	%r139, %f217;
+	shfl.sync.bfly.b32	%r140, %r139, 8, 31, -1;
+	mov.b32 	%f218, %r140;
+$L__tmp75:
+	.loc	2 233 15
+	add.f32 	%f219, %f217, %f218;
+$L__tmp76:
+	.loc	2 243 36
+	mov.b32 	%r141, %f219;
+	shfl.sync.bfly.b32	%r142, %r141, 4, 31, -1;
+	mov.b32 	%f220, %r142;
+$L__tmp77:
+	.loc	2 233 15
+	add.f32 	%f221, %f219, %f220;
+$L__tmp78:
+	.loc	2 243 36
+	mov.b32 	%r143, %f221;
+	shfl.sync.bfly.b32	%r144, %r143, 2, 31, -1;
+	mov.b32 	%f222, %r144;
+$L__tmp79:
+	.loc	2 233 15
+	add.f32 	%f223, %f221, %f222;
+$L__tmp80:
+	.loc	2 243 36
+	mov.b32 	%r145, %f223;
+	shfl.sync.bfly.b32	%r146, %r145, 1, 31, -1;
+	mov.b32 	%f224, %r146;
+$L__tmp81:
+	.loc	2 233 15
+	add.f32 	%f225, %f223, %f224;
+$L__tmp82:
+	.loc	2 243 36
+	setp.eq.s32 	%p52, %r65, 0;
+	shl.b32 	%r147, %r66, 2;
+	mov.u32 	%r148, global_smem;
+	add.s32 	%r45, %r148, %r147;
+	mov.b32 	%r46, %f155;
+	@%p52 st.shared.b32 [ %r45 + 0 ], %r46;
+	add.s32 	%r47, %r45, 32;
+	mov.b32 	%r48, %f165;
+	@%p52 st.shared.b32 [ %r47 + 0 ], %r48;
+	add.s32 	%r49, %r45, 64;
+	mov.b32 	%r50, %f175;
+	@%p52 st.shared.b32 [ %r49 + 0 ], %r50;
+	add.s32 	%r51, %r45, 96;
+	mov.b32 	%r52, %f185;
+	@%p52 st.shared.b32 [ %r51 + 0 ], %r52;
+	add.s32 	%r53, %r45, 128;
+	mov.b32 	%r54, %f195;
+	@%p52 st.shared.b32 [ %r53 + 0 ], %r54;
+	add.s32 	%r55, %r45, 160;
+	mov.b32 	%r56, %f205;
+	@%p52 st.shared.b32 [ %r55 + 0 ], %r56;
+	add.s32 	%r57, %r45, 192;
+	mov.b32 	%r58, %f215;
+	@%p52 st.shared.b32 [ %r57 + 0 ], %r58;
+	add.s32 	%r59, %r45, 224;
+	mov.b32 	%r60, %f225;
+	@%p52 st.shared.b32 [ %r59 + 0 ], %r60;
+	bar.sync 	0;
+	setp.lt.s32 	%p60, %r1, 64;
+	shl.b32 	%r149, %r1, 2;
+	add.s32 	%r62, %r148, %r149;
+	@%p60 ld.shared.b32 %r61, [ %r62 + 0 ];
+	mov.b32 	%f226, %r61;
+	shfl.sync.bfly.b32	%r150, %r61, 4, 31, -1;
+	mov.b32 	%f227, %r150;
+$L__tmp83:
+	.loc	2 233 15
+	add.f32 	%f228, %f226, %f227;
+$L__tmp84:
+	.loc	2 243 36
+	mov.b32 	%r151, %f228;
+	shfl.sync.bfly.b32	%r152, %r151, 2, 31, -1;
+	mov.b32 	%f229, %r152;
+$L__tmp85:
+	.loc	2 233 15
+	add.f32 	%f230, %f228, %f229;
+$L__tmp86:
+	.loc	2 243 36
+	mov.b32 	%r153, %f230;
+	shfl.sync.bfly.b32	%r154, %r153, 1, 31, -1;
+	mov.b32 	%f231, %r154;
+$L__tmp87:
+	.loc	2 233 15
+	add.f32 	%f232, %f230, %f231;
+$L__tmp88:
+	.loc	2 243 36
+	and.b32  	%r155, %r1, 7;
+	setp.eq.s32 	%p62, %r155, 0;
+	and.pred  	%p61, %p60, %p62;
+	mov.b32 	%r64, %f232;
+	@%p61 st.shared.b32 [ %r62 + 0 ], %r64;
+	bar.sync 	0;
+	ld.shared.f32 	%f57, [global_smem];
+	ld.shared.f32 	%f58, [global_smem+32];
+	ld.shared.f32 	%f59, [global_smem+64];
+	ld.shared.f32 	%f60, [global_smem+96];
+	ld.shared.f32 	%f61, [global_smem+128];
+	ld.shared.f32 	%f62, [global_smem+160];
+	ld.shared.f32 	%f63, [global_smem+192];
+	ld.shared.f32 	%f64, [global_smem+224];
+$L__tmp89:
+	.loc	1 51 36
+	mul.lo.s64 	%rd10, %rd1, 804112;
+	shl.b64 	%rd88, %rd3, 1;
+	add.s64 	%rd164, %rd39, %rd88;
+	add.s64 	%rd163, %rd38, %rd88;
+	shl.b64 	%rd13, %rd3, 2;
+	mul.lo.s64 	%rd89, %rd1, 1608224;
+	add.s64 	%rd162, %rd36, %rd89;
+	add.s64 	%rd161, %rd37, %rd88;
+	shl.b64 	%rd90, %rd2, 1;
+	add.s64 	%rd160, %rd39, %rd90;
+	add.s64 	%rd159, %rd38, %rd90;
+	shl.b64 	%rd18, %rd2, 2;
+	add.s64 	%rd158, %rd37, %rd90;
+	mov.u64 	%rd165, 0;
+	mov.u16 	%rs2, 0;
+$L__BB0_3:
+	.loc	1 52 27
+	add.s64 	%rd155, %rd2, %rd165;
+	.loc	1 53 25
+	add.s64 	%rd156, %rd3, %rd165;
+	setp.lt.u64 	%p63, %rd155, 50257;
+	setp.lt.u64 	%p65, %rd156, 50257;
+	.loc	1 55 35
+	add.s64 	%rd91, %rd158, %rd10;
+	add.s64 	%rd92, %rd161, %rd10;
+	add.s64 	%rd93, %rd91, 100514;
+	add.s64 	%rd94, %rd92, 100514;
+	add.s64 	%rd95, %rd91, 201028;
+	add.s64 	%rd96, %rd92, 201028;
+	add.s64 	%rd97, %rd91, 301542;
+	add.s64 	%rd98, %rd92, 301542;
+	add.s64 	%rd99, %rd91, 402056;
+	add.s64 	%rd100, %rd92, 402056;
+	add.s64 	%rd101, %rd91, 502570;
+	add.s64 	%rd102, %rd92, 502570;
+	add.s64 	%rd103, %rd91, 603084;
+	add.s64 	%rd104, %rd92, 603084;
+	add.s64 	%rd105, %rd91, 703598;
+	.loc	1 55 53
+	add.s64 	%rd106, %rd92, 703598;
+	mov.u16 %rs1, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs1 }, [ %rd91 + 0 ];
+	@!%p63 mov.u16 %rs1, %rs2;
+	mov.u16 %rs3, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs3 }, [ %rd92 + 0 ];
+	@!%p65 mov.u16 %rs3, %rs2;
+	mov.u16 %rs5, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs5 }, [ %rd93 + 0 ];
+	@!%p63 mov.u16 %rs5, %rs2;
+	mov.u16 %rs7, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs7 }, [ %rd94 + 0 ];
+	@!%p65 mov.u16 %rs7, %rs2;
+	mov.u16 %rs9, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs9 }, [ %rd95 + 0 ];
+	@!%p63 mov.u16 %rs9, %rs2;
+	mov.u16 %rs11, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs11 }, [ %rd96 + 0 ];
+	@!%p65 mov.u16 %rs11, %rs2;
+	mov.u16 %rs13, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs13 }, [ %rd97 + 0 ];
+	@!%p63 mov.u16 %rs13, %rs2;
+	mov.u16 %rs15, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs15 }, [ %rd98 + 0 ];
+	@!%p65 mov.u16 %rs15, %rs2;
+	mov.u16 %rs17, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs17 }, [ %rd99 + 0 ];
+	@!%p63 mov.u16 %rs17, %rs2;
+	mov.u16 %rs19, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs19 }, [ %rd100 + 0 ];
+	@!%p65 mov.u16 %rs19, %rs2;
+	mov.u16 %rs21, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs21 }, [ %rd101 + 0 ];
+	@!%p63 mov.u16 %rs21, %rs2;
+	mov.u16 %rs23, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs23 }, [ %rd102 + 0 ];
+	@!%p65 mov.u16 %rs23, %rs2;
+	mov.u16 %rs25, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs25 }, [ %rd103 + 0 ];
+	@!%p63 mov.u16 %rs25, %rs2;
+	mov.u16 %rs27, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs27 }, [ %rd104 + 0 ];
+	@!%p65 mov.u16 %rs27, %rs2;
+	mov.u16 %rs29, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs29 }, [ %rd105 + 0 ];
+	@!%p63 mov.u16 %rs29, %rs2;
+	mov.u16 %rs31, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs31 }, [ %rd106 + 0 ];
+	@!%p65 mov.u16 %rs31, %rs2;
+	.loc	1 55 105
+	cvt.f32.bf16 %r156, %rs1;
+	mov.b32 	%f265, %r156;
+	cvt.f32.bf16 %r157, %rs3;
+	mov.b32 	%f266, %r157;
+	cvt.f32.bf16 %r158, %rs5;
+	mov.b32 	%f267, %r158;
+	cvt.f32.bf16 %r159, %rs7;
+	mov.b32 	%f268, %r159;
+	cvt.f32.bf16 %r160, %rs9;
+	mov.b32 	%f269, %r160;
+	cvt.f32.bf16 %r161, %rs11;
+	mov.b32 	%f270, %r161;
+	cvt.f32.bf16 %r162, %rs13;
+	mov.b32 	%f271, %r162;
+	cvt.f32.bf16 %r163, %rs15;
+	mov.b32 	%f272, %r163;
+	cvt.f32.bf16 %r164, %rs17;
+	mov.b32 	%f273, %r164;
+	cvt.f32.bf16 %r165, %rs19;
+	mov.b32 	%f274, %r165;
+	cvt.f32.bf16 %r166, %rs21;
+	mov.b32 	%f275, %r166;
+	cvt.f32.bf16 %r167, %rs23;
+	mov.b32 	%f276, %r167;
+	cvt.f32.bf16 %r168, %rs25;
+	mov.b32 	%f277, %r168;
+	cvt.f32.bf16 %r169, %rs27;
+	mov.b32 	%f278, %r169;
+	cvt.f32.bf16 %r170, %rs29;
+	mov.b32 	%f279, %r170;
+	cvt.f32.bf16 %r171, %rs31;
+	mov.b32 	%f280, %r171;
+	.loc	1 56 35
+	add.s64 	%rd107, %rd162, %rd18;
+	add.s64 	%rd108, %rd162, %rd13;
+	add.s64 	%rd109, %rd107, 201028;
+	add.s64 	%rd110, %rd108, 201028;
+	add.s64 	%rd111, %rd107, 402056;
+	add.s64 	%rd112, %rd108, 402056;
+	add.s64 	%rd113, %rd107, 603084;
+	add.s64 	%rd114, %rd108, 603084;
+	add.s64 	%rd115, %rd107, 804112;
+	add.s64 	%rd116, %rd108, 804112;
+	add.s64 	%rd117, %rd107, 1005140;
+	add.s64 	%rd118, %rd108, 1005140;
+	add.s64 	%rd119, %rd107, 1206168;
+	add.s64 	%rd120, %rd108, 1206168;
+	add.s64 	%rd121, %rd107, 1407196;
+	.loc	1 56 53
+	add.s64 	%rd122, %rd108, 1407196;
+	mov.u32 %r172, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r172 }, [ %rd107 + 0 ];
+	@!%p63 mov.u32 %r172, %r173;
+	mov.b32 	%f281, %r172;
+	mov.u32 %r174, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r174 }, [ %rd108 + 0 ];
+	@!%p65 mov.u32 %r174, %r173;
+	mov.b32 	%f282, %r174;
+	mov.u32 %r176, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r176 }, [ %rd109 + 0 ];
+	@!%p63 mov.u32 %r176, %r173;
+	mov.b32 	%f283, %r176;
+	mov.u32 %r178, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r178 }, [ %rd110 + 0 ];
+	@!%p65 mov.u32 %r178, %r173;
+	mov.b32 	%f284, %r178;
+	mov.u32 %r180, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r180 }, [ %rd111 + 0 ];
+	@!%p63 mov.u32 %r180, %r173;
+	mov.b32 	%f285, %r180;
+	mov.u32 %r182, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r182 }, [ %rd112 + 0 ];
+	@!%p65 mov.u32 %r182, %r173;
+	mov.b32 	%f286, %r182;
+	mov.u32 %r184, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r184 }, [ %rd113 + 0 ];
+	@!%p63 mov.u32 %r184, %r173;
+	mov.b32 	%f287, %r184;
+	mov.u32 %r186, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r186 }, [ %rd114 + 0 ];
+	@!%p65 mov.u32 %r186, %r173;
+	mov.b32 	%f288, %r186;
+	mov.u32 %r188, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r188 }, [ %rd115 + 0 ];
+	@!%p63 mov.u32 %r188, %r173;
+	mov.b32 	%f289, %r188;
+	mov.u32 %r190, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r190 }, [ %rd116 + 0 ];
+	@!%p65 mov.u32 %r190, %r173;
+	mov.b32 	%f290, %r190;
+	mov.u32 %r192, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r192 }, [ %rd117 + 0 ];
+	@!%p63 mov.u32 %r192, %r173;
+	mov.b32 	%f291, %r192;
+	mov.u32 %r194, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r194 }, [ %rd118 + 0 ];
+	@!%p65 mov.u32 %r194, %r173;
+	mov.b32 	%f292, %r194;
+	mov.u32 %r196, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r196 }, [ %rd119 + 0 ];
+	@!%p63 mov.u32 %r196, %r173;
+	mov.b32 	%f293, %r196;
+	mov.u32 %r198, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r198 }, [ %rd120 + 0 ];
+	@!%p65 mov.u32 %r198, %r173;
+	mov.b32 	%f294, %r198;
+	mov.u32 %r200, 0x0;
+	@%p63 ld.global.L1::evict_first.b32 { %r200 }, [ %rd121 + 0 ];
+	@!%p63 mov.u32 %r200, %r173;
+	mov.b32 	%f295, %r200;
+	mov.u32 %r202, 0x0;
+	@%p65 ld.global.L1::evict_first.b32 { %r202 }, [ %rd122 + 0 ];
+	@!%p65 mov.u32 %r202, %r173;
+	mov.b32 	%f296, %r202;
+	.loc	1 57 35
+	add.s64 	%rd123, %rd159, %rd10;
+	add.s64 	%rd124, %rd163, %rd10;
+	add.s64 	%rd125, %rd123, 100514;
+	add.s64 	%rd126, %rd124, 100514;
+	add.s64 	%rd127, %rd123, 201028;
+	add.s64 	%rd128, %rd124, 201028;
+	add.s64 	%rd129, %rd123, 301542;
+	add.s64 	%rd130, %rd124, 301542;
+	add.s64 	%rd131, %rd123, 402056;
+	add.s64 	%rd132, %rd124, 402056;
+	add.s64 	%rd133, %rd123, 502570;
+	add.s64 	%rd134, %rd124, 502570;
+	add.s64 	%rd135, %rd123, 603084;
+	add.s64 	%rd136, %rd124, 603084;
+	add.s64 	%rd137, %rd123, 703598;
+	.loc	1 57 53
+	add.s64 	%rd138, %rd124, 703598;
+	mov.u16 %rs49, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs49 }, [ %rd123 + 0 ];
+	@!%p63 mov.u16 %rs49, %rs2;
+	mov.u16 %rs51, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs51 }, [ %rd124 + 0 ];
+	@!%p65 mov.u16 %rs51, %rs2;
+	mov.u16 %rs53, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs53 }, [ %rd125 + 0 ];
+	@!%p63 mov.u16 %rs53, %rs2;
+	mov.u16 %rs55, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs55 }, [ %rd126 + 0 ];
+	@!%p65 mov.u16 %rs55, %rs2;
+	mov.u16 %rs57, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs57 }, [ %rd127 + 0 ];
+	@!%p63 mov.u16 %rs57, %rs2;
+	mov.u16 %rs59, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs59 }, [ %rd128 + 0 ];
+	@!%p65 mov.u16 %rs59, %rs2;
+	mov.u16 %rs61, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs61 }, [ %rd129 + 0 ];
+	@!%p63 mov.u16 %rs61, %rs2;
+	mov.u16 %rs63, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs63 }, [ %rd130 + 0 ];
+	@!%p65 mov.u16 %rs63, %rs2;
+	mov.u16 %rs65, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs65 }, [ %rd131 + 0 ];
+	@!%p63 mov.u16 %rs65, %rs2;
+	mov.u16 %rs67, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs67 }, [ %rd132 + 0 ];
+	@!%p65 mov.u16 %rs67, %rs2;
+	mov.u16 %rs69, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs69 }, [ %rd133 + 0 ];
+	@!%p63 mov.u16 %rs69, %rs2;
+	mov.u16 %rs71, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs71 }, [ %rd134 + 0 ];
+	@!%p65 mov.u16 %rs71, %rs2;
+	mov.u16 %rs73, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs73 }, [ %rd135 + 0 ];
+	@!%p63 mov.u16 %rs73, %rs2;
+	mov.u16 %rs75, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs75 }, [ %rd136 + 0 ];
+	@!%p65 mov.u16 %rs75, %rs2;
+	mov.u16 %rs77, 0x0;
+	@%p63 ld.global.L1::evict_first.b16 { %rs77 }, [ %rd137 + 0 ];
+	@!%p63 mov.u16 %rs77, %rs2;
+	mov.u16 %rs79, 0x0;
+	@%p65 ld.global.L1::evict_first.b16 { %rs79 }, [ %rd138 + 0 ];
+	@!%p65 mov.u16 %rs79, %rs2;
+	.loc	1 57 105
+	cvt.f32.bf16 %r204, %rs49;
+	mov.b32 	%f297, %r204;
+	cvt.f32.bf16 %r205, %rs51;
+	mov.b32 	%f298, %r205;
+	cvt.f32.bf16 %r206, %rs53;
+	mov.b32 	%f299, %r206;
+	cvt.f32.bf16 %r207, %rs55;
+	mov.b32 	%f300, %r207;
+	cvt.f32.bf16 %r208, %rs57;
+	mov.b32 	%f301, %r208;
+	cvt.f32.bf16 %r209, %rs59;
+	mov.b32 	%f302, %r209;
+	cvt.f32.bf16 %r210, %rs61;
+	mov.b32 	%f303, %r210;
+	cvt.f32.bf16 %r211, %rs63;
+	mov.b32 	%f304, %r211;
+	cvt.f32.bf16 %r212, %rs65;
+	mov.b32 	%f305, %r212;
+	cvt.f32.bf16 %r213, %rs67;
+	mov.b32 	%f306, %r213;
+	cvt.f32.bf16 %r214, %rs69;
+	mov.b32 	%f307, %r214;
+	cvt.f32.bf16 %r215, %rs71;
+	mov.b32 	%f308, %r215;
+	cvt.f32.bf16 %r216, %rs73;
+	mov.b32 	%f309, %r216;
+	cvt.f32.bf16 %r217, %rs75;
+	mov.b32 	%f310, %r217;
+	cvt.f32.bf16 %r218, %rs77;
+	mov.b32 	%f311, %r218;
+	cvt.f32.bf16 %r219, %rs79;
+	mov.b32 	%f312, %r219;
+	.loc	1 65 23
+	mul.f32 	%f234, %f297, 0f3FB8AA3B;
+	ex2.approx.f32 %f233, %f234;
+	mul.f32 	%f236, %f298, 0f3FB8AA3B;
+	ex2.approx.f32 %f235, %f236;
+	mul.f32 	%f238, %f299, 0f3FB8AA3B;
+	ex2.approx.f32 %f237, %f238;
+	mul.f32 	%f240, %f300, 0f3FB8AA3B;
+	ex2.approx.f32 %f239, %f240;
+	mul.f32 	%f242, %f301, 0f3FB8AA3B;
+	ex2.approx.f32 %f241, %f242;
+	mul.f32 	%f244, %f302, 0f3FB8AA3B;
+	ex2.approx.f32 %f243, %f244;
+	mul.f32 	%f246, %f303, 0f3FB8AA3B;
+	ex2.approx.f32 %f245, %f246;
+	mul.f32 	%f248, %f304, 0f3FB8AA3B;
+	ex2.approx.f32 %f247, %f248;
+	mul.f32 	%f250, %f305, 0f3FB8AA3B;
+	ex2.approx.f32 %f249, %f250;
+	mul.f32 	%f252, %f306, 0f3FB8AA3B;
+	ex2.approx.f32 %f251, %f252;
+	mul.f32 	%f254, %f307, 0f3FB8AA3B;
+	ex2.approx.f32 %f253, %f254;
+	mul.f32 	%f256, %f308, 0f3FB8AA3B;
+	ex2.approx.f32 %f255, %f256;
+	mul.f32 	%f258, %f309, 0f3FB8AA3B;
+	ex2.approx.f32 %f257, %f258;
+	mul.f32 	%f260, %f310, 0f3FB8AA3B;
+	ex2.approx.f32 %f259, %f260;
+	mul.f32 	%f262, %f311, 0f3FB8AA3B;
+	ex2.approx.f32 %f261, %f262;
+	mul.f32 	%f264, %f312, 0f3FB8AA3B;
+	ex2.approx.f32 %f263, %f264;
+	.loc	1 66 24
+	mul.f32 	%f313, %f57, %f233;
+	mul.f32 	%f314, %f57, %f235;
+	mul.f32 	%f315, %f58, %f237;
+	mul.f32 	%f316, %f58, %f239;
+	mul.f32 	%f317, %f59, %f241;
+	mul.f32 	%f318, %f59, %f243;
+	mul.f32 	%f319, %f60, %f245;
+	mul.f32 	%f320, %f60, %f247;
+	mul.f32 	%f321, %f61, %f249;
+	mul.f32 	%f322, %f61, %f251;
+	mul.f32 	%f323, %f62, %f253;
+	mul.f32 	%f324, %f62, %f255;
+	mul.f32 	%f325, %f63, %f257;
+	mul.f32 	%f326, %f63, %f259;
+	mul.f32 	%f327, %f64, %f261;
+	mul.f32 	%f328, %f64, %f263;
+	.loc	1 67 24
+	neg.f32 	%f329, %f313;
+	fma.rn.f32 	%f330, %f1, %f281, %f329;
+	neg.f32 	%f331, %f314;
+	fma.rn.f32 	%f332, %f1, %f282, %f331;
+	neg.f32 	%f333, %f315;
+	fma.rn.f32 	%f334, %f2, %f283, %f333;
+	neg.f32 	%f335, %f316;
+	fma.rn.f32 	%f336, %f2, %f284, %f335;
+	neg.f32 	%f337, %f317;
+	fma.rn.f32 	%f338, %f3, %f285, %f337;
+	neg.f32 	%f339, %f318;
+	fma.rn.f32 	%f340, %f3, %f286, %f339;
+	neg.f32 	%f341, %f319;
+	fma.rn.f32 	%f342, %f4, %f287, %f341;
+	neg.f32 	%f343, %f320;
+	fma.rn.f32 	%f344, %f4, %f288, %f343;
+	neg.f32 	%f345, %f321;
+	fma.rn.f32 	%f346, %f5, %f289, %f345;
+	neg.f32 	%f347, %f322;
+	fma.rn.f32 	%f348, %f5, %f290, %f347;
+	neg.f32 	%f349, %f323;
+	fma.rn.f32 	%f350, %f6, %f291, %f349;
+	neg.f32 	%f351, %f324;
+	fma.rn.f32 	%f352, %f6, %f292, %f351;
+	neg.f32 	%f353, %f325;
+	fma.rn.f32 	%f354, %f7, %f293, %f353;
+	neg.f32 	%f355, %f326;
+	fma.rn.f32 	%f356, %f7, %f294, %f355;
+	neg.f32 	%f357, %f327;
+	fma.rn.f32 	%f358, %f8, %f295, %f357;
+	neg.f32 	%f359, %f328;
+	fma.rn.f32 	%f360, %f8, %f296, %f359;
+	.loc	1 69 24
+	add.f32 	%f361, %f265, %f330;
+	add.f32 	%f362, %f266, %f332;
+	add.f32 	%f363, %f267, %f334;
+	add.f32 	%f364, %f268, %f336;
+	add.f32 	%f365, %f269, %f338;
+	add.f32 	%f366, %f270, %f340;
+	add.f32 	%f367, %f271, %f342;
+	add.f32 	%f368, %f272, %f344;
+	add.f32 	%f369, %f273, %f346;
+	add.f32 	%f370, %f274, %f348;
+	add.f32 	%f371, %f275, %f350;
+	add.f32 	%f372, %f276, %f352;
+	add.f32 	%f373, %f277, %f354;
+	add.f32 	%f374, %f278, %f356;
+	add.f32 	%f375, %f279, %f358;
+	add.f32 	%f376, %f280, %f360;
+	.loc	1 70 29
+	add.s64 	%rd139, %rd160, %rd10;
+	add.s64 	%rd140, %rd164, %rd10;
+	add.s64 	%rd141, %rd139, 100514;
+	add.s64 	%rd142, %rd140, 100514;
+	add.s64 	%rd143, %rd139, 201028;
+	add.s64 	%rd144, %rd140, 201028;
+	add.s64 	%rd145, %rd139, 301542;
+	add.s64 	%rd146, %rd140, 301542;
+	add.s64 	%rd147, %rd139, 402056;
+	add.s64 	%rd148, %rd140, 402056;
+	add.s64 	%rd149, %rd139, 502570;
+	add.s64 	%rd150, %rd140, 502570;
+	add.s64 	%rd151, %rd139, 603084;
+	add.s64 	%rd152, %rd140, 603084;
+	add.s64 	%rd153, %rd139, 703598;
+	.loc	1 70 54
+	add.s64 	%rd154, %rd140, 703598;
+	mov.b32 	%r220, %f361;
+	cvt.rn.bf16.f32 %rs97, %r220;
+	mov.b32 	%r221, %f362;
+	cvt.rn.bf16.f32 %rs98, %r221;
+	mov.b32 	%r222, %f363;
+	cvt.rn.bf16.f32 %rs99, %r222;
+	mov.b32 	%r223, %f364;
+	cvt.rn.bf16.f32 %rs100, %r223;
+	mov.b32 	%r224, %f365;
+	cvt.rn.bf16.f32 %rs101, %r224;
+	mov.b32 	%r225, %f366;
+	cvt.rn.bf16.f32 %rs102, %r225;
+	mov.b32 	%r226, %f367;
+	cvt.rn.bf16.f32 %rs103, %r226;
+	mov.b32 	%r227, %f368;
+	cvt.rn.bf16.f32 %rs104, %r227;
+	mov.b32 	%r228, %f369;
+	cvt.rn.bf16.f32 %rs105, %r228;
+	mov.b32 	%r229, %f370;
+	cvt.rn.bf16.f32 %rs106, %r229;
+	mov.b32 	%r230, %f371;
+	cvt.rn.bf16.f32 %rs107, %r230;
+	mov.b32 	%r231, %f372;
+	cvt.rn.bf16.f32 %rs108, %r231;
+	mov.b32 	%r232, %f373;
+	cvt.rn.bf16.f32 %rs109, %r232;
+	mov.b32 	%r233, %f374;
+	cvt.rn.bf16.f32 %rs110, %r233;
+	mov.b32 	%r234, %f375;
+	cvt.rn.bf16.f32 %rs111, %r234;
+	mov.b32 	%r235, %f376;
+	cvt.rn.bf16.f32 %rs112, %r235;
+	@%p63 st.global.b16 [ %rd139 + 0 ], { %rs97 };
+	@%p65 st.global.b16 [ %rd140 + 0 ], { %rs98 };
+	@%p63 st.global.b16 [ %rd141 + 0 ], { %rs99 };
+	@%p65 st.global.b16 [ %rd142 + 0 ], { %rs100 };
+	@%p63 st.global.b16 [ %rd143 + 0 ], { %rs101 };
+	@%p65 st.global.b16 [ %rd144 + 0 ], { %rs102 };
+	@%p63 st.global.b16 [ %rd145 + 0 ], { %rs103 };
+	@%p65 st.global.b16 [ %rd146 + 0 ], { %rs104 };
+	@%p63 st.global.b16 [ %rd147 + 0 ], { %rs105 };
+	@%p65 st.global.b16 [ %rd148 + 0 ], { %rs106 };
+	@%p63 st.global.b16 [ %rd149 + 0 ], { %rs107 };
+	@%p65 st.global.b16 [ %rd150 + 0 ], { %rs108 };
+	@%p63 st.global.b16 [ %rd151 + 0 ], { %rs109 };
+	@%p65 st.global.b16 [ %rd152 + 0 ], { %rs110 };
+	@%p63 st.global.b16 [ %rd153 + 0 ], { %rs111 };
+	@%p65 st.global.b16 [ %rd154 + 0 ], { %rs112 };
+	.loc	1 51 36
+	add.s64 	%rd165, %rd165, 512;
+	cvt.u32.u64 	%r236, %rd165;
+	add.s32 	%r237, %r236, -512;
+	add.s64 	%rd164, %rd164, 1024;
+	add.s64 	%rd163, %rd163, 1024;
+	add.s64 	%rd162, %rd162, 2048;
+	add.s64 	%rd161, %rd161, 1024;
+	add.s64 	%rd160, %rd160, 1024;
+	add.s64 	%rd159, %rd159, 1024;
+	add.s64 	%rd158, %rd158, 1024;
+	setp.lt.u32 	%p175, %r237, 49745;
+	@%p175 bra 	$L__BB0_3;
+	.loc	1 51 4
+	ret;
+$L__tmp90:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/kz/ckzgl7thb4xdfkfnd2tidks6mt5f3hauwfyjflbtzyepo5oxkvhk.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
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+.b8 5
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+.b8 49
+.b8 19
+.b8 17
+.b8 1
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+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 278
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
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+.b8 53
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+.b8 51
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+.b8 97
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+.b8 111
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+.b8 107
+.b8 118
+.b8 104
+.b8 107
+.b8 46
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+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
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+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
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+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
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+.b8 116
+.b8 47
+.b8 107
+.b8 122
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
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+.b8 100
+.b8 49
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+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp88
+.b8 2
+.b8 46
+.b8 27
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp88
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp89
+.b8 2
+.b8 46
+.b8 27
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
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+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 101
+.b8 56
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/33dcd7dc40e8b1089e9a4c61a9c826b5/triton_.ttgir

@@ -0,0 +1,92 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 8], order = [1, 0], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7de8(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg7: i64 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg8: i64) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<8x1xf32, #blocked>
+    %cst_0 = arith.constant dense<50257> : tensor<8x1xi64, #blocked>
+    %cst_1 = arith.constant dense<-1> : tensor<8x1xi64, #blocked>
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<8x512xf32, #blocked>
+    %c8_i64 = arith.constant 8 : i64
+    %cst_3 = arith.constant dense<50257> : tensor<1x512xi64, #blocked>
+    %c0_i32 = arith.constant 0 : i32
+    %c512_i32 = arith.constant 512 : i32
+    %c50257_i32 = arith.constant 50257 : i32
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<8x512xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = arith.extsi %0 : i32 to i64
+    %2 = arith.muli %1, %c8_i64 : i64
+    %3 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %4 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<8x1xi32, #blocked>
+    %5 = arith.extsi %4 : tensor<8x1xi32, #blocked> to tensor<8x1xi64, #blocked>
+    %6 = tt.splat %2 : (i64) -> tensor<8x1xi64, #blocked>
+    %7 = arith.addi %6, %5 : tensor<8x1xi64, #blocked>
+    %8 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>
+    %9 = tt.expand_dims %8 {axis = 0 : i32} : (tensor<512xi32, #triton_gpu.slice<{dim = 0, parent = #blocked}>>) -> tensor<1x512xi32, #blocked>
+    %10 = arith.extsi %9 : tensor<1x512xi32, #blocked> to tensor<1x512xi64, #blocked>
+    %11 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<8x1x!tt.ptr<i64, 1>, #blocked>
+    %12 = tt.addptr %11, %7 : tensor<8x1x!tt.ptr<i64, 1>, #blocked>, tensor<8x1xi64, #blocked>
+    %13 = tt.load %12 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<8x1xi64, #blocked>
+    %14 = tt.addptr %arg2, %c0_i32 : !tt.ptr<f32, 1>, i32
+    %15 = tt.load %14 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : f32
+    %16 = tt.addptr %arg3, %c0_i32 : !tt.ptr<f32, 1>, i32
+    %17 = tt.load %16 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : f32
+    %18 = arith.muli %7, %cst_0 : tensor<8x1xi64, #blocked>
+    %19 = tt.broadcast %18 : (tensor<8x1xi64, #blocked>) -> tensor<8x512xi64, #blocked>
+    %20 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<8x512x!tt.ptr<f32, 1>, #blocked>
+    %21 = arith.cmpi ne, %13, %cst_1 : tensor<8x1xi64, #blocked>
+    %22 = arith.divf %15, %17 : f32
+    %23 = tt.splat %22 : (f32) -> tensor<8x1xf32, #blocked>
+    %24 = arith.select %21, %23, %cst : tensor<8x1xi1, #blocked>, tensor<8x1xf32, #blocked>
+    %25 = tt.broadcast %24 : (tensor<8x1xf32, #blocked>) -> tensor<8x512xf32, #blocked>
+    %26 = scf.for %arg9 = %c0_i32 to %c50257_i32 step %c512_i32 iter_args(%arg10 = %cst_2) -> (tensor<8x512xf32, #blocked>)  : i32 {
+      %33 = arith.extsi %arg9 : i32 to i64
+      %34 = tt.splat %33 : (i64) -> tensor<1x512xi64, #blocked>
+      %35 = arith.addi %34, %10 : tensor<1x512xi64, #blocked>
+      %36 = arith.cmpi slt, %35, %cst_3 : tensor<1x512xi64, #blocked>
+      %37 = tt.broadcast %35 : (tensor<1x512xi64, #blocked>) -> tensor<8x512xi64, #blocked>
+      %38 = arith.addi %37, %19 : tensor<8x512xi64, #blocked>
+      %39 = tt.addptr %20, %38 : tensor<8x512x!tt.ptr<f32, 1>, #blocked>, tensor<8x512xi64, #blocked>
+      %40 = tt.broadcast %36 : (tensor<1x512xi1, #blocked>) -> tensor<8x512xi1, #blocked>
+      %41 = tt.load %39, %40, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<8x512xf32, #blocked>
+      %42 = arith.mulf %41, %25 : tensor<8x512xf32, #blocked>
+      %43 = arith.addf %arg10, %42 : tensor<8x512xf32, #blocked>
+      %44 = arith.select %40, %43, %arg10 : tensor<8x512xi1, #blocked>, tensor<8x512xf32, #blocked>
+      scf.yield %44 : tensor<8x512xf32, #blocked>
+    }
+    %27 = "tt.reduce"(%26) <{axis = 1 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %33 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %33 : f32
+    }) : (tensor<8x512xf32, #blocked>) -> tensor<8xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %28 = tt.expand_dims %27 {axis = 1 : i32} : (tensor<8xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<8x1xf32, #blocked>
+    %29 = tt.splat %arg4 : (!tt.ptr<bf16, 1>) -> tensor<8x512x!tt.ptr<bf16, 1>, #blocked>
+    %30 = tt.splat %arg5 : (!tt.ptr<bf16, 1>) -> tensor<8x512x!tt.ptr<bf16, 1>, #blocked>
+    %31 = tt.broadcast %28 : (tensor<8x1xf32, #blocked>) -> tensor<8x512xf32, #blocked>
+    %32 = tt.splat %arg6 : (!tt.ptr<bf16, 1>) -> tensor<8x512x!tt.ptr<bf16, 1>, #blocked>
+    scf.for %arg9 = %c0_i32 to %c50257_i32 step %c512_i32  : i32 {
+      %33 = arith.extsi %arg9 : i32 to i64
+      %34 = tt.splat %33 : (i64) -> tensor<1x512xi64, #blocked>
+      %35 = arith.addi %34, %10 : tensor<1x512xi64, #blocked>
+      %36 = arith.cmpi slt, %35, %cst_3 : tensor<1x512xi64, #blocked>
+      %37 = tt.broadcast %35 : (tensor<1x512xi64, #blocked>) -> tensor<8x512xi64, #blocked>
+      %38 = arith.addi %37, %19 : tensor<8x512xi64, #blocked>
+      %39 = tt.addptr %29, %38 : tensor<8x512x!tt.ptr<bf16, 1>, #blocked>, tensor<8x512xi64, #blocked>
+      %40 = tt.broadcast %36 : (tensor<1x512xi1, #blocked>) -> tensor<8x512xi1, #blocked>
+      %41 = tt.load %39, %40, %cst_4 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<8x512xbf16, #blocked>
+      %42 = arith.extf %41 : tensor<8x512xbf16, #blocked> to tensor<8x512xf32, #blocked>
+      %43 = tt.addptr %20, %38 : tensor<8x512x!tt.ptr<f32, 1>, #blocked>, tensor<8x512xi64, #blocked>
+      %44 = tt.load %43, %40, %cst_2 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<8x512xf32, #blocked>
+      %45 = tt.addptr %30, %38 : tensor<8x512x!tt.ptr<bf16, 1>, #blocked>, tensor<8x512xi64, #blocked>
+      %46 = tt.load %45, %40, %cst_4 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<8x512xbf16, #blocked>
+      %47 = arith.extf %46 : tensor<8x512xbf16, #blocked> to tensor<8x512xf32, #blocked>
+      %48 = arith.mulf %44, %25 : tensor<8x512xf32, #blocked>
+      %49 = math.exp %47 : tensor<8x512xf32, #blocked>
+      %50 = arith.mulf %49, %31 : tensor<8x512xf32, #blocked>
+      %51 = arith.subf %48, %50 : tensor<8x512xf32, #blocked>
+      %52 = arith.addf %42, %51 : tensor<8x512xf32, #blocked>
+      %53 = tt.addptr %32, %38 : tensor<8x512x!tt.ptr<bf16, 1>, #blocked>, tensor<8x512xi64, #blocked>
+      %54 = arith.truncf %52 : tensor<8x512xf32, #blocked> to tensor<8x512xbf16, #blocked>
+      tt.store %53, %54, %40 {cache = 1 : i32, evict = 1 : i32} : tensor<8x512xbf16, #blocked>
+    }
+    tt.return
+  }
+}

.triton/dump/36c33e585c0636c631d3aeea97f0cc97/triton_.llir

@@ -0,0 +1,43 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1de(ptr addrspace(1) %0, i32 %1) local_unnamed_addr !dbg !5 {
+  %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %4 = shl i32 %3, 1, !dbg !8
+  %5 = and i32 %4, 510, !dbg !8
+  %6 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %7 = shl i32 %6, 9, !dbg !10
+  %8 = or i32 %7, %5, !dbg !11
+  %9 = icmp slt i32 %8, 12865792, !dbg !12
+  %10 = sext i32 %8 to i64, !dbg !13
+  %11 = getelementptr float, ptr addrspace(1) %0, i64 %10, !dbg !13
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 0, i32 0, ptr addrspace(1) %11, i1 %9) #1, !dbg !14
+  ret void, !dbg !15
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c4yseldwmu3to52pbh2md2oeufrq3fcdmapkt4nxdzmyqtgd2ysp.py", directory: "/tmp/torchinductor_root/4y")
+!3 = !{ptr @triton__0d1de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1de, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1de", linkageName: "triton__0d1de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 22, column: 21, scope: !5)
+!13 = !DILocation(line: 25, column: 25, scope: !5)
+!14 = !DILocation(line: 25, column: 36, scope: !5)
+!15 = !DILocation(line: 25, column: 4, scope: !5)

.triton/dump/36c33e585c0636c631d3aeea97f0cc97/triton_.ptx

@@ -0,0 +1,278 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1de
+
+.visible .entry triton__0d1de(
+	.param .u64 triton__0d1de_param_0,
+	.param .u32 triton__0d1de_param_1
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<2>;
+	.reg .b32 	%r<9>;
+	.reg .b64 	%rd<4>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd2, [triton__0d1de_param_0];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r4, %tid.x;
+	shl.b32 	%r5, %r4, 1;
+	and.b32  	%r6, %r5, 510;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r7, %r1, 9;
+	.loc	1 21 23
+	or.b32  	%r8, %r7, %r6;
+	.loc	1 22 21
+	setp.lt.s32 	%p1, %r8, 12865792;
+	.loc	1 25 25
+	mul.wide.s32 	%rd3, %r8, 4;
+	add.s64 	%rd1, %rd2, %rd3;
+	mov.b32 	%r2, 0;
+	.loc	1 25 36
+	@%p1 st.global.v2.b32 [ %rd1 + 0 ], { %r2, %r2 };
+	.loc	1 25 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/4y/c4yseldwmu3to52pbh2md2oeufrq3fcdmapkt4nxdzmyqtgd2ysp.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
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+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 172
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
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+.b8 100
+.b8 50
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+.b8 115
+.b8 112
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
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+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 52
+.b8 121
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
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+.b8 100
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 176
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 176
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/36c33e585c0636c631d3aeea97f0cc97/triton_.ttgir

@@ -0,0 +1,18 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [8], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 8 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<12865792> : tensor<512xi32, #blocked>
+    %c512_i32 = arith.constant 512 : i32
+    %cst_0 = arith.constant dense<0.000000e+00> : tensor<512xf32, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<512xi32, #blocked>
+    %5 = arith.cmpi slt, %4, %cst : tensor<512xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>, #blocked>
+    %7 = tt.addptr %6, %4 : tensor<512x!tt.ptr<f32, 1>, #blocked>, tensor<512xi32, #blocked>
+    tt.store %7, %cst_0, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/36c33e585c0636c631d3aeea97f0cc97/triton_.ttir

@@ -0,0 +1,17 @@
+module {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<512xf32>
+    %cst_0 = arith.constant dense<12865792> : tensor<512xi32>
+    %c512_i32 = arith.constant 512 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32>
+    %4 = arith.addi %3, %2 : tensor<512xi32>
+    %5 = arith.cmpi slt, %4, %cst_0 : tensor<512xi32>
+    %6 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>>
+    %7 = tt.addptr %6, %4 : tensor<512x!tt.ptr<f32, 1>>, tensor<512xi32>
+    tt.store %7, %cst, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32>
+    tt.return
+  }
+}

.triton/dump/3791d630ba27aad5e647360045d2f1b5/triton_.llir

@@ -0,0 +1,296 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@global_smem = external addrspace(3) global [0 x i8]
+
+define void @triton__0d1d2d3d4d5d6d7de8de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, ptr addrspace(1) %5, ptr addrspace(1) %6, i32 %7, i32 %8) local_unnamed_addr !dbg !5 {
+  %10 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %11 = and i32 %10, 31, !dbg !8
+  %12 = lshr i32 %10, 5, !dbg !8
+  %13 = and i32 %12, 1, !dbg !8
+  %urem = shl i32 %10, 2, !dbg !8
+  %14 = and i32 %urem, 252, !dbg !8
+  %15 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #3, !dbg !9
+  %16 = shl i32 %15, 8, !dbg !10
+  %17 = or i32 %16, %14, !dbg !11
+  %18 = sext i32 %17 to i64, !dbg !12
+  %19 = getelementptr i16, ptr addrspace(1) %1, i64 %18, !dbg !12
+  %20 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];\0A\09@!$5 mov.u32 $0, $4;\0A\09@!$7 mov.u32 $1, $6;", "=r,=r,l,b,r,b,r,b"(ptr addrspace(1) %19, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !13
+  %21 = extractvalue { i32, i32 } %20, 0, !dbg !13
+  %22 = extractvalue { i32, i32 } %20, 1, !dbg !13
+  %23 = trunc i32 %21 to i16, !dbg !13
+  %extelt.offset = lshr i32 %21, 16, !dbg !13
+  %24 = trunc i32 %extelt.offset to i16, !dbg !13
+  %25 = trunc i32 %22 to i16, !dbg !13
+  %extelt.offset1 = lshr i32 %22, 16, !dbg !13
+  %26 = trunc i32 %extelt.offset1 to i16, !dbg !13
+  %27 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %23) #3, !dbg !14
+  %28 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %24) #3, !dbg !14
+  %29 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %25) #3, !dbg !14
+  %30 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %26) #3, !dbg !14
+  %31 = zext nneg i32 %14 to i64, !dbg !15
+  %32 = getelementptr float, ptr addrspace(1) %2, i64 %31, !dbg !15
+  %33 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.L1::evict_last.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %32, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !16
+  %34 = extractvalue { i32, i32, i32, i32 } %33, 0, !dbg !16
+  %35 = extractvalue { i32, i32, i32, i32 } %33, 1, !dbg !16
+  %36 = extractvalue { i32, i32, i32, i32 } %33, 2, !dbg !16
+  %37 = extractvalue { i32, i32, i32, i32 } %33, 3, !dbg !16
+  %38 = bitcast i32 %34 to float, !dbg !16
+  %39 = bitcast i32 %35 to float, !dbg !16
+  %40 = bitcast i32 %36 to float, !dbg !16
+  %41 = bitcast i32 %37 to float, !dbg !16
+  %42 = getelementptr float, ptr addrspace(1) %3, i64 %18, !dbg !17
+  %43 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %42, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !18
+  %44 = extractvalue { i32, i32, i32, i32 } %43, 0, !dbg !18
+  %45 = extractvalue { i32, i32, i32, i32 } %43, 1, !dbg !18
+  %46 = extractvalue { i32, i32, i32, i32 } %43, 2, !dbg !18
+  %47 = extractvalue { i32, i32, i32, i32 } %43, 3, !dbg !18
+  %48 = bitcast i32 %44 to float, !dbg !18
+  %49 = bitcast i32 %45 to float, !dbg !18
+  %50 = bitcast i32 %46 to float, !dbg !18
+  %51 = bitcast i32 %47 to float, !dbg !18
+  %52 = sext i32 %15 to i64, !dbg !19
+  %53 = getelementptr float, ptr addrspace(1) %4, i64 %52, !dbg !19
+  %54 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %53, i1 true) #3, !dbg !20
+  %55 = bitcast i32 %54 to float, !dbg !20
+  %56 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %53, i1 true) #3, !dbg !20
+  %57 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %53, i1 true) #3, !dbg !20
+  %58 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %53, i1 true) #3, !dbg !20
+  %59 = getelementptr float, ptr addrspace(1) %5, i64 %52, !dbg !21
+  %60 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %59, i1 true) #3, !dbg !22
+  %61 = bitcast i32 %60 to float, !dbg !22
+  %62 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %59, i1 true) #3, !dbg !22
+  %63 = bitcast i32 %62 to float, !dbg !22
+  %64 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %59, i1 true) #3, !dbg !22
+  %65 = bitcast i32 %64 to float, !dbg !22
+  %66 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %59, i1 true) #3, !dbg !22
+  %67 = bitcast i32 %66 to float, !dbg !22
+  %68 = getelementptr float, ptr addrspace(1) %0, i64 %18, !dbg !23
+  %69 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];\0A\09@!$7 mov.u32 $0, $6;\0A\09@!$9 mov.u32 $1, $8;\0A\09@!$11 mov.u32 $2, $10;\0A\09@!$13 mov.u32 $3, $12;", "=r,=r,=r,=r,l,b,r,b,r,b,r,b,r,b"(ptr addrspace(1) %68, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true, i32 0, i1 true) #3, !dbg !24
+  %70 = extractvalue { i32, i32, i32, i32 } %69, 0, !dbg !24
+  %71 = extractvalue { i32, i32, i32, i32 } %69, 1, !dbg !24
+  %72 = extractvalue { i32, i32, i32, i32 } %69, 2, !dbg !24
+  %73 = extractvalue { i32, i32, i32, i32 } %69, 3, !dbg !24
+  %74 = bitcast i32 %70 to float, !dbg !24
+  %75 = bitcast i32 %71 to float, !dbg !24
+  %76 = bitcast i32 %72 to float, !dbg !24
+  %77 = bitcast i32 %73 to float, !dbg !24
+  %78 = fmul float %27, %38, !dbg !25
+  %79 = fmul float %28, %39, !dbg !25
+  %80 = fmul float %29, %40, !dbg !25
+  %81 = fmul float %30, %41, !dbg !25
+  %82 = fadd float %78, %79, !dbg !26
+  %83 = fadd float %80, %82, !dbg !26
+  %84 = fadd float %81, %83, !dbg !26
+  %85 = bitcast float %84 to i32, !dbg !32
+  %86 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %85, i32 16, i32 31), !dbg !32
+  %87 = bitcast i32 %86 to float, !dbg !32
+  %88 = fadd float %84, %87, !dbg !26
+  %89 = bitcast float %88 to i32, !dbg !32
+  %90 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %89, i32 8, i32 31), !dbg !32
+  %91 = bitcast i32 %90 to float, !dbg !32
+  %92 = fadd float %88, %91, !dbg !26
+  %93 = bitcast float %92 to i32, !dbg !32
+  %94 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %93, i32 4, i32 31), !dbg !32
+  %95 = bitcast i32 %94 to float, !dbg !32
+  %96 = fadd float %92, %95, !dbg !26
+  %97 = bitcast float %96 to i32, !dbg !32
+  %98 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %97, i32 2, i32 31), !dbg !32
+  %99 = bitcast i32 %98 to float, !dbg !32
+  %100 = fadd float %96, %99, !dbg !26
+  %101 = bitcast float %100 to i32, !dbg !32
+  %102 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %101, i32 1, i32 31), !dbg !32
+  %103 = bitcast i32 %102 to float, !dbg !32
+  %104 = fadd float %100, %103, !dbg !26
+  %105 = icmp eq i32 %11, 0, !dbg !32
+  %106 = zext nneg i32 %13 to i64, !dbg !32
+  %107 = getelementptr float, ptr addrspace(3) @global_smem, i64 %106, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %107, float %104, i1 %105) #3, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %108 = icmp slt i32 %10, 2, !dbg !32
+  %109 = sext i32 %10 to i64, !dbg !32
+  %110 = getelementptr float, ptr addrspace(3) @global_smem, i64 %109, !dbg !32
+  %111 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %110, i1 %108) #3, !dbg !32
+  %112 = bitcast float %111 to i32, !dbg !32
+  %113 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %112, i32 1, i32 31), !dbg !32
+  %114 = bitcast i32 %113 to float, !dbg !32
+  %115 = fadd float %111, %114, !dbg !26
+  %116 = and i32 %10, 1, !dbg !32
+  %117 = icmp eq i32 %116, 0, !dbg !32
+  %118 = and i1 %108, %117, !dbg !32
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %110, float %115, i1 %118) #3, !dbg !32
+  tail call void @llvm.nvvm.barrier0(), !dbg !32
+  %119 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !32
+  %120 = fadd float %119, 0.000000e+00, !dbg !34
+  %121 = fsub float %48, %55, !dbg !38
+  %122 = fsub float %49, %55, !dbg !38
+  %123 = fsub float %50, %55, !dbg !38
+  %124 = fsub float %51, %55, !dbg !38
+  %125 = fmul float %121, %61, !dbg !39
+  %126 = fmul float %122, %61, !dbg !39
+  %127 = fmul float %123, %61, !dbg !39
+  %128 = fmul float %124, %61, !dbg !39
+  %129 = fmul float %78, %125, !dbg !40
+  %130 = fmul float %79, %126, !dbg !40
+  %131 = fmul float %80, %127, !dbg !40
+  %132 = fmul float %81, %128, !dbg !40
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %133 = fadd float %129, %130, !dbg !43
+  %134 = fadd float %131, %133, !dbg !43
+  %135 = fadd float %132, %134, !dbg !43
+  %136 = bitcast float %135 to i32, !dbg !41
+  %137 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %136, i32 16, i32 31), !dbg !41
+  %138 = bitcast i32 %137 to float, !dbg !41
+  %139 = fadd float %135, %138, !dbg !43
+  %140 = bitcast float %139 to i32, !dbg !41
+  %141 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %140, i32 8, i32 31), !dbg !41
+  %142 = bitcast i32 %141 to float, !dbg !41
+  %143 = fadd float %139, %142, !dbg !43
+  %144 = bitcast float %143 to i32, !dbg !41
+  %145 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %144, i32 4, i32 31), !dbg !41
+  %146 = bitcast i32 %145 to float, !dbg !41
+  %147 = fadd float %143, %146, !dbg !43
+  %148 = bitcast float %147 to i32, !dbg !41
+  %149 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %148, i32 2, i32 31), !dbg !41
+  %150 = bitcast i32 %149 to float, !dbg !41
+  %151 = fadd float %147, %150, !dbg !43
+  %152 = bitcast float %151 to i32, !dbg !41
+  %153 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %152, i32 1, i32 31), !dbg !41
+  %154 = bitcast i32 %153 to float, !dbg !41
+  %155 = fadd float %151, %154, !dbg !43
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %107, float %155, i1 %105) #3, !dbg !41
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %156 = tail call float asm sideeffect "@$2 ld.shared.b32 $0, [ $1 + 0 ];", "=r,r,b"(ptr addrspace(3) %110, i1 %108) #3, !dbg !41
+  %157 = bitcast float %156 to i32, !dbg !41
+  %158 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %157, i32 1, i32 31), !dbg !41
+  %159 = bitcast i32 %158 to float, !dbg !41
+  %160 = fadd float %156, %159, !dbg !43
+  tail call void asm sideeffect "@$2 st.shared.b32 [ $0 + 0 ], $1;", "r,r,b"(ptr addrspace(3) %110, float %160, i1 %118) #3, !dbg !41
+  tail call void @llvm.nvvm.barrier0(), !dbg !41
+  %161 = load float, ptr addrspace(3) @global_smem, align 4, !dbg !41
+  %162 = fadd float %161, 0.000000e+00, !dbg !46
+  %163 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %61, float 2.560000e+02) #3, !dbg !48
+  %164 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %63, float 2.560000e+02) #3, !dbg !48
+  %165 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %65, float 2.560000e+02) #3, !dbg !48
+  %166 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %67, float 2.560000e+02) #3, !dbg !48
+  %167 = fmul float %78, 2.560000e+02, !dbg !49
+  %168 = fmul float %79, 2.560000e+02, !dbg !49
+  %169 = fmul float %80, 2.560000e+02, !dbg !49
+  %170 = fmul float %81, 2.560000e+02, !dbg !49
+  %171 = fsub float %167, %120, !dbg !50
+  %172 = fsub float %168, %120, !dbg !50
+  %173 = fsub float %169, %120, !dbg !50
+  %174 = fsub float %170, %120, !dbg !50
+  %175 = fmul float %125, %162, !dbg !51
+  %176 = fmul float %126, %162, !dbg !51
+  %177 = fmul float %127, %162, !dbg !51
+  %178 = fmul float %128, %162, !dbg !51
+  %179 = fsub float %171, %175, !dbg !52
+  %180 = fsub float %172, %176, !dbg !52
+  %181 = fsub float %173, %177, !dbg !52
+  %182 = fsub float %174, %178, !dbg !52
+  %183 = fmul float %163, %179, !dbg !53
+  %184 = fmul float %163, %180, !dbg !53
+  %185 = fmul float %163, %181, !dbg !53
+  %186 = fmul float %163, %182, !dbg !53
+  %187 = fadd float %183, %74, !dbg !54
+  %188 = fadd float %184, %75, !dbg !54
+  %189 = fadd float %185, %76, !dbg !54
+  %190 = fadd float %186, %77, !dbg !54
+  %191 = bitcast float %187 to i32, !dbg !55
+  %192 = bitcast float %188 to i32, !dbg !55
+  %193 = bitcast float %189 to i32, !dbg !55
+  %194 = bitcast float %190 to i32, !dbg !55
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %191, i32 %192, i32 %193, i32 %194, ptr addrspace(1) %68, i1 true) #3, !dbg !55
+  %195 = getelementptr i16, ptr addrspace(1) %6, i64 %18, !dbg !56
+  %196 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %187) #3, !dbg !57
+  %197 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %188) #3, !dbg !57
+  %198 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %189) #3, !dbg !57
+  %199 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %190) #3, !dbg !57
+  %200 = insertelement <2 x i16> undef, i16 %196, i64 0, !dbg !57
+  %201 = insertelement <2 x i16> %200, i16 %197, i64 1, !dbg !57
+  %202 = bitcast <2 x i16> %201 to i32, !dbg !57
+  %203 = insertelement <2 x i16> undef, i16 %198, i64 0, !dbg !57
+  %204 = insertelement <2 x i16> %203, i16 %199, i64 1, !dbg !57
+  %205 = bitcast <2 x i16> %204 to i32, !dbg !57
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %202, i32 %205, ptr addrspace(1) %195, i1 true) #3, !dbg !57
+  ret void, !dbg !58
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
+declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1
+
+; Function Attrs: convergent nocallback nounwind
+declare void @llvm.nvvm.barrier0() #2
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
+attributes #2 = { convergent nocallback nounwind }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "csned4hyxpgwu5ttubs3r7uxkjq5yfl3zh6c2sozobtkek2uzfcv.py", directory: "/tmp/torchinductor_root/sn")
+!3 = !{ptr @triton__0d1d2d3d4d5d6d7de8de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2d3d4d5d6d7de8de, !"maxntidx", i32 64}
+!5 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5d6d7de8de", linkageName: "triton__0d1d2d3d4d5d6d7de8de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 26, column: 26, scope: !5)
+!9 = !DILocation(line: 23, column: 28, scope: !5)
+!10 = !DILocation(line: 30, column: 40, scope: !5)
+!11 = !DILocation(line: 30, column: 36, scope: !5)
+!12 = !DILocation(line: 30, column: 30, scope: !5)
+!13 = !DILocation(line: 30, column: 46, scope: !5)
+!14 = !DILocation(line: 30, column: 67, scope: !5)
+!15 = !DILocation(line: 31, column: 30, scope: !5)
+!16 = !DILocation(line: 31, column: 35, scope: !5)
+!17 = !DILocation(line: 32, column: 30, scope: !5)
+!18 = !DILocation(line: 32, column: 46, scope: !5)
+!19 = !DILocation(line: 33, column: 30, scope: !5)
+!20 = !DILocation(line: 33, column: 35, scope: !5)
+!21 = !DILocation(line: 34, column: 31, scope: !5)
+!22 = !DILocation(line: 34, column: 36, scope: !5)
+!23 = !DILocation(line: 35, column: 35, scope: !5)
+!24 = !DILocation(line: 35, column: 51, scope: !5)
+!25 = !DILocation(line: 37, column: 18, scope: !5)
+!26 = !DILocation(line: 233, column: 15, scope: !27, inlinedAt: !30)
+!27 = distinct !DILexicalBlockFile(scope: !29, file: !28, discriminator: 0)
+!28 = !DIFile(filename: "standard.py", directory: "/usr/local/lib/python3.10/dist-packages/triton/language")
+!29 = distinct !DILexicalBlockFile(scope: !5, file: !28, discriminator: 0)
+!30 = !DILocation(line: 243, column: 36, scope: !27, inlinedAt: !31)
+!31 = !DILocation(line: 40, column: 57, scope: !27)
+!32 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !33)
+!33 = !DILocation(line: 40, column: 57, scope: !29)
+!34 = !DILocation(line: 8, column: 15, scope: !35, inlinedAt: !37)
+!35 = distinct !DILexicalBlockFile(scope: !5, file: !36, discriminator: 0)
+!36 = !DIFile(filename: "triton_helpers.py", directory: "/usr/local/lib/python3.10/dist-packages/torch/_inductor")
+!37 = !DILocation(line: 40, column: 44, scope: !35)
+!38 = !DILocation(line: 41, column: 19, scope: !5)
+!39 = !DILocation(line: 42, column: 20, scope: !5)
+!40 = !DILocation(line: 43, column: 19, scope: !5)
+!41 = !DILocation(line: 243, column: 36, scope: !29, inlinedAt: !42)
+!42 = !DILocation(line: 46, column: 59, scope: !29)
+!43 = !DILocation(line: 233, column: 15, scope: !27, inlinedAt: !44)
+!44 = !DILocation(line: 243, column: 36, scope: !27, inlinedAt: !45)
+!45 = !DILocation(line: 46, column: 59, scope: !27)
+!46 = !DILocation(line: 8, column: 15, scope: !35, inlinedAt: !47)
+!47 = !DILocation(line: 46, column: 45, scope: !35)
+!48 = !DILocation(line: 48, column: 20, scope: !5)
+!49 = !DILocation(line: 49, column: 19, scope: !5)
+!50 = !DILocation(line: 50, column: 20, scope: !5)
+!51 = !DILocation(line: 51, column: 20, scope: !5)
+!52 = !DILocation(line: 52, column: 20, scope: !5)
+!53 = !DILocation(line: 53, column: 20, scope: !5)
+!54 = !DILocation(line: 54, column: 20, scope: !5)
+!55 = !DILocation(line: 56, column: 51, scope: !5)
+!56 = !DILocation(line: 57, column: 25, scope: !5)
+!57 = !DILocation(line: 57, column: 48, scope: !5)
+!58 = !DILocation(line: 57, column: 4, scope: !5)

.triton/dump/3791d630ba27aad5e647360045d2f1b5/triton_.ttgir

@@ -0,0 +1,73 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [2], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 2 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3d4d5d6d7de8de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg7: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<256xi32, #blocked>
+    %cst_0 = arith.constant dense<2.560000e+02> : tensor<1xf32, #blocked>
+    %cst_1 = arith.constant 0.000000e+00 : f32
+    %c256_i32 = arith.constant 256 : i32
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<256xf32, #blocked>
+    %cst_3 = arith.constant dense<2.560000e+02> : tensor<256xf32, #blocked>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<256xbf16, #blocked>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %2 = arith.cmpi slt, %1, %cst : tensor<256xi32, #blocked>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32, #blocked>
+    %5 = arith.addi %1, %4 : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = tt.load %7, %2, %cst_4 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16, #blocked>
+    %9 = arith.extf %8 : tensor<256xbf16, #blocked> to tensor<256xf32, #blocked>
+    %10 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %11 = tt.addptr %10, %1 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %12 = tt.load %11, %2, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %13 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %15 = tt.load %14, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %16 = tt.addptr %arg4, %0 : !tt.ptr<f32, 1>, i32
+    %17 = tt.splat %16 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>, #blocked>
+    %18 = tt.load %17 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32, #blocked>
+    %19 = tt.addptr %arg5, %0 : !tt.ptr<f32, 1>, i32
+    %20 = tt.splat %19 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>, #blocked>
+    %21 = tt.load %20 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xf32, #blocked>
+    %22 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>, #blocked>
+    %23 = tt.addptr %22, %5 : tensor<256x!tt.ptr<f32, 1>, #blocked>, tensor<256xi32, #blocked>
+    %24 = tt.load %23, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32, #blocked>
+    %25 = arith.mulf %9, %12 : tensor<256xf32, #blocked>
+    %26 = arith.select %2, %25, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %27 = "tt.reduce"(%26) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %50 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %50 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %28 = arith.addf %27, %cst_1 : f32
+    %29 = tt.broadcast %18 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %30 = arith.subf %15, %29 : tensor<256xf32, #blocked>
+    %31 = tt.broadcast %21 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %32 = arith.mulf %30, %31 : tensor<256xf32, #blocked>
+    %33 = arith.mulf %25, %32 : tensor<256xf32, #blocked>
+    %34 = arith.select %2, %33, %cst_2 : tensor<256xi1, #blocked>, tensor<256xf32, #blocked>
+    %35 = "tt.reduce"(%34) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %50 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %50 : f32
+    }) : (tensor<256xf32, #blocked>) -> f32
+    %36 = arith.addf %35, %cst_1 : f32
+    %37 = arith.divf %21, %cst_0 : tensor<1xf32, #blocked>
+    %38 = arith.mulf %25, %cst_3 : tensor<256xf32, #blocked>
+    %39 = tt.splat %28 : (f32) -> tensor<256xf32, #blocked>
+    %40 = arith.subf %38, %39 : tensor<256xf32, #blocked>
+    %41 = tt.splat %36 : (f32) -> tensor<256xf32, #blocked>
+    %42 = arith.mulf %32, %41 : tensor<256xf32, #blocked>
+    %43 = arith.subf %40, %42 : tensor<256xf32, #blocked>
+    %44 = tt.broadcast %37 : (tensor<1xf32, #blocked>) -> tensor<256xf32, #blocked>
+    %45 = arith.mulf %44, %43 : tensor<256xf32, #blocked>
+    %46 = arith.addf %24, %45 : tensor<256xf32, #blocked>
+    tt.store %23, %46, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32, #blocked>
+    %47 = tt.splat %arg6 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>, #blocked>
+    %48 = tt.addptr %47, %5 : tensor<256x!tt.ptr<bf16, 1>, #blocked>, tensor<256xi32, #blocked>
+    %49 = arith.truncf %46 : tensor<256xf32, #blocked> to tensor<256xbf16, #blocked>
+    tt.store %48, %49, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16, #blocked>
+    tt.return
+  }
+}

.triton/dump/3a1c03243d4f9adf7326739f5f7e7c9b/triton_.ptx

@@ -0,0 +1,1927 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7de8
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6d7de8(
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_7,
+	.param .u64 triton__0d1d2d3d4d5d6d7de8_param_8
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<201>;
+	.reg .b16 	%rs<129>;
+	.reg .b32 	%r<399>;
+	.reg .f32 	%f<469>;
+	.reg .b64 	%rd<150>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd17, [triton__0d1d2d3d4d5d6d7de8_param_6];
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7de8_param_5];
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6d7de8_param_4];
+	ld.param.u64 	%rd52, [triton__0d1d2d3d4d5d6d7de8_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r1, %tid.x;
+	ld.param.u64 	%rd53, [triton__0d1d2d3d4d5d6d7de8_param_1];
+	and.b32  	%r2, %r1, 31;
+	ld.param.u64 	%rd50, [triton__0d1d2d3d4d5d6d7de8_param_2];
+	ld.param.u64 	%rd51, [triton__0d1d2d3d4d5d6d7de8_param_3];
+	bfe.u32 	%r30, %r1, 6, 2;
+	or.b32  	%r3, %r30, 4;
+	or.b32  	%r4, %r30, 8;
+	or.b32  	%r5, %r30, 12;
+	or.b32  	%r6, %r30, 16;
+	or.b32  	%r7, %r30, 20;
+	or.b32  	%r8, %r30, 24;
+	or.b32  	%r9, %r30, 28;
+	or.b32  	%r10, %r30, 32;
+	or.b32  	%r11, %r30, 36;
+	or.b32  	%r12, %r30, 40;
+	or.b32  	%r13, %r30, 44;
+	or.b32  	%r14, %r30, 48;
+	or.b32  	%r15, %r30, 52;
+	or.b32  	%r16, %r30, 56;
+	or.b32  	%r17, %r30, 60;
+	.loc	1 24 33
+	and.b32  	%r18, %r1, 63;
+	.loc	1 21 28
+	mov.u32 %r23, %ctaid.x;
+	.loc	1 21 34
+	cvt.s64.s32 	%rd1, %r23;
+	.loc	1 21 46
+	mul.wide.s32 	%rd54, %r23, 64;
+	cvt.u64.u32 	%rd2, %r30;
+	.loc	1 22 23
+	or.b64  	%rd55, %rd54, %rd2;
+	.loc	1 26 30
+	shl.b64 	%rd56, %rd55, 3;
+	add.s64 	%rd19, %rd53, %rd56;
+	add.s64 	%rd21, %rd19, 32;
+	add.s64 	%rd23, %rd19, 64;
+	add.s64 	%rd25, %rd19, 96;
+	add.s64 	%rd27, %rd19, 128;
+	add.s64 	%rd29, %rd19, 160;
+	add.s64 	%rd31, %rd19, 192;
+	add.s64 	%rd33, %rd19, 224;
+	add.s64 	%rd35, %rd19, 256;
+	add.s64 	%rd37, %rd19, 288;
+	add.s64 	%rd39, %rd19, 320;
+	add.s64 	%rd41, %rd19, 352;
+	add.s64 	%rd43, %rd19, 384;
+	add.s64 	%rd45, %rd19, 416;
+	add.s64 	%rd47, %rd19, 448;
+	add.s64 	%rd49, %rd19, 480;
+	mov.pred 	%p1, -1;
+	.loc	1 26 35
+	mov.u64 %rd18, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd18 }, [ %rd19 + 0 ];
+	mov.u64 %rd20, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd20 }, [ %rd21 + 0 ];
+	mov.u64 %rd22, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd22 }, [ %rd23 + 0 ];
+	mov.u64 %rd24, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd24 }, [ %rd25 + 0 ];
+	mov.u64 %rd26, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd26 }, [ %rd27 + 0 ];
+	mov.u64 %rd28, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd28 }, [ %rd29 + 0 ];
+	mov.u64 %rd30, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd30 }, [ %rd31 + 0 ];
+	mov.u64 %rd32, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd32 }, [ %rd33 + 0 ];
+	mov.u64 %rd34, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd34 }, [ %rd35 + 0 ];
+	mov.u64 %rd36, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd36 }, [ %rd37 + 0 ];
+	mov.u64 %rd38, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd38 }, [ %rd39 + 0 ];
+	mov.u64 %rd40, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd40 }, [ %rd41 + 0 ];
+	mov.u64 %rd42, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd42 }, [ %rd43 + 0 ];
+	mov.u64 %rd44, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd44 }, [ %rd45 + 0 ];
+	mov.u64 %rd46, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd46 }, [ %rd47 + 0 ];
+	mov.u64 %rd48, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd48 }, [ %rd49 + 0 ];
+	.loc	1 27 19
+	mov.u32 %r27, 0x0;
+	@%p1 ld.global.b32 { %r27 }, [ %rd50 + 0 ];
+	.loc	1 29 19
+	mov.u32 %r28, 0x0;
+	@%p1 ld.global.b32 { %r28 }, [ %rd51 + 0 ];
+	.loc	1 38 23
+	setp.eq.s64 	%p19, %rd18, -1;
+	setp.eq.s64 	%p20, %rd20, -1;
+	setp.eq.s64 	%p21, %rd22, -1;
+	setp.eq.s64 	%p22, %rd24, -1;
+	setp.eq.s64 	%p23, %rd26, -1;
+	setp.eq.s64 	%p24, %rd28, -1;
+	setp.eq.s64 	%p25, %rd30, -1;
+	setp.eq.s64 	%p26, %rd32, -1;
+	setp.eq.s64 	%p27, %rd34, -1;
+	setp.eq.s64 	%p28, %rd36, -1;
+	setp.eq.s64 	%p29, %rd38, -1;
+	setp.eq.s64 	%p30, %rd40, -1;
+	setp.eq.s64 	%p31, %rd42, -1;
+	setp.eq.s64 	%p32, %rd44, -1;
+	setp.eq.s64 	%p33, %rd46, -1;
+	setp.eq.s64 	%p34, %rd48, -1;
+	.loc	1 39 22
+	div.full.f32 %r26, %r27, %r28;
+	mov.b32 	%f97, %r26;
+	.loc	1 41 37
+	selp.f32 	%f16, 0f00000000, %f97, %p34;
+	selp.f32 	%f15, 0f00000000, %f97, %p33;
+	selp.f32 	%f14, 0f00000000, %f97, %p32;
+	selp.f32 	%f13, 0f00000000, %f97, %p31;
+	selp.f32 	%f12, 0f00000000, %f97, %p30;
+	selp.f32 	%f11, 0f00000000, %f97, %p29;
+	selp.f32 	%f10, 0f00000000, %f97, %p28;
+	selp.f32 	%f9, 0f00000000, %f97, %p27;
+	selp.f32 	%f8, 0f00000000, %f97, %p26;
+	selp.f32 	%f7, 0f00000000, %f97, %p25;
+	selp.f32 	%f6, 0f00000000, %f97, %p24;
+	selp.f32 	%f5, 0f00000000, %f97, %p23;
+	selp.f32 	%f4, 0f00000000, %f97, %p22;
+	selp.f32 	%f3, 0f00000000, %f97, %p21;
+	selp.f32 	%f2, 0f00000000, %f97, %p20;
+	selp.f32 	%f1, 0f00000000, %f97, %p19;
+	.loc	1 32 36
+	mul.wide.s32 	%rd57, %r23, 12865792;
+	mul.wide.u32 	%rd58, %r30, 201028;
+	add.s64 	%rd59, %rd57, %rd58;
+	cvt.u64.u32 	%rd60, %r1;
+	and.b64  	%rd3, %rd60, 63;
+	mul.wide.u32 	%rd61, %r18, 4;
+	add.s64 	%rd62, %rd59, %rd61;
+	add.s64 	%rd63, %rd62, %rd52;
+	add.s64 	%rd149, %rd63, 12061680;
+	mov.f32 	%f453, 0f00000000;
+	mov.b32 	%r397, -64;
+	mov.u64 	%rd147, %rd149;
+	mov.f32 	%f454, %f453;
+	mov.f32 	%f455, %f453;
+	mov.f32 	%f456, %f453;
+	mov.f32 	%f457, %f453;
+	mov.f32 	%f458, %f453;
+	mov.f32 	%f459, %f453;
+	mov.f32 	%f460, %f453;
+	mov.f32 	%f461, %f453;
+	mov.f32 	%f462, %f453;
+	mov.f32 	%f463, %f453;
+	mov.f32 	%f464, %f453;
+	mov.f32 	%f465, %f453;
+	mov.f32 	%f466, %f453;
+	mov.f32 	%f467, %f453;
+	mov.f32 	%f468, %f453;
+$L__BB0_1:
+	add.s32 	%r397, %r397, 64;
+	.loc	1 33 27
+	add.s32 	%r63, %r397, %r18;
+	.loc	1 34 25
+	setp.lt.u32 	%p35, %r63, 50257;
+	.loc	1 36 34
+	add.s64 	%rd64, %rd147, -12061680;
+	add.s64 	%rd65, %rd147, -11257568;
+	add.s64 	%rd66, %rd147, -10453456;
+	add.s64 	%rd67, %rd147, -9649344;
+	add.s64 	%rd68, %rd147, -8845232;
+	add.s64 	%rd69, %rd147, -8041120;
+	add.s64 	%rd70, %rd147, -7237008;
+	add.s64 	%rd71, %rd147, -6432896;
+	add.s64 	%rd72, %rd147, -5628784;
+	add.s64 	%rd73, %rd147, -4824672;
+	add.s64 	%rd74, %rd147, -4020560;
+	add.s64 	%rd75, %rd147, -3216448;
+	add.s64 	%rd76, %rd147, -2412336;
+	add.s64 	%rd77, %rd147, -1608224;
+	add.s64 	%rd78, %rd147, -804112;
+	mov.b32 	%r333, 0;
+	.loc	1 36 52
+	mov.u32 %r31, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r31 }, [ %rd64 + 0 ];
+	@!%p35 mov.u32 %r31, %r333;
+	mov.u32 %r33, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r33 }, [ %rd65 + 0 ];
+	@!%p35 mov.u32 %r33, %r333;
+	mov.u32 %r35, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r35 }, [ %rd66 + 0 ];
+	@!%p35 mov.u32 %r35, %r333;
+	mov.u32 %r37, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r37 }, [ %rd67 + 0 ];
+	@!%p35 mov.u32 %r37, %r333;
+	mov.u32 %r39, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r39 }, [ %rd68 + 0 ];
+	@!%p35 mov.u32 %r39, %r333;
+	mov.u32 %r41, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r41 }, [ %rd69 + 0 ];
+	@!%p35 mov.u32 %r41, %r333;
+	mov.u32 %r43, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r43 }, [ %rd70 + 0 ];
+	@!%p35 mov.u32 %r43, %r333;
+	mov.u32 %r45, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r45 }, [ %rd71 + 0 ];
+	@!%p35 mov.u32 %r45, %r333;
+	mov.u32 %r47, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r47 }, [ %rd72 + 0 ];
+	@!%p35 mov.u32 %r47, %r333;
+	mov.u32 %r49, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r49 }, [ %rd73 + 0 ];
+	@!%p35 mov.u32 %r49, %r333;
+	mov.u32 %r51, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r51 }, [ %rd74 + 0 ];
+	@!%p35 mov.u32 %r51, %r333;
+	mov.u32 %r53, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r53 }, [ %rd75 + 0 ];
+	@!%p35 mov.u32 %r53, %r333;
+	mov.u32 %r55, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r55 }, [ %rd76 + 0 ];
+	@!%p35 mov.u32 %r55, %r333;
+	mov.u32 %r57, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r57 }, [ %rd77 + 0 ];
+	@!%p35 mov.u32 %r57, %r333;
+	mov.u32 %r59, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r59 }, [ %rd78 + 0 ];
+	@!%p35 mov.u32 %r59, %r333;
+	mov.u32 %r61, 0x0;
+	@%p35 ld.global.L1::evict_last.b32 { %r61 }, [ %rd147 + 0 ];
+	@!%p35 mov.u32 %r61, %r333;
+	mov.b32 	%f98, %r61;
+	mov.b32 	%f99, %r59;
+	mov.b32 	%f100, %r57;
+	mov.b32 	%f101, %r55;
+	mov.b32 	%f102, %r53;
+	mov.b32 	%f103, %r51;
+	mov.b32 	%f104, %r49;
+	mov.b32 	%f105, %r47;
+	mov.b32 	%f106, %r45;
+	mov.b32 	%f107, %r43;
+	mov.b32 	%f108, %r41;
+	mov.b32 	%f109, %r39;
+	mov.b32 	%f110, %r37;
+	mov.b32 	%f111, %r35;
+	mov.b32 	%f112, %r33;
+	mov.b32 	%f113, %r31;
+	.loc	1 42 23
+	mul.f32 	%f114, %f1, %f113;
+	mul.f32 	%f115, %f2, %f112;
+	mul.f32 	%f116, %f3, %f111;
+	mul.f32 	%f117, %f4, %f110;
+	mul.f32 	%f118, %f5, %f109;
+	mul.f32 	%f119, %f6, %f108;
+	mul.f32 	%f120, %f7, %f107;
+	mul.f32 	%f121, %f8, %f106;
+	mul.f32 	%f122, %f9, %f105;
+	mul.f32 	%f123, %f10, %f104;
+	mul.f32 	%f124, %f11, %f103;
+	mul.f32 	%f125, %f12, %f102;
+	mul.f32 	%f126, %f13, %f101;
+	mul.f32 	%f127, %f14, %f100;
+	mul.f32 	%f128, %f15, %f99;
+	mul.f32 	%f129, %f16, %f98;
+	.loc	1 45 40
+	selp.f32 	%f130, %f129, 0f80000000, %p35;
+	selp.f32 	%f131, %f128, 0f80000000, %p35;
+	selp.f32 	%f132, %f127, 0f80000000, %p35;
+	selp.f32 	%f133, %f126, 0f80000000, %p35;
+	selp.f32 	%f134, %f125, 0f80000000, %p35;
+	selp.f32 	%f135, %f124, 0f80000000, %p35;
+	selp.f32 	%f136, %f123, 0f80000000, %p35;
+	selp.f32 	%f137, %f122, 0f80000000, %p35;
+	selp.f32 	%f138, %f121, 0f80000000, %p35;
+	selp.f32 	%f139, %f120, 0f80000000, %p35;
+	selp.f32 	%f140, %f119, 0f80000000, %p35;
+	selp.f32 	%f141, %f118, 0f80000000, %p35;
+	selp.f32 	%f142, %f117, 0f80000000, %p35;
+	selp.f32 	%f143, %f116, 0f80000000, %p35;
+	selp.f32 	%f144, %f115, 0f80000000, %p35;
+	selp.f32 	%f145, %f114, 0f80000000, %p35;
+	add.f32 	%f453, %f453, %f145;
+	add.f32 	%f454, %f454, %f144;
+	add.f32 	%f455, %f455, %f143;
+	add.f32 	%f456, %f456, %f142;
+	add.f32 	%f457, %f457, %f141;
+	add.f32 	%f458, %f458, %f140;
+	add.f32 	%f459, %f459, %f139;
+	add.f32 	%f460, %f460, %f138;
+	add.f32 	%f461, %f461, %f137;
+	add.f32 	%f462, %f462, %f136;
+	add.f32 	%f463, %f463, %f135;
+	add.f32 	%f464, %f464, %f134;
+	add.f32 	%f465, %f465, %f133;
+	add.f32 	%f466, %f466, %f132;
+	add.f32 	%f467, %f467, %f131;
+	add.f32 	%f468, %f468, %f130;
+	.loc	1 32 36
+	add.s64 	%rd147, %rd147, 256;
+	setp.lt.u32 	%p67, %r397, 50193;
+	@%p67 bra 	$L__BB0_1;
+	.loc	1 0 36
+	cvt.u32.u64 	%r101, %rd2;
+$L__tmp1:
+	.loc	2 243 36
+	mov.b32 	%r102, %f453;
+	shfl.sync.bfly.b32	%r103, %r102, 16, 31, -1;
+	mov.b32 	%f146, %r103;
+$L__tmp2:
+	.loc	2 233 15
+	add.f32 	%f147, %f453, %f146;
+$L__tmp3:
+	.loc	2 243 36
+	mov.b32 	%r104, %f147;
+	shfl.sync.bfly.b32	%r105, %r104, 8, 31, -1;
+	mov.b32 	%f148, %r105;
+$L__tmp4:
+	.loc	2 233 15
+	add.f32 	%f149, %f147, %f148;
+$L__tmp5:
+	.loc	2 243 36
+	mov.b32 	%r106, %f149;
+	shfl.sync.bfly.b32	%r107, %r106, 4, 31, -1;
+	mov.b32 	%f150, %r107;
+$L__tmp6:
+	.loc	2 233 15
+	add.f32 	%f151, %f149, %f150;
+$L__tmp7:
+	.loc	2 243 36
+	mov.b32 	%r108, %f151;
+	shfl.sync.bfly.b32	%r109, %r108, 2, 31, -1;
+	mov.b32 	%f152, %r109;
+$L__tmp8:
+	.loc	2 233 15
+	add.f32 	%f153, %f151, %f152;
+$L__tmp9:
+	.loc	2 243 36
+	mov.b32 	%r110, %f153;
+	shfl.sync.bfly.b32	%r111, %r110, 1, 31, -1;
+	mov.b32 	%f154, %r111;
+$L__tmp10:
+	.loc	2 233 15
+	add.f32 	%f155, %f153, %f154;
+$L__tmp11:
+	.loc	2 243 36
+	mov.b32 	%r112, %f454;
+	shfl.sync.bfly.b32	%r113, %r112, 16, 31, -1;
+	mov.b32 	%f156, %r113;
+$L__tmp12:
+	.loc	2 233 15
+	add.f32 	%f157, %f454, %f156;
+$L__tmp13:
+	.loc	2 243 36
+	mov.b32 	%r114, %f157;
+	shfl.sync.bfly.b32	%r115, %r114, 8, 31, -1;
+	mov.b32 	%f158, %r115;
+$L__tmp14:
+	.loc	2 233 15
+	add.f32 	%f159, %f157, %f158;
+$L__tmp15:
+	.loc	2 243 36
+	mov.b32 	%r116, %f159;
+	shfl.sync.bfly.b32	%r117, %r116, 4, 31, -1;
+	mov.b32 	%f160, %r117;
+$L__tmp16:
+	.loc	2 233 15
+	add.f32 	%f161, %f159, %f160;
+$L__tmp17:
+	.loc	2 243 36
+	mov.b32 	%r118, %f161;
+	shfl.sync.bfly.b32	%r119, %r118, 2, 31, -1;
+	mov.b32 	%f162, %r119;
+$L__tmp18:
+	.loc	2 233 15
+	add.f32 	%f163, %f161, %f162;
+$L__tmp19:
+	.loc	2 243 36
+	mov.b32 	%r120, %f163;
+	shfl.sync.bfly.b32	%r121, %r120, 1, 31, -1;
+	mov.b32 	%f164, %r121;
+$L__tmp20:
+	.loc	2 233 15
+	add.f32 	%f165, %f163, %f164;
+$L__tmp21:
+	.loc	2 243 36
+	mov.b32 	%r122, %f455;
+	shfl.sync.bfly.b32	%r123, %r122, 16, 31, -1;
+	mov.b32 	%f166, %r123;
+$L__tmp22:
+	.loc	2 233 15
+	add.f32 	%f167, %f455, %f166;
+$L__tmp23:
+	.loc	2 243 36
+	mov.b32 	%r124, %f167;
+	shfl.sync.bfly.b32	%r125, %r124, 8, 31, -1;
+	mov.b32 	%f168, %r125;
+$L__tmp24:
+	.loc	2 233 15
+	add.f32 	%f169, %f167, %f168;
+$L__tmp25:
+	.loc	2 243 36
+	mov.b32 	%r126, %f169;
+	shfl.sync.bfly.b32	%r127, %r126, 4, 31, -1;
+	mov.b32 	%f170, %r127;
+$L__tmp26:
+	.loc	2 233 15
+	add.f32 	%f171, %f169, %f170;
+$L__tmp27:
+	.loc	2 243 36
+	mov.b32 	%r128, %f171;
+	shfl.sync.bfly.b32	%r129, %r128, 2, 31, -1;
+	mov.b32 	%f172, %r129;
+$L__tmp28:
+	.loc	2 233 15
+	add.f32 	%f173, %f171, %f172;
+$L__tmp29:
+	.loc	2 243 36
+	mov.b32 	%r130, %f173;
+	shfl.sync.bfly.b32	%r131, %r130, 1, 31, -1;
+	mov.b32 	%f174, %r131;
+$L__tmp30:
+	.loc	2 233 15
+	add.f32 	%f175, %f173, %f174;
+$L__tmp31:
+	.loc	2 243 36
+	mov.b32 	%r132, %f456;
+	shfl.sync.bfly.b32	%r133, %r132, 16, 31, -1;
+	mov.b32 	%f176, %r133;
+$L__tmp32:
+	.loc	2 233 15
+	add.f32 	%f177, %f456, %f176;
+$L__tmp33:
+	.loc	2 243 36
+	mov.b32 	%r134, %f177;
+	shfl.sync.bfly.b32	%r135, %r134, 8, 31, -1;
+	mov.b32 	%f178, %r135;
+$L__tmp34:
+	.loc	2 233 15
+	add.f32 	%f179, %f177, %f178;
+$L__tmp35:
+	.loc	2 243 36
+	mov.b32 	%r136, %f179;
+	shfl.sync.bfly.b32	%r137, %r136, 4, 31, -1;
+	mov.b32 	%f180, %r137;
+$L__tmp36:
+	.loc	2 233 15
+	add.f32 	%f181, %f179, %f180;
+$L__tmp37:
+	.loc	2 243 36
+	mov.b32 	%r138, %f181;
+	shfl.sync.bfly.b32	%r139, %r138, 2, 31, -1;
+	mov.b32 	%f182, %r139;
+$L__tmp38:
+	.loc	2 233 15
+	add.f32 	%f183, %f181, %f182;
+$L__tmp39:
+	.loc	2 243 36
+	mov.b32 	%r140, %f183;
+	shfl.sync.bfly.b32	%r141, %r140, 1, 31, -1;
+	mov.b32 	%f184, %r141;
+$L__tmp40:
+	.loc	2 233 15
+	add.f32 	%f185, %f183, %f184;
+$L__tmp41:
+	.loc	2 243 36
+	mov.b32 	%r142, %f457;
+	shfl.sync.bfly.b32	%r143, %r142, 16, 31, -1;
+	mov.b32 	%f186, %r143;
+$L__tmp42:
+	.loc	2 233 15
+	add.f32 	%f187, %f457, %f186;
+$L__tmp43:
+	.loc	2 243 36
+	mov.b32 	%r144, %f187;
+	shfl.sync.bfly.b32	%r145, %r144, 8, 31, -1;
+	mov.b32 	%f188, %r145;
+$L__tmp44:
+	.loc	2 233 15
+	add.f32 	%f189, %f187, %f188;
+$L__tmp45:
+	.loc	2 243 36
+	mov.b32 	%r146, %f189;
+	shfl.sync.bfly.b32	%r147, %r146, 4, 31, -1;
+	mov.b32 	%f190, %r147;
+$L__tmp46:
+	.loc	2 233 15
+	add.f32 	%f191, %f189, %f190;
+$L__tmp47:
+	.loc	2 243 36
+	mov.b32 	%r148, %f191;
+	shfl.sync.bfly.b32	%r149, %r148, 2, 31, -1;
+	mov.b32 	%f192, %r149;
+$L__tmp48:
+	.loc	2 233 15
+	add.f32 	%f193, %f191, %f192;
+$L__tmp49:
+	.loc	2 243 36
+	mov.b32 	%r150, %f193;
+	shfl.sync.bfly.b32	%r151, %r150, 1, 31, -1;
+	mov.b32 	%f194, %r151;
+$L__tmp50:
+	.loc	2 233 15
+	add.f32 	%f195, %f193, %f194;
+$L__tmp51:
+	.loc	2 243 36
+	mov.b32 	%r152, %f458;
+	shfl.sync.bfly.b32	%r153, %r152, 16, 31, -1;
+	mov.b32 	%f196, %r153;
+$L__tmp52:
+	.loc	2 233 15
+	add.f32 	%f197, %f458, %f196;
+$L__tmp53:
+	.loc	2 243 36
+	mov.b32 	%r154, %f197;
+	shfl.sync.bfly.b32	%r155, %r154, 8, 31, -1;
+	mov.b32 	%f198, %r155;
+$L__tmp54:
+	.loc	2 233 15
+	add.f32 	%f199, %f197, %f198;
+$L__tmp55:
+	.loc	2 243 36
+	mov.b32 	%r156, %f199;
+	shfl.sync.bfly.b32	%r157, %r156, 4, 31, -1;
+	mov.b32 	%f200, %r157;
+$L__tmp56:
+	.loc	2 233 15
+	add.f32 	%f201, %f199, %f200;
+$L__tmp57:
+	.loc	2 243 36
+	mov.b32 	%r158, %f201;
+	shfl.sync.bfly.b32	%r159, %r158, 2, 31, -1;
+	mov.b32 	%f202, %r159;
+$L__tmp58:
+	.loc	2 233 15
+	add.f32 	%f203, %f201, %f202;
+$L__tmp59:
+	.loc	2 243 36
+	mov.b32 	%r160, %f203;
+	shfl.sync.bfly.b32	%r161, %r160, 1, 31, -1;
+	mov.b32 	%f204, %r161;
+$L__tmp60:
+	.loc	2 233 15
+	add.f32 	%f205, %f203, %f204;
+$L__tmp61:
+	.loc	2 243 36
+	mov.b32 	%r162, %f459;
+	shfl.sync.bfly.b32	%r163, %r162, 16, 31, -1;
+	mov.b32 	%f206, %r163;
+$L__tmp62:
+	.loc	2 233 15
+	add.f32 	%f207, %f459, %f206;
+$L__tmp63:
+	.loc	2 243 36
+	mov.b32 	%r164, %f207;
+	shfl.sync.bfly.b32	%r165, %r164, 8, 31, -1;
+	mov.b32 	%f208, %r165;
+$L__tmp64:
+	.loc	2 233 15
+	add.f32 	%f209, %f207, %f208;
+$L__tmp65:
+	.loc	2 243 36
+	mov.b32 	%r166, %f209;
+	shfl.sync.bfly.b32	%r167, %r166, 4, 31, -1;
+	mov.b32 	%f210, %r167;
+$L__tmp66:
+	.loc	2 233 15
+	add.f32 	%f211, %f209, %f210;
+$L__tmp67:
+	.loc	2 243 36
+	mov.b32 	%r168, %f211;
+	shfl.sync.bfly.b32	%r169, %r168, 2, 31, -1;
+	mov.b32 	%f212, %r169;
+$L__tmp68:
+	.loc	2 233 15
+	add.f32 	%f213, %f211, %f212;
+$L__tmp69:
+	.loc	2 243 36
+	mov.b32 	%r170, %f213;
+	shfl.sync.bfly.b32	%r171, %r170, 1, 31, -1;
+	mov.b32 	%f214, %r171;
+$L__tmp70:
+	.loc	2 233 15
+	add.f32 	%f215, %f213, %f214;
+$L__tmp71:
+	.loc	2 243 36
+	mov.b32 	%r172, %f460;
+	shfl.sync.bfly.b32	%r173, %r172, 16, 31, -1;
+	mov.b32 	%f216, %r173;
+$L__tmp72:
+	.loc	2 233 15
+	add.f32 	%f217, %f460, %f216;
+$L__tmp73:
+	.loc	2 243 36
+	mov.b32 	%r174, %f217;
+	shfl.sync.bfly.b32	%r175, %r174, 8, 31, -1;
+	mov.b32 	%f218, %r175;
+$L__tmp74:
+	.loc	2 233 15
+	add.f32 	%f219, %f217, %f218;
+$L__tmp75:
+	.loc	2 243 36
+	mov.b32 	%r176, %f219;
+	shfl.sync.bfly.b32	%r177, %r176, 4, 31, -1;
+	mov.b32 	%f220, %r177;
+$L__tmp76:
+	.loc	2 233 15
+	add.f32 	%f221, %f219, %f220;
+$L__tmp77:
+	.loc	2 243 36
+	mov.b32 	%r178, %f221;
+	shfl.sync.bfly.b32	%r179, %r178, 2, 31, -1;
+	mov.b32 	%f222, %r179;
+$L__tmp78:
+	.loc	2 233 15
+	add.f32 	%f223, %f221, %f222;
+$L__tmp79:
+	.loc	2 243 36
+	mov.b32 	%r180, %f223;
+	shfl.sync.bfly.b32	%r181, %r180, 1, 31, -1;
+	mov.b32 	%f224, %r181;
+$L__tmp80:
+	.loc	2 233 15
+	add.f32 	%f225, %f223, %f224;
+$L__tmp81:
+	.loc	2 243 36
+	mov.b32 	%r182, %f461;
+	shfl.sync.bfly.b32	%r183, %r182, 16, 31, -1;
+	mov.b32 	%f226, %r183;
+$L__tmp82:
+	.loc	2 233 15
+	add.f32 	%f227, %f461, %f226;
+$L__tmp83:
+	.loc	2 243 36
+	mov.b32 	%r184, %f227;
+	shfl.sync.bfly.b32	%r185, %r184, 8, 31, -1;
+	mov.b32 	%f228, %r185;
+$L__tmp84:
+	.loc	2 233 15
+	add.f32 	%f229, %f227, %f228;
+$L__tmp85:
+	.loc	2 243 36
+	mov.b32 	%r186, %f229;
+	shfl.sync.bfly.b32	%r187, %r186, 4, 31, -1;
+	mov.b32 	%f230, %r187;
+$L__tmp86:
+	.loc	2 233 15
+	add.f32 	%f231, %f229, %f230;
+$L__tmp87:
+	.loc	2 243 36
+	mov.b32 	%r188, %f231;
+	shfl.sync.bfly.b32	%r189, %r188, 2, 31, -1;
+	mov.b32 	%f232, %r189;
+$L__tmp88:
+	.loc	2 233 15
+	add.f32 	%f233, %f231, %f232;
+$L__tmp89:
+	.loc	2 243 36
+	mov.b32 	%r190, %f233;
+	shfl.sync.bfly.b32	%r191, %r190, 1, 31, -1;
+	mov.b32 	%f234, %r191;
+$L__tmp90:
+	.loc	2 233 15
+	add.f32 	%f235, %f233, %f234;
+$L__tmp91:
+	.loc	2 243 36
+	mov.b32 	%r192, %f462;
+	shfl.sync.bfly.b32	%r193, %r192, 16, 31, -1;
+	mov.b32 	%f236, %r193;
+$L__tmp92:
+	.loc	2 233 15
+	add.f32 	%f237, %f462, %f236;
+$L__tmp93:
+	.loc	2 243 36
+	mov.b32 	%r194, %f237;
+	shfl.sync.bfly.b32	%r195, %r194, 8, 31, -1;
+	mov.b32 	%f238, %r195;
+$L__tmp94:
+	.loc	2 233 15
+	add.f32 	%f239, %f237, %f238;
+$L__tmp95:
+	.loc	2 243 36
+	mov.b32 	%r196, %f239;
+	shfl.sync.bfly.b32	%r197, %r196, 4, 31, -1;
+	mov.b32 	%f240, %r197;
+$L__tmp96:
+	.loc	2 233 15
+	add.f32 	%f241, %f239, %f240;
+$L__tmp97:
+	.loc	2 243 36
+	mov.b32 	%r198, %f241;
+	shfl.sync.bfly.b32	%r199, %r198, 2, 31, -1;
+	mov.b32 	%f242, %r199;
+$L__tmp98:
+	.loc	2 233 15
+	add.f32 	%f243, %f241, %f242;
+$L__tmp99:
+	.loc	2 243 36
+	mov.b32 	%r200, %f243;
+	shfl.sync.bfly.b32	%r201, %r200, 1, 31, -1;
+	mov.b32 	%f244, %r201;
+$L__tmp100:
+	.loc	2 233 15
+	add.f32 	%f245, %f243, %f244;
+$L__tmp101:
+	.loc	2 243 36
+	mov.b32 	%r202, %f463;
+	shfl.sync.bfly.b32	%r203, %r202, 16, 31, -1;
+	mov.b32 	%f246, %r203;
+$L__tmp102:
+	.loc	2 233 15
+	add.f32 	%f247, %f463, %f246;
+$L__tmp103:
+	.loc	2 243 36
+	mov.b32 	%r204, %f247;
+	shfl.sync.bfly.b32	%r205, %r204, 8, 31, -1;
+	mov.b32 	%f248, %r205;
+$L__tmp104:
+	.loc	2 233 15
+	add.f32 	%f249, %f247, %f248;
+$L__tmp105:
+	.loc	2 243 36
+	mov.b32 	%r206, %f249;
+	shfl.sync.bfly.b32	%r207, %r206, 4, 31, -1;
+	mov.b32 	%f250, %r207;
+$L__tmp106:
+	.loc	2 233 15
+	add.f32 	%f251, %f249, %f250;
+$L__tmp107:
+	.loc	2 243 36
+	mov.b32 	%r208, %f251;
+	shfl.sync.bfly.b32	%r209, %r208, 2, 31, -1;
+	mov.b32 	%f252, %r209;
+$L__tmp108:
+	.loc	2 233 15
+	add.f32 	%f253, %f251, %f252;
+$L__tmp109:
+	.loc	2 243 36
+	mov.b32 	%r210, %f253;
+	shfl.sync.bfly.b32	%r211, %r210, 1, 31, -1;
+	mov.b32 	%f254, %r211;
+$L__tmp110:
+	.loc	2 233 15
+	add.f32 	%f255, %f253, %f254;
+$L__tmp111:
+	.loc	2 243 36
+	mov.b32 	%r212, %f464;
+	shfl.sync.bfly.b32	%r213, %r212, 16, 31, -1;
+	mov.b32 	%f256, %r213;
+$L__tmp112:
+	.loc	2 233 15
+	add.f32 	%f257, %f464, %f256;
+$L__tmp113:
+	.loc	2 243 36
+	mov.b32 	%r214, %f257;
+	shfl.sync.bfly.b32	%r215, %r214, 8, 31, -1;
+	mov.b32 	%f258, %r215;
+$L__tmp114:
+	.loc	2 233 15
+	add.f32 	%f259, %f257, %f258;
+$L__tmp115:
+	.loc	2 243 36
+	mov.b32 	%r216, %f259;
+	shfl.sync.bfly.b32	%r217, %r216, 4, 31, -1;
+	mov.b32 	%f260, %r217;
+$L__tmp116:
+	.loc	2 233 15
+	add.f32 	%f261, %f259, %f260;
+$L__tmp117:
+	.loc	2 243 36
+	mov.b32 	%r218, %f261;
+	shfl.sync.bfly.b32	%r219, %r218, 2, 31, -1;
+	mov.b32 	%f262, %r219;
+$L__tmp118:
+	.loc	2 233 15
+	add.f32 	%f263, %f261, %f262;
+$L__tmp119:
+	.loc	2 243 36
+	mov.b32 	%r220, %f263;
+	shfl.sync.bfly.b32	%r221, %r220, 1, 31, -1;
+	mov.b32 	%f264, %r221;
+$L__tmp120:
+	.loc	2 233 15
+	add.f32 	%f265, %f263, %f264;
+$L__tmp121:
+	.loc	2 243 36
+	mov.b32 	%r222, %f465;
+	shfl.sync.bfly.b32	%r223, %r222, 16, 31, -1;
+	mov.b32 	%f266, %r223;
+$L__tmp122:
+	.loc	2 233 15
+	add.f32 	%f267, %f465, %f266;
+$L__tmp123:
+	.loc	2 243 36
+	mov.b32 	%r224, %f267;
+	shfl.sync.bfly.b32	%r225, %r224, 8, 31, -1;
+	mov.b32 	%f268, %r225;
+$L__tmp124:
+	.loc	2 233 15
+	add.f32 	%f269, %f267, %f268;
+$L__tmp125:
+	.loc	2 243 36
+	mov.b32 	%r226, %f269;
+	shfl.sync.bfly.b32	%r227, %r226, 4, 31, -1;
+	mov.b32 	%f270, %r227;
+$L__tmp126:
+	.loc	2 233 15
+	add.f32 	%f271, %f269, %f270;
+$L__tmp127:
+	.loc	2 243 36
+	mov.b32 	%r228, %f271;
+	shfl.sync.bfly.b32	%r229, %r228, 2, 31, -1;
+	mov.b32 	%f272, %r229;
+$L__tmp128:
+	.loc	2 233 15
+	add.f32 	%f273, %f271, %f272;
+$L__tmp129:
+	.loc	2 243 36
+	mov.b32 	%r230, %f273;
+	shfl.sync.bfly.b32	%r231, %r230, 1, 31, -1;
+	mov.b32 	%f274, %r231;
+$L__tmp130:
+	.loc	2 233 15
+	add.f32 	%f275, %f273, %f274;
+$L__tmp131:
+	.loc	2 243 36
+	mov.b32 	%r232, %f466;
+	shfl.sync.bfly.b32	%r233, %r232, 16, 31, -1;
+	mov.b32 	%f276, %r233;
+$L__tmp132:
+	.loc	2 233 15
+	add.f32 	%f277, %f466, %f276;
+$L__tmp133:
+	.loc	2 243 36
+	mov.b32 	%r234, %f277;
+	shfl.sync.bfly.b32	%r235, %r234, 8, 31, -1;
+	mov.b32 	%f278, %r235;
+$L__tmp134:
+	.loc	2 233 15
+	add.f32 	%f279, %f277, %f278;
+$L__tmp135:
+	.loc	2 243 36
+	mov.b32 	%r236, %f279;
+	shfl.sync.bfly.b32	%r237, %r236, 4, 31, -1;
+	mov.b32 	%f280, %r237;
+$L__tmp136:
+	.loc	2 233 15
+	add.f32 	%f281, %f279, %f280;
+$L__tmp137:
+	.loc	2 243 36
+	mov.b32 	%r238, %f281;
+	shfl.sync.bfly.b32	%r239, %r238, 2, 31, -1;
+	mov.b32 	%f282, %r239;
+$L__tmp138:
+	.loc	2 233 15
+	add.f32 	%f283, %f281, %f282;
+$L__tmp139:
+	.loc	2 243 36
+	mov.b32 	%r240, %f283;
+	shfl.sync.bfly.b32	%r241, %r240, 1, 31, -1;
+	mov.b32 	%f284, %r241;
+$L__tmp140:
+	.loc	2 233 15
+	add.f32 	%f285, %f283, %f284;
+$L__tmp141:
+	.loc	2 243 36
+	mov.b32 	%r242, %f467;
+	shfl.sync.bfly.b32	%r243, %r242, 16, 31, -1;
+	mov.b32 	%f286, %r243;
+$L__tmp142:
+	.loc	2 233 15
+	add.f32 	%f287, %f467, %f286;
+$L__tmp143:
+	.loc	2 243 36
+	mov.b32 	%r244, %f287;
+	shfl.sync.bfly.b32	%r245, %r244, 8, 31, -1;
+	mov.b32 	%f288, %r245;
+$L__tmp144:
+	.loc	2 233 15
+	add.f32 	%f289, %f287, %f288;
+$L__tmp145:
+	.loc	2 243 36
+	mov.b32 	%r246, %f289;
+	shfl.sync.bfly.b32	%r247, %r246, 4, 31, -1;
+	mov.b32 	%f290, %r247;
+$L__tmp146:
+	.loc	2 233 15
+	add.f32 	%f291, %f289, %f290;
+$L__tmp147:
+	.loc	2 243 36
+	mov.b32 	%r248, %f291;
+	shfl.sync.bfly.b32	%r249, %r248, 2, 31, -1;
+	mov.b32 	%f292, %r249;
+$L__tmp148:
+	.loc	2 233 15
+	add.f32 	%f293, %f291, %f292;
+$L__tmp149:
+	.loc	2 243 36
+	mov.b32 	%r250, %f293;
+	shfl.sync.bfly.b32	%r251, %r250, 1, 31, -1;
+	mov.b32 	%f294, %r251;
+$L__tmp150:
+	.loc	2 233 15
+	add.f32 	%f295, %f293, %f294;
+$L__tmp151:
+	.loc	2 243 36
+	mov.b32 	%r252, %f468;
+	shfl.sync.bfly.b32	%r253, %r252, 16, 31, -1;
+	mov.b32 	%f296, %r253;
+$L__tmp152:
+	.loc	2 233 15
+	add.f32 	%f297, %f468, %f296;
+$L__tmp153:
+	.loc	2 243 36
+	mov.b32 	%r254, %f297;
+	shfl.sync.bfly.b32	%r255, %r254, 8, 31, -1;
+	mov.b32 	%f298, %r255;
+$L__tmp154:
+	.loc	2 233 15
+	add.f32 	%f299, %f297, %f298;
+$L__tmp155:
+	.loc	2 243 36
+	mov.b32 	%r256, %f299;
+	shfl.sync.bfly.b32	%r257, %r256, 4, 31, -1;
+	mov.b32 	%f300, %r257;
+$L__tmp156:
+	.loc	2 233 15
+	add.f32 	%f301, %f299, %f300;
+$L__tmp157:
+	.loc	2 243 36
+	mov.b32 	%r258, %f301;
+	shfl.sync.bfly.b32	%r259, %r258, 2, 31, -1;
+	mov.b32 	%f302, %r259;
+$L__tmp158:
+	.loc	2 233 15
+	add.f32 	%f303, %f301, %f302;
+$L__tmp159:
+	.loc	2 243 36
+	mov.b32 	%r260, %f303;
+	shfl.sync.bfly.b32	%r261, %r260, 1, 31, -1;
+	mov.b32 	%f304, %r261;
+$L__tmp160:
+	.loc	2 233 15
+	add.f32 	%f305, %f303, %f304;
+$L__tmp161:
+	.loc	2 243 36
+	setp.eq.s32 	%p68, %r2, 0;
+	shr.u32 	%r262, %r1, 3;
+	and.b32  	%r263, %r262, 4;
+	shl.b32 	%r264, %r101, 3;
+	or.b32  	%r265, %r264, %r263;
+	mov.u32 	%r266, global_smem;
+	add.s32 	%r64, %r266, %r265;
+	mov.b32 	%r65, %f155;
+	@%p68 st.shared.b32 [ %r64 + 0 ], %r65;
+	shl.b32 	%r267, %r3, 3;
+	or.b32  	%r268, %r267, %r263;
+	add.s32 	%r66, %r266, %r268;
+	mov.b32 	%r67, %f165;
+	@%p68 st.shared.b32 [ %r66 + 0 ], %r67;
+	shl.b32 	%r269, %r4, 3;
+	or.b32  	%r270, %r269, %r263;
+	add.s32 	%r68, %r266, %r270;
+	mov.b32 	%r69, %f175;
+	@%p68 st.shared.b32 [ %r68 + 0 ], %r69;
+	shl.b32 	%r271, %r5, 3;
+	or.b32  	%r272, %r271, %r263;
+	add.s32 	%r70, %r266, %r272;
+	mov.b32 	%r71, %f185;
+	@%p68 st.shared.b32 [ %r70 + 0 ], %r71;
+	shl.b32 	%r273, %r6, 3;
+	or.b32  	%r274, %r273, %r263;
+	add.s32 	%r72, %r266, %r274;
+	mov.b32 	%r73, %f195;
+	@%p68 st.shared.b32 [ %r72 + 0 ], %r73;
+	shl.b32 	%r275, %r7, 3;
+	or.b32  	%r276, %r275, %r263;
+	add.s32 	%r74, %r266, %r276;
+	mov.b32 	%r75, %f205;
+	@%p68 st.shared.b32 [ %r74 + 0 ], %r75;
+	shl.b32 	%r277, %r8, 3;
+	or.b32  	%r278, %r277, %r263;
+	add.s32 	%r76, %r266, %r278;
+	mov.b32 	%r77, %f215;
+	@%p68 st.shared.b32 [ %r76 + 0 ], %r77;
+	shl.b32 	%r279, %r9, 3;
+	or.b32  	%r280, %r279, %r263;
+	add.s32 	%r78, %r266, %r280;
+	mov.b32 	%r79, %f225;
+	@%p68 st.shared.b32 [ %r78 + 0 ], %r79;
+	shl.b32 	%r281, %r10, 3;
+	or.b32  	%r282, %r281, %r263;
+	add.s32 	%r80, %r266, %r282;
+	mov.b32 	%r81, %f235;
+	@%p68 st.shared.b32 [ %r80 + 0 ], %r81;
+	shl.b32 	%r283, %r11, 3;
+	or.b32  	%r284, %r283, %r263;
+	add.s32 	%r82, %r266, %r284;
+	mov.b32 	%r83, %f245;
+	@%p68 st.shared.b32 [ %r82 + 0 ], %r83;
+	shl.b32 	%r285, %r12, 3;
+	or.b32  	%r286, %r285, %r263;
+	add.s32 	%r84, %r266, %r286;
+	mov.b32 	%r85, %f255;
+	@%p68 st.shared.b32 [ %r84 + 0 ], %r85;
+	shl.b32 	%r287, %r13, 3;
+	or.b32  	%r288, %r287, %r263;
+	add.s32 	%r86, %r266, %r288;
+	mov.b32 	%r87, %f265;
+	@%p68 st.shared.b32 [ %r86 + 0 ], %r87;
+	shl.b32 	%r289, %r14, 3;
+	or.b32  	%r290, %r289, %r263;
+	add.s32 	%r88, %r266, %r290;
+	mov.b32 	%r89, %f275;
+	@%p68 st.shared.b32 [ %r88 + 0 ], %r89;
+	shl.b32 	%r291, %r15, 3;
+	or.b32  	%r292, %r291, %r263;
+	add.s32 	%r90, %r266, %r292;
+	mov.b32 	%r91, %f285;
+	@%p68 st.shared.b32 [ %r90 + 0 ], %r91;
+	shl.b32 	%r293, %r16, 3;
+	or.b32  	%r294, %r293, %r263;
+	add.s32 	%r92, %r266, %r294;
+	mov.b32 	%r93, %f295;
+	@%p68 st.shared.b32 [ %r92 + 0 ], %r93;
+	shl.b32 	%r295, %r17, 3;
+	or.b32  	%r296, %r295, %r263;
+	add.s32 	%r94, %r266, %r296;
+	mov.b32 	%r95, %f305;
+	@%p68 st.shared.b32 [ %r94 + 0 ], %r95;
+	bar.sync 	0;
+	setp.lt.s32 	%p84, %r1, 128;
+	shl.b32 	%r297, %r1, 2;
+	add.s32 	%r97, %r266, %r297;
+	@%p84 ld.shared.b32 %r96, [ %r97 + 0 ];
+	mov.b32 	%f306, %r96;
+	shfl.sync.bfly.b32	%r298, %r96, 1, 31, -1;
+	mov.b32 	%f307, %r298;
+$L__tmp162:
+	.loc	2 233 15
+	add.f32 	%f308, %f306, %f307;
+$L__tmp163:
+	.loc	2 243 36
+	and.b32  	%r299, %r1, 1;
+	setp.eq.b32 	%p86, %r299, 1;
+	not.pred 	%p87, %p86;
+	and.pred  	%p85, %p84, %p87;
+	mov.b32 	%r99, %f308;
+	@%p85 st.shared.b32 [ %r97 + 0 ], %r99;
+	bar.sync 	0;
+	add.s32 	%r300, %r266, %r264;
+	ld.shared.f32 	%f49, [%r300];
+	add.s32 	%r301, %r266, %r267;
+	ld.shared.f32 	%f50, [%r301];
+	add.s32 	%r302, %r266, %r269;
+	ld.shared.f32 	%f51, [%r302];
+	add.s32 	%r303, %r266, %r271;
+	ld.shared.f32 	%f52, [%r303];
+	add.s32 	%r304, %r266, %r273;
+	ld.shared.f32 	%f53, [%r304];
+	add.s32 	%r305, %r266, %r275;
+	ld.shared.f32 	%f54, [%r305];
+	add.s32 	%r306, %r266, %r277;
+	ld.shared.f32 	%f55, [%r306];
+	add.s32 	%r307, %r266, %r279;
+	ld.shared.f32 	%f56, [%r307];
+	add.s32 	%r308, %r266, %r281;
+	ld.shared.f32 	%f57, [%r308];
+	add.s32 	%r309, %r266, %r283;
+	ld.shared.f32 	%f58, [%r309];
+	add.s32 	%r310, %r266, %r285;
+	ld.shared.f32 	%f59, [%r310];
+	add.s32 	%r311, %r266, %r287;
+	ld.shared.f32 	%f60, [%r311];
+	add.s32 	%r312, %r266, %r289;
+	ld.shared.f32 	%f61, [%r312];
+	add.s32 	%r313, %r266, %r291;
+	ld.shared.f32 	%f62, [%r313];
+	add.s32 	%r314, %r266, %r293;
+	ld.shared.f32 	%f63, [%r314];
+	add.s32 	%r315, %r266, %r295;
+	ld.shared.f32 	%f64, [%r315];
+$L__tmp164:
+	.loc	1 51 36
+	shl.b64 	%rd80, %rd3, 1;
+	add.s64 	%rd7, %rd17, %rd80;
+	mul.lo.s64 	%rd81, %rd1, 6432896;
+	mul.lo.s64 	%rd82, %rd2, 100514;
+	add.s64 	%rd148, %rd81, %rd82;
+	add.s64 	%rd9, %rd16, %rd80;
+	add.s64 	%rd10, %rd15, %rd80;
+	mov.b32 	%r398, -64;
+	mov.u16 	%rs2, 0;
+$L__BB0_3:
+	add.s32 	%r398, %r398, 64;
+	.loc	1 52 27
+	add.s32 	%r396, %r398, %r18;
+	.loc	1 53 25
+	setp.lt.u32 	%p88, %r396, 50257;
+	.loc	1 55 35
+	add.s64 	%rd83, %rd10, %rd148;
+	add.s64 	%rd84, %rd83, 402056;
+	add.s64 	%rd85, %rd83, 804112;
+	add.s64 	%rd86, %rd83, 1206168;
+	add.s64 	%rd87, %rd83, 1608224;
+	add.s64 	%rd88, %rd83, 2010280;
+	add.s64 	%rd89, %rd83, 2412336;
+	add.s64 	%rd90, %rd83, 2814392;
+	add.s64 	%rd91, %rd83, 3216448;
+	add.s64 	%rd92, %rd83, 3618504;
+	add.s64 	%rd93, %rd83, 4020560;
+	add.s64 	%rd94, %rd83, 4422616;
+	add.s64 	%rd95, %rd83, 4824672;
+	add.s64 	%rd96, %rd83, 5226728;
+	add.s64 	%rd97, %rd83, 5628784;
+	.loc	1 55 53
+	add.s64 	%rd98, %rd83, 6030840;
+	mov.u16 %rs1, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs1 }, [ %rd83 + 0 ];
+	@!%p88 mov.u16 %rs1, %rs2;
+	mov.u16 %rs3, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs3 }, [ %rd84 + 0 ];
+	@!%p88 mov.u16 %rs3, %rs2;
+	mov.u16 %rs5, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs5 }, [ %rd85 + 0 ];
+	@!%p88 mov.u16 %rs5, %rs2;
+	mov.u16 %rs7, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs7 }, [ %rd86 + 0 ];
+	@!%p88 mov.u16 %rs7, %rs2;
+	mov.u16 %rs9, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs9 }, [ %rd87 + 0 ];
+	@!%p88 mov.u16 %rs9, %rs2;
+	mov.u16 %rs11, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs11 }, [ %rd88 + 0 ];
+	@!%p88 mov.u16 %rs11, %rs2;
+	mov.u16 %rs13, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs13 }, [ %rd89 + 0 ];
+	@!%p88 mov.u16 %rs13, %rs2;
+	mov.u16 %rs15, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs15 }, [ %rd90 + 0 ];
+	@!%p88 mov.u16 %rs15, %rs2;
+	mov.u16 %rs17, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs17 }, [ %rd91 + 0 ];
+	@!%p88 mov.u16 %rs17, %rs2;
+	mov.u16 %rs19, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs19 }, [ %rd92 + 0 ];
+	@!%p88 mov.u16 %rs19, %rs2;
+	mov.u16 %rs21, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs21 }, [ %rd93 + 0 ];
+	@!%p88 mov.u16 %rs21, %rs2;
+	mov.u16 %rs23, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs23 }, [ %rd94 + 0 ];
+	@!%p88 mov.u16 %rs23, %rs2;
+	mov.u16 %rs25, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs25 }, [ %rd95 + 0 ];
+	@!%p88 mov.u16 %rs25, %rs2;
+	mov.u16 %rs27, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs27 }, [ %rd96 + 0 ];
+	@!%p88 mov.u16 %rs27, %rs2;
+	mov.u16 %rs29, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs29 }, [ %rd97 + 0 ];
+	@!%p88 mov.u16 %rs29, %rs2;
+	mov.u16 %rs31, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs31 }, [ %rd98 + 0 ];
+	@!%p88 mov.u16 %rs31, %rs2;
+	.loc	1 55 105
+	cvt.f32.bf16 %r316, %rs1;
+	mov.b32 	%f341, %r316;
+	cvt.f32.bf16 %r317, %rs3;
+	mov.b32 	%f342, %r317;
+	cvt.f32.bf16 %r318, %rs5;
+	mov.b32 	%f343, %r318;
+	cvt.f32.bf16 %r319, %rs7;
+	mov.b32 	%f344, %r319;
+	cvt.f32.bf16 %r320, %rs9;
+	mov.b32 	%f345, %r320;
+	cvt.f32.bf16 %r321, %rs11;
+	mov.b32 	%f346, %r321;
+	cvt.f32.bf16 %r322, %rs13;
+	mov.b32 	%f347, %r322;
+	cvt.f32.bf16 %r323, %rs15;
+	mov.b32 	%f348, %r323;
+	cvt.f32.bf16 %r324, %rs17;
+	mov.b32 	%f349, %r324;
+	cvt.f32.bf16 %r325, %rs19;
+	mov.b32 	%f350, %r325;
+	cvt.f32.bf16 %r326, %rs21;
+	mov.b32 	%f351, %r326;
+	cvt.f32.bf16 %r327, %rs23;
+	mov.b32 	%f352, %r327;
+	cvt.f32.bf16 %r328, %rs25;
+	mov.b32 	%f353, %r328;
+	cvt.f32.bf16 %r329, %rs27;
+	mov.b32 	%f354, %r329;
+	cvt.f32.bf16 %r330, %rs29;
+	mov.b32 	%f355, %r330;
+	cvt.f32.bf16 %r331, %rs31;
+	mov.b32 	%f356, %r331;
+	.loc	1 56 35
+	add.s64 	%rd99, %rd149, -12061680;
+	add.s64 	%rd100, %rd149, -11257568;
+	add.s64 	%rd101, %rd149, -10453456;
+	add.s64 	%rd102, %rd149, -9649344;
+	add.s64 	%rd103, %rd149, -8845232;
+	add.s64 	%rd104, %rd149, -8041120;
+	add.s64 	%rd105, %rd149, -7237008;
+	add.s64 	%rd106, %rd149, -6432896;
+	add.s64 	%rd107, %rd149, -5628784;
+	add.s64 	%rd108, %rd149, -4824672;
+	add.s64 	%rd109, %rd149, -4020560;
+	add.s64 	%rd110, %rd149, -3216448;
+	add.s64 	%rd111, %rd149, -2412336;
+	add.s64 	%rd112, %rd149, -1608224;
+	add.s64 	%rd113, %rd149, -804112;
+	.loc	1 56 53
+	mov.u32 %r332, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r332 }, [ %rd99 + 0 ];
+	@!%p88 mov.u32 %r332, %r333;
+	mov.b32 	%f357, %r332;
+	mov.u32 %r334, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r334 }, [ %rd100 + 0 ];
+	@!%p88 mov.u32 %r334, %r333;
+	mov.b32 	%f358, %r334;
+	mov.u32 %r336, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r336 }, [ %rd101 + 0 ];
+	@!%p88 mov.u32 %r336, %r333;
+	mov.b32 	%f359, %r336;
+	mov.u32 %r338, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r338 }, [ %rd102 + 0 ];
+	@!%p88 mov.u32 %r338, %r333;
+	mov.b32 	%f360, %r338;
+	mov.u32 %r340, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r340 }, [ %rd103 + 0 ];
+	@!%p88 mov.u32 %r340, %r333;
+	mov.b32 	%f361, %r340;
+	mov.u32 %r342, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r342 }, [ %rd104 + 0 ];
+	@!%p88 mov.u32 %r342, %r333;
+	mov.b32 	%f362, %r342;
+	mov.u32 %r344, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r344 }, [ %rd105 + 0 ];
+	@!%p88 mov.u32 %r344, %r333;
+	mov.b32 	%f363, %r344;
+	mov.u32 %r346, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r346 }, [ %rd106 + 0 ];
+	@!%p88 mov.u32 %r346, %r333;
+	mov.b32 	%f364, %r346;
+	mov.u32 %r348, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r348 }, [ %rd107 + 0 ];
+	@!%p88 mov.u32 %r348, %r333;
+	mov.b32 	%f365, %r348;
+	mov.u32 %r350, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r350 }, [ %rd108 + 0 ];
+	@!%p88 mov.u32 %r350, %r333;
+	mov.b32 	%f366, %r350;
+	mov.u32 %r352, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r352 }, [ %rd109 + 0 ];
+	@!%p88 mov.u32 %r352, %r333;
+	mov.b32 	%f367, %r352;
+	mov.u32 %r354, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r354 }, [ %rd110 + 0 ];
+	@!%p88 mov.u32 %r354, %r333;
+	mov.b32 	%f368, %r354;
+	mov.u32 %r356, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r356 }, [ %rd111 + 0 ];
+	@!%p88 mov.u32 %r356, %r333;
+	mov.b32 	%f369, %r356;
+	mov.u32 %r358, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r358 }, [ %rd112 + 0 ];
+	@!%p88 mov.u32 %r358, %r333;
+	mov.b32 	%f370, %r358;
+	mov.u32 %r360, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r360 }, [ %rd113 + 0 ];
+	@!%p88 mov.u32 %r360, %r333;
+	mov.b32 	%f371, %r360;
+	mov.u32 %r362, 0x0;
+	@%p88 ld.global.L1::evict_first.b32 { %r362 }, [ %rd149 + 0 ];
+	@!%p88 mov.u32 %r362, %r333;
+	mov.b32 	%f372, %r362;
+	.loc	1 57 35
+	add.s64 	%rd115, %rd9, %rd148;
+	add.s64 	%rd116, %rd115, 402056;
+	add.s64 	%rd117, %rd115, 804112;
+	add.s64 	%rd118, %rd115, 1206168;
+	add.s64 	%rd119, %rd115, 1608224;
+	add.s64 	%rd120, %rd115, 2010280;
+	add.s64 	%rd121, %rd115, 2412336;
+	add.s64 	%rd122, %rd115, 2814392;
+	add.s64 	%rd123, %rd115, 3216448;
+	add.s64 	%rd124, %rd115, 3618504;
+	add.s64 	%rd125, %rd115, 4020560;
+	add.s64 	%rd126, %rd115, 4422616;
+	add.s64 	%rd127, %rd115, 4824672;
+	add.s64 	%rd128, %rd115, 5226728;
+	add.s64 	%rd129, %rd115, 5628784;
+	.loc	1 57 53
+	add.s64 	%rd130, %rd115, 6030840;
+	mov.u16 %rs49, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs49 }, [ %rd115 + 0 ];
+	@!%p88 mov.u16 %rs49, %rs2;
+	mov.u16 %rs51, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs51 }, [ %rd116 + 0 ];
+	@!%p88 mov.u16 %rs51, %rs2;
+	mov.u16 %rs53, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs53 }, [ %rd117 + 0 ];
+	@!%p88 mov.u16 %rs53, %rs2;
+	mov.u16 %rs55, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs55 }, [ %rd118 + 0 ];
+	@!%p88 mov.u16 %rs55, %rs2;
+	mov.u16 %rs57, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs57 }, [ %rd119 + 0 ];
+	@!%p88 mov.u16 %rs57, %rs2;
+	mov.u16 %rs59, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs59 }, [ %rd120 + 0 ];
+	@!%p88 mov.u16 %rs59, %rs2;
+	mov.u16 %rs61, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs61 }, [ %rd121 + 0 ];
+	@!%p88 mov.u16 %rs61, %rs2;
+	mov.u16 %rs63, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs63 }, [ %rd122 + 0 ];
+	@!%p88 mov.u16 %rs63, %rs2;
+	mov.u16 %rs65, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs65 }, [ %rd123 + 0 ];
+	@!%p88 mov.u16 %rs65, %rs2;
+	mov.u16 %rs67, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs67 }, [ %rd124 + 0 ];
+	@!%p88 mov.u16 %rs67, %rs2;
+	mov.u16 %rs69, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs69 }, [ %rd125 + 0 ];
+	@!%p88 mov.u16 %rs69, %rs2;
+	mov.u16 %rs71, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs71 }, [ %rd126 + 0 ];
+	@!%p88 mov.u16 %rs71, %rs2;
+	mov.u16 %rs73, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs73 }, [ %rd127 + 0 ];
+	@!%p88 mov.u16 %rs73, %rs2;
+	mov.u16 %rs75, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs75 }, [ %rd128 + 0 ];
+	@!%p88 mov.u16 %rs75, %rs2;
+	mov.u16 %rs77, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs77 }, [ %rd129 + 0 ];
+	@!%p88 mov.u16 %rs77, %rs2;
+	mov.u16 %rs79, 0x0;
+	@%p88 ld.global.L1::evict_first.b16 { %rs79 }, [ %rd130 + 0 ];
+	@!%p88 mov.u16 %rs79, %rs2;
+	.loc	1 57 105
+	cvt.f32.bf16 %r364, %rs49;
+	mov.b32 	%f373, %r364;
+	cvt.f32.bf16 %r365, %rs51;
+	mov.b32 	%f374, %r365;
+	cvt.f32.bf16 %r366, %rs53;
+	mov.b32 	%f375, %r366;
+	cvt.f32.bf16 %r367, %rs55;
+	mov.b32 	%f376, %r367;
+	cvt.f32.bf16 %r368, %rs57;
+	mov.b32 	%f377, %r368;
+	cvt.f32.bf16 %r369, %rs59;
+	mov.b32 	%f378, %r369;
+	cvt.f32.bf16 %r370, %rs61;
+	mov.b32 	%f379, %r370;
+	cvt.f32.bf16 %r371, %rs63;
+	mov.b32 	%f380, %r371;
+	cvt.f32.bf16 %r372, %rs65;
+	mov.b32 	%f381, %r372;
+	cvt.f32.bf16 %r373, %rs67;
+	mov.b32 	%f382, %r373;
+	cvt.f32.bf16 %r374, %rs69;
+	mov.b32 	%f383, %r374;
+	cvt.f32.bf16 %r375, %rs71;
+	mov.b32 	%f384, %r375;
+	cvt.f32.bf16 %r376, %rs73;
+	mov.b32 	%f385, %r376;
+	cvt.f32.bf16 %r377, %rs75;
+	mov.b32 	%f386, %r377;
+	cvt.f32.bf16 %r378, %rs77;
+	mov.b32 	%f387, %r378;
+	cvt.f32.bf16 %r379, %rs79;
+	mov.b32 	%f388, %r379;
+	.loc	1 65 23
+	mul.f32 	%f310, %f373, 0f3FB8AA3B;
+	ex2.approx.f32 %f309, %f310;
+	mul.f32 	%f312, %f374, 0f3FB8AA3B;
+	ex2.approx.f32 %f311, %f312;
+	mul.f32 	%f314, %f375, 0f3FB8AA3B;
+	ex2.approx.f32 %f313, %f314;
+	mul.f32 	%f316, %f376, 0f3FB8AA3B;
+	ex2.approx.f32 %f315, %f316;
+	mul.f32 	%f318, %f377, 0f3FB8AA3B;
+	ex2.approx.f32 %f317, %f318;
+	mul.f32 	%f320, %f378, 0f3FB8AA3B;
+	ex2.approx.f32 %f319, %f320;
+	mul.f32 	%f322, %f379, 0f3FB8AA3B;
+	ex2.approx.f32 %f321, %f322;
+	mul.f32 	%f324, %f380, 0f3FB8AA3B;
+	ex2.approx.f32 %f323, %f324;
+	mul.f32 	%f326, %f381, 0f3FB8AA3B;
+	ex2.approx.f32 %f325, %f326;
+	mul.f32 	%f328, %f382, 0f3FB8AA3B;
+	ex2.approx.f32 %f327, %f328;
+	mul.f32 	%f330, %f383, 0f3FB8AA3B;
+	ex2.approx.f32 %f329, %f330;
+	mul.f32 	%f332, %f384, 0f3FB8AA3B;
+	ex2.approx.f32 %f331, %f332;
+	mul.f32 	%f334, %f385, 0f3FB8AA3B;
+	ex2.approx.f32 %f333, %f334;
+	mul.f32 	%f336, %f386, 0f3FB8AA3B;
+	ex2.approx.f32 %f335, %f336;
+	mul.f32 	%f338, %f387, 0f3FB8AA3B;
+	ex2.approx.f32 %f337, %f338;
+	mul.f32 	%f340, %f388, 0f3FB8AA3B;
+	ex2.approx.f32 %f339, %f340;
+	.loc	1 66 24
+	mul.f32 	%f389, %f49, %f309;
+	mul.f32 	%f390, %f50, %f311;
+	mul.f32 	%f391, %f51, %f313;
+	mul.f32 	%f392, %f52, %f315;
+	mul.f32 	%f393, %f53, %f317;
+	mul.f32 	%f394, %f54, %f319;
+	mul.f32 	%f395, %f55, %f321;
+	mul.f32 	%f396, %f56, %f323;
+	mul.f32 	%f397, %f57, %f325;
+	mul.f32 	%f398, %f58, %f327;
+	mul.f32 	%f399, %f59, %f329;
+	mul.f32 	%f400, %f60, %f331;
+	mul.f32 	%f401, %f61, %f333;
+	mul.f32 	%f402, %f62, %f335;
+	mul.f32 	%f403, %f63, %f337;
+	mul.f32 	%f404, %f64, %f339;
+	.loc	1 67 24
+	neg.f32 	%f405, %f389;
+	fma.rn.f32 	%f406, %f1, %f357, %f405;
+	neg.f32 	%f407, %f390;
+	fma.rn.f32 	%f408, %f2, %f358, %f407;
+	neg.f32 	%f409, %f391;
+	fma.rn.f32 	%f410, %f3, %f359, %f409;
+	neg.f32 	%f411, %f392;
+	fma.rn.f32 	%f412, %f4, %f360, %f411;
+	neg.f32 	%f413, %f393;
+	fma.rn.f32 	%f414, %f5, %f361, %f413;
+	neg.f32 	%f415, %f394;
+	fma.rn.f32 	%f416, %f6, %f362, %f415;
+	neg.f32 	%f417, %f395;
+	fma.rn.f32 	%f418, %f7, %f363, %f417;
+	neg.f32 	%f419, %f396;
+	fma.rn.f32 	%f420, %f8, %f364, %f419;
+	neg.f32 	%f421, %f397;
+	fma.rn.f32 	%f422, %f9, %f365, %f421;
+	neg.f32 	%f423, %f398;
+	fma.rn.f32 	%f424, %f10, %f366, %f423;
+	neg.f32 	%f425, %f399;
+	fma.rn.f32 	%f426, %f11, %f367, %f425;
+	neg.f32 	%f427, %f400;
+	fma.rn.f32 	%f428, %f12, %f368, %f427;
+	neg.f32 	%f429, %f401;
+	fma.rn.f32 	%f430, %f13, %f369, %f429;
+	neg.f32 	%f431, %f402;
+	fma.rn.f32 	%f432, %f14, %f370, %f431;
+	neg.f32 	%f433, %f403;
+	fma.rn.f32 	%f434, %f15, %f371, %f433;
+	neg.f32 	%f435, %f404;
+	fma.rn.f32 	%f436, %f16, %f372, %f435;
+	.loc	1 69 24
+	add.f32 	%f437, %f341, %f406;
+	add.f32 	%f438, %f342, %f408;
+	add.f32 	%f439, %f343, %f410;
+	add.f32 	%f440, %f344, %f412;
+	add.f32 	%f441, %f345, %f414;
+	add.f32 	%f442, %f346, %f416;
+	add.f32 	%f443, %f347, %f418;
+	add.f32 	%f444, %f348, %f420;
+	add.f32 	%f445, %f349, %f422;
+	add.f32 	%f446, %f350, %f424;
+	add.f32 	%f447, %f351, %f426;
+	add.f32 	%f448, %f352, %f428;
+	add.f32 	%f449, %f353, %f430;
+	add.f32 	%f450, %f354, %f432;
+	add.f32 	%f451, %f355, %f434;
+	add.f32 	%f452, %f356, %f436;
+	.loc	1 70 29
+	add.s64 	%rd131, %rd7, %rd148;
+	add.s64 	%rd132, %rd131, 402056;
+	add.s64 	%rd133, %rd131, 804112;
+	add.s64 	%rd134, %rd131, 1206168;
+	add.s64 	%rd135, %rd131, 1608224;
+	add.s64 	%rd136, %rd131, 2010280;
+	add.s64 	%rd137, %rd131, 2412336;
+	add.s64 	%rd138, %rd131, 2814392;
+	add.s64 	%rd139, %rd131, 3216448;
+	add.s64 	%rd140, %rd131, 3618504;
+	add.s64 	%rd141, %rd131, 4020560;
+	add.s64 	%rd142, %rd131, 4422616;
+	add.s64 	%rd143, %rd131, 4824672;
+	add.s64 	%rd144, %rd131, 5226728;
+	add.s64 	%rd145, %rd131, 5628784;
+	.loc	1 70 54
+	add.s64 	%rd146, %rd131, 6030840;
+	mov.b32 	%r380, %f437;
+	cvt.rn.bf16.f32 %rs97, %r380;
+	mov.b32 	%r381, %f438;
+	cvt.rn.bf16.f32 %rs98, %r381;
+	mov.b32 	%r382, %f439;
+	cvt.rn.bf16.f32 %rs99, %r382;
+	mov.b32 	%r383, %f440;
+	cvt.rn.bf16.f32 %rs100, %r383;
+	mov.b32 	%r384, %f441;
+	cvt.rn.bf16.f32 %rs101, %r384;
+	mov.b32 	%r385, %f442;
+	cvt.rn.bf16.f32 %rs102, %r385;
+	mov.b32 	%r386, %f443;
+	cvt.rn.bf16.f32 %rs103, %r386;
+	mov.b32 	%r387, %f444;
+	cvt.rn.bf16.f32 %rs104, %r387;
+	mov.b32 	%r388, %f445;
+	cvt.rn.bf16.f32 %rs105, %r388;
+	mov.b32 	%r389, %f446;
+	cvt.rn.bf16.f32 %rs106, %r389;
+	mov.b32 	%r390, %f447;
+	cvt.rn.bf16.f32 %rs107, %r390;
+	mov.b32 	%r391, %f448;
+	cvt.rn.bf16.f32 %rs108, %r391;
+	mov.b32 	%r392, %f449;
+	cvt.rn.bf16.f32 %rs109, %r392;
+	mov.b32 	%r393, %f450;
+	cvt.rn.bf16.f32 %rs110, %r393;
+	mov.b32 	%r394, %f451;
+	cvt.rn.bf16.f32 %rs111, %r394;
+	mov.b32 	%r395, %f452;
+	cvt.rn.bf16.f32 %rs112, %r395;
+	@%p88 st.global.b16 [ %rd131 + 0 ], { %rs97 };
+	@%p88 st.global.b16 [ %rd132 + 0 ], { %rs98 };
+	@%p88 st.global.b16 [ %rd133 + 0 ], { %rs99 };
+	@%p88 st.global.b16 [ %rd134 + 0 ], { %rs100 };
+	@%p88 st.global.b16 [ %rd135 + 0 ], { %rs101 };
+	@%p88 st.global.b16 [ %rd136 + 0 ], { %rs102 };
+	@%p88 st.global.b16 [ %rd137 + 0 ], { %rs103 };
+	@%p88 st.global.b16 [ %rd138 + 0 ], { %rs104 };
+	@%p88 st.global.b16 [ %rd139 + 0 ], { %rs105 };
+	@%p88 st.global.b16 [ %rd140 + 0 ], { %rs106 };
+	@%p88 st.global.b16 [ %rd141 + 0 ], { %rs107 };
+	@%p88 st.global.b16 [ %rd142 + 0 ], { %rs108 };
+	@%p88 st.global.b16 [ %rd143 + 0 ], { %rs109 };
+	@%p88 st.global.b16 [ %rd144 + 0 ], { %rs110 };
+	@%p88 st.global.b16 [ %rd145 + 0 ], { %rs111 };
+	@%p88 st.global.b16 [ %rd146 + 0 ], { %rs112 };
+	.loc	1 51 36
+	add.s64 	%rd149, %rd149, 256;
+	add.s64 	%rd148, %rd148, 128;
+	setp.lt.u32 	%p200, %r398, 50193;
+	@%p200 bra 	$L__BB0_3;
+	.loc	1 51 4
+	ret;
+$L__tmp165:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/kz/ckzgl7thb4xdfkfnd2tidks6mt5f3hauwfyjflbtzyepo5oxkvhk.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
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+.b8 11
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+.b8 87
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+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 278
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
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+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
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+.b8 116
+.b8 111
+.b8 110
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+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
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+.b64 $L__tmp1
+.b64 $L__tmp164
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+.b64 $L__tmp2
+.b64 $L__tmp163
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
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+.b8 56
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 282
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/415aac87553b7d064f52694fa7254686/triton_.llir

@@ -0,0 +1,860 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1
+
+define void @triton__0d1d2de(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2) local_unnamed_addr !dbg !7 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
+  %5 = shl i32 %4, 3, !dbg !10
+  %6 = and i32 %5, 1016, !dbg !10
+  %7 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #4, !dbg !11
+  %8 = shl i32 %7, 10, !dbg !12
+  %9 = or i32 %8, %6, !dbg !13
+  %10 = sext i32 %9 to i64, !dbg !14
+  %11 = getelementptr i16, ptr addrspace(1) %0, i64 %10, !dbg !14
+  %12 = tail call { i32, i32, i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09mov.u32 $2, 0x0;\0A\09mov.u32 $3, 0x0;\0A\09@$5 ld.global.v4.b32 { $0, $1, $2, $3 }, [ $4 + 0 ];", "=r,=r,=r,=r,l,b"(ptr addrspace(1) %11, i1 true) #4, !dbg !15
+  %13 = extractvalue { i32, i32, i32, i32 } %12, 0, !dbg !15
+  %14 = extractvalue { i32, i32, i32, i32 } %12, 1, !dbg !15
+  %15 = extractvalue { i32, i32, i32, i32 } %12, 2, !dbg !15
+  %16 = extractvalue { i32, i32, i32, i32 } %12, 3, !dbg !15
+  %17 = trunc i32 %13 to i16, !dbg !15
+  %extelt.offset = lshr i32 %13, 16, !dbg !15
+  %18 = trunc i32 %extelt.offset to i16, !dbg !15
+  %19 = trunc i32 %14 to i16, !dbg !15
+  %extelt.offset1 = lshr i32 %14, 16, !dbg !15
+  %20 = trunc i32 %extelt.offset1 to i16, !dbg !15
+  %21 = trunc i32 %15 to i16, !dbg !15
+  %extelt.offset2 = lshr i32 %15, 16, !dbg !15
+  %22 = trunc i32 %extelt.offset2 to i16, !dbg !15
+  %23 = trunc i32 %16 to i16, !dbg !15
+  %extelt.offset3 = lshr i32 %16, 16, !dbg !15
+  %24 = trunc i32 %extelt.offset3 to i16, !dbg !15
+  %25 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %17) #4, !dbg !16
+  %26 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %18) #4, !dbg !16
+  %27 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %19) #4, !dbg !16
+  %28 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %20) #4, !dbg !16
+  %29 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %21) #4, !dbg !16
+  %30 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %22) #4, !dbg !16
+  %31 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %23) #4, !dbg !16
+  %32 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %24) #4, !dbg !16
+  %33 = fmul float %25, 0x3FE6A09E60000000, !dbg !17
+  %34 = fmul float %26, 0x3FE6A09E60000000, !dbg !17
+  %35 = fmul float %27, 0x3FE6A09E60000000, !dbg !17
+  %36 = fmul float %28, 0x3FE6A09E60000000, !dbg !17
+  %37 = fmul float %29, 0x3FE6A09E60000000, !dbg !17
+  %38 = fmul float %30, 0x3FE6A09E60000000, !dbg !17
+  %39 = fmul float %31, 0x3FE6A09E60000000, !dbg !17
+  %40 = fmul float %32, 0x3FE6A09E60000000, !dbg !17
+  %41 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i = icmp eq i32 %41, 0, !dbg !18
+  %42 = tail call float @llvm.nvvm.fabs.ftz.f(float %33) #4, !dbg !18
+  %43 = tail call float @llvm.nvvm.fabs.f(float %33) #4, !dbg !18
+  %.0.i = select i1 %.not.i, float %43, float %42, !dbg !18
+  %44 = fcmp oge float %.0.i, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %44, label %__nv_fabsf.exit1.i, label %46, !dbg !18
+
+__nv_fabsf.exit1.i:                               ; preds = %3
+  %45 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i = icmp eq i32 %45, 0, !dbg !18
+  %.01.i = select i1 %.not1.i, float %43, float %42, !dbg !18
+  br label %__internal_fmad.exit.i, !dbg !18
+
+46:                                               ; preds = %3
+  %47 = fmul float %33, %33, !dbg !18
+  br label %__internal_fmad.exit.i, !dbg !18
+
+__internal_fmad.exit.i:                           ; preds = %46, %__nv_fabsf.exit1.i
+  %48 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i ], [ 0x3FC06EBA60000000, %46 ], !dbg !18
+  %49 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i ], [ 0xBFD8127580000000, %46 ], !dbg !18
+  %50 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i ], [ 0x3FBCE315E0000000, %46 ], !dbg !18
+  %51 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i ], [ 0xBF9B837CE0000000, %46 ], !dbg !18
+  %52 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i ], [ 0x3F755ABD40000000, %46 ], !dbg !18
+  %53 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i ], [ 0xBF4AE9A400000000, %46 ], !dbg !18
+  %54 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i ], [ 0x3F163D2D40000000, %46 ], !dbg !18
+  %55 = phi float [ %.01.i, %__nv_fabsf.exit1.i ], [ %47, %46 ], !dbg !18
+  %56 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i = icmp eq i32 %56, 0, !dbg !18
+  %57 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %54, float %55, float %53) #4, !dbg !18
+  %58 = tail call float @llvm.nvvm.fma.rn.f(float %54, float %55, float %53) #4, !dbg !18
+  %.02.i = select i1 %.not2.i, float %58, float %57, !dbg !18
+  %59 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i = icmp eq i32 %59, 0, !dbg !18
+  %60 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i, float %55, float %52) #4, !dbg !18
+  %61 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i, float %55, float %52) #4, !dbg !18
+  %.03.i = select i1 %.not3.i, float %61, float %60, !dbg !18
+  %62 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i = icmp eq i32 %62, 0, !dbg !18
+  %63 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i, float %55, float %51) #4, !dbg !18
+  %64 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i, float %55, float %51) #4, !dbg !18
+  %.04.i = select i1 %.not4.i, float %64, float %63, !dbg !18
+  %65 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i = icmp eq i32 %65, 0, !dbg !18
+  %66 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i, float %55, float %50) #4, !dbg !18
+  %67 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i, float %55, float %50) #4, !dbg !18
+  %.05.i = select i1 %.not5.i, float %67, float %66, !dbg !18
+  %68 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i = icmp eq i32 %68, 0, !dbg !18
+  %69 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i, float %55, float %49) #4, !dbg !18
+  %70 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i, float %55, float %49) #4, !dbg !18
+  %.06.i = select i1 %.not6.i, float %70, float %69, !dbg !18
+  %71 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i = icmp eq i32 %71, 0, !dbg !18
+  %72 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i, float %55, float %48) #4, !dbg !18
+  %73 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i, float %55, float %48) #4, !dbg !18
+  %.07.i = select i1 %.not7.i, float %73, float %72, !dbg !18
+  %74 = fneg float %55, !dbg !18
+  %75 = select i1 %44, float %74, float %33, !dbg !18
+  %76 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i = icmp eq i32 %76, 0, !dbg !18
+  %77 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i, float %75, float %75) #4, !dbg !18
+  %78 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i, float %75, float %75) #4, !dbg !18
+  %.08.i = select i1 %.not8.i, float %78, float %77, !dbg !18
+  br i1 %44, label %79, label %__nv_erff.exit, !dbg !18
+
+79:                                               ; preds = %__internal_fmad.exit.i
+  %80 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i) #4, !dbg !18
+  %81 = fsub float 1.000000e+00, %80, !dbg !18
+  %82 = bitcast float %81 to i32, !dbg !18
+  %83 = bitcast float %33 to i32, !dbg !18
+  %84 = and i32 %83, -2147483648, !dbg !18
+  %85 = or i32 %84, %82, !dbg !18
+  %86 = bitcast i32 %85 to float, !dbg !18
+  br label %__nv_erff.exit, !dbg !18
+
+__nv_erff.exit:                                   ; preds = %__internal_fmad.exit.i, %79
+  %r.0.i = phi float [ %86, %79 ], [ %.08.i, %__internal_fmad.exit.i ], !dbg !18
+  %87 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i4 = icmp eq i32 %87, 0, !dbg !18
+  %88 = tail call float @llvm.nvvm.fabs.ftz.f(float %34) #4, !dbg !18
+  %89 = tail call float @llvm.nvvm.fabs.f(float %34) #4, !dbg !18
+  %.0.i5 = select i1 %.not.i4, float %89, float %88, !dbg !18
+  %90 = fcmp oge float %.0.i5, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %90, label %__nv_fabsf.exit1.i22, label %92, !dbg !18
+
+__nv_fabsf.exit1.i22:                             ; preds = %__nv_erff.exit
+  %91 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i23 = icmp eq i32 %91, 0, !dbg !18
+  %.01.i24 = select i1 %.not1.i23, float %89, float %88, !dbg !18
+  br label %__internal_fmad.exit.i6, !dbg !18
+
+92:                                               ; preds = %__nv_erff.exit
+  %93 = fmul float %34, %34, !dbg !18
+  br label %__internal_fmad.exit.i6, !dbg !18
+
+__internal_fmad.exit.i6:                          ; preds = %92, %__nv_fabsf.exit1.i22
+  %94 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i22 ], [ 0x3FC06EBA60000000, %92 ], !dbg !18
+  %95 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i22 ], [ 0xBFD8127580000000, %92 ], !dbg !18
+  %96 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i22 ], [ 0x3FBCE315E0000000, %92 ], !dbg !18
+  %97 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i22 ], [ 0xBF9B837CE0000000, %92 ], !dbg !18
+  %98 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i22 ], [ 0x3F755ABD40000000, %92 ], !dbg !18
+  %99 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i22 ], [ 0xBF4AE9A400000000, %92 ], !dbg !18
+  %100 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i22 ], [ 0x3F163D2D40000000, %92 ], !dbg !18
+  %101 = phi float [ %.01.i24, %__nv_fabsf.exit1.i22 ], [ %93, %92 ], !dbg !18
+  %102 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i7 = icmp eq i32 %102, 0, !dbg !18
+  %103 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %100, float %101, float %99) #4, !dbg !18
+  %104 = tail call float @llvm.nvvm.fma.rn.f(float %100, float %101, float %99) #4, !dbg !18
+  %.02.i8 = select i1 %.not2.i7, float %104, float %103, !dbg !18
+  %105 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i9 = icmp eq i32 %105, 0, !dbg !18
+  %106 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i8, float %101, float %98) #4, !dbg !18
+  %107 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i8, float %101, float %98) #4, !dbg !18
+  %.03.i10 = select i1 %.not3.i9, float %107, float %106, !dbg !18
+  %108 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i11 = icmp eq i32 %108, 0, !dbg !18
+  %109 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i10, float %101, float %97) #4, !dbg !18
+  %110 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i10, float %101, float %97) #4, !dbg !18
+  %.04.i12 = select i1 %.not4.i11, float %110, float %109, !dbg !18
+  %111 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i13 = icmp eq i32 %111, 0, !dbg !18
+  %112 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i12, float %101, float %96) #4, !dbg !18
+  %113 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i12, float %101, float %96) #4, !dbg !18
+  %.05.i14 = select i1 %.not5.i13, float %113, float %112, !dbg !18
+  %114 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i15 = icmp eq i32 %114, 0, !dbg !18
+  %115 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i14, float %101, float %95) #4, !dbg !18
+  %116 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i14, float %101, float %95) #4, !dbg !18
+  %.06.i16 = select i1 %.not6.i15, float %116, float %115, !dbg !18
+  %117 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i17 = icmp eq i32 %117, 0, !dbg !18
+  %118 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i16, float %101, float %94) #4, !dbg !18
+  %119 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i16, float %101, float %94) #4, !dbg !18
+  %.07.i18 = select i1 %.not7.i17, float %119, float %118, !dbg !18
+  %120 = fneg float %101, !dbg !18
+  %121 = select i1 %90, float %120, float %34, !dbg !18
+  %122 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i19 = icmp eq i32 %122, 0, !dbg !18
+  %123 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i18, float %121, float %121) #4, !dbg !18
+  %124 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i18, float %121, float %121) #4, !dbg !18
+  %.08.i20 = select i1 %.not8.i19, float %124, float %123, !dbg !18
+  br i1 %90, label %125, label %__nv_erff.exit25, !dbg !18
+
+125:                                              ; preds = %__internal_fmad.exit.i6
+  %126 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i20) #4, !dbg !18
+  %127 = fsub float 1.000000e+00, %126, !dbg !18
+  %128 = bitcast float %127 to i32, !dbg !18
+  %129 = bitcast float %34 to i32, !dbg !18
+  %130 = and i32 %129, -2147483648, !dbg !18
+  %131 = or i32 %130, %128, !dbg !18
+  %132 = bitcast i32 %131 to float, !dbg !18
+  br label %__nv_erff.exit25, !dbg !18
+
+__nv_erff.exit25:                                 ; preds = %__internal_fmad.exit.i6, %125
+  %r.0.i21 = phi float [ %132, %125 ], [ %.08.i20, %__internal_fmad.exit.i6 ], !dbg !18
+  %133 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i26 = icmp eq i32 %133, 0, !dbg !18
+  %134 = tail call float @llvm.nvvm.fabs.ftz.f(float %35) #4, !dbg !18
+  %135 = tail call float @llvm.nvvm.fabs.f(float %35) #4, !dbg !18
+  %.0.i27 = select i1 %.not.i26, float %135, float %134, !dbg !18
+  %136 = fcmp oge float %.0.i27, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %136, label %__nv_fabsf.exit1.i44, label %138, !dbg !18
+
+__nv_fabsf.exit1.i44:                             ; preds = %__nv_erff.exit25
+  %137 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i45 = icmp eq i32 %137, 0, !dbg !18
+  %.01.i46 = select i1 %.not1.i45, float %135, float %134, !dbg !18
+  br label %__internal_fmad.exit.i28, !dbg !18
+
+138:                                              ; preds = %__nv_erff.exit25
+  %139 = fmul float %35, %35, !dbg !18
+  br label %__internal_fmad.exit.i28, !dbg !18
+
+__internal_fmad.exit.i28:                         ; preds = %138, %__nv_fabsf.exit1.i44
+  %140 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i44 ], [ 0x3FC06EBA60000000, %138 ], !dbg !18
+  %141 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i44 ], [ 0xBFD8127580000000, %138 ], !dbg !18
+  %142 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i44 ], [ 0x3FBCE315E0000000, %138 ], !dbg !18
+  %143 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i44 ], [ 0xBF9B837CE0000000, %138 ], !dbg !18
+  %144 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i44 ], [ 0x3F755ABD40000000, %138 ], !dbg !18
+  %145 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i44 ], [ 0xBF4AE9A400000000, %138 ], !dbg !18
+  %146 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i44 ], [ 0x3F163D2D40000000, %138 ], !dbg !18
+  %147 = phi float [ %.01.i46, %__nv_fabsf.exit1.i44 ], [ %139, %138 ], !dbg !18
+  %148 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i29 = icmp eq i32 %148, 0, !dbg !18
+  %149 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %146, float %147, float %145) #4, !dbg !18
+  %150 = tail call float @llvm.nvvm.fma.rn.f(float %146, float %147, float %145) #4, !dbg !18
+  %.02.i30 = select i1 %.not2.i29, float %150, float %149, !dbg !18
+  %151 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i31 = icmp eq i32 %151, 0, !dbg !18
+  %152 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i30, float %147, float %144) #4, !dbg !18
+  %153 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i30, float %147, float %144) #4, !dbg !18
+  %.03.i32 = select i1 %.not3.i31, float %153, float %152, !dbg !18
+  %154 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i33 = icmp eq i32 %154, 0, !dbg !18
+  %155 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i32, float %147, float %143) #4, !dbg !18
+  %156 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i32, float %147, float %143) #4, !dbg !18
+  %.04.i34 = select i1 %.not4.i33, float %156, float %155, !dbg !18
+  %157 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i35 = icmp eq i32 %157, 0, !dbg !18
+  %158 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i34, float %147, float %142) #4, !dbg !18
+  %159 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i34, float %147, float %142) #4, !dbg !18
+  %.05.i36 = select i1 %.not5.i35, float %159, float %158, !dbg !18
+  %160 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i37 = icmp eq i32 %160, 0, !dbg !18
+  %161 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i36, float %147, float %141) #4, !dbg !18
+  %162 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i36, float %147, float %141) #4, !dbg !18
+  %.06.i38 = select i1 %.not6.i37, float %162, float %161, !dbg !18
+  %163 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i39 = icmp eq i32 %163, 0, !dbg !18
+  %164 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i38, float %147, float %140) #4, !dbg !18
+  %165 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i38, float %147, float %140) #4, !dbg !18
+  %.07.i40 = select i1 %.not7.i39, float %165, float %164, !dbg !18
+  %166 = fneg float %147, !dbg !18
+  %167 = select i1 %136, float %166, float %35, !dbg !18
+  %168 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i41 = icmp eq i32 %168, 0, !dbg !18
+  %169 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i40, float %167, float %167) #4, !dbg !18
+  %170 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i40, float %167, float %167) #4, !dbg !18
+  %.08.i42 = select i1 %.not8.i41, float %170, float %169, !dbg !18
+  br i1 %136, label %171, label %__nv_erff.exit47, !dbg !18
+
+171:                                              ; preds = %__internal_fmad.exit.i28
+  %172 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i42) #4, !dbg !18
+  %173 = fsub float 1.000000e+00, %172, !dbg !18
+  %174 = bitcast float %173 to i32, !dbg !18
+  %175 = bitcast float %35 to i32, !dbg !18
+  %176 = and i32 %175, -2147483648, !dbg !18
+  %177 = or i32 %176, %174, !dbg !18
+  %178 = bitcast i32 %177 to float, !dbg !18
+  br label %__nv_erff.exit47, !dbg !18
+
+__nv_erff.exit47:                                 ; preds = %__internal_fmad.exit.i28, %171
+  %r.0.i43 = phi float [ %178, %171 ], [ %.08.i42, %__internal_fmad.exit.i28 ], !dbg !18
+  %179 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i48 = icmp eq i32 %179, 0, !dbg !18
+  %180 = tail call float @llvm.nvvm.fabs.ftz.f(float %36) #4, !dbg !18
+  %181 = tail call float @llvm.nvvm.fabs.f(float %36) #4, !dbg !18
+  %.0.i49 = select i1 %.not.i48, float %181, float %180, !dbg !18
+  %182 = fcmp oge float %.0.i49, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %182, label %__nv_fabsf.exit1.i66, label %184, !dbg !18
+
+__nv_fabsf.exit1.i66:                             ; preds = %__nv_erff.exit47
+  %183 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i67 = icmp eq i32 %183, 0, !dbg !18
+  %.01.i68 = select i1 %.not1.i67, float %181, float %180, !dbg !18
+  br label %__internal_fmad.exit.i50, !dbg !18
+
+184:                                              ; preds = %__nv_erff.exit47
+  %185 = fmul float %36, %36, !dbg !18
+  br label %__internal_fmad.exit.i50, !dbg !18
+
+__internal_fmad.exit.i50:                         ; preds = %184, %__nv_fabsf.exit1.i66
+  %186 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i66 ], [ 0x3FC06EBA60000000, %184 ], !dbg !18
+  %187 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i66 ], [ 0xBFD8127580000000, %184 ], !dbg !18
+  %188 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i66 ], [ 0x3FBCE315E0000000, %184 ], !dbg !18
+  %189 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i66 ], [ 0xBF9B837CE0000000, %184 ], !dbg !18
+  %190 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i66 ], [ 0x3F755ABD40000000, %184 ], !dbg !18
+  %191 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i66 ], [ 0xBF4AE9A400000000, %184 ], !dbg !18
+  %192 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i66 ], [ 0x3F163D2D40000000, %184 ], !dbg !18
+  %193 = phi float [ %.01.i68, %__nv_fabsf.exit1.i66 ], [ %185, %184 ], !dbg !18
+  %194 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i51 = icmp eq i32 %194, 0, !dbg !18
+  %195 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %192, float %193, float %191) #4, !dbg !18
+  %196 = tail call float @llvm.nvvm.fma.rn.f(float %192, float %193, float %191) #4, !dbg !18
+  %.02.i52 = select i1 %.not2.i51, float %196, float %195, !dbg !18
+  %197 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i53 = icmp eq i32 %197, 0, !dbg !18
+  %198 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i52, float %193, float %190) #4, !dbg !18
+  %199 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i52, float %193, float %190) #4, !dbg !18
+  %.03.i54 = select i1 %.not3.i53, float %199, float %198, !dbg !18
+  %200 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i55 = icmp eq i32 %200, 0, !dbg !18
+  %201 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i54, float %193, float %189) #4, !dbg !18
+  %202 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i54, float %193, float %189) #4, !dbg !18
+  %.04.i56 = select i1 %.not4.i55, float %202, float %201, !dbg !18
+  %203 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i57 = icmp eq i32 %203, 0, !dbg !18
+  %204 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i56, float %193, float %188) #4, !dbg !18
+  %205 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i56, float %193, float %188) #4, !dbg !18
+  %.05.i58 = select i1 %.not5.i57, float %205, float %204, !dbg !18
+  %206 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i59 = icmp eq i32 %206, 0, !dbg !18
+  %207 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i58, float %193, float %187) #4, !dbg !18
+  %208 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i58, float %193, float %187) #4, !dbg !18
+  %.06.i60 = select i1 %.not6.i59, float %208, float %207, !dbg !18
+  %209 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i61 = icmp eq i32 %209, 0, !dbg !18
+  %210 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i60, float %193, float %186) #4, !dbg !18
+  %211 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i60, float %193, float %186) #4, !dbg !18
+  %.07.i62 = select i1 %.not7.i61, float %211, float %210, !dbg !18
+  %212 = fneg float %193, !dbg !18
+  %213 = select i1 %182, float %212, float %36, !dbg !18
+  %214 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i63 = icmp eq i32 %214, 0, !dbg !18
+  %215 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i62, float %213, float %213) #4, !dbg !18
+  %216 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i62, float %213, float %213) #4, !dbg !18
+  %.08.i64 = select i1 %.not8.i63, float %216, float %215, !dbg !18
+  br i1 %182, label %217, label %__nv_erff.exit69, !dbg !18
+
+217:                                              ; preds = %__internal_fmad.exit.i50
+  %218 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i64) #4, !dbg !18
+  %219 = fsub float 1.000000e+00, %218, !dbg !18
+  %220 = bitcast float %219 to i32, !dbg !18
+  %221 = bitcast float %36 to i32, !dbg !18
+  %222 = and i32 %221, -2147483648, !dbg !18
+  %223 = or i32 %222, %220, !dbg !18
+  %224 = bitcast i32 %223 to float, !dbg !18
+  br label %__nv_erff.exit69, !dbg !18
+
+__nv_erff.exit69:                                 ; preds = %__internal_fmad.exit.i50, %217
+  %r.0.i65 = phi float [ %224, %217 ], [ %.08.i64, %__internal_fmad.exit.i50 ], !dbg !18
+  %225 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i70 = icmp eq i32 %225, 0, !dbg !18
+  %226 = tail call float @llvm.nvvm.fabs.ftz.f(float %37) #4, !dbg !18
+  %227 = tail call float @llvm.nvvm.fabs.f(float %37) #4, !dbg !18
+  %.0.i71 = select i1 %.not.i70, float %227, float %226, !dbg !18
+  %228 = fcmp oge float %.0.i71, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %228, label %__nv_fabsf.exit1.i88, label %230, !dbg !18
+
+__nv_fabsf.exit1.i88:                             ; preds = %__nv_erff.exit69
+  %229 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i89 = icmp eq i32 %229, 0, !dbg !18
+  %.01.i90 = select i1 %.not1.i89, float %227, float %226, !dbg !18
+  br label %__internal_fmad.exit.i72, !dbg !18
+
+230:                                              ; preds = %__nv_erff.exit69
+  %231 = fmul float %37, %37, !dbg !18
+  br label %__internal_fmad.exit.i72, !dbg !18
+
+__internal_fmad.exit.i72:                         ; preds = %230, %__nv_fabsf.exit1.i88
+  %232 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i88 ], [ 0x3FC06EBA60000000, %230 ], !dbg !18
+  %233 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i88 ], [ 0xBFD8127580000000, %230 ], !dbg !18
+  %234 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i88 ], [ 0x3FBCE315E0000000, %230 ], !dbg !18
+  %235 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i88 ], [ 0xBF9B837CE0000000, %230 ], !dbg !18
+  %236 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i88 ], [ 0x3F755ABD40000000, %230 ], !dbg !18
+  %237 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i88 ], [ 0xBF4AE9A400000000, %230 ], !dbg !18
+  %238 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i88 ], [ 0x3F163D2D40000000, %230 ], !dbg !18
+  %239 = phi float [ %.01.i90, %__nv_fabsf.exit1.i88 ], [ %231, %230 ], !dbg !18
+  %240 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i73 = icmp eq i32 %240, 0, !dbg !18
+  %241 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %238, float %239, float %237) #4, !dbg !18
+  %242 = tail call float @llvm.nvvm.fma.rn.f(float %238, float %239, float %237) #4, !dbg !18
+  %.02.i74 = select i1 %.not2.i73, float %242, float %241, !dbg !18
+  %243 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i75 = icmp eq i32 %243, 0, !dbg !18
+  %244 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i74, float %239, float %236) #4, !dbg !18
+  %245 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i74, float %239, float %236) #4, !dbg !18
+  %.03.i76 = select i1 %.not3.i75, float %245, float %244, !dbg !18
+  %246 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i77 = icmp eq i32 %246, 0, !dbg !18
+  %247 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i76, float %239, float %235) #4, !dbg !18
+  %248 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i76, float %239, float %235) #4, !dbg !18
+  %.04.i78 = select i1 %.not4.i77, float %248, float %247, !dbg !18
+  %249 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i79 = icmp eq i32 %249, 0, !dbg !18
+  %250 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i78, float %239, float %234) #4, !dbg !18
+  %251 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i78, float %239, float %234) #4, !dbg !18
+  %.05.i80 = select i1 %.not5.i79, float %251, float %250, !dbg !18
+  %252 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i81 = icmp eq i32 %252, 0, !dbg !18
+  %253 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i80, float %239, float %233) #4, !dbg !18
+  %254 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i80, float %239, float %233) #4, !dbg !18
+  %.06.i82 = select i1 %.not6.i81, float %254, float %253, !dbg !18
+  %255 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i83 = icmp eq i32 %255, 0, !dbg !18
+  %256 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i82, float %239, float %232) #4, !dbg !18
+  %257 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i82, float %239, float %232) #4, !dbg !18
+  %.07.i84 = select i1 %.not7.i83, float %257, float %256, !dbg !18
+  %258 = fneg float %239, !dbg !18
+  %259 = select i1 %228, float %258, float %37, !dbg !18
+  %260 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i85 = icmp eq i32 %260, 0, !dbg !18
+  %261 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i84, float %259, float %259) #4, !dbg !18
+  %262 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i84, float %259, float %259) #4, !dbg !18
+  %.08.i86 = select i1 %.not8.i85, float %262, float %261, !dbg !18
+  br i1 %228, label %263, label %__nv_erff.exit91, !dbg !18
+
+263:                                              ; preds = %__internal_fmad.exit.i72
+  %264 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i86) #4, !dbg !18
+  %265 = fsub float 1.000000e+00, %264, !dbg !18
+  %266 = bitcast float %265 to i32, !dbg !18
+  %267 = bitcast float %37 to i32, !dbg !18
+  %268 = and i32 %267, -2147483648, !dbg !18
+  %269 = or i32 %268, %266, !dbg !18
+  %270 = bitcast i32 %269 to float, !dbg !18
+  br label %__nv_erff.exit91, !dbg !18
+
+__nv_erff.exit91:                                 ; preds = %__internal_fmad.exit.i72, %263
+  %r.0.i87 = phi float [ %270, %263 ], [ %.08.i86, %__internal_fmad.exit.i72 ], !dbg !18
+  %271 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i92 = icmp eq i32 %271, 0, !dbg !18
+  %272 = tail call float @llvm.nvvm.fabs.ftz.f(float %38) #4, !dbg !18
+  %273 = tail call float @llvm.nvvm.fabs.f(float %38) #4, !dbg !18
+  %.0.i93 = select i1 %.not.i92, float %273, float %272, !dbg !18
+  %274 = fcmp oge float %.0.i93, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %274, label %__nv_fabsf.exit1.i110, label %276, !dbg !18
+
+__nv_fabsf.exit1.i110:                            ; preds = %__nv_erff.exit91
+  %275 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i111 = icmp eq i32 %275, 0, !dbg !18
+  %.01.i112 = select i1 %.not1.i111, float %273, float %272, !dbg !18
+  br label %__internal_fmad.exit.i94, !dbg !18
+
+276:                                              ; preds = %__nv_erff.exit91
+  %277 = fmul float %38, %38, !dbg !18
+  br label %__internal_fmad.exit.i94, !dbg !18
+
+__internal_fmad.exit.i94:                         ; preds = %276, %__nv_fabsf.exit1.i110
+  %278 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i110 ], [ 0x3FC06EBA60000000, %276 ], !dbg !18
+  %279 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i110 ], [ 0xBFD8127580000000, %276 ], !dbg !18
+  %280 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i110 ], [ 0x3FBCE315E0000000, %276 ], !dbg !18
+  %281 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i110 ], [ 0xBF9B837CE0000000, %276 ], !dbg !18
+  %282 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i110 ], [ 0x3F755ABD40000000, %276 ], !dbg !18
+  %283 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i110 ], [ 0xBF4AE9A400000000, %276 ], !dbg !18
+  %284 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i110 ], [ 0x3F163D2D40000000, %276 ], !dbg !18
+  %285 = phi float [ %.01.i112, %__nv_fabsf.exit1.i110 ], [ %277, %276 ], !dbg !18
+  %286 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i95 = icmp eq i32 %286, 0, !dbg !18
+  %287 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %284, float %285, float %283) #4, !dbg !18
+  %288 = tail call float @llvm.nvvm.fma.rn.f(float %284, float %285, float %283) #4, !dbg !18
+  %.02.i96 = select i1 %.not2.i95, float %288, float %287, !dbg !18
+  %289 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i97 = icmp eq i32 %289, 0, !dbg !18
+  %290 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i96, float %285, float %282) #4, !dbg !18
+  %291 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i96, float %285, float %282) #4, !dbg !18
+  %.03.i98 = select i1 %.not3.i97, float %291, float %290, !dbg !18
+  %292 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i99 = icmp eq i32 %292, 0, !dbg !18
+  %293 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i98, float %285, float %281) #4, !dbg !18
+  %294 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i98, float %285, float %281) #4, !dbg !18
+  %.04.i100 = select i1 %.not4.i99, float %294, float %293, !dbg !18
+  %295 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i101 = icmp eq i32 %295, 0, !dbg !18
+  %296 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i100, float %285, float %280) #4, !dbg !18
+  %297 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i100, float %285, float %280) #4, !dbg !18
+  %.05.i102 = select i1 %.not5.i101, float %297, float %296, !dbg !18
+  %298 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i103 = icmp eq i32 %298, 0, !dbg !18
+  %299 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i102, float %285, float %279) #4, !dbg !18
+  %300 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i102, float %285, float %279) #4, !dbg !18
+  %.06.i104 = select i1 %.not6.i103, float %300, float %299, !dbg !18
+  %301 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i105 = icmp eq i32 %301, 0, !dbg !18
+  %302 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i104, float %285, float %278) #4, !dbg !18
+  %303 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i104, float %285, float %278) #4, !dbg !18
+  %.07.i106 = select i1 %.not7.i105, float %303, float %302, !dbg !18
+  %304 = fneg float %285, !dbg !18
+  %305 = select i1 %274, float %304, float %38, !dbg !18
+  %306 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i107 = icmp eq i32 %306, 0, !dbg !18
+  %307 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i106, float %305, float %305) #4, !dbg !18
+  %308 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i106, float %305, float %305) #4, !dbg !18
+  %.08.i108 = select i1 %.not8.i107, float %308, float %307, !dbg !18
+  br i1 %274, label %309, label %__nv_erff.exit113, !dbg !18
+
+309:                                              ; preds = %__internal_fmad.exit.i94
+  %310 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i108) #4, !dbg !18
+  %311 = fsub float 1.000000e+00, %310, !dbg !18
+  %312 = bitcast float %311 to i32, !dbg !18
+  %313 = bitcast float %38 to i32, !dbg !18
+  %314 = and i32 %313, -2147483648, !dbg !18
+  %315 = or i32 %314, %312, !dbg !18
+  %316 = bitcast i32 %315 to float, !dbg !18
+  br label %__nv_erff.exit113, !dbg !18
+
+__nv_erff.exit113:                                ; preds = %__internal_fmad.exit.i94, %309
+  %r.0.i109 = phi float [ %316, %309 ], [ %.08.i108, %__internal_fmad.exit.i94 ], !dbg !18
+  %317 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i114 = icmp eq i32 %317, 0, !dbg !18
+  %318 = tail call float @llvm.nvvm.fabs.ftz.f(float %39) #4, !dbg !18
+  %319 = tail call float @llvm.nvvm.fabs.f(float %39) #4, !dbg !18
+  %.0.i115 = select i1 %.not.i114, float %319, float %318, !dbg !18
+  %320 = fcmp oge float %.0.i115, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %320, label %__nv_fabsf.exit1.i132, label %322, !dbg !18
+
+__nv_fabsf.exit1.i132:                            ; preds = %__nv_erff.exit113
+  %321 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i133 = icmp eq i32 %321, 0, !dbg !18
+  %.01.i134 = select i1 %.not1.i133, float %319, float %318, !dbg !18
+  br label %__internal_fmad.exit.i116, !dbg !18
+
+322:                                              ; preds = %__nv_erff.exit113
+  %323 = fmul float %39, %39, !dbg !18
+  br label %__internal_fmad.exit.i116, !dbg !18
+
+__internal_fmad.exit.i116:                        ; preds = %322, %__nv_fabsf.exit1.i132
+  %324 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i132 ], [ 0x3FC06EBA60000000, %322 ], !dbg !18
+  %325 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i132 ], [ 0xBFD8127580000000, %322 ], !dbg !18
+  %326 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i132 ], [ 0x3FBCE315E0000000, %322 ], !dbg !18
+  %327 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i132 ], [ 0xBF9B837CE0000000, %322 ], !dbg !18
+  %328 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i132 ], [ 0x3F755ABD40000000, %322 ], !dbg !18
+  %329 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i132 ], [ 0xBF4AE9A400000000, %322 ], !dbg !18
+  %330 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i132 ], [ 0x3F163D2D40000000, %322 ], !dbg !18
+  %331 = phi float [ %.01.i134, %__nv_fabsf.exit1.i132 ], [ %323, %322 ], !dbg !18
+  %332 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i117 = icmp eq i32 %332, 0, !dbg !18
+  %333 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %330, float %331, float %329) #4, !dbg !18
+  %334 = tail call float @llvm.nvvm.fma.rn.f(float %330, float %331, float %329) #4, !dbg !18
+  %.02.i118 = select i1 %.not2.i117, float %334, float %333, !dbg !18
+  %335 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i119 = icmp eq i32 %335, 0, !dbg !18
+  %336 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i118, float %331, float %328) #4, !dbg !18
+  %337 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i118, float %331, float %328) #4, !dbg !18
+  %.03.i120 = select i1 %.not3.i119, float %337, float %336, !dbg !18
+  %338 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i121 = icmp eq i32 %338, 0, !dbg !18
+  %339 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i120, float %331, float %327) #4, !dbg !18
+  %340 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i120, float %331, float %327) #4, !dbg !18
+  %.04.i122 = select i1 %.not4.i121, float %340, float %339, !dbg !18
+  %341 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i123 = icmp eq i32 %341, 0, !dbg !18
+  %342 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i122, float %331, float %326) #4, !dbg !18
+  %343 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i122, float %331, float %326) #4, !dbg !18
+  %.05.i124 = select i1 %.not5.i123, float %343, float %342, !dbg !18
+  %344 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i125 = icmp eq i32 %344, 0, !dbg !18
+  %345 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i124, float %331, float %325) #4, !dbg !18
+  %346 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i124, float %331, float %325) #4, !dbg !18
+  %.06.i126 = select i1 %.not6.i125, float %346, float %345, !dbg !18
+  %347 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i127 = icmp eq i32 %347, 0, !dbg !18
+  %348 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i126, float %331, float %324) #4, !dbg !18
+  %349 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i126, float %331, float %324) #4, !dbg !18
+  %.07.i128 = select i1 %.not7.i127, float %349, float %348, !dbg !18
+  %350 = fneg float %331, !dbg !18
+  %351 = select i1 %320, float %350, float %39, !dbg !18
+  %352 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i129 = icmp eq i32 %352, 0, !dbg !18
+  %353 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i128, float %351, float %351) #4, !dbg !18
+  %354 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i128, float %351, float %351) #4, !dbg !18
+  %.08.i130 = select i1 %.not8.i129, float %354, float %353, !dbg !18
+  br i1 %320, label %355, label %__nv_erff.exit135, !dbg !18
+
+355:                                              ; preds = %__internal_fmad.exit.i116
+  %356 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i130) #4, !dbg !18
+  %357 = fsub float 1.000000e+00, %356, !dbg !18
+  %358 = bitcast float %357 to i32, !dbg !18
+  %359 = bitcast float %39 to i32, !dbg !18
+  %360 = and i32 %359, -2147483648, !dbg !18
+  %361 = or i32 %360, %358, !dbg !18
+  %362 = bitcast i32 %361 to float, !dbg !18
+  br label %__nv_erff.exit135, !dbg !18
+
+__nv_erff.exit135:                                ; preds = %__internal_fmad.exit.i116, %355
+  %r.0.i131 = phi float [ %362, %355 ], [ %.08.i130, %__internal_fmad.exit.i116 ], !dbg !18
+  %363 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not.i136 = icmp eq i32 %363, 0, !dbg !18
+  %364 = tail call float @llvm.nvvm.fabs.ftz.f(float %40) #4, !dbg !18
+  %365 = tail call float @llvm.nvvm.fabs.f(float %40) #4, !dbg !18
+  %.0.i137 = select i1 %.not.i136, float %365, float %364, !dbg !18
+  %366 = fcmp oge float %.0.i137, 0x3FF00C1FC0000000, !dbg !18
+  br i1 %366, label %__nv_fabsf.exit1.i154, label %368, !dbg !18
+
+__nv_fabsf.exit1.i154:                            ; preds = %__nv_erff.exit135
+  %367 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not1.i155 = icmp eq i32 %367, 0, !dbg !18
+  %.01.i156 = select i1 %.not1.i155, float %365, float %364, !dbg !18
+  br label %__internal_fmad.exit.i138, !dbg !18
+
+368:                                              ; preds = %__nv_erff.exit135
+  %369 = fmul float %40, %40, !dbg !18
+  br label %__internal_fmad.exit.i138, !dbg !18
+
+__internal_fmad.exit.i138:                        ; preds = %368, %__nv_fabsf.exit1.i154
+  %370 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1.i154 ], [ 0x3FC06EBA60000000, %368 ], !dbg !18
+  %371 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1.i154 ], [ 0xBFD8127580000000, %368 ], !dbg !18
+  %372 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1.i154 ], [ 0x3FBCE315E0000000, %368 ], !dbg !18
+  %373 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1.i154 ], [ 0xBF9B837CE0000000, %368 ], !dbg !18
+  %374 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1.i154 ], [ 0x3F755ABD40000000, %368 ], !dbg !18
+  %375 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1.i154 ], [ 0xBF4AE9A400000000, %368 ], !dbg !18
+  %376 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1.i154 ], [ 0x3F163D2D40000000, %368 ], !dbg !18
+  %377 = phi float [ %.01.i156, %__nv_fabsf.exit1.i154 ], [ %369, %368 ], !dbg !18
+  %378 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not2.i139 = icmp eq i32 %378, 0, !dbg !18
+  %379 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %376, float %377, float %375) #4, !dbg !18
+  %380 = tail call float @llvm.nvvm.fma.rn.f(float %376, float %377, float %375) #4, !dbg !18
+  %.02.i140 = select i1 %.not2.i139, float %380, float %379, !dbg !18
+  %381 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not3.i141 = icmp eq i32 %381, 0, !dbg !18
+  %382 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02.i140, float %377, float %374) #4, !dbg !18
+  %383 = tail call float @llvm.nvvm.fma.rn.f(float %.02.i140, float %377, float %374) #4, !dbg !18
+  %.03.i142 = select i1 %.not3.i141, float %383, float %382, !dbg !18
+  %384 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not4.i143 = icmp eq i32 %384, 0, !dbg !18
+  %385 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03.i142, float %377, float %373) #4, !dbg !18
+  %386 = tail call float @llvm.nvvm.fma.rn.f(float %.03.i142, float %377, float %373) #4, !dbg !18
+  %.04.i144 = select i1 %.not4.i143, float %386, float %385, !dbg !18
+  %387 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not5.i145 = icmp eq i32 %387, 0, !dbg !18
+  %388 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04.i144, float %377, float %372) #4, !dbg !18
+  %389 = tail call float @llvm.nvvm.fma.rn.f(float %.04.i144, float %377, float %372) #4, !dbg !18
+  %.05.i146 = select i1 %.not5.i145, float %389, float %388, !dbg !18
+  %390 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not6.i147 = icmp eq i32 %390, 0, !dbg !18
+  %391 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05.i146, float %377, float %371) #4, !dbg !18
+  %392 = tail call float @llvm.nvvm.fma.rn.f(float %.05.i146, float %377, float %371) #4, !dbg !18
+  %.06.i148 = select i1 %.not6.i147, float %392, float %391, !dbg !18
+  %393 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not7.i149 = icmp eq i32 %393, 0, !dbg !18
+  %394 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06.i148, float %377, float %370) #4, !dbg !18
+  %395 = tail call float @llvm.nvvm.fma.rn.f(float %.06.i148, float %377, float %370) #4, !dbg !18
+  %.07.i150 = select i1 %.not7.i149, float %395, float %394, !dbg !18
+  %396 = fneg float %377, !dbg !18
+  %397 = select i1 %366, float %396, float %40, !dbg !18
+  %398 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4, !dbg !18
+  %.not8.i151 = icmp eq i32 %398, 0, !dbg !18
+  %399 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07.i150, float %397, float %397) #4, !dbg !18
+  %400 = tail call float @llvm.nvvm.fma.rn.f(float %.07.i150, float %397, float %397) #4, !dbg !18
+  %.08.i152 = select i1 %.not8.i151, float %400, float %399, !dbg !18
+  br i1 %366, label %401, label %__nv_erff.exit157, !dbg !18
+
+401:                                              ; preds = %__internal_fmad.exit.i138
+  %402 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08.i152) #4, !dbg !18
+  %403 = fsub float 1.000000e+00, %402, !dbg !18
+  %404 = bitcast float %403 to i32, !dbg !18
+  %405 = bitcast float %40 to i32, !dbg !18
+  %406 = and i32 %405, -2147483648, !dbg !18
+  %407 = or i32 %406, %404, !dbg !18
+  %408 = bitcast i32 %407 to float, !dbg !18
+  br label %__nv_erff.exit157, !dbg !18
+
+__nv_erff.exit157:                                ; preds = %__internal_fmad.exit.i138, %401
+  %r.0.i153 = phi float [ %408, %401 ], [ %.08.i152, %__internal_fmad.exit.i138 ], !dbg !18
+  %409 = fmul float %32, 5.000000e-01, !dbg !19
+  %410 = fmul float %31, 5.000000e-01, !dbg !19
+  %411 = fmul float %30, 5.000000e-01, !dbg !19
+  %412 = fmul float %29, 5.000000e-01, !dbg !19
+  %413 = fmul float %28, 5.000000e-01, !dbg !19
+  %414 = fmul float %27, 5.000000e-01, !dbg !19
+  %415 = fmul float %26, 5.000000e-01, !dbg !19
+  %416 = fmul float %25, 5.000000e-01, !dbg !19
+  %417 = fadd float %r.0.i, 1.000000e+00, !dbg !20
+  %418 = fadd float %r.0.i21, 1.000000e+00, !dbg !20
+  %419 = fadd float %r.0.i43, 1.000000e+00, !dbg !20
+  %420 = fadd float %r.0.i65, 1.000000e+00, !dbg !20
+  %421 = fadd float %r.0.i87, 1.000000e+00, !dbg !20
+  %422 = fadd float %r.0.i109, 1.000000e+00, !dbg !20
+  %423 = fadd float %r.0.i131, 1.000000e+00, !dbg !20
+  %424 = fadd float %r.0.i153, 1.000000e+00, !dbg !20
+  %425 = fmul float %416, %417, !dbg !21
+  %426 = fmul float %415, %418, !dbg !21
+  %427 = fmul float %414, %419, !dbg !21
+  %428 = fmul float %413, %420, !dbg !21
+  %429 = fmul float %412, %421, !dbg !21
+  %430 = fmul float %411, %422, !dbg !21
+  %431 = fmul float %410, %423, !dbg !21
+  %432 = fmul float %409, %424, !dbg !21
+  %433 = getelementptr i16, ptr addrspace(1) %1, i64 %10, !dbg !22
+  %434 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %425) #4, !dbg !23
+  %435 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %426) #4, !dbg !23
+  %436 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %427) #4, !dbg !23
+  %437 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %428) #4, !dbg !23
+  %438 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %429) #4, !dbg !23
+  %439 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %430) #4, !dbg !23
+  %440 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %431) #4, !dbg !23
+  %441 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %432) #4, !dbg !23
+  %442 = insertelement <2 x i16> undef, i16 %434, i64 0, !dbg !23
+  %443 = insertelement <2 x i16> %442, i16 %435, i64 1, !dbg !23
+  %444 = bitcast <2 x i16> %443 to i32, !dbg !23
+  %445 = insertelement <2 x i16> undef, i16 %436, i64 0, !dbg !23
+  %446 = insertelement <2 x i16> %445, i16 %437, i64 1, !dbg !23
+  %447 = bitcast <2 x i16> %446 to i32, !dbg !23
+  %448 = insertelement <2 x i16> undef, i16 %438, i64 0, !dbg !23
+  %449 = insertelement <2 x i16> %448, i16 %439, i64 1, !dbg !23
+  %450 = bitcast <2 x i16> %449 to i32, !dbg !23
+  %451 = insertelement <2 x i16> undef, i16 %440, i64 0, !dbg !23
+  %452 = insertelement <2 x i16> %451, i16 %441, i64 1, !dbg !23
+  %453 = bitcast <2 x i16> %452 to i32, !dbg !23
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 %444, i32 %447, i32 %450, i32 %453, ptr addrspace(1) %433, i1 true) #4, !dbg !23
+  ret void, !dbg !24
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+; Function Attrs: alwaysinline nounwind
+define float @__nv_erff(float %a) local_unnamed_addr #1 {
+__nv_fabsf.exit:
+  %0 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not = icmp eq i32 %0, 0
+  %1 = tail call float @llvm.nvvm.fabs.ftz.f(float %a) #4
+  %2 = tail call float @llvm.nvvm.fabs.f(float %a) #4
+  %.0 = select i1 %.not, float %2, float %1
+  %3 = fcmp oge float %.0, 0x3FF00C1FC0000000
+  br i1 %3, label %__nv_fabsf.exit1, label %5
+
+__nv_fabsf.exit1:                                 ; preds = %__nv_fabsf.exit
+  %4 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not1 = icmp eq i32 %4, 0
+  %.01 = select i1 %.not1, float %2, float %1
+  br label %__internal_fmad.exit
+
+5:                                                ; preds = %__nv_fabsf.exit
+  %6 = fmul float %a, %a
+  br label %__internal_fmad.exit
+
+__internal_fmad.exit:                             ; preds = %5, %__nv_fabsf.exit1
+  %7 = phi float [ 0x3FE41B0840000000, %__nv_fabsf.exit1 ], [ 0x3FC06EBA60000000, %5 ]
+  %8 = phi float [ 0x3FED526FC0000000, %__nv_fabsf.exit1 ], [ 0xBFD8127580000000, %5 ]
+  %9 = phi float [ 0x3FC39F20C0000000, %__nv_fabsf.exit1 ], [ 0x3FBCE315E0000000, %5 ]
+  %10 = phi float [ 0xBFA1902C40000000, %__nv_fabsf.exit1 ], [ 0xBF9B837CE0000000, %5 ]
+  %11 = phi float [ 0x3F75908160000000, %__nv_fabsf.exit1 ], [ 0x3F755ABD40000000, %5 ]
+  %12 = phi float [ 0xBF3EAC1720000000, %__nv_fabsf.exit1 ], [ 0xBF4AE9A400000000, %5 ]
+  %13 = phi float [ 0x3EF1394780000000, %__nv_fabsf.exit1 ], [ 0x3F163D2D40000000, %5 ]
+  %14 = phi float [ %.01, %__nv_fabsf.exit1 ], [ %6, %5 ]
+  %15 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not2 = icmp eq i32 %15, 0
+  %16 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %13, float %14, float %12) #4
+  %17 = tail call float @llvm.nvvm.fma.rn.f(float %13, float %14, float %12) #4
+  %.02 = select i1 %.not2, float %17, float %16
+  %18 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not3 = icmp eq i32 %18, 0
+  %19 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.02, float %14, float %11) #4
+  %20 = tail call float @llvm.nvvm.fma.rn.f(float %.02, float %14, float %11) #4
+  %.03 = select i1 %.not3, float %20, float %19
+  %21 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not4 = icmp eq i32 %21, 0
+  %22 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.03, float %14, float %10) #4
+  %23 = tail call float @llvm.nvvm.fma.rn.f(float %.03, float %14, float %10) #4
+  %.04 = select i1 %.not4, float %23, float %22
+  %24 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not5 = icmp eq i32 %24, 0
+  %25 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.04, float %14, float %9) #4
+  %26 = tail call float @llvm.nvvm.fma.rn.f(float %.04, float %14, float %9) #4
+  %.05 = select i1 %.not5, float %26, float %25
+  %27 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not6 = icmp eq i32 %27, 0
+  %28 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.05, float %14, float %8) #4
+  %29 = tail call float @llvm.nvvm.fma.rn.f(float %.05, float %14, float %8) #4
+  %.06 = select i1 %.not6, float %29, float %28
+  %30 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not7 = icmp eq i32 %30, 0
+  %31 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.06, float %14, float %7) #4
+  %32 = tail call float @llvm.nvvm.fma.rn.f(float %.06, float %14, float %7) #4
+  %.07 = select i1 %.not7, float %32, float %31
+  %33 = fneg float %14
+  %34 = select i1 %3, float %33, float %a
+  %35 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #4
+  %.not8 = icmp eq i32 %35, 0
+  %36 = tail call float @llvm.nvvm.fma.rn.ftz.f(float %.07, float %34, float %34) #4
+  %37 = tail call float @llvm.nvvm.fma.rn.f(float %.07, float %34, float %34) #4
+  %.08 = select i1 %.not8, float %37, float %36
+  br i1 %3, label %38, label %46
+
+38:                                               ; preds = %__internal_fmad.exit
+  %39 = tail call float @llvm.nvvm.ex2.approx.ftz.f(float %.08) #4
+  %40 = fsub float 1.000000e+00, %39
+  %41 = bitcast float %40 to i32
+  %42 = bitcast float %a to i32
+  %43 = and i32 %42, -2147483648
+  %44 = or i32 %43, %41
+  %45 = bitcast i32 %44 to float
+  br label %46
+
+46:                                               ; preds = %38, %__internal_fmad.exit
+  %r.0 = phi float [ %45, %38 ], [ %.08, %__internal_fmad.exit ]
+  ret float %r.0
+}
+
+declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #2
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare float @llvm.nvvm.fabs.ftz.f(float) #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare float @llvm.nvvm.fabs.f(float) #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare float @llvm.nvvm.fma.rn.ftz.f(float, float, float) #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare float @llvm.nvvm.fma.rn.f(float, float, float) #0
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
+declare float @llvm.nvvm.ex2.approx.ftz.f(float) #3
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #4 = { nounwind }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.dbg.cu = !{!2}
+!nvvm.annotations = !{!4, !5, !5, !4}
+!llvm.ident = !{!6}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
+!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!3 = !DIFile(filename: "cjfoqo3nutni5cmtw4brla34cz45fusadehkxfkr2fie2qgo7vwt.py", directory: "/tmp/torchinductor_root/jf")
+!4 = !{ptr @triton__0d1d2de, !"kernel", i32 1}
+!5 = !{ptr @triton__0d1d2de, !"maxntidx", i32 128}
+!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
+!7 = distinct !DISubprogram(name: "triton__0d1d2de", linkageName: "triton__0d1d2de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
+!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
+!9 = !{}
+!10 = !DILocation(line: 21, column: 36, scope: !7)
+!11 = !DILocation(line: 20, column: 28, scope: !7)
+!12 = !DILocation(line: 20, column: 33, scope: !7)
+!13 = !DILocation(line: 21, column: 23, scope: !7)
+!14 = !DILocation(line: 24, column: 30, scope: !7)
+!15 = !DILocation(line: 24, column: 35, scope: !7)
+!16 = !DILocation(line: 24, column: 44, scope: !7)
+!17 = !DILocation(line: 29, column: 18, scope: !7)
+!18 = !DILocation(line: 30, column: 23, scope: !7)
+!19 = !DILocation(line: 27, column: 18, scope: !7)
+!20 = !DILocation(line: 32, column: 18, scope: !7)
+!21 = !DILocation(line: 33, column: 18, scope: !7)
+!22 = !DILocation(line: 35, column: 25, scope: !7)
+!23 = !DILocation(line: 35, column: 37, scope: !7)
+!24 = !DILocation(line: 35, column: 4, scope: !7)

.triton/dump/415aac87553b7d064f52694fa7254686/triton_.ttir

@@ -0,0 +1,27 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<1.000000e+00> : tensor<1024xf32>
+    %cst_0 = arith.constant dense<0.707106769> : tensor<1024xf32>
+    %cst_1 = arith.constant dense<5.000000e-01> : tensor<1024xf32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16>
+    %8 = arith.extf %7 : tensor<1024xbf16> to tensor<1024xf32>
+    %9 = arith.mulf %8, %cst_1 : tensor<1024xf32>
+    %10 = arith.mulf %8, %cst_0 : tensor<1024xf32>
+    %11 = tt.extern_elementwise %10 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_erff"} : (tensor<1024xf32>) -> tensor<1024xf32>
+    %12 = arith.addf %11, %cst : tensor<1024xf32>
+    %13 = arith.mulf %9, %12 : tensor<1024xf32>
+    %14 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %15 = tt.addptr %14, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %16 = arith.truncf %13 : tensor<1024xf32> to tensor<1024xbf16>
+    tt.store %15, %16 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xbf16>
+    tt.return
+  }
+}

.triton/dump/4993935f9a0e5939755cfb42600362cf/triton_.llir

@@ -0,0 +1,54 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1d2de(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2) local_unnamed_addr !dbg !5 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %5 = shl i32 %4, 1, !dbg !8
+  %6 = and i32 %5, 510, !dbg !8
+  %7 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %8 = shl i32 %7, 9, !dbg !10
+  %9 = or i32 %8, %6, !dbg !11
+  %10 = sext i32 %9 to i64, !dbg !12
+  %11 = getelementptr float, ptr addrspace(1) %0, i64 %10, !dbg !12
+  %12 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];", "=r,=r,l,b"(ptr addrspace(1) %11, i1 true) #1, !dbg !13
+  %13 = extractvalue { i32, i32 } %12, 0, !dbg !13
+  %14 = extractvalue { i32, i32 } %12, 1, !dbg !13
+  %15 = bitcast i32 %13 to float, !dbg !13
+  %16 = bitcast i32 %14 to float, !dbg !13
+  %17 = getelementptr i16, ptr addrspace(1) %1, i64 %10, !dbg !14
+  %18 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %15) #1, !dbg !15
+  %19 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %16) #1, !dbg !15
+  %20 = insertelement <2 x i16> undef, i16 %18, i64 0, !dbg !15
+  %21 = insertelement <2 x i16> %20, i16 %19, i64 1, !dbg !15
+  %22 = bitcast <2 x i16> %21 to i32, !dbg !15
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %22, ptr addrspace(1) %17, i1 true) #1, !dbg !15
+  ret void, !dbg !16
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "czjxjqxojsyyr4zmce6q6twysnucw6p4l5ujgp6ts2ecrm3ue3ex.py", directory: "/tmp/torchinductor_root/zj")
+!3 = !{ptr @triton__0d1d2de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2de, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1d2de", linkageName: "triton__0d1d2de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 24, column: 30, scope: !5)
+!13 = !DILocation(line: 24, column: 35, scope: !5)
+!14 = !DILocation(line: 26, column: 25, scope: !5)
+!15 = !DILocation(line: 26, column: 36, scope: !5)
+!16 = !DILocation(line: 26, column: 4, scope: !5)

.triton/dump/645565eaba0a18dd23ef200fe9abb0c0/triton_.ttir

@@ -0,0 +1,89 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8de9de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg9: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c512_i32 = arith.constant 512 : i32
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant 0.000000e+00 : f32
+    %cst_0 = arith.constant 2.560000e+02 : f32
+    %cst_1 = arith.constant 9.99999974E-6 : f32
+    %cst_2 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_3 = arith.constant dense<256> : tensor<1xi64>
+    %cst_4 = arith.constant dense<50257> : tensor<1xi64>
+    %cst_5 = arith.constant dense<0> : tensor<1xi64>
+    %cst_6 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_6 : tensor<256xi32>
+    %3 = arith.remsi %0, %c512_i32 : i32
+    %4 = tt.addptr %arg1, %0 : !tt.ptr<i64, 1>, i32
+    %5 = tt.splat %4 : (!tt.ptr<i64, 1>) -> tensor<1x!tt.ptr<i64, 1>>
+    %6 = tt.load %5 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<1xi64>
+    %7 = arith.muli %3, %c256_i32 : i32
+    %8 = tt.splat %7 : (i32) -> tensor<256xi32>
+    %9 = arith.addi %1, %8 : tensor<256xi32>
+    %10 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %11 = tt.addptr %10, %9 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %12 = tt.load %11, %2, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %13 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %14 = tt.addptr %13, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst_2 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %16 = arith.addi %6, %cst_4 : tensor<1xi64>
+    %17 = arith.cmpi slt, %6, %cst_5 : tensor<1xi64>
+    %18 = arith.select %17, %16, %6 : tensor<1xi1>, tensor<1xi64>
+    %19 = arith.cmpi sge, %18, %cst_5 : tensor<1xi64>
+    %20 = arith.cmpi slt, %18, %cst_4 : tensor<1xi64>
+    %21 = arith.andi %19, %20 : tensor<1xi1>
+    tt.assert %21, "index out of bounds: 0 <= tmp3 < 50257", "<frozen importlib._bootstrap_external>", "_call_with_frames_removed", 883 : tensor<1xi1>
+    %22 = arith.muli %18, %cst_3 : tensor<1xi64>
+    %23 = tt.broadcast %22 : (tensor<1xi64>) -> tensor<256xi64>
+    %24 = arith.extsi %1 : tensor<256xi32> to tensor<256xi64>
+    %25 = arith.addi %24, %23 : tensor<256xi64>
+    %26 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %27 = tt.addptr %26, %25 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi64>
+    %28 = tt.load %27, %2, %cst_2 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %29 = arith.addf %28, %12 : tensor<256xf32>
+    %30 = arith.select %2, %29, %cst_2 : tensor<256xi1>, tensor<256xf32>
+    %31 = "tt.reduce"(%30) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %60 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %60 : f32
+    }) : (tensor<256xf32>) -> f32
+    %32 = arith.addf %31, %cst : f32
+    %33 = arith.divf %32, %cst_0 : f32
+    %34 = tt.splat %33 : (f32) -> tensor<1xf32>
+    %35 = tt.splat %33 : (f32) -> tensor<256xf32>
+    %36 = arith.subf %29, %35 : tensor<256xf32>
+    %37 = arith.mulf %36, %36 : tensor<256xf32>
+    %38 = arith.select %2, %37, %cst_2 : tensor<256xi1>, tensor<256xf32>
+    %39 = "tt.reduce"(%38) <{axis = 0 : i32}> ({
+    ^bb0(%arg10: f32, %arg11: f32):
+      %60 = arith.addf %arg10, %arg11 : f32
+      tt.reduce.return %60 : f32
+    }) : (tensor<256xf32>) -> f32
+    %40 = arith.addf %39, %cst : f32
+    %41 = arith.divf %40, %cst_0 : f32
+    %42 = arith.addf %41, %cst_1 : f32
+    %43 = tt.extern_elementwise %42 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %44 = tt.splat %43 : (f32) -> tensor<1xf32>
+    %45 = tt.splat %43 : (f32) -> tensor<256xf32>
+    %46 = arith.mulf %36, %45 : tensor<256xf32>
+    %47 = arith.mulf %46, %15 : tensor<256xf32>
+    %48 = arith.muli %0, %c256_i32 : i32
+    %49 = tt.splat %48 : (i32) -> tensor<256xi32>
+    %50 = arith.addi %1, %49 : tensor<256xi32>
+    %51 = tt.splat %arg5 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %52 = tt.addptr %51, %50 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    tt.store %52, %29, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xf32>
+    gpu.barrier
+    %53 = tt.addptr %arg0, %0 : !tt.ptr<f32, 1>, i32
+    %54 = tt.splat %53 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    tt.store %54, %44 {cache = 1 : i32, evict = 1 : i32} : tensor<1xf32>
+    %55 = tt.splat %arg7 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %56 = tt.addptr %55, %50 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %57 = arith.truncf %47 : tensor<256xf32> to tensor<256xbf16>
+    tt.store %56, %57, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16>
+    %58 = tt.addptr %arg6, %0 : !tt.ptr<f32, 1>, i32
+    %59 = tt.splat %58 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    tt.store %59, %34 {cache = 1 : i32, evict = 1 : i32} : tensor<1xf32>
+    tt.return
+  }
+}

.triton/dump/7264a35f8f1de26b089f0a94e23a0d84/triton_.llir

@@ -0,0 +1,55 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1d2de(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2) local_unnamed_addr !dbg !5 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %5 = shl i32 %4, 1, !dbg !8
+  %6 = and i32 %5, 510, !dbg !8
+  %7 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %8 = shl i32 %7, 9, !dbg !10
+  %9 = or i32 %8, %6, !dbg !11
+  %10 = icmp slt i32 %9, 12865792, !dbg !12
+  %11 = sext i32 %9 to i64, !dbg !13
+  %12 = getelementptr i16, ptr addrspace(1) %0, i64 %11, !dbg !13
+  %13 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.b32 { $0 }, [ $1 + 0 ];", "=r,l,b"(ptr addrspace(1) %12, i1 %10) #1, !dbg !14
+  %14 = trunc i32 %13 to i16, !dbg !14
+  %extelt.offset = lshr i32 %13, 16, !dbg !14
+  %15 = trunc i32 %extelt.offset to i16, !dbg !14
+  %16 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %14) #1, !dbg !15
+  %17 = tail call float asm "cvt.f32.bf16 $0, $1;", "=r,h"(i16 %15) #1, !dbg !15
+  %18 = getelementptr float, ptr addrspace(1) %1, i64 %11, !dbg !16
+  %19 = bitcast float %16 to i32, !dbg !17
+  %20 = bitcast float %17 to i32, !dbg !17
+  tail call void asm sideeffect "@$3 st.global.v2.b32 [ $2 + 0 ], { $0, $1 };", "r,r,l,b"(i32 %19, i32 %20, ptr addrspace(1) %18, i1 %10) #1, !dbg !17
+  ret void, !dbg !18
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "cmxm2obucqff2z4vc55zcnscfuvur5s2b3e36dvgm57qobanlpho.py", directory: "/tmp/torchinductor_root/mx")
+!3 = !{ptr @triton__0d1d2de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2de, !"maxntidx", i32 256}
+!5 = distinct !DISubprogram(name: "triton__0d1d2de", linkageName: "triton__0d1d2de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 22, column: 21, scope: !5)
+!13 = !DILocation(line: 24, column: 30, scope: !5)
+!14 = !DILocation(line: 24, column: 35, scope: !5)
+!15 = !DILocation(line: 24, column: 45, scope: !5)
+!16 = !DILocation(line: 26, column: 25, scope: !5)
+!17 = !DILocation(line: 26, column: 36, scope: !5)
+!18 = !DILocation(line: 26, column: 4, scope: !5)

.triton/dump/7b1a931e36ddc741e8bf98e3cbffe01d/triton_.llir

@@ -0,0 +1,45 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1de(ptr addrspace(1) %0, i32 %1) local_unnamed_addr !dbg !5 {
+  %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %4 = shl i32 %3, 2, !dbg !8
+  %5 = and i32 %4, 508, !dbg !8
+  %6 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %7 = shl i32 %6, 10, !dbg !10
+  %8 = or i32 %7, %5, !dbg !11
+  %9 = or i32 %8, 512, !dbg !11
+  %10 = sext i32 %8 to i64, !dbg !12
+  %11 = getelementptr float, ptr addrspace(1) %0, i64 %10, !dbg !12
+  %12 = sext i32 %9 to i64, !dbg !12
+  %13 = getelementptr float, ptr addrspace(1) %0, i64 %12, !dbg !12
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %11, i1 true) #1, !dbg !13
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %13, i1 true) #1, !dbg !13
+  ret void, !dbg !14
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c7w5r66fcggm6aokktzwmg24mlevq2hqdw2bgwzwlovrel6re5ym.py", directory: "/tmp/torchinductor_root/7w")
+!3 = !{ptr @triton__0d1de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1de", linkageName: "triton__0d1de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 25, column: 25, scope: !5)
+!13 = !DILocation(line: 25, column: 36, scope: !5)
+!14 = !DILocation(line: 25, column: 4, scope: !5)

.triton/dump/7dc5bb3e5c2bb99527fff34c6fba7810/triton_.ttgir

@@ -0,0 +1,18 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<512> : tensor<128xi32, #blocked>
+    %c128_i32 = arith.constant 128 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c128_i32 : i32
+    %2 = tt.make_range {end = 128 : i32, start = 0 : i32} : tensor<128xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<128xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<128xi32, #blocked>
+    %5 = arith.cmpi slt, %4, %cst : tensor<128xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<128x!tt.ptr<i64, 1>, #blocked>
+    %7 = tt.addptr %6, %4 : tensor<128x!tt.ptr<i64, 1>, #blocked>, tensor<128xi32, #blocked>
+    %8 = arith.extsi %4 : tensor<128xi32, #blocked> to tensor<128xi64, #blocked>
+    tt.store %7, %8, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<128xi64, #blocked>
+    tt.return
+  }
+}

.triton/dump/884b5df35d2a25fd91308249e7657806/triton_.llir

@@ -0,0 +1,48 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1de(ptr addrspace(1) %0, i64 %1) local_unnamed_addr !dbg !5 {
+  %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %4 = shl i32 %3, 2, !dbg !8
+  %5 = and i32 %4, 508, !dbg !8
+  %6 = or i32 %5, 512, !dbg !8
+  %7 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %8 = sext i32 %7 to i64, !dbg !10
+  %9 = shl nsw i64 %8, 10, !dbg !11
+  %10 = zext nneg i32 %5 to i64
+  %11 = zext nneg i32 %6 to i64
+  %12 = or i64 %9, %10, !dbg !12
+  %13 = or i64 %9, %11, !dbg !12
+  %14 = getelementptr float, ptr addrspace(1) %0, i64 %12, !dbg !13
+  %15 = getelementptr float, ptr addrspace(1) %0, i64 %13, !dbg !13
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %14, i1 true) #1, !dbg !14
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %15, i1 true) #1, !dbg !14
+  ret void, !dbg !15
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "cpkw3bdoamlgzvqjeyuk34b3jcjf57htisara7lukflexo3t22ew.py", directory: "/tmp/torchinductor_root/pk")
+!3 = !{ptr @triton__0d1de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1de", linkageName: "triton__0d1de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 34, scope: !5)
+!11 = !DILocation(line: 20, column: 46, scope: !5)
+!12 = !DILocation(line: 21, column: 23, scope: !5)
+!13 = !DILocation(line: 25, column: 25, scope: !5)
+!14 = !DILocation(line: 25, column: 36, scope: !5)
+!15 = !DILocation(line: 25, column: 4, scope: !5)

.triton/dump/884b5df35d2a25fd91308249e7657806/triton_.ttgir

@@ -0,0 +1,18 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: i64 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<1024xf32, #blocked>
+    %c1024_i64 = arith.constant 1024 : i64
+    %0 = tt.get_program_id x : i32
+    %1 = arith.extsi %0 : i32 to i64
+    %2 = arith.muli %1, %c1024_i64 : i64
+    %3 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %4 = arith.extsi %3 : tensor<1024xi32, #blocked> to tensor<1024xi64, #blocked>
+    %5 = tt.splat %2 : (i64) -> tensor<1024xi64, #blocked>
+    %6 = arith.addi %5, %4 : tensor<1024xi64, #blocked>
+    %7 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked>
+    %8 = tt.addptr %7, %6 : tensor<1024x!tt.ptr<f32, 1>, #blocked>, tensor<1024xi64, #blocked>
+    tt.store %8, %cst {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/8c4bac4d904709a8b7e8c698132d974c/triton_.ttgir

@@ -0,0 +1,18 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [2], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1de(%arg0: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg1: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<512> : tensor<256xi32, #blocked>
+    %c256_i32 = arith.constant 256 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c256_i32 : i32
+    %2 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32, #blocked>
+    %3 = tt.splat %1 : (i32) -> tensor<256xi32, #blocked>
+    %4 = arith.addi %3, %2 : tensor<256xi32, #blocked>
+    %5 = arith.cmpi slt, %4, %cst : tensor<256xi32, #blocked>
+    %6 = tt.splat %arg0 : (!tt.ptr<i64, 1>) -> tensor<256x!tt.ptr<i64, 1>, #blocked>
+    %7 = tt.addptr %6, %4 : tensor<256x!tt.ptr<i64, 1>, #blocked>, tensor<256xi32, #blocked>
+    %8 = arith.extsi %4 : tensor<256xi32, #blocked> to tensor<256xi64, #blocked>
+    tt.store %7, %8, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<256xi64, #blocked>
+    tt.return
+  }
+}

.triton/dump/94361ae8a918b76700c87078e3d5a751/triton_.ttgir

@@ -0,0 +1,28 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [8], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [4], threadsPerWarp = [32], warpsPerCTA = [4], order = [0], CTAsPerCGA = [1], CTASplitNum = [1], CTAOrder = [0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<12865792> : tensor<1024xi32, #blocked>
+    %cst_0 = arith.constant dense<12865792> : tensor<1024xi32, #blocked1>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked>
+    %3 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32, #blocked1>
+    %4 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked>
+    %5 = tt.splat %1 : (i32) -> tensor<1024xi32, #blocked1>
+    %6 = arith.addi %4, %2 : tensor<1024xi32, #blocked>
+    %7 = arith.addi %5, %3 : tensor<1024xi32, #blocked1>
+    %8 = arith.cmpi slt, %6, %cst : tensor<1024xi32, #blocked>
+    %9 = arith.cmpi slt, %7, %cst_0 : tensor<1024xi32, #blocked1>
+    %10 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>, #blocked>
+    %11 = tt.addptr %10, %6 : tensor<1024x!tt.ptr<bf16, 1>, #blocked>, tensor<1024xi32, #blocked>
+    %12 = tt.load %11, %8 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16, #blocked>
+    %13 = triton_gpu.convert_layout %12 : (tensor<1024xbf16, #blocked>) -> tensor<1024xbf16, #blocked1>
+    %14 = arith.extf %13 : tensor<1024xbf16, #blocked1> to tensor<1024xf32, #blocked1>
+    %15 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>, #blocked1>
+    %16 = tt.addptr %15, %7 : tensor<1024x!tt.ptr<f32, 1>, #blocked1>, tensor<1024xi32, #blocked1>
+    tt.store %16, %14, %9 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32, #blocked1>
+    tt.return
+  }
+}

.triton/dump/94361ae8a918b76700c87078e3d5a751/triton_.ttir

@@ -0,0 +1,20 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<12865792> : tensor<1024xi32>
+    %c1024_i32 = arith.constant 1024 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c1024_i32 : i32
+    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<1024xi32>
+    %4 = arith.addi %3, %2 : tensor<1024xi32>
+    %5 = arith.cmpi slt, %4, %cst : tensor<1024xi32>
+    %6 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<1024x!tt.ptr<bf16, 1>>
+    %7 = tt.addptr %6, %4 : tensor<1024x!tt.ptr<bf16, 1>>, tensor<1024xi32>
+    %8 = tt.load %7, %5 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<1024xbf16>
+    %9 = arith.extf %8 : tensor<1024xbf16> to tensor<1024xf32>
+    %10 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<1024x!tt.ptr<f32, 1>>
+    %11 = tt.addptr %10, %4 : tensor<1024x!tt.ptr<f32, 1>>, tensor<1024xi32>
+    tt.store %11, %9, %5 {cache = 1 : i32, evict = 1 : i32} : tensor<1024xf32>
+    tt.return
+  }
+}

.triton/dump/962d1809855a53123762906133b1d960/triton_.llir

@@ -0,0 +1,48 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1de(ptr addrspace(1) %0, i32 %1) local_unnamed_addr !dbg !5 {
+  %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %4 = shl i32 %3, 2, !dbg !8
+  %5 = and i32 %4, 508, !dbg !8
+  %6 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %7 = shl i32 %6, 10, !dbg !10
+  %8 = or i32 %7, %5, !dbg !11
+  %9 = or i32 %8, 512, !dbg !11
+  %10 = icmp slt i32 %8, 12865792, !dbg !12
+  %11 = icmp slt i32 %9, 12865792, !dbg !12
+  %12 = sext i32 %8 to i64, !dbg !13
+  %13 = getelementptr float, ptr addrspace(1) %0, i64 %12, !dbg !13
+  %14 = sext i32 %9 to i64, !dbg !13
+  %15 = getelementptr float, ptr addrspace(1) %0, i64 %14, !dbg !13
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %13, i1 %10) #1, !dbg !14
+  tail call void asm sideeffect "@$5 st.global.v4.b32 [ $4 + 0 ], { $0, $1, $2, $3 };", "r,r,r,r,l,b"(i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %15, i1 %11) #1, !dbg !14
+  ret void, !dbg !15
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "c4yseldwmu3to52pbh2md2oeufrq3fcdmapkt4nxdzmyqtgd2ysp.py", directory: "/tmp/torchinductor_root/4y")
+!3 = !{ptr @triton__0d1de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1de", linkageName: "triton__0d1de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 22, column: 21, scope: !5)
+!13 = !DILocation(line: 25, column: 25, scope: !5)
+!14 = !DILocation(line: 25, column: 36, scope: !5)
+!15 = !DILocation(line: 25, column: 4, scope: !5)

.triton/dump/99e09ac62cbb6a1b0eda5bd8218743c3/triton_.ptx

@@ -0,0 +1,771 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3d4d5d6d7d8d9d10de11de
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3d4d5d6d7d8d9d10de11de(
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_0,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_1,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_2,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_3,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_4,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_5,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_6,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_7,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_8,
+	.param .u64 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_9,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_10,
+	.param .u32 triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_11
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<38>;
+	.reg .b16 	%rs<13>;
+	.reg .b32 	%r<135>;
+	.reg .f32 	%f<103>;
+	.reg .b64 	%rd<41>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd18, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_9];
+	ld.param.u64 	%rd17, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_8];
+	ld.param.u64 	%rd16, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_5];
+	ld.param.u64 	%rd15, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_2];
+	ld.param.u64 	%rd14, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_1];
+	ld.param.u64 	%rd13, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r1, %tid.x;
+	ld.param.u64 	%rd19, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_3];
+	shl.b32 	%r17, %r1, 2;
+	ld.param.u64 	%rd20, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_4];
+	and.b32  	%r18, %r17, 60;
+	bfe.u32 	%r19, %r1, 5, 2;
+	ld.param.u64 	%rd21, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_6];
+	bfe.u32 	%r20, %r1, 1, 4;
+	ld.param.u64 	%rd22, [triton__0d1d2d3d4d5d6d7d8d9d10de11de_param_7];
+	shl.b32 	%r21, %r19, 4;
+	or.b32  	%r2, %r21, %r20;
+	.loc	1 24 33
+	and.b32  	%r22, %r17, 4;
+	bfe.u32 	%r23, %r1, 4, 1;
+	shl.b32 	%r24, %r19, 1;
+	or.b32  	%r25, %r24, %r23;
+	.loc	1 21 28
+	mov.u32 %r15, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r3, %r15, 6;
+	.loc	1 22 23
+	or.b32  	%r26, %r3, %r18;
+	or.b32  	%r27, %r3, %r2;
+	.loc	1 26 20
+	shr.s32 	%r29, %r26, 31;
+	shr.u32 	%r30, %r29, 24;
+	add.s32 	%r31, %r26, %r30;
+	shr.s32 	%r32, %r31, 8;
+	bfe.s32 	%r33, %r15, 25, 1;
+	shr.u32 	%r34, %r33, 24;
+	add.s32 	%r35, %r27, %r34;
+	shr.s32 	%r36, %r35, 8;
+	.loc	1 37 44
+	shl.b32 	%r37, %r36, 7;
+	mul.lo.s32 	%r38, %r18, 12;
+	or.b32  	%r39, %r25, %r38;
+	shl.b32 	%r40, %r39, 1;
+	mov.u32 	%r41, global_smem;
+	add.s32 	%r4, %r41, %r40;
+	mad.lo.s32 	%r42, %r2, 12, %r22;
+	shl.b32 	%r43, %r42, 1;
+	add.s32 	%r6, %r41, %r43;
+	shl.b32 	%r44, %r39, 2;
+	add.s32 	%r7, %r41, %r44;
+	shl.b32 	%r45, %r42, 2;
+	add.s32 	%r9, %r41, %r45;
+	.loc	1 30 36
+	mad.lo.s32 	%r46, %r32, 32512, %r26;
+	shl.b32 	%r47, %r19, 9;
+	add.s32 	%r48, %r46, %r47;
+	shl.b32 	%r49, %r23, 8;
+	add.s32 	%r133, %r48, %r49;
+	or.b32  	%r50, %r37, %r22;
+	mul.wide.s32 	%rd23, %r50, 4;
+	add.s64 	%rd40, %rd22, %rd23;
+	add.s64 	%rd39, %rd21, %rd23;
+	add.s64 	%rd38, %rd20, %rd23;
+	add.s64 	%rd37, %rd19, %rd23;
+	mov.f32 	%f95, 0f00000000;
+	mov.b32 	%r134, -8;
+	mov.pred 	%p1, -1;
+	mov.f32 	%f96, %f95;
+	mov.f32 	%f97, %f95;
+	mov.f32 	%f98, %f95;
+	mov.f32 	%f99, %f95;
+	mov.f32 	%f100, %f95;
+	mov.f32 	%f101, %f95;
+	mov.f32 	%f102, %f95;
+$L__BB0_1:
+	.loc	1 34 34
+	mul.wide.s32 	%rd32, %r133, 2;
+	add.s64 	%rd24, %rd13, %rd32;
+	mov.b32 	%r53, 0;
+	.loc	1 34 63
+	mov.u32 %r51, 0x0;
+	mov.u32 %r52, 0x0;
+	@%p1 ld.global.L1::evict_first.v2.b32 { %r51, %r52 }, [ %rd24 + 0 ];
+	@!%p1 mov.u32 %r51, %r53;
+	@!%p1 mov.u32 %r52, %r53;
+	shr.u32 	%r115, %r51, 16;
+	shr.u32 	%r116, %r52, 16;
+	.loc	1 34 115
+	bar.sync 	0;
+	st.shared.u16 	[%r4], %r51;
+	st.shared.u16 	[%r4+24], %r115;
+	st.shared.u16 	[%r4+48], %r52;
+	st.shared.u16 	[%r4+72], %r116;
+	bar.sync 	0;
+	ld.shared.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%r6];
+	cvt.f32.bf16 %r55, %rs1;
+	mov.b32 	%f25, %r55;
+	cvt.f32.bf16 %r56, %rs2;
+	mov.b32 	%f26, %r56;
+	cvt.f32.bf16 %r57, %rs3;
+	mov.b32 	%f27, %r57;
+	cvt.f32.bf16 %r58, %rs4;
+	mov.b32 	%f28, %r58;
+	.loc	1 35 34
+	mul.wide.s32 	%rd33, %r133, 4;
+	add.s64 	%rd25, %rd14, %rd33;
+	.loc	1 35 63
+	mov.u32 %r59, 0x0;
+	mov.u32 %r60, 0x0;
+	mov.u32 %r61, 0x0;
+	mov.u32 %r62, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r59, %r60, %r61, %r62 }, [ %rd25 + 0 ];
+	@!%p1 mov.u32 %r59, %r53;
+	@!%p1 mov.u32 %r60, %r53;
+	@!%p1 mov.u32 %r61, %r53;
+	@!%p1 mov.u32 %r62, %r53;
+	mov.b32 	%f29, %r59;
+	mov.b32 	%f30, %r60;
+	mov.b32 	%f31, %r61;
+	mov.b32 	%f32, %r62;
+	bar.sync 	0;
+	st.shared.u32 	[%r7], %r59;
+	st.shared.u32 	[%r7+48], %r60;
+	st.shared.u32 	[%r7+96], %r61;
+	st.shared.u32 	[%r7+144], %r62;
+	bar.sync 	0;
+	ld.shared.v4.f32 	{%f33, %f34, %f35, %f36}, [%r9];
+	.loc	1 36 34
+	add.s64 	%rd26, %rd15, %rd32;
+	.loc	1 36 63
+	mov.u32 %r67, 0x0;
+	mov.u32 %r68, 0x0;
+	@%p1 ld.global.L1::evict_first.v2.b32 { %r67, %r68 }, [ %rd26 + 0 ];
+	@!%p1 mov.u32 %r67, %r53;
+	@!%p1 mov.u32 %r68, %r53;
+	cvt.u16.u32 	%rs5, %r67;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs6}, %r67; }
+	cvt.u16.u32 	%rs7, %r68;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r68; }
+	.loc	1 36 115
+	cvt.f32.bf16 %r71, %rs5;
+	mov.b32 	%f37, %r71;
+	cvt.f32.bf16 %r72, %rs6;
+	mov.b32 	%f38, %r72;
+	cvt.f32.bf16 %r73, %rs7;
+	mov.b32 	%f39, %r73;
+	cvt.f32.bf16 %r74, %rs8;
+	mov.b32 	%f40, %r74;
+	.loc	1 37 50
+	mov.u32 %r75, 0x0;
+	mov.u32 %r76, 0x0;
+	mov.u32 %r77, 0x0;
+	mov.u32 %r78, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r75, %r76, %r77, %r78 }, [ %rd37 + 0 ];
+	@!%p1 mov.u32 %r75, %r53;
+	@!%p1 mov.u32 %r76, %r53;
+	@!%p1 mov.u32 %r77, %r53;
+	@!%p1 mov.u32 %r78, %r53;
+	.loc	1 38 50
+	mov.u32 %r83, 0x0;
+	mov.u32 %r84, 0x0;
+	mov.u32 %r85, 0x0;
+	mov.u32 %r86, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r83, %r84, %r85, %r86 }, [ %rd38 + 0 ];
+	@!%p1 mov.u32 %r83, %r53;
+	@!%p1 mov.u32 %r84, %r53;
+	@!%p1 mov.u32 %r85, %r53;
+	@!%p1 mov.u32 %r86, %r53;
+	.loc	1 39 35
+	add.s64 	%rd29, %rd16, %rd32;
+	.loc	1 39 64
+	mov.u32 %r91, 0x0;
+	mov.u32 %r92, 0x0;
+	@%p1 ld.global.L1::evict_first.v2.b32 { %r91, %r92 }, [ %rd29 + 0 ];
+	@!%p1 mov.u32 %r91, %r53;
+	@!%p1 mov.u32 %r92, %r53;
+	shr.u32 	%r117, %r91, 16;
+	shr.u32 	%r118, %r92, 16;
+	.loc	1 39 116
+	bar.sync 	0;
+	st.shared.u16 	[%r4], %r91;
+	st.shared.u16 	[%r4+24], %r117;
+	st.shared.u16 	[%r4+48], %r92;
+	st.shared.u16 	[%r4+72], %r118;
+	bar.sync 	0;
+	ld.shared.v4.u16 	{%rs9, %rs10, %rs11, %rs12}, [%r6];
+	cvt.f32.bf16 %r95, %rs9;
+	mov.b32 	%f41, %r95;
+	cvt.f32.bf16 %r96, %rs10;
+	mov.b32 	%f42, %r96;
+	cvt.f32.bf16 %r97, %rs11;
+	mov.b32 	%f43, %r97;
+	cvt.f32.bf16 %r98, %rs12;
+	mov.b32 	%f44, %r98;
+	.loc	1 40 51
+	mov.u32 %r99, 0x0;
+	mov.u32 %r100, 0x0;
+	mov.u32 %r101, 0x0;
+	mov.u32 %r102, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r99, %r100, %r101, %r102 }, [ %rd39 + 0 ];
+	@!%p1 mov.u32 %r99, %r53;
+	@!%p1 mov.u32 %r100, %r53;
+	@!%p1 mov.u32 %r101, %r53;
+	@!%p1 mov.u32 %r102, %r53;
+	.loc	1 41 51
+	mov.u32 %r107, 0x0;
+	mov.u32 %r108, 0x0;
+	mov.u32 %r109, 0x0;
+	mov.u32 %r110, 0x0;
+	@%p1 ld.global.L1::evict_last.v4.b32 { %r107, %r108, %r109, %r110 }, [ %rd40 + 0 ];
+	@!%p1 mov.u32 %r107, %r53;
+	@!%p1 mov.u32 %r108, %r53;
+	@!%p1 mov.u32 %r109, %r53;
+	@!%p1 mov.u32 %r110, %r53;
+	.loc	1 44 22
+	add.f32 	%f45, %f37, %f29;
+	add.f32 	%f46, %f38, %f30;
+	add.f32 	%f47, %f39, %f31;
+	add.f32 	%f48, %f40, %f32;
+	bar.sync 	0;
+	st.shared.f32 	[%r7], %f45;
+	st.shared.f32 	[%r7+48], %f46;
+	st.shared.f32 	[%r7+96], %f47;
+	st.shared.f32 	[%r7+144], %f48;
+	bar.sync 	0;
+	ld.shared.v4.f32 	{%f49, %f50, %f51, %f52}, [%r9];
+	.loc	1 40 51
+	mov.b32 	%f53, %r75;
+	mov.b32 	%f54, %r76;
+	mov.b32 	%f55, %r77;
+	mov.b32 	%f56, %r78;
+	mov.b32 	%f57, %r99;
+	mov.b32 	%f58, %r100;
+	mov.b32 	%f59, %r101;
+	mov.b32 	%f60, %r102;
+	.loc	1 41 51
+	mov.b32 	%f61, %r110;
+	mov.b32 	%f62, %r109;
+	mov.b32 	%f63, %r108;
+	mov.b32 	%f64, %r107;
+	mov.b32 	%f65, %r86;
+	mov.b32 	%f66, %r85;
+	mov.b32 	%f67, %r84;
+	mov.b32 	%f68, %r83;
+	.loc	1 52 23
+	sub.f32 	%f69, %f36, %f60;
+	sub.f32 	%f70, %f35, %f59;
+	sub.f32 	%f71, %f34, %f58;
+	sub.f32 	%f72, %f33, %f57;
+	sub.f32 	%f73, %f52, %f56;
+	sub.f32 	%f74, %f51, %f55;
+	sub.f32 	%f75, %f50, %f54;
+	sub.f32 	%f76, %f49, %f53;
+	.loc	1 53 24
+	mul.f32 	%f77, %f76, %f68;
+	mul.f32 	%f78, %f75, %f67;
+	mul.f32 	%f79, %f74, %f66;
+	mul.f32 	%f80, %f73, %f65;
+	mul.f32 	%f81, %f72, %f64;
+	mul.f32 	%f82, %f71, %f63;
+	mul.f32 	%f83, %f70, %f62;
+	mul.f32 	%f84, %f69, %f61;
+	.loc	1 57 40
+	fma.rn.f32 	%f98, %f44, %f84, %f98;
+	fma.rn.f32 	%f97, %f43, %f83, %f97;
+	fma.rn.f32 	%f96, %f42, %f82, %f96;
+	fma.rn.f32 	%f95, %f41, %f81, %f95;
+	fma.rn.f32 	%f102, %f28, %f80, %f102;
+	fma.rn.f32 	%f101, %f27, %f79, %f101;
+	fma.rn.f32 	%f100, %f26, %f78, %f100;
+	fma.rn.f32 	%f99, %f25, %f77, %f99;
+	.loc	1 30 36
+	add.s32 	%r134, %r134, 8;
+	add.s32 	%r133, %r133, 2048;
+	add.s64 	%rd40, %rd40, 32;
+	add.s64 	%rd39, %rd39, 32;
+	add.s64 	%rd38, %rd38, 32;
+	add.s64 	%rd37, %rd37, 32;
+	setp.lt.u32 	%p35, %r134, 120;
+	@%p35 bra 	$L__BB0_1;
+	.loc	1 22 44
+	and.b32  	%r121, %r1, 63;
+	.loc	1 22 23
+	or.b32  	%r122, %r3, %r121;
+$L__tmp1:
+	.loc	2 233 15
+	add.f32 	%f85, %f99, %f100;
+	add.f32 	%f86, %f101, %f85;
+	add.f32 	%f87, %f102, %f86;
+$L__tmp2:
+	.loc	2 243 36
+	mov.b32 	%r123, %f87;
+	shfl.sync.bfly.b32	%r124, %r123, 1, 31, -1;
+	mov.b32 	%f88, %r124;
+$L__tmp3:
+	.loc	2 233 15
+	add.f32 	%f89, %f87, %f88;
+$L__tmp4:
+	.loc	1 58 30
+	bar.sync 	0;
+	shl.b32 	%r125, %r2, 2;
+	add.s32 	%r127, %r41, %r125;
+	st.shared.f32 	[%r127], %f89;
+	bar.sync 	0;
+	shl.b32 	%r128, %r121, 2;
+	add.s32 	%r129, %r41, %r128;
+	ld.shared.u32 	%r119, [%r129];
+	.loc	1 59 25
+	mul.wide.s32 	%rd36, %r122, 4;
+	add.s64 	%rd34, %rd17, %rd36;
+	.loc	1 59 37
+	and.b32  	%r130, %r1, 64;
+	setp.eq.s32 	%p36, %r130, 0;
+	@%p36 st.global.b32 [ %rd34 + 0 ], { %r119 };
+$L__tmp5:
+	.loc	2 233 15
+	add.f32 	%f90, %f95, %f96;
+	add.f32 	%f91, %f97, %f90;
+	add.f32 	%f92, %f98, %f91;
+$L__tmp6:
+	.loc	2 243 36
+	mov.b32 	%r131, %f92;
+	shfl.sync.bfly.b32	%r132, %r131, 1, 31, -1;
+	mov.b32 	%f93, %r132;
+$L__tmp7:
+	.loc	2 233 15
+	add.f32 	%f94, %f92, %f93;
+$L__tmp8:
+	.loc	1 60 30
+	bar.sync 	0;
+	st.shared.f32 	[%r127], %f94;
+	bar.sync 	0;
+	ld.shared.u32 	%r120, [%r129];
+	.loc	1 61 25
+	add.s64 	%rd35, %rd18, %rd36;
+	.loc	1 61 37
+	@%p36 st.global.b32 [ %rd35 + 0 ], { %r120 };
+	.loc	1 61 4
+	ret;
+$L__tmp9:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/3x/c3xxszvgtfnjb7welqvr33z4cqouxhqjy3dpwa2qmmx2xto6sgvz.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 32
+.b8 11
+.b8 0
+.b8 0
+.b8 3
+.b8 46
+.b8 1
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 49
+.b8 19
+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 1
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 371
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 51
+.b8 120
+.b8 120
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+.b8 118
+.b8 103
+.b8 116
+.b8 102
+.b8 110
+.b8 106
+.b8 98
+.b8 55
+.b8 119
+.b8 101
+.b8 108
+.b8 113
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+.b8 114
+.b8 51
+.b8 51
+.b8 122
+.b8 52
+.b8 99
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+.b8 111
+.b8 117
+.b8 120
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+.b8 113
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+.b8 121
+.b8 51
+.b8 100
+.b8 112
+.b8 119
+.b8 97
+.b8 50
+.b8 113
+.b8 109
+.b8 109
+.b8 120
+.b8 50
+.b8 120
+.b8 116
+.b8 111
+.b8 54
+.b8 115
+.b8 103
+.b8 118
+.b8 122
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 51
+.b8 120
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
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+.b8 51
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+.b8 100
+.b8 56
+.b8 100
+.b8 57
+.b8 100
+.b8 49
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+.b8 100
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+.b8 49
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 57
+.b8 100
+.b8 49
+.b8 48
+.b8 100
+.b8 101
+.b8 49
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp4
+.b8 2
+.b8 58
+.b8 27
+.b8 5
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp4
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp3
+.b8 2
+.b8 58
+.b8 27
+.b8 4
+.b32 125
+.b64 $L__tmp5
+.b64 $L__tmp8
+.b8 2
+.b8 60
+.b8 27
+.b8 5
+.b32 125
+.b64 $L__tmp5
+.b64 $L__tmp8
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 5
+.b32 125
+.b64 $L__tmp6
+.b64 $L__tmp7
+.b8 2
+.b8 60
+.b8 27
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 375
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 52
+.b8 100
+.b8 53
+.b8 100
+.b8 54
+.b8 100
+.b8 55
+.b8 100
+.b8 56
+.b8 100
+.b8 57
+.b8 100
+.b8 49
+.b8 48
+.b8 100
+.b8 101
+.b8 49
+.b8 49
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 375
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/99e09ac62cbb6a1b0eda5bd8218743c3/triton_.ttir

@@ -0,0 +1,100 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5d6d7d8d9d10de11de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg7: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg8: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg9: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg10: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg11: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<0.000000e+00> : tensor<64x8xbf16>
+    %c8_i32 = arith.constant 8 : i32
+    %c128_i32 = arith.constant 128 : i32
+    %c0_i32 = arith.constant 0 : i32
+    %cst_0 = arith.constant dense<128> : tensor<64x1xi32>
+    %cst_1 = arith.constant dense<32768> : tensor<64x1xi32>
+    %cst_2 = arith.constant dense<256> : tensor<1x8xi32>
+    %cst_3 = arith.constant dense<128> : tensor<1x8xi32>
+    %cst_4 = arith.constant dense<0.000000e+00> : tensor<64x8xf32>
+    %cst_5 = arith.constant dense<256> : tensor<64x1xi32>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32>
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32>) -> tensor<64x1xi32>
+    %4 = tt.splat %1 : (i32) -> tensor<64x1xi32>
+    %5 = arith.addi %4, %3 : tensor<64x1xi32>
+    %6 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32>
+    %7 = tt.expand_dims %6 {axis = 0 : i32} : (tensor<8xi32>) -> tensor<1x8xi32>
+    %8 = arith.remsi %5, %cst_5 : tensor<64x1xi32>
+    %9 = arith.divsi %5, %cst_5 : tensor<64x1xi32>
+    %10 = tt.broadcast %8 : (tensor<64x1xi32>) -> tensor<64x8xi32>
+    %11 = arith.muli %9, %cst_1 : tensor<64x1xi32>
+    %12 = tt.broadcast %11 : (tensor<64x1xi32>) -> tensor<64x8xi32>
+    %13 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>>
+    %14 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %15 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>>
+    %16 = arith.muli %9, %cst_0 : tensor<64x1xi32>
+    %17 = tt.broadcast %16 : (tensor<64x1xi32>) -> tensor<64x8xi32>
+    %18 = tt.splat %arg3 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %19 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %20 = tt.splat %arg5 : (!tt.ptr<bf16, 1>) -> tensor<64x8x!tt.ptr<bf16, 1>>
+    %21 = tt.splat %arg6 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %22 = tt.splat %arg7 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %23:2 = scf.for %arg12 = %c0_i32 to %c128_i32 step %c8_i32 iter_args(%arg13 = %cst_4, %arg14 = %cst_4) -> (tensor<64x8xf32>, tensor<64x8xf32>)  : i32 {
+      %32 = tt.splat %arg12 : (i32) -> tensor<1x8xi32>
+      %33 = arith.addi %32, %7 : tensor<1x8xi32>
+      %34 = arith.cmpi slt, %33, %cst_3 : tensor<1x8xi32>
+      %35 = arith.muli %33, %cst_2 : tensor<1x8xi32>
+      %36 = tt.broadcast %35 : (tensor<1x8xi32>) -> tensor<64x8xi32>
+      %37 = arith.addi %10, %36 : tensor<64x8xi32>
+      %38 = arith.addi %37, %12 : tensor<64x8xi32>
+      %39 = tt.addptr %13, %38 : tensor<64x8x!tt.ptr<bf16, 1>>, tensor<64x8xi32>
+      %40 = tt.broadcast %34 : (tensor<1x8xi1>) -> tensor<64x8xi1>
+      %41 = tt.load %39, %40, %cst {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16>
+      %42 = arith.extf %41 : tensor<64x8xbf16> to tensor<64x8xf32>
+      %43 = tt.addptr %14, %38 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %44 = tt.load %43, %40, %cst_4 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32>
+      %45 = tt.addptr %15, %38 : tensor<64x8x!tt.ptr<bf16, 1>>, tensor<64x8xi32>
+      %46 = tt.load %45, %40, %cst {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16>
+      %47 = arith.extf %46 : tensor<64x8xbf16> to tensor<64x8xf32>
+      %48 = tt.broadcast %33 : (tensor<1x8xi32>) -> tensor<64x8xi32>
+      %49 = arith.addi %48, %17 : tensor<64x8xi32>
+      %50 = tt.addptr %18, %49 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %51 = tt.load %50, %40, %cst_4 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32>
+      %52 = tt.addptr %19, %49 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %53 = tt.load %52, %40, %cst_4 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32>
+      %54 = tt.addptr %20, %38 : tensor<64x8x!tt.ptr<bf16, 1>>, tensor<64x8xi32>
+      %55 = tt.load %54, %40, %cst {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xbf16>
+      %56 = arith.extf %55 : tensor<64x8xbf16> to tensor<64x8xf32>
+      %57 = tt.addptr %21, %49 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %58 = tt.load %57, %40, %cst_4 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32>
+      %59 = tt.addptr %22, %49 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %60 = tt.load %59, %40, %cst_4 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x8xf32>
+      %61 = arith.addf %44, %47 : tensor<64x8xf32>
+      %62 = arith.subf %61, %51 : tensor<64x8xf32>
+      %63 = arith.mulf %62, %53 : tensor<64x8xf32>
+      %64 = arith.mulf %42, %63 : tensor<64x8xf32>
+      %65 = arith.addf %arg13, %64 : tensor<64x8xf32>
+      %66 = arith.select %40, %65, %arg13 : tensor<64x8xi1>, tensor<64x8xf32>
+      %67 = arith.subf %44, %58 : tensor<64x8xf32>
+      %68 = arith.mulf %67, %60 : tensor<64x8xf32>
+      %69 = arith.mulf %56, %68 : tensor<64x8xf32>
+      %70 = arith.addf %arg14, %69 : tensor<64x8xf32>
+      %71 = arith.select %40, %70, %arg14 : tensor<64x8xi1>, tensor<64x8xf32>
+      scf.yield %66, %71 : tensor<64x8xf32>, tensor<64x8xf32>
+    }
+    %24 = "tt.reduce"(%23#0) <{axis = 1 : i32}> ({
+    ^bb0(%arg12: f32, %arg13: f32):
+      %32 = arith.addf %arg12, %arg13 : f32
+      tt.reduce.return %32 : f32
+    }) : (tensor<64x8xf32>) -> tensor<64xf32>
+    %25 = tt.expand_dims %24 {axis = 1 : i32} : (tensor<64xf32>) -> tensor<64x1xf32>
+    %26 = tt.splat %arg8 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>>
+    %27 = tt.addptr %26, %5 : tensor<64x1x!tt.ptr<f32, 1>>, tensor<64x1xi32>
+    tt.store %27, %25 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32>
+    %28 = "tt.reduce"(%23#1) <{axis = 1 : i32}> ({
+    ^bb0(%arg12: f32, %arg13: f32):
+      %32 = arith.addf %arg12, %arg13 : f32
+      tt.reduce.return %32 : f32
+    }) : (tensor<64x8xf32>) -> tensor<64xf32>
+    %29 = tt.expand_dims %28 {axis = 1 : i32} : (tensor<64xf32>) -> tensor<64x1xf32>
+    %30 = tt.splat %arg9 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>>
+    %31 = tt.addptr %30, %5 : tensor<64x1x!tt.ptr<f32, 1>>, tensor<64x1xi32>
+    tt.store %31, %29 {cache = 1 : i32, evict = 1 : i32} : tensor<64x1xf32>
+    tt.return
+  }
+}

.triton/dump/9a2fb05196b13393bea452d08e9aaca8/triton_.ptx

@@ -0,0 +1,295 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2de
+
+.visible .entry triton__0d1d2de(
+	.param .u64 triton__0d1d2de_param_0,
+	.param .u64 triton__0d1d2de_param_1,
+	.param .u32 triton__0d1d2de_param_2
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<3>;
+	.reg .b16 	%rs<3>;
+	.reg .b32 	%r<13>;
+	.reg .b64 	%rd<7>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1d2de_param_0];
+	ld.param.u64 	%rd4, [triton__0d1d2de_param_1];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r7, %tid.x;
+	shl.b32 	%r8, %r7, 1;
+	and.b32  	%r9, %r8, 510;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r10, %r1, 9;
+	.loc	1 21 23
+	or.b32  	%r11, %r10, %r9;
+	.loc	1 24 30
+	mul.wide.s32 	%rd5, %r11, 4;
+	add.s64 	%rd1, %rd3, %rd5;
+	mov.pred 	%p1, -1;
+	.loc	1 24 35
+	mov.u32 %r4, 0x0;
+	mov.u32 %r5, 0x0;
+	@%p1 ld.global.v2.b32 { %r4, %r5 }, [ %rd1 + 0 ];
+	.loc	1 26 25
+	mul.wide.s32 	%rd6, %r11, 2;
+	add.s64 	%rd2, %rd4, %rd6;
+	.loc	1 26 36
+	cvt.rn.bf16.f32 %rs1, %r4;
+	cvt.rn.bf16.f32 %rs2, %r5;
+	mov.b32 	%r12, {%rs1, %rs2};
+	@%p1 st.global.b32 [ %rd2 + 0 ], { %r12 };
+	.loc	1 26 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/5t/c5tryp5qwkhreijk7s5x327wofz54lwj4kvctuqdzv2vrf2xyons.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 176
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 53
+.b8 116
+.b8 114
+.b8 121
+.b8 112
+.b8 53
+.b8 113
+.b8 119
+.b8 107
+.b8 104
+.b8 114
+.b8 101
+.b8 105
+.b8 106
+.b8 107
+.b8 55
+.b8 115
+.b8 53
+.b8 120
+.b8 51
+.b8 50
+.b8 55
+.b8 119
+.b8 111
+.b8 102
+.b8 122
+.b8 53
+.b8 52
+.b8 108
+.b8 119
+.b8 106
+.b8 52
+.b8 107
+.b8 118
+.b8 99
+.b8 116
+.b8 117
+.b8 113
+.b8 100
+.b8 122
+.b8 118
+.b8 50
+.b8 118
+.b8 114
+.b8 102
+.b8 50
+.b8 120
+.b8 121
+.b8 111
+.b8 110
+.b8 115
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 53
+.b8 116
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/9a2fb05196b13393bea452d08e9aaca8/triton_.ttir

@@ -0,0 +1,18 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c512_i32 = arith.constant 512 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32>
+    %4 = arith.addi %3, %2 : tensor<512xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>>
+    %6 = tt.addptr %5, %4 : tensor<512x!tt.ptr<f32, 1>>, tensor<512xi32>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xf32>
+    %8 = tt.splat %arg1 : (!tt.ptr<bf16, 1>) -> tensor<512x!tt.ptr<bf16, 1>>
+    %9 = tt.addptr %8, %4 : tensor<512x!tt.ptr<bf16, 1>>, tensor<512xi32>
+    %10 = arith.truncf %7 : tensor<512xf32> to tensor<512xbf16>
+    tt.store %9, %10 {cache = 1 : i32, evict = 1 : i32} : tensor<512xbf16>
+    tt.return
+  }
+}

.triton/dump/9aec2dd769dc1991d76fa64c70ec0e92/triton_.ptx

@@ -0,0 +1,565 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2d3de4e
+.extern .shared .align 1 .b8 global_smem[];
+
+.visible .entry triton__0d1d2d3de4e(
+	.param .u64 triton__0d1d2d3de4e_param_0,
+	.param .u64 triton__0d1d2d3de4e_param_1,
+	.param .u64 triton__0d1d2d3de4e_param_2,
+	.param .u32 triton__0d1d2d3de4e_param_3,
+	.param .u32 triton__0d1d2d3de4e_param_4
+)
+.maxntid 128, 1, 1
+{
+	.reg .pred 	%p<18>;
+	.reg .b32 	%r<92>;
+	.reg .f32 	%f<43>;
+	.reg .b64 	%rd<16>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1d2d3de4e_param_2];
+	ld.param.u64 	%rd2, [triton__0d1d2d3de4e_param_1];
+	ld.param.u64 	%rd1, [triton__0d1d2d3de4e_param_0];
+$L__tmp0:
+	.loc	1 22 44
+	mov.u32 	%r1, %tid.x;
+	and.b32  	%r2, %r1, 31;
+	shl.b32 	%r13, %r1, 2;
+	and.b32  	%r3, %r13, 60;
+	.loc	1 24 33
+	bfe.u32 	%r4, %r1, 5, 2;
+	.loc	1 21 28
+	mov.u32 %r11, %ctaid.x;
+	.loc	1 21 33
+	shl.b32 	%r5, %r11, 6;
+	.loc	1 27 36
+	shl.b32 	%r14, %r4, 18;
+	shl.b32 	%r15, %r1, 13;
+	and.b32  	%r16, %r15, 131072;
+	or.b32  	%r17, %r14, %r16;
+	add.s32 	%r18, %r17, %r5;
+	or.b32  	%r90, %r18, %r3;
+	mov.f32 	%f39, 0f00000000;
+	mov.b32 	%r91, -8;
+	mov.pred 	%p1, -1;
+	mov.f32 	%f40, %f39;
+	mov.f32 	%f41, %f39;
+	mov.f32 	%f42, %f39;
+$L__BB0_1:
+	.loc	1 31 34
+	mul.wide.s32 	%rd5, %r90, 4;
+	add.s64 	%rd4, %rd1, %rd5;
+	mov.b32 	%r23, 0;
+	.loc	1 31 53
+	mov.u32 %r19, 0x0;
+	mov.u32 %r20, 0x0;
+	mov.u32 %r21, 0x0;
+	mov.u32 %r22, 0x0;
+	@%p1 ld.global.L1::evict_first.v4.b32 { %r19, %r20, %r21, %r22 }, [ %rd4 + 0 ];
+	@!%p1 mov.u32 %r19, %r23;
+	@!%p1 mov.u32 %r20, %r23;
+	@!%p1 mov.u32 %r21, %r23;
+	@!%p1 mov.u32 %r22, %r23;
+	mov.b32 	%f13, %r19;
+	mov.b32 	%f14, %r20;
+	mov.b32 	%f15, %r21;
+	mov.b32 	%f16, %r22;
+	.loc	1 34 38
+	add.f32 	%f42, %f42, %f16;
+	add.f32 	%f41, %f41, %f15;
+	add.f32 	%f40, %f40, %f14;
+	add.f32 	%f39, %f39, %f13;
+	.loc	1 27 36
+	add.s32 	%r91, %r91, 8;
+	add.s32 	%r90, %r90, 1048576;
+	setp.lt.u32 	%p6, %r91, 112;
+	@%p6 bra 	$L__BB0_1;
+	.loc	1 22 44
+	and.b32  	%r45, %r1, 63;
+	.loc	1 22 23
+	or.b32  	%r46, %r5, %r45;
+$L__tmp1:
+	.loc	2 243 36
+	mov.b32 	%r47, %f39;
+	shfl.sync.bfly.b32	%r48, %r47, 16, 31, -1;
+	mov.b32 	%f17, %r48;
+$L__tmp2:
+	.loc	2 233 15
+	add.f32 	%f18, %f39, %f17;
+$L__tmp3:
+	.loc	2 243 36
+	mov.b32 	%r49, %f40;
+	shfl.sync.bfly.b32	%r50, %r49, 16, 31, -1;
+	mov.b32 	%f19, %r50;
+$L__tmp4:
+	.loc	2 233 15
+	add.f32 	%f20, %f40, %f19;
+$L__tmp5:
+	.loc	2 243 36
+	mov.b32 	%r51, %f41;
+	shfl.sync.bfly.b32	%r52, %r51, 16, 31, -1;
+	mov.b32 	%f21, %r52;
+$L__tmp6:
+	.loc	2 233 15
+	add.f32 	%f22, %f41, %f21;
+$L__tmp7:
+	.loc	2 243 36
+	mov.b32 	%r53, %f42;
+	shfl.sync.bfly.b32	%r54, %r53, 16, 31, -1;
+	mov.b32 	%f23, %r54;
+$L__tmp8:
+	.loc	2 233 15
+	add.f32 	%f24, %f42, %f23;
+$L__tmp9:
+	.loc	2 243 36
+	setp.lt.u32 	%p7, %r2, 16;
+	shl.b32 	%r55, %r3, 2;
+	or.b32  	%r56, %r55, %r4;
+	shl.b32 	%r57, %r56, 2;
+	mov.u32 	%r58, global_smem;
+	add.s32 	%r27, %r58, %r57;
+	mov.b32 	%r28, %f18;
+	@%p7 st.shared.b32 [ %r27 + 0 ], %r28;
+	shl.b32 	%r59, %r4, 2;
+	shl.b32 	%r60, %r3, 4;
+	or.b32  	%r61, %r60, 16;
+	or.b32  	%r62, %r61, %r59;
+	add.s32 	%r29, %r58, %r62;
+	mov.b32 	%r30, %f20;
+	@%p7 st.shared.b32 [ %r29 + 0 ], %r30;
+	or.b32  	%r63, %r60, 32;
+	or.b32  	%r64, %r63, %r59;
+	add.s32 	%r31, %r58, %r64;
+	mov.b32 	%r32, %f22;
+	@%p7 st.shared.b32 [ %r31 + 0 ], %r32;
+	or.b32  	%r65, %r60, 48;
+	or.b32  	%r66, %r65, %r59;
+	add.s32 	%r33, %r58, %r66;
+	mov.b32 	%r34, %f24;
+	@%p7 st.shared.b32 [ %r33 + 0 ], %r34;
+	bar.sync 	0;
+	setp.lt.s32 	%p11, %r1, 256;
+	add.s32 	%r36, %r58, %r13;
+	@%p11 ld.shared.b32 %r35, [ %r36 + 0 ];
+	mov.b32 	%f25, %r35;
+	shfl.sync.bfly.b32	%r68, %r35, 2, 31, -1;
+	mov.b32 	%f26, %r68;
+$L__tmp10:
+	.loc	2 233 15
+	add.f32 	%f27, %f25, %f26;
+$L__tmp11:
+	.loc	2 243 36
+	mov.b32 	%r69, %f27;
+	shfl.sync.bfly.b32	%r70, %r69, 1, 31, -1;
+	mov.b32 	%f28, %r70;
+$L__tmp12:
+	.loc	2 233 15
+	add.f32 	%f29, %f27, %f28;
+$L__tmp13:
+	.loc	2 243 36
+	and.b32  	%r71, %r1, 3;
+	setp.eq.s32 	%p17, %r71, 0;
+	and.pred  	%p12, %p11, %p17;
+	mov.b32 	%r38, %f29;
+	@%p12 st.shared.b32 [ %r36 + 0 ], %r38;
+	add.s32 	%r40, %r36, 512;
+	@%p11 ld.shared.b32 %r39, [ %r40 + 0 ];
+	mov.b32 	%f30, %r39;
+	shfl.sync.bfly.b32	%r72, %r39, 2, 31, -1;
+	mov.b32 	%f31, %r72;
+$L__tmp14:
+	.loc	2 233 15
+	add.f32 	%f32, %f30, %f31;
+$L__tmp15:
+	.loc	2 243 36
+	mov.b32 	%r73, %f32;
+	shfl.sync.bfly.b32	%r74, %r73, 1, 31, -1;
+	mov.b32 	%f33, %r74;
+$L__tmp16:
+	.loc	2 233 15
+	add.f32 	%f34, %f32, %f33;
+$L__tmp17:
+	.loc	2 243 36
+	mov.b32 	%r42, %f34;
+	@%p12 st.shared.b32 [ %r40 + 0 ], %r42;
+	bar.sync 	0;
+	add.s32 	%r75, %r58, %r60;
+	ld.shared.f32 	%f35, [%r75];
+	add.s32 	%r76, %r58, %r61;
+	ld.shared.f32 	%f36, [%r76];
+	add.s32 	%r77, %r58, %r63;
+	ld.shared.f32 	%f37, [%r77];
+	add.s32 	%r78, %r58, %r65;
+	ld.shared.f32 	%f38, [%r78];
+$L__tmp18:
+	.loc	1 35 28
+	bar.sync 	0;
+	add.s32 	%r79, %r58, %r55;
+	st.shared.f32 	[%r79], %f35;
+	st.shared.f32 	[%r79+4], %f36;
+	st.shared.f32 	[%r79+8], %f37;
+	st.shared.f32 	[%r79+12], %f38;
+	bar.sync 	0;
+	shl.b32 	%r80, %r45, 2;
+	add.s32 	%r81, %r58, %r80;
+	.loc	1 36 20
+	shr.s32 	%r83, %r46, 31;
+	shr.u32 	%r84, %r83, 24;
+	add.s32 	%r85, %r46, %r84;
+	shr.s32 	%r86, %r85, 8;
+	and.b32  	%r87, %r85, -256;
+	sub.s32 	%r88, %r46, %r87;
+	.loc	1 38 30
+	mul.wide.s32 	%rd9, %r86, 8;
+	add.s64 	%rd7, %rd2, %rd9;
+	.loc	1 45 55
+	ld.shared.u32 	%r44, [%r81];
+	.loc	1 38 35
+	mov.u64 %rd6, 0x0;
+	@%p1 ld.global.L1::evict_last.b64 { %rd6 }, [ %rd7 + 0 ];
+	.loc	1 41 32
+	shr.u64 	%rd10, %rd6, 54;
+	and.b64  	%rd11, %rd10, 512;
+	add.s64 	%rd12, %rd11, %rd6;
+	.loc	1 45 30
+	shl.b64 	%rd13, %rd12, 10;
+	add.s64 	%rd14, %rd3, %rd13;
+	mul.wide.s32 	%rd15, %r88, 4;
+	add.s64 	%rd8, %rd14, %rd15;
+	.loc	1 45 55
+	and.b32  	%r89, %r1, 64;
+	setp.eq.s32 	%p16, %r89, 0;
+	mov.u32 %r43, 0x0;
+	@%p16 atom.global.gpu.acq_rel.add.f32 %r43, [ %rd8 + 0 ], %r44;
+	.loc	1 45 4
+	ret;
+$L__tmp19:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/6i/c6ik5vx7p22fpk4dcvh55zimw4t5nr5zn2b7inujxjauxshljumm.py"
+	.file	2 "/usr/local/lib/python3.10/dist-packages/triton/language/standard.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
+.b8 27
+.b8 8
+.b8 180
+.b8 66
+.b8 12
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+.b8 0
+.b8 2
+.b8 46
+.b8 0
+.b8 135
+.b8 64
+.b8 8
+.b8 3
+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 32
+.b8 11
+.b8 0
+.b8 0
+.b8 3
+.b8 46
+.b8 1
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 64
+.b8 10
+.b8 49
+.b8 19
+.b8 0
+.b8 0
+.b8 4
+.b8 29
+.b8 0
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 5
+.b8 29
+.b8 1
+.b8 49
+.b8 19
+.b8 17
+.b8 1
+.b8 18
+.b8 1
+.b8 88
+.b8 11
+.b8 89
+.b8 11
+.b8 87
+.b8 11
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 264
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
+.b8 2
+.b8 0
+.b8 99
+.b8 54
+.b8 105
+.b8 107
+.b8 53
+.b8 118
+.b8 120
+.b8 55
+.b8 112
+.b8 50
+.b8 50
+.b8 102
+.b8 112
+.b8 107
+.b8 52
+.b8 100
+.b8 99
+.b8 118
+.b8 104
+.b8 53
+.b8 53
+.b8 122
+.b8 105
+.b8 109
+.b8 119
+.b8 52
+.b8 116
+.b8 53
+.b8 110
+.b8 114
+.b8 53
+.b8 122
+.b8 110
+.b8 50
+.b8 98
+.b8 55
+.b8 105
+.b8 110
+.b8 117
+.b8 106
+.b8 120
+.b8 106
+.b8 97
+.b8 117
+.b8 120
+.b8 115
+.b8 104
+.b8 108
+.b8 106
+.b8 117
+.b8 109
+.b8 109
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
+.b8 110
+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 54
+.b8 105
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 101
+.b8 0
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 1
+.b8 3
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b32 125
+.b8 4
+.b32 125
+.b64 $L__tmp1
+.b64 $L__tmp18
+.b8 2
+.b8 35
+.b8 25
+.b8 5
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp17
+.b8 2
+.b8 35
+.b8 25
+.b8 4
+.b32 125
+.b64 $L__tmp2
+.b64 $L__tmp17
+.b8 2
+.b8 243
+.b8 36
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 268
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 51
+.b8 100
+.b8 101
+.b8 52
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 268
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/9aec2dd769dc1991d76fa64c70ec0e92/triton_.ttgir

@@ -0,0 +1,68 @@
+#blocked = #triton_gpu.blocked<{sizePerThread = [1, 1], threadsPerWarp = [32, 1], warpsPerCTA = [2, 2], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+#blocked1 = #triton_gpu.blocked<{sizePerThread = [4, 1], threadsPerWarp = [16, 2], warpsPerCTA = [1, 4], order = [0, 1], CTAsPerCGA = [1, 1], CTASplitNum = [1, 1], CTAOrder = [1, 0]}>
+module attributes {"triton_gpu.compute-capability" = 89 : i32, "triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @triton__0d1d2d3de4e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<64x1xi64, #blocked>
+    %cst_0 = arith.constant dense<0> : tensor<64x1xi64, #blocked>
+    %cst_1 = arith.constant dense<512> : tensor<64x1xi64, #blocked>
+    %cst_2 = arith.constant dense<256> : tensor<64x1xi32, #blocked>
+    %cst_3 = arith.constant dense<131072> : tensor<1x8xi32, #blocked1>
+    %cst_4 = arith.constant dense<120> : tensor<1x8xi32, #blocked1>
+    %c0_i32 = arith.constant 0 : i32
+    %c120_i32 = arith.constant 120 : i32
+    %c8_i32 = arith.constant 8 : i32
+    %cst_5 = arith.constant dense<0.000000e+00> : tensor<64x8xf32, #blocked1>
+    %cst_6 = arith.constant dense<true> : tensor<64x1xi1, #blocked>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %3 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %4 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64x1xi32, #blocked1>
+    %5 = tt.expand_dims %3 {axis = 1 : i32} : (tensor<64xi32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64x1xi32, #blocked>
+    %6 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked1>
+    %7 = tt.splat %1 : (i32) -> tensor<64x1xi32, #blocked>
+    %8 = arith.addi %6, %4 : tensor<64x1xi32, #blocked1>
+    %9 = arith.addi %7, %5 : tensor<64x1xi32, #blocked>
+    %10 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>
+    %11 = tt.expand_dims %10 {axis = 0 : i32} : (tensor<8xi32, #triton_gpu.slice<{dim = 0, parent = #blocked1}>>) -> tensor<1x8xi32, #blocked1>
+    %12 = tt.broadcast %8 : (tensor<64x1xi32, #blocked1>) -> tensor<64x8xi32, #blocked1>
+    %13 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>, #blocked1>
+    %14 = scf.for %arg5 = %c0_i32 to %c120_i32 step %c8_i32 iter_args(%arg6 = %cst_5) -> (tensor<64x8xf32, #blocked1>)  : i32 {
+      %32 = tt.splat %arg5 : (i32) -> tensor<1x8xi32, #blocked1>
+      %33 = arith.addi %32, %11 : tensor<1x8xi32, #blocked1>
+      %34 = arith.cmpi slt, %33, %cst_4 : tensor<1x8xi32, #blocked1>
+      %35 = arith.muli %33, %cst_3 : tensor<1x8xi32, #blocked1>
+      %36 = tt.broadcast %35 : (tensor<1x8xi32, #blocked1>) -> tensor<64x8xi32, #blocked1>
+      %37 = arith.addi %12, %36 : tensor<64x8xi32, #blocked1>
+      %38 = tt.addptr %13, %37 : tensor<64x8x!tt.ptr<f32, 1>, #blocked1>, tensor<64x8xi32, #blocked1>
+      %39 = tt.broadcast %34 : (tensor<1x8xi1, #blocked1>) -> tensor<64x8xi1, #blocked1>
+      %40 = tt.load %38, %39, %cst_5 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32, #blocked1>
+      %41 = arith.addf %arg6, %40 : tensor<64x8xf32, #blocked1>
+      %42 = arith.select %39, %41, %arg6 : tensor<64x8xi1, #blocked1>, tensor<64x8xf32, #blocked1>
+      scf.yield %42 : tensor<64x8xf32, #blocked1>
+    }
+    %15 = "tt.reduce"(%14) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %32 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %32 : f32
+    }) : (tensor<64x8xf32, #blocked1>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>
+    %16 = triton_gpu.convert_layout %15 : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked1}>>) -> tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>
+    %17 = tt.expand_dims %16 {axis = 1 : i32} : (tensor<64xf32, #triton_gpu.slice<{dim = 1, parent = #blocked}>>) -> tensor<64x1xf32, #blocked>
+    %18 = arith.divsi %9, %cst_2 : tensor<64x1xi32, #blocked>
+    %19 = arith.remsi %9, %cst_2 : tensor<64x1xi32, #blocked>
+    %20 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<64x1x!tt.ptr<i64, 1>, #blocked>
+    %21 = tt.addptr %20, %18 : tensor<64x1x!tt.ptr<i64, 1>, #blocked>, tensor<64x1xi32, #blocked>
+    %22 = tt.load %21 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x1xi64, #blocked>
+    %23 = arith.addi %22, %cst_1 : tensor<64x1xi64, #blocked>
+    %24 = arith.cmpi slt, %22, %cst_0 : tensor<64x1xi64, #blocked>
+    %25 = arith.select %24, %23, %22 : tensor<64x1xi1, #blocked>, tensor<64x1xi64, #blocked>
+    %26 = arith.muli %25, %cst : tensor<64x1xi64, #blocked>
+    %27 = arith.extsi %19 : tensor<64x1xi32, #blocked> to tensor<64x1xi64, #blocked>
+    %28 = arith.addi %27, %26 : tensor<64x1xi64, #blocked>
+    %29 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>, #blocked>
+    %30 = tt.addptr %29, %28 : tensor<64x1x!tt.ptr<f32, 1>, #blocked>, tensor<64x1xi64, #blocked>
+    %31 = "tt.atomic_rmw"(%30, %17, %cst_6) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<64x1x!tt.ptr<f32, 1>, #blocked>, tensor<64x1xf32, #blocked>, tensor<64x1xi1, #blocked>) -> tensor<64x1xf32, #blocked>
+    tt.return
+  }
+}

.triton/dump/9aec2dd769dc1991d76fa64c70ec0e92/triton_.ttir

@@ -0,0 +1,61 @@
+module {
+  tt.func public @triton__0d1d2d3de4e(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<i64, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg4: i32 {tt.max_divisibility = 8 : i32}) attributes {noinline = false} {
+    %cst = arith.constant dense<256> : tensor<64x1xi64>
+    %cst_0 = arith.constant dense<0> : tensor<64x1xi64>
+    %cst_1 = arith.constant dense<512> : tensor<64x1xi64>
+    %c8_i32 = arith.constant 8 : i32
+    %c120_i32 = arith.constant 120 : i32
+    %c0_i32 = arith.constant 0 : i32
+    %cst_2 = arith.constant dense<true> : tensor<64x1xi1>
+    %cst_3 = arith.constant dense<256> : tensor<64x1xi32>
+    %cst_4 = arith.constant dense<131072> : tensor<1x8xi32>
+    %cst_5 = arith.constant dense<120> : tensor<1x8xi32>
+    %cst_6 = arith.constant dense<0.000000e+00> : tensor<64x8xf32>
+    %c64_i32 = arith.constant 64 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c64_i32 : i32
+    %2 = tt.make_range {end = 64 : i32, start = 0 : i32} : tensor<64xi32>
+    %3 = tt.expand_dims %2 {axis = 1 : i32} : (tensor<64xi32>) -> tensor<64x1xi32>
+    %4 = tt.splat %1 : (i32) -> tensor<64x1xi32>
+    %5 = arith.addi %4, %3 : tensor<64x1xi32>
+    %6 = tt.make_range {end = 8 : i32, start = 0 : i32} : tensor<8xi32>
+    %7 = tt.expand_dims %6 {axis = 0 : i32} : (tensor<8xi32>) -> tensor<1x8xi32>
+    %8 = tt.broadcast %5 : (tensor<64x1xi32>) -> tensor<64x8xi32>
+    %9 = tt.splat %arg0 : (!tt.ptr<f32, 1>) -> tensor<64x8x!tt.ptr<f32, 1>>
+    %10 = scf.for %arg5 = %c0_i32 to %c120_i32 step %c8_i32 iter_args(%arg6 = %cst_6) -> (tensor<64x8xf32>)  : i32 {
+      %27 = tt.splat %arg5 : (i32) -> tensor<1x8xi32>
+      %28 = arith.addi %27, %7 : tensor<1x8xi32>
+      %29 = arith.cmpi slt, %28, %cst_5 : tensor<1x8xi32>
+      %30 = arith.muli %28, %cst_4 : tensor<1x8xi32>
+      %31 = tt.broadcast %30 : (tensor<1x8xi32>) -> tensor<64x8xi32>
+      %32 = arith.addi %8, %31 : tensor<64x8xi32>
+      %33 = tt.addptr %9, %32 : tensor<64x8x!tt.ptr<f32, 1>>, tensor<64x8xi32>
+      %34 = tt.broadcast %29 : (tensor<1x8xi1>) -> tensor<64x8xi1>
+      %35 = tt.load %33, %34, %cst_6 {cache = 1 : i32, evict = 2 : i32, isVolatile = false} : tensor<64x8xf32>
+      %36 = arith.addf %arg6, %35 : tensor<64x8xf32>
+      %37 = arith.select %34, %36, %arg6 : tensor<64x8xi1>, tensor<64x8xf32>
+      scf.yield %37 : tensor<64x8xf32>
+    }
+    %11 = "tt.reduce"(%10) <{axis = 1 : i32}> ({
+    ^bb0(%arg5: f32, %arg6: f32):
+      %27 = arith.addf %arg5, %arg6 : f32
+      tt.reduce.return %27 : f32
+    }) : (tensor<64x8xf32>) -> tensor<64xf32>
+    %12 = tt.expand_dims %11 {axis = 1 : i32} : (tensor<64xf32>) -> tensor<64x1xf32>
+    %13 = arith.divsi %5, %cst_3 : tensor<64x1xi32>
+    %14 = arith.remsi %5, %cst_3 : tensor<64x1xi32>
+    %15 = tt.splat %arg1 : (!tt.ptr<i64, 1>) -> tensor<64x1x!tt.ptr<i64, 1>>
+    %16 = tt.addptr %15, %13 : tensor<64x1x!tt.ptr<i64, 1>>, tensor<64x1xi32>
+    %17 = tt.load %16 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<64x1xi64>
+    %18 = arith.addi %17, %cst_1 : tensor<64x1xi64>
+    %19 = arith.cmpi slt, %17, %cst_0 : tensor<64x1xi64>
+    %20 = arith.select %19, %18, %17 : tensor<64x1xi1>, tensor<64x1xi64>
+    %21 = arith.muli %20, %cst : tensor<64x1xi64>
+    %22 = arith.extsi %14 : tensor<64x1xi32> to tensor<64x1xi64>
+    %23 = arith.addi %22, %21 : tensor<64x1xi64>
+    %24 = tt.splat %arg2 : (!tt.ptr<f32, 1>) -> tensor<64x1x!tt.ptr<f32, 1>>
+    %25 = tt.addptr %24, %23 : tensor<64x1x!tt.ptr<f32, 1>>, tensor<64x1xi64>
+    %26 = "tt.atomic_rmw"(%25, %12, %cst_2) <{atomic_rmw_op = 5 : i32, scope = 1 : i32, sem = 4 : i32}> : (tensor<64x1x!tt.ptr<f32, 1>>, tensor<64x1xf32>, tensor<64x1xi1>) -> tensor<64x1xf32>
+    tt.return
+  }
+}

.triton/dump/a37de85bdb85634924fdf498b7d8602b/triton_.ptx

@@ -0,0 +1,296 @@
+//
+// Generated by LLVM NVPTX Back-End
+//
+
+.version 8.2
+.target sm_89
+.address_size 64
+
+	// .globl	triton__0d1d2de
+
+.visible .entry triton__0d1d2de(
+	.param .u64 triton__0d1d2de_param_0,
+	.param .u64 triton__0d1d2de_param_1,
+	.param .u32 triton__0d1d2de_param_2
+)
+.maxntid 256, 1, 1
+{
+	.reg .pred 	%p<3>;
+	.reg .b16 	%rs<3>;
+	.reg .b32 	%r<12>;
+	.reg .b64 	%rd<7>;
+	.loc	1 18 0
+$L__func_begin0:
+	.loc	1 18 0
+
+	ld.param.u64 	%rd3, [triton__0d1d2de_param_0];
+	ld.param.u64 	%rd4, [triton__0d1d2de_param_1];
+$L__tmp0:
+	.loc	1 21 36
+	mov.u32 	%r7, %tid.x;
+	shl.b32 	%r8, %r7, 1;
+	and.b32  	%r9, %r8, 510;
+	.loc	1 20 28
+	mov.u32 %r1, %ctaid.x;
+	.loc	1 20 33
+	shl.b32 	%r10, %r1, 9;
+	.loc	1 21 23
+	or.b32  	%r11, %r10, %r9;
+	.loc	1 24 30
+	mul.wide.s32 	%rd5, %r11, 2;
+	add.s64 	%rd1, %rd3, %rd5;
+	mov.pred 	%p1, -1;
+	.loc	1 24 35
+	mov.u32 %r2, 0x0;
+	@%p1 ld.global.b32 { %r2 }, [ %rd1 + 0 ];
+	cvt.u16.u32 	%rs1, %r2;
+	{ .reg .b16 tmp; mov.b32 {tmp, %rs2}, %r2; }
+	.loc	1 24 44
+	cvt.f32.bf16 %r5, %rs1;
+	cvt.f32.bf16 %r6, %rs2;
+	.loc	1 26 25
+	mul.wide.s32 	%rd6, %r11, 4;
+	add.s64 	%rd2, %rd4, %rd6;
+	.loc	1 26 36
+	@%p1 st.global.v2.b32 [ %rd2 + 0 ], { %r5, %r6 };
+	.loc	1 26 4
+	ret;
+$L__tmp1:
+$L__func_end0:
+
+}
+	.file	1 "/tmp/torchinductor_root/k6/ck62k2xzbb657snfdowwanzszaij6qzw6vuc7cfidomjpkk6igcm.py"
+	.section	.debug_abbrev
+	{
+.b8 1
+.b8 17
+.b8 1
+.b8 37
+.b8 8
+.b8 19
+.b8 5
+.b8 3
+.b8 8
+.b8 16
+.b8 6
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+.b8 8
+.b8 180
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+.b8 64
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+.b8 8
+.b8 58
+.b8 11
+.b8 59
+.b8 11
+.b8 63
+.b8 12
+.b8 0
+.b8 0
+.b8 0
+	}
+	.section	.debug_info
+	{
+.b32 176
+.b8 2
+.b8 0
+.b32 .debug_abbrev
+.b8 8
+.b8 1
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 0
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+.b8 107
+.b8 54
+.b8 105
+.b8 103
+.b8 99
+.b8 109
+.b8 46
+.b8 112
+.b8 121
+.b8 0
+.b32 .debug_line
+.b8 47
+.b8 116
+.b8 109
+.b8 112
+.b8 47
+.b8 116
+.b8 111
+.b8 114
+.b8 99
+.b8 104
+.b8 105
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+.b8 100
+.b8 117
+.b8 99
+.b8 116
+.b8 111
+.b8 114
+.b8 95
+.b8 114
+.b8 111
+.b8 111
+.b8 116
+.b8 47
+.b8 107
+.b8 54
+.b8 0
+.b8 1
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 2
+.b64 $L__func_begin0
+.b64 $L__func_end0
+.b8 1
+.b8 156
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
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+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b8 1
+.b8 18
+.b8 1
+.b8 0
+	}
+	.section	.debug_pubnames
+	{
+.b32 $L__pubNames_end0-$L__pubNames_start0
+$L__pubNames_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 125
+.b8 116
+.b8 114
+.b8 105
+.b8 116
+.b8 111
+.b8 110
+.b8 95
+.b8 95
+.b8 48
+.b8 100
+.b8 49
+.b8 100
+.b8 50
+.b8 100
+.b8 101
+.b8 0
+.b32 0
+$L__pubNames_end0:
+	}
+	.section	.debug_pubtypes
+	{
+.b32 $L__pubTypes_end0-$L__pubTypes_start0
+$L__pubTypes_start0:
+.b8 2
+.b8 0
+.b32 .debug_info
+.b32 180
+.b32 0
+$L__pubTypes_end0:
+	}
+	.section	.debug_loc	{	}

.triton/dump/a37de85bdb85634924fdf498b7d8602b/triton_.ttir

@@ -0,0 +1,18 @@
+module {
+  tt.func public @triton__0d1d2de(%arg0: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c512_i32 = arith.constant 512 : i32
+    %0 = tt.get_program_id x : i32
+    %1 = arith.muli %0, %c512_i32 : i32
+    %2 = tt.make_range {end = 512 : i32, start = 0 : i32} : tensor<512xi32>
+    %3 = tt.splat %1 : (i32) -> tensor<512xi32>
+    %4 = arith.addi %3, %2 : tensor<512xi32>
+    %5 = tt.splat %arg0 : (!tt.ptr<bf16, 1>) -> tensor<512x!tt.ptr<bf16, 1>>
+    %6 = tt.addptr %5, %4 : tensor<512x!tt.ptr<bf16, 1>>, tensor<512xi32>
+    %7 = tt.load %6 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<512xbf16>
+    %8 = arith.extf %7 : tensor<512xbf16> to tensor<512xf32>
+    %9 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<512x!tt.ptr<f32, 1>>
+    %10 = tt.addptr %9, %4 : tensor<512x!tt.ptr<f32, 1>>, tensor<512xi32>
+    tt.store %10, %8 {cache = 1 : i32, evict = 1 : i32} : tensor<512xf32>
+    tt.return
+  }
+}

.triton/dump/a69784da01a97187168f22847465505f/triton_.ttir

@@ -0,0 +1,71 @@
+module {
+  tt.func public @triton__0d1d2d3d4d5d6d7de8de(%arg0: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg3: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg4: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg5: !tt.ptr<f32, 1> {tt.divisibility = 16 : i32}, %arg6: !tt.ptr<bf16, 1> {tt.divisibility = 16 : i32}, %arg7: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}, %arg8: i32 {tt.divisibility = 16 : i32, tt.max_divisibility = 16 : i32}) attributes {noinline = false} {
+    %c256_i32 = arith.constant 256 : i32
+    %cst = arith.constant dense<0.000000e+00> : tensor<256xbf16>
+    %cst_0 = arith.constant 0.000000e+00 : f32
+    %cst_1 = arith.constant 2.560000e+02 : f32
+    %cst_2 = arith.constant 9.99999974E-6 : f32
+    %cst_3 = arith.constant dense<0.000000e+00> : tensor<256xf32>
+    %cst_4 = arith.constant dense<256> : tensor<256xi32>
+    %0 = tt.get_program_id x : i32
+    %1 = tt.make_range {end = 256 : i32, start = 0 : i32} : tensor<256xi32>
+    %2 = arith.cmpi slt, %1, %cst_4 : tensor<256xi32>
+    %3 = arith.muli %0, %c256_i32 : i32
+    %4 = tt.splat %3 : (i32) -> tensor<256xi32>
+    %5 = arith.addi %1, %4 : tensor<256xi32>
+    %6 = tt.splat %arg1 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %7 = tt.addptr %6, %5 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %8 = tt.load %7, %2, %cst_3 {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xf32>
+    %9 = tt.splat %arg2 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %10 = tt.addptr %9, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %11 = tt.load %10, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %12 = arith.extf %11 : tensor<256xbf16> to tensor<256xf32>
+    %13 = tt.splat %arg3 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %14 = tt.addptr %13, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %15 = tt.load %14, %2, %cst {cache = 1 : i32, evict = 1 : i32, isVolatile = false} : tensor<256xbf16>
+    %16 = arith.extf %15 : tensor<256xbf16> to tensor<256xf32>
+    %17 = tt.splat %arg4 : (!tt.ptr<f32, 1>) -> tensor<256x!tt.ptr<f32, 1>>
+    %18 = tt.addptr %17, %1 : tensor<256x!tt.ptr<f32, 1>>, tensor<256xi32>
+    %19 = tt.load %18, %2, %cst_3 {cache = 1 : i32, evict = 3 : i32, isVolatile = false} : tensor<256xf32>
+    %20 = arith.addf %8, %12 : tensor<256xf32>
+    %21 = arith.addf %20, %16 : tensor<256xf32>
+    %22 = arith.select %2, %21, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %23 = "tt.reduce"(%22) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %47 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %47 : f32
+    }) : (tensor<256xf32>) -> f32
+    %24 = arith.addf %23, %cst_0 : f32
+    %25 = arith.divf %24, %cst_1 : f32
+    %26 = tt.splat %25 : (f32) -> tensor<1xf32>
+    %27 = tt.splat %25 : (f32) -> tensor<256xf32>
+    %28 = arith.subf %21, %27 : tensor<256xf32>
+    %29 = arith.mulf %28, %28 : tensor<256xf32>
+    %30 = arith.select %2, %29, %cst_3 : tensor<256xi1>, tensor<256xf32>
+    %31 = "tt.reduce"(%30) <{axis = 0 : i32}> ({
+    ^bb0(%arg9: f32, %arg10: f32):
+      %47 = arith.addf %arg9, %arg10 : f32
+      tt.reduce.return %47 : f32
+    }) : (tensor<256xf32>) -> f32
+    %32 = arith.addf %31, %cst_0 : f32
+    %33 = arith.divf %32, %cst_1 : f32
+    %34 = arith.addf %33, %cst_2 : f32
+    %35 = tt.extern_elementwise %34 {libname = "libdevice", libpath = "/usr/local/lib/python3.10/dist-packages/triton/language/../third_party/cuda/lib/libdevice.10.bc", pure = true, symbol = "__nv_rsqrtf"} : (f32) -> f32
+    %36 = tt.splat %35 : (f32) -> tensor<1xf32>
+    %37 = tt.splat %35 : (f32) -> tensor<256xf32>
+    %38 = arith.mulf %28, %37 : tensor<256xf32>
+    %39 = arith.mulf %38, %19 : tensor<256xf32>
+    gpu.barrier
+    %40 = tt.addptr %arg0, %0 : !tt.ptr<f32, 1>, i32
+    %41 = tt.splat %40 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    tt.store %41, %36 {cache = 1 : i32, evict = 1 : i32} : tensor<1xf32>
+    %42 = tt.splat %arg6 : (!tt.ptr<bf16, 1>) -> tensor<256x!tt.ptr<bf16, 1>>
+    %43 = tt.addptr %42, %5 : tensor<256x!tt.ptr<bf16, 1>>, tensor<256xi32>
+    %44 = arith.truncf %39 : tensor<256xf32> to tensor<256xbf16>
+    tt.store %43, %44, %2 {cache = 1 : i32, evict = 1 : i32} : tensor<256xbf16>
+    %45 = tt.addptr %arg5, %0 : !tt.ptr<f32, 1>, i32
+    %46 = tt.splat %45 : (!tt.ptr<f32, 1>) -> tensor<1x!tt.ptr<f32, 1>>
+    tt.store %46, %26 {cache = 1 : i32, evict = 1 : i32} : tensor<1xf32>
+    tt.return
+  }
+}

.triton/dump/a75e14a8d2d1ec8471f1c7b615552f8c/triton_.llir

@@ -0,0 +1,54 @@
+; ModuleID = 'LLVMDialectModule'
+source_filename = "LLVMDialectModule"
+
+define void @triton__0d1d2de(ptr addrspace(1) %0, ptr addrspace(1) %1, i32 %2) local_unnamed_addr !dbg !5 {
+  %4 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !8
+  %5 = shl i32 %4, 1, !dbg !8
+  %6 = and i32 %5, 254, !dbg !8
+  %7 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #1, !dbg !9
+  %8 = shl i32 %7, 8, !dbg !10
+  %9 = or i32 %8, %6, !dbg !11
+  %10 = sext i32 %9 to i64, !dbg !12
+  %11 = getelementptr float, ptr addrspace(1) %0, i64 %10, !dbg !12
+  %12 = tail call { i32, i32 } asm sideeffect "mov.u32 $0, 0x0;\0A\09mov.u32 $1, 0x0;\0A\09@$3 ld.global.v2.b32 { $0, $1 }, [ $2 + 0 ];", "=r,=r,l,b"(ptr addrspace(1) %11, i1 true) #1, !dbg !13
+  %13 = extractvalue { i32, i32 } %12, 0, !dbg !13
+  %14 = extractvalue { i32, i32 } %12, 1, !dbg !13
+  %15 = bitcast i32 %13 to float, !dbg !13
+  %16 = bitcast i32 %14 to float, !dbg !13
+  %17 = getelementptr i16, ptr addrspace(1) %1, i64 %10, !dbg !14
+  %18 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %15) #1, !dbg !15
+  %19 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %16) #1, !dbg !15
+  %20 = insertelement <2 x i16> undef, i16 %18, i64 0, !dbg !15
+  %21 = insertelement <2 x i16> %20, i16 %19, i64 1, !dbg !15
+  %22 = bitcast <2 x i16> %21 to i32, !dbg !15
+  tail call void asm sideeffect "@$2 st.global.b32 [ $1 + 0 ], { $0 };", "r,l,b"(i32 %22, ptr addrspace(1) %17, i1 true) #1, !dbg !15
+  ret void, !dbg !16
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+
+attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #1 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!llvm.dbg.cu = !{!1}
+!nvvm.annotations = !{!3, !4, !4, !3}
+
+!0 = !{i32 2, !"Debug Info Version", i32 3}
+!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "cpqhcwm5bfrhuwddh4c4qks6bh7sovfbpfnmqhnm4h4w23icqnu6.py", directory: "/tmp/torchinductor_root/pq")
+!3 = !{ptr @triton__0d1d2de, !"kernel", i32 1}
+!4 = !{ptr @triton__0d1d2de, !"maxntidx", i32 128}
+!5 = distinct !DISubprogram(name: "triton__0d1d2de", linkageName: "triton__0d1d2de", scope: !2, file: !2, line: 18, type: !6, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1)
+!6 = !DISubroutineType(cc: DW_CC_normal, types: !7)
+!7 = !{}
+!8 = !DILocation(line: 21, column: 36, scope: !5)
+!9 = !DILocation(line: 20, column: 28, scope: !5)
+!10 = !DILocation(line: 20, column: 33, scope: !5)
+!11 = !DILocation(line: 21, column: 23, scope: !5)
+!12 = !DILocation(line: 24, column: 30, scope: !5)
+!13 = !DILocation(line: 24, column: 35, scope: !5)
+!14 = !DILocation(line: 26, column: 25, scope: !5)
+!15 = !DILocation(line: 26, column: 36, scope: !5)
+!16 = !DILocation(line: 26, column: 4, scope: !5)