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gpt2-pos-encoding-experiment-10B
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; ModuleID = 'LLVMDialectModule'
source_filename = "LLVMDialectModule"

@assertFunc_1 = internal constant [25 x i8] c"_call_with_frames_removed"
@assertFile_1 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
@assertMessage_1 = internal constant [39 x i8] c"index out of bounds: 0 <= tmp13 < 50257"
@assertFunc_0 = internal constant [25 x i8] c"_call_with_frames_removed"
@assertFile_0 = internal constant [38 x i8] c"<frozen importlib._bootstrap_external>"
@assertMessage_0 = internal constant [38 x i8] c"index out of bounds: 0 <= tmp3 < 50257"
@.str = private unnamed_addr constant [11 x i8] c"__CUDA_FTZ\00", align 1

declare void @__assertfail(ptr, ptr, i32, ptr, i64) local_unnamed_addr

define void @triton__0d1d2d3d4d5de6de(ptr addrspace(1) %0, ptr addrspace(1) %1, ptr addrspace(1) %2, ptr addrspace(1) %3, ptr addrspace(1) %4, i32 %5, i32 %6) local_unnamed_addr !dbg !7 {
  %8 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !dbg !10
  %9 = lshr i32 %8, 2, !dbg !10
  %10 = and i32 %9, 63, !dbg !10
  %11 = and i32 %8, 63, !dbg !10
  %12 = and i32 %8, 3, !dbg !11
  %13 = tail call i32 asm "mov.u32 $0, %ctaid.x;", "=r"() #5, !dbg !12
  %14 = shl i32 %13, 6, !dbg !13
  %15 = or i32 %14, %10, !dbg !14
  %16 = or i32 %14, %11, !dbg !14
  %17 = sext i32 %15 to i64, !dbg !15
  %18 = getelementptr i64, ptr addrspace(1) %0, i64 %17, !dbg !15
  %19 = sext i32 %16 to i64, !dbg !15
  %20 = getelementptr i64, ptr addrspace(1) %0, i64 %19, !dbg !15
  %21 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %18, i1 true) #5, !dbg !16
  %22 = tail call i64 asm sideeffect "mov.u64 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b64 { $0 }, [ $1 + 0 ];", "=l,l,b"(ptr addrspace(1) %20, i1 true) #5, !dbg !16
  %23 = srem i32 %15, 512, !dbg !17
  %24 = shl nsw i32 %23, 8, !dbg !18
  %25 = add i64 %22, 50257, !dbg !19
  %26 = icmp slt i64 %21, 0, !dbg !20
  %27 = icmp slt i64 %22, 0, !dbg !20
  %28 = select i1 %27, i64 %25, i64 %22, !dbg !21
  %.fr8 = freeze i64 %28, !dbg !22
  %29 = icmp ugt i64 %.fr8, 50256, !dbg !22
  %30 = shl i64 %21, 8, !dbg !23
  %31 = add i64 %30, 12865792, !dbg !23
  %32 = select i1 %26, i64 %31, i64 %30, !dbg !23
  %33 = getelementptr float, ptr addrspace(1) %1, i64 %32
  br i1 %29, label %.split.us, label %.split, !dbg !24

.split.us:                                        ; preds = %7, %.split.us
  %34 = phi float [ %50, %.split.us ], [ 0.000000e+00, %7 ]
  %35 = phi float [ %55, %.split.us ], [ 0.000000e+00, %7 ]
  %36 = phi float [ %52, %.split.us ], [ 0.000000e+00, %7 ]
  %37 = phi i32 [ %56, %.split.us ], [ 0, %7 ]
  %38 = or i32 %37, %12, !dbg !25
  %39 = add i32 %38, %24, !dbg !26
  %40 = sext i32 %39 to i64, !dbg !27
  %41 = getelementptr float, ptr addrspace(1) %2, i64 %40, !dbg !27
  %42 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %41, i1 true, i32 0, i1 true) #5, !dbg !28
  %43 = bitcast i32 %42 to float, !dbg !28
  tail call void @__assertfail(ptr nonnull @assertMessage_0, ptr nonnull @assertFile_0, i32 883, ptr nonnull @assertFunc_0, i64 1), !dbg !24
  %44 = zext nneg i32 %38 to i64, !dbg !29
  %45 = getelementptr float, ptr addrspace(1) %33, i64 %44, !dbg !30
  %46 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %45, i1 true, i32 0, i1 true) #5, !dbg !31
  %47 = bitcast i32 %46 to float, !dbg !31
  %48 = fadd float %43, %47, !dbg !32
  %49 = fsub float %48, %36, !dbg !33
  %50 = fadd float %34, 1.000000e+00, !dbg !37
  %51 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %49, float %50) #5, !dbg !38
  %52 = fadd float %36, %51, !dbg !39
  %53 = fsub float %48, %52, !dbg !40
  %54 = fmul float %49, %53, !dbg !41
  %55 = fadd float %35, %54, !dbg !42
  %56 = add nuw nsw i32 %37, 4, !dbg !43
  %57 = icmp ult i32 %37, 252, !dbg !43
  br i1 %57, label %.split.us, label %.split5.us, !dbg !43

.split:                                           ; preds = %7, %.split
  %58 = phi float [ %74, %.split ], [ 0.000000e+00, %7 ]
  %59 = phi float [ %79, %.split ], [ 0.000000e+00, %7 ]
  %60 = phi float [ %76, %.split ], [ 0.000000e+00, %7 ]
  %61 = phi i32 [ %80, %.split ], [ 0, %7 ]
  %62 = or i32 %61, %12, !dbg !25
  %63 = add i32 %62, %24, !dbg !26
  %64 = sext i32 %63 to i64, !dbg !27
  %65 = getelementptr float, ptr addrspace(1) %2, i64 %64, !dbg !27
  %66 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %65, i1 true, i32 0, i1 true) #5, !dbg !28
  %67 = bitcast i32 %66 to float, !dbg !28
  %68 = zext nneg i32 %62 to i64, !dbg !29
  %69 = getelementptr float, ptr addrspace(1) %33, i64 %68, !dbg !30
  %70 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %69, i1 true, i32 0, i1 true) #5, !dbg !31
  %71 = bitcast i32 %70 to float, !dbg !31
  %72 = fadd float %67, %71, !dbg !32
  %73 = fsub float %72, %60, !dbg !33
  %74 = fadd float %58, 1.000000e+00, !dbg !37
  %75 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %73, float %74) #5, !dbg !38
  %76 = fadd float %60, %75, !dbg !39
  %77 = fsub float %72, %76, !dbg !40
  %78 = fmul float %73, %77, !dbg !41
  %79 = fadd float %59, %78, !dbg !42
  %80 = add nuw nsw i32 %61, 4, !dbg !43
  %81 = icmp ult i32 %61, 252, !dbg !43
  br i1 %81, label %.split, label %.split5.us, !dbg !43

.split5.us:                                       ; preds = %.split, %.split.us
  %.us-phi = phi float [ %52, %.split.us ], [ %76, %.split ]
  %.us-phi6 = phi float [ %55, %.split.us ], [ %79, %.split ]
  %.us-phi7 = phi float [ %50, %.split.us ], [ %74, %.split ]
  %82 = bitcast float %.us-phi to i32, !dbg !44
  %83 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %82, i32 2, i32 31), !dbg !44
  %84 = bitcast i32 %83 to float, !dbg !44
  %85 = bitcast float %.us-phi6 to i32, !dbg !44
  %86 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %85, i32 2, i32 31), !dbg !44
  %87 = bitcast i32 %86 to float, !dbg !44
  %88 = bitcast float %.us-phi7 to i32, !dbg !44
  %89 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %88, i32 2, i32 31), !dbg !44
  %90 = bitcast i32 %89 to float, !dbg !44
  %91 = fsub float %84, %.us-phi, !dbg !46
  %92 = fadd float %.us-phi7, %90, !dbg !50
  %93 = fcmp oeq float %92, 0.000000e+00, !dbg !51
  %94 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %90, float %92) #5, !dbg !52
  %95 = select i1 %93, float 0.000000e+00, float %94, !dbg !53
  %96 = fmul float %91, %95, !dbg !54
  %97 = fadd float %.us-phi, %96, !dbg !55
  %98 = fadd float %.us-phi6, %87, !dbg !56
  %99 = fmul float %91, %91, !dbg !57
  %100 = fmul float %.us-phi7, %99, !dbg !58
  %101 = fmul float %100, %95, !dbg !59
  %102 = fadd float %98, %101, !dbg !60
  %103 = bitcast float %97 to i32, !dbg !44
  %104 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %103, i32 1, i32 31), !dbg !44
  %105 = bitcast i32 %104 to float, !dbg !44
  %106 = bitcast float %102 to i32, !dbg !44
  %107 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %106, i32 1, i32 31), !dbg !44
  %108 = bitcast i32 %107 to float, !dbg !44
  %109 = bitcast float %92 to i32, !dbg !44
  %110 = tail call i32 @llvm.nvvm.shfl.sync.bfly.i32(i32 -1, i32 %109, i32 1, i32 31), !dbg !44
  %111 = bitcast i32 %110 to float, !dbg !44
  %112 = fsub float %105, %97, !dbg !46
  %113 = fadd float %92, %111, !dbg !50
  %114 = fcmp oeq float %113, 0.000000e+00, !dbg !51
  %115 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %111, float %113) #5, !dbg !52
  %116 = select i1 %114, float 0.000000e+00, float %115, !dbg !53
  %117 = fmul float %112, %116, !dbg !54
  %118 = fadd float %97, %117, !dbg !55
  %119 = fadd float %102, %108, !dbg !56
  %120 = fmul float %112, %112, !dbg !57
  %121 = fmul float %92, %120, !dbg !58
  %122 = fmul float %116, %121, !dbg !59
  %123 = fadd float %119, %122, !dbg !60
  %124 = tail call float asm "div.full.f32 $0, $1, $2;", "=r,r,r"(float %123, float 2.560000e+02) #5, !dbg !61
  %125 = fadd float %124, 0x3EE4F8B580000000, !dbg !62
  %126 = shl i32 %15, 8, !dbg !63
  br label %127, !dbg !64

127:                                              ; preds = %.split5.us, %__nv_rsqrtf.exit
  %128 = phi i32 [ 0, %.split5.us ], [ %157, %__nv_rsqrtf.exit ]
  %129 = or i32 %128, %12, !dbg !65
  %130 = add i32 %129, %24, !dbg !66
  %131 = sext i32 %130 to i64, !dbg !67
  %132 = getelementptr float, ptr addrspace(1) %2, i64 %131, !dbg !67
  %133 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %132, i1 true, i32 0, i1 true) #5, !dbg !68
  %134 = bitcast i32 %133 to float, !dbg !68
  %135 = zext nneg i32 %129 to i64, !dbg !69
  %136 = getelementptr float, ptr addrspace(1) %3, i64 %135, !dbg !69
  %137 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_last.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %136, i1 true, i32 0, i1 true) #5, !dbg !70
  %138 = bitcast i32 %137 to float, !dbg !70
  br i1 %29, label %139, label %140, !dbg !71

139:                                              ; preds = %127
  tail call void @__assertfail(ptr nonnull @assertMessage_1, ptr nonnull @assertFile_1, i32 883, ptr nonnull @assertFunc_1, i64 1), !dbg !71
  br label %140, !dbg !71

140:                                              ; preds = %139, %127
  %141 = getelementptr float, ptr addrspace(1) %33, i64 %135, !dbg !72
  %142 = tail call i32 asm sideeffect "mov.u32 $0, 0x0;\0A\09@$2 ld.global.L1::evict_first.b32 { $0 }, [ $1 + 0 ];\0A\09@!$4 mov.u32 $0, $3;", "=r,l,b,r,b"(ptr addrspace(1) %141, i1 true, i32 0, i1 true) #5, !dbg !73
  %143 = bitcast i32 %142 to float, !dbg !73
  %144 = fadd float %134, %143, !dbg !74
  %145 = fsub float %144, %118, !dbg !75
  %146 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5, !dbg !76
  %.not.i = icmp eq i32 %146, 0, !dbg !76
  br i1 %.not.i, label %149, label %147, !dbg !76

147:                                              ; preds = %140
  %148 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %125), !dbg !76
  br label %__nv_rsqrtf.exit, !dbg !76

149:                                              ; preds = %140
  %150 = tail call float @llvm.nvvm.rsqrt.approx.f(float %125), !dbg !76
  br label %__nv_rsqrtf.exit, !dbg !76

__nv_rsqrtf.exit:                                 ; preds = %147, %149
  %.0.i = phi float [ %148, %147 ], [ %150, %149 ], !dbg !76
  %151 = fmul float %145, %.0.i, !dbg !77
  %152 = fmul float %151, %138, !dbg !78
  %153 = add i32 %129, %126, !dbg !79
  %154 = sext i32 %153 to i64, !dbg !80
  %155 = getelementptr i16, ptr addrspace(1) %4, i64 %154, !dbg !80
  %156 = tail call i16 asm "cvt.rn.bf16.f32 $0, $1;", "=h,r"(float %152) #5, !dbg !81
  tail call void asm sideeffect "@$2 st.global.b16 [ $1 + 0 ], { $0 };", "c,l,b"(i16 %156, ptr addrspace(1) %155, i1 true) #5, !dbg !81
  %157 = add nuw nsw i32 %128, 4, !dbg !64
  %158 = icmp ult i32 %128, 252, !dbg !64
  br i1 %158, label %127, label %159, !dbg !64

159:                                              ; preds = %__nv_rsqrtf.exit
  ret void, !dbg !82
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare noundef i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0

; Function Attrs: convergent nocallback nounwind memory(inaccessiblemem: readwrite)
declare i32 @llvm.nvvm.shfl.sync.bfly.i32(i32, i32, i32, i32) #1

; Function Attrs: alwaysinline nounwind
define float @__nv_rsqrtf(float %x) local_unnamed_addr #2 {
  %1 = tail call i32 @__nvvm_reflect(ptr nonnull @.str) #5
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %4, label %2

2:                                                ; preds = %0
  %3 = tail call float @llvm.nvvm.rsqrt.approx.ftz.f(float %x)
  br label %6

4:                                                ; preds = %0
  %5 = tail call float @llvm.nvvm.rsqrt.approx.f(float %x)
  br label %6

6:                                                ; preds = %4, %2
  %.0 = phi float [ %3, %2 ], [ %5, %4 ]
  ret float %.0
}

declare i32 @__nvvm_reflect(ptr) local_unnamed_addr #3

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare float @llvm.nvvm.rsqrt.approx.ftz.f(float) #4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
declare float @llvm.nvvm.rsqrt.approx.f(float) #4

attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { convergent nocallback nounwind memory(inaccessiblemem: readwrite) }
attributes #2 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #3 = { "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1}
!llvm.dbg.cu = !{!2}
!nvvm.annotations = !{!4, !5, !5, !4}
!llvm.ident = !{!6}

!0 = !{i32 2, !"Debug Info Version", i32 3}
!1 = !{i32 4, !"nvvm-reflect-ftz", i32 1}
!2 = distinct !DICompileUnit(language: DW_LANG_C, file: !3, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
!3 = !DIFile(filename: "clhe4a3stvufxafmq3kk5hodazz2efctffte646znjdnv3lqi5oa.py", directory: "/tmp/torchinductor_root/lh")
!4 = !{ptr @triton__0d1d2d3d4d5de6de, !"kernel", i32 1}
!5 = !{ptr @triton__0d1d2d3d4d5de6de, !"maxntidx", i32 256}
!6 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"}
!7 = distinct !DISubprogram(name: "triton__0d1d2d3d4d5de6de", linkageName: "triton__0d1d2d3d4d5de6de", scope: !3, file: !3, line: 18, type: !8, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2)
!8 = !DISubroutineType(cc: DW_CC_normal, types: !9)
!9 = !{}
!10 = !DILocation(line: 22, column: 44, scope: !7)
!11 = !DILocation(line: 24, column: 33, scope: !7)
!12 = !DILocation(line: 21, column: 28, scope: !7)
!13 = !DILocation(line: 21, column: 33, scope: !7)
!14 = !DILocation(line: 22, column: 23, scope: !7)
!15 = !DILocation(line: 26, column: 30, scope: !7)
!16 = !DILocation(line: 26, column: 35, scope: !7)
!17 = !DILocation(line: 27, column: 18, scope: !7)
!18 = !DILocation(line: 35, column: 44, scope: !7)
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